; --------------------------------------------------------------------------------
; @Title: IMX8MP On-Chip Peripherals
; @Props: Released
; @Author: KWI, KRZ
; @Changelog: 2021-01-19 KWI
;             2021-04-09 KWI
;             2022-02-28 KRZ
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: SVD generated, based on: i.MX8MPlus_Header_POST_RFP_20210302
; @Core: Cortex-A53, Cortex-M7F
; @Chip: IMX8M-PLUS
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perimx8mp.per 17736 2024-04-08 09:26:07Z kwisniewski $

sif (CORENAME()=="CORTEXA53")
tree "Core Registers (Cortex-A53)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x0
line.long 0x0 "MIDR_EL1,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23.  "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
newline
hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field"
newline
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.quad SPR:0x30006++0x0
line.long 0x0 "REVIDR_EL1,Revision ID Register"
rgroup.quad SPR:0x30014++0x00
line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30015++0x00
line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad SPR:0x30016++0x00
line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad SPR:0x30017++0x00
line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1"
endif
rgroup.quad SPR:0x30020++0x00
line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.quad SPR:0x30021++0x00
line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30022++0x00
line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30023++0x00
line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30024++0x00
line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30025++0x00
line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0"
bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1"
endif
rgroup.quad SPR:0x30010++0x00
line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30011++0x00
line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..."
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1"
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..."
bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1"
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1"
endif
rgroup.quad SPR:0x30013++0x00
line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad SPR:0x31007++0x00
line.long 0x00 "AIDR_EL1,Auxiliary ID Register"
rgroup.quad SPR:0x33007++0x00
line.long 0x00 "DCZID_EL0,Data Cache Zero ID"
bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited"
bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
group.quad SPR:0x30100++0x0
line.long 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x34100++0x0
line.long 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x36100++0x0
line.long 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
rgroup.quad SPR:0x30101++0x0
line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)"
group.quad SPR:0x34101++0x0
line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x36101++0x0
line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x30102++0x00
line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register"
bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..."
bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped"
group.quad SPR:0x36110++0x0
line.long 0x0 "SCR_EL3,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled"
bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
tree.open "Exception Syndrome Registers"
if (CORENAME()=="CORTEXA57")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
elif (CORENAME()=="CORTEXA53")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External,"
newline
hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
endif
tree.end
newline
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address"
rgroup.quad SPR:0x30C10++0x00
line.long 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.quad SPR:0x36C02++0x00
line.long 0x00 "RMR_EL3,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]"
endif
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID Register"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID Register"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID Register"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID Register"
tree.end
tree "Memory Management Unit"
group.quad spr:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB"
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad SPR:0x34300++0x00
line.long 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
rgroup.quad SPR:0x30510++0x00
line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
rgroup.quad SPR:0x34510++0x00
line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
rgroup.quad SPR:0x36510++0x00
line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
rgroup.quad SPR:0x30511++0x00
line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
rgroup.quad SPR:0x34511++0x00
line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
rgroup.quad SPR:0x36511++0x00
line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..."
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
newline
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
rgroup.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)"
rgroup.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)"
rgroup.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)"
tree.end
newline
group.quad SPR:0x30D01++0x00
line.long 0x0 "CONTEXTIDR_EL1,Context ID Register"
tree.end
tree "Virtualization Extensions"
group.quad SPR:0x34000++0x0
line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
endif
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6"
endif
group.quad SPR:0x34112++0x00
line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x36131++0x00
line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes"
bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
group.quad SPR:0x36112++0x00
line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x34113++0x00
line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..."
bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped"
bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped"
newline
bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped"
bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped"
bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped"
newline
bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped"
bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped"
bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped"
newline
bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped"
bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped"
bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped"
newline
bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped"
bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped"
bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped"
rgroup.quad SPR:0x34117++0x00
line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..."
bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..."
bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..."
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits"
tree.end
tree "Cache Control and Configuration"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
group.quad SPR:0x32000++0x0
line.long 0x0 "CSSELR_EL1,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..."
endif
tree "Level 1 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x30F10++0x00
line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register"
group.quad SPR:0x30F11++0x00
line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register"
group.quad SPR:0x30F12++0x00
line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register"
group.quad SPR:0x30F13++0x00
line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register"
group.quad SPR:0x30F00++0x00
line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register"
group.quad SPR:0x30F01++0x00
line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register"
group.quad SPR:0x30F02++0x00
line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register"
group.quad SPR:0x30F03++0x00
line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register"
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
newline
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
newline
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
newline
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
newline
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
newline
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
newline
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
newline
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8"
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
endif
if (CORENAME()=="CORTEXA57")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
endif
tree.end
tree "Level 2 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..."
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
newline
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
newline
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
newline
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
newline
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
newline
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3"
bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled"
bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled"
newline
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.quad SPR:0x339C0++0x00
line.long 0x0 "PMCR_EL0,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad SPR:0x339C1++0x00
line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.quad SPR:0x339C2++0x00
line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.quad SPR:0x339C3++0x00
line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00  30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled"
wgroup.quad SPR:0x339C4++0x00
line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment"
bitfld.long 0x00  30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00  29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00  28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00  27. "P27,Increment PMN27" "No action,Increment"
newline
bitfld.long 0x00  26. "P26,Increment PMN26" "No action,Increment"
bitfld.long 0x00  25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00  24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00  23. "P23,Increment PMN23" "No action,Increment"
newline
bitfld.long 0x00  22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00  21. "P21,Increment PMN21" "No action,Increment"
bitfld.long 0x00  20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00  19. "P19,Increment PMN19" "No action,Increment"
newline
bitfld.long 0x00  18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00  17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00  16. "P16,Increment PMN16" "No action,Increment"
bitfld.long 0x00  15. "P15,Increment PMN15" "No action,Increment"
newline
bitfld.long 0x00  14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00  13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00  12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00  11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00  10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00  9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00  8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00  7. "P7,Increment PMN7" "No action,Increment"
newline
bitfld.long 0x00  6. "P6,Increment PMN6" "No action,Increment"
bitfld.long 0x00  5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00  4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00  3. "P3,Increment PMN3" "No action,Increment"
newline
bitfld.long 0x00  2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00  1. "P1,Increment PMN1" "No action,Increment"
bitfld.long 0x00  0. "P0,Increment PMN0" "No action,Increment"
group.quad SPR:0x339C5++0x00
line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
newline
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
newline
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
newline
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
newline
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
newline
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
newline
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
newline
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
endif
rgroup.quad SPR:0x339C7++0x0
line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented"
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register"
group.quad SPR:0x339D1++0x00
line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
group.quad SPR:0x339D2++0x00
line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register"
group.quad SPR:0x339E0++0x00
line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.quad SPR:0x309E1++0x00
line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad SPR:0x309E2++0x00
line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.quad SPR:0x339E3++0x00
line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register"
group.quad SPR:(0x33E80+0x0)++0x00
line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.quad SPR:(0x33EC0+0x0)++0x00
line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x1)++0x00
line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.quad SPR:(0x33EC0+0x1)++0x00
line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x2)++0x00
line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.quad SPR:(0x33EC0+0x2)++0x00
line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x3)++0x00
line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.quad SPR:(0x33EC0+0x3)++0x00
line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x4)++0x00
line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.quad SPR:(0x33EC0+0x4)++0x00
line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x5)++0x00
line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.quad SPR:(0x33EC0+0x5)++0x00
line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:0x33EF7++0x00
line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad SPR:0x33E00++0x00
line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register"
group.quad SPR:0x30E10++0x00
line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x33E20++0x00
line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register"
group.quad SPR:0x33E21++0x00
line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad SPR:0x33E30++0x00
line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register"
group.quad SPR:0x33E31++0x00
line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register"
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register"
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register"
group.quad SPR:0x34E10++0x00
line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x34E20++0x00
line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register"
group.quad SPR:0x34E21++0x00
line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register"
group.quad SPR:0x37E20++0x00
line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register"
group.quad SPR:0x37E21++0x00
line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)"
rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported"
rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register"
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register"
if (((per.q(spr:0x30CC4))&0x3800)==0x00)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
elif (((per.q(spr:0x30CC4))&0x3800)==0x800)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
endif
hgroup.quad spr:0x30C80++0x00
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad SPR:0x30CC6++0x00
line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x30CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x36CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad SPR:0x30460++0x00
line.long 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad SPR:0x30CB3++0x00
line.long 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad SPR:0x30CC5++0x00
line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x34C95++0x00
line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x36CC5++0x00
line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.quad SPR:0x34C80++0x00
line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
if (CORENAME()=="CORTEXA53")
group.quad SPR:0x34C90++0x00
line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
endif
tree.end
newline
rgroup.quad SPR:0x34CB3++0x00
line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.quad SPR:0x34CB5++0x00
line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.quad SPR:0x34CB0++0x00
line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
rgroup.quad SPR:0x34CB2++0x00
line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.quad SPR:0x34CB7++0x00
line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.quad SPR:0x34C94++0x00
line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register"
rgroup.quad SPR:0x34CB1++0x00
line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
rgroup.quad SPR:0x23010++0x00
line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad SPR:0x20020++0x00
line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register"
bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
rgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad SPR:0x24070++0x00
line.long 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High"
newline
bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High"
newline
bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High"
group.quad SPR:0x20002++0x00
line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20022++0x00
line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High"
bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3"
bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High"
bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled"
bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High"
bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled"
group.quad SPR:0x20032++0x00
line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20062++0x00
line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad SPR:0x20104++0x00
line.long 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad SPR:0x20114++0x00
line.long 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..."
group.quad SPR:0x20134++0x00
line.long 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad SPR:0x20144++0x00
line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes"
group.quad SPR:0x20786++0x00
line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.quad SPR:0x20796++0x00
line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.quad SPR:0x207E6++0x00
line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
group.quad SPR:0x33450++0x00
line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
group.quad spr:0x33451++0x00
line.quad 0x00 "DLR_EL0,Debug Link Register"
tree.end
tree "Breakpoint Registers"
if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x0)++0x0
line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x10)++0x0
line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x20)++0x0
line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x30)++0x0
line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x40)++0x0
line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x50)++0x0
line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0"
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1"
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2"
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3"
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
rgroup.long c15:0x0000++0x0
line.long 0x0 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
newline
hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0300++0x0
line.long 0x0 "TLBTR,TLB Type Register"
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4"
elif corename()=="CORTEXA53"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..."
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.long c15:0x0600++0x0
line.long 0x0 "REVIDR,Revision ID Register"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,ID_MMFR4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
group.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
if corename()=="CORTEXA57"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
elif corename()=="CORTEXA53"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented"
endif
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
tree.end
tree "System Control and Configuration"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,System Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
else
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
endif
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
newline
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
newline
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
newline
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
newline
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
newline
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
newline
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
newline
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
newline
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
newline
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
newline
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
newline
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
newline
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
newline
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
newline
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
newline
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
endif
if corename()=="CORTEXA57"
group.long c15:0x0201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes"
newline
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
elif corename()=="CORTEXA53"
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
newline
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
endif
group.long c15:0x0011++0x0
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
newline
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
if corename()=="CORTEXA57"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
elif corename()=="CORTEXA53"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
endif
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
group.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
group.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
endif
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
if corename()=="CORTEXA57"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]"
elif corename()=="CORTEXA53"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]"
endif
group.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE Process ID register"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
tree.end
tree "Memory Management Unit"
if corename()=="CORTEXA57"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
// MPIDR[31]==1 case is missing here for TTBR0 and TTBR1
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
endif
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
endif
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address"
bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
endif
endif
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
else
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
endif
tree.open "Memory Attribute Indirection Registers"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x002A++0x0
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
group.long c15:0x012A++0x0
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
endif
tree.end
newline
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier"
endif
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x0
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
if corename()=="CORTEXA57"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
newline
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
newline
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
elif corename()=="CORTEXA53"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
newline
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
newline
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
newline
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted"
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override"
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
newline
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
endif
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
newline
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..."
newline
bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped"
bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
newline
bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..."
newline
hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13"
bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High"
bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
group.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
tree.open "Hypervisor Memory Attribute Indirection Registers"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
tree.end
newline
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT"
newline
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
endif
rgroup.long c15:0x1700++0x0
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x0
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported"
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
newline
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..."
group.long c15:0x2000++0x0
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
tree "Level 1 memory system"
if corename()=="CORTEXA57"
group.long c15:0x001F++0x00
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
group.long c15:0x011F++0x00
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
group.long c15:0x021F++0x00
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
group.long c15:0x031F++0x00
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
group.long c15:0x000F++0x00
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
group.long c15:0x010F++0x00
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
group.long c15:0x020F++0x00
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
group.long c15:0x030F++0x00
line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register"
wgroup.long c15:0x04F++0x00
line.long 0x00 "RAMINDEX,RAM Index Operation Register"
elif corename()=="CORTEXA53"
rgroup.long c15:0x300F++0x00
line.long 0x00 "CDBGDR0,Cache Debug Data Register 0"
rgroup.long c15:0x310F++0x00
line.long 0x00 "CDBGDR1,Cache Debug Data Register 1"
rgroup.long c15:0x320F++0x00
line.long 0x00 "CDBGDR2,Cache Debug Data Register 2"
rgroup.long c15:0x330F++0x00
line.long 0x00 "CDBGDR3,Cache Debug Data Register 3"
wgroup.long c15:0x302F++0x00
line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register"
wgroup.long c15:0x312F++0x00
line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register"
wgroup.long c15:0x304F++0x00
line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register"
wgroup.long c15:0x314F++0x00
line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register"
wgroup.long c15:0x324F++0x00
line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register"
endif
tree.end
tree "Level 2 memory system"
if corename()=="CORTEXA57"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
newline
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported"
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present"
newline
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
newline
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
newline
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
newline
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
newline
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad c15:0x130F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif corename()=="CORTEXA53"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
newline
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x0 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x1c9++0x00
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow"
eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow"
eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow"
eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow"
eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow"
eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow"
eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow"
eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow"
eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow"
eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow"
eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow"
eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow"
eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow"
eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow"
eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow"
eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow"
eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow"
eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow"
eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow"
eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment"
bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment"
newline
bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment"
bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment"
newline
bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment"
bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment"
newline
bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment"
bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment"
bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment"
newline
bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment"
bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment"
newline
bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
group.long c15:0x1d9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
group.long c15:0x2d9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.long c15:0x3e9++0x00
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x40)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x40)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x40)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x40)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x40)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x40)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
rgroup.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch32 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
newline
bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register"
if (((per.l(c15:0x4CC))&0x3800)==0x00)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
elif (((per.l(c15:0x4CC))&0x3800)==0x800)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
endif
hgroup.long c15:0x008C++0x00
hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
in
hgroup.long c15:0x00CC++0x00
hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
in
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
if corename()=="CORTEXA53"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
endif
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x459C++0x00
line.long 0x00 "ICH_SRE,Hypervisor System Register"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.long c15:0x449C++0x00
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
if corename()=="CORTEXA57"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
elif corename()=="CORTEXA53"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
newline
bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number"
newline
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number"
endif
rgroup.long c14:0x0060++0x0
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register"
bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled"
group.long c14:0x0200++0x0
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
group.long c14:0x0220++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
rgroup.long c14:0x0010++0x0
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
wgroup.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
group.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)"
group.long c14:0x0687++0x0
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x0
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x0
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented"
newline
bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1"
newline
bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1"
rgroup.long c14:0x0707++0x0
line.long 0x0 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x0
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..."
bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented"
newline
bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
tree.end
newline
rgroup.quad c14:0x10010++0x1
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address"
hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address"
bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid"
newline
bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid"
rgroup.quad c14:0x10020++0x1
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
if (((per.l(c14:0x0411))&0x2)==0x2)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
hgroup.long c14:0x0260++0x00
hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register"
bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High"
tree.end
tree "Breakpoint Registers"
if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x0)++0x0
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x10)++0x0
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x20)++0x0
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x30)++0x0
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x40)++0x0
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x50)++0x0
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
group.long c14:0x0141++0x0
line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
group.long c14:0x0151++0x0
line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
tree.end
tree "Watchpoint Control Registers"
group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0"
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1"
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2"
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3"
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree.open "Interrupt Controller (GIC-500)"
base COMP.BASE("GICD",-1.)
width 17.
tree "Distributor Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)))
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 6. "       DS            ,Disable Security" "No,Yes"
textline "                          "
bitfld.long 0x00 5. " ARE_NS       ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_S      ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "       ENABLEGRP1S   ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_NS        ,Affinity Routing Enable" "Reserved,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1A  ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
rbitfld.long 0x00 6. "       DS            ,Disable Security" "Reserved,Yes"
textline "                          "
bitfld.long 0x00 4. " ARE          ,Affinity Routing Enable" "Reserved,Enabled"
bitfld.long 0x00 1. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0    ,Enable Group 0 interrupts" "Disabled,Enabled"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 25. " NO1N         ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported"
bitfld.long 0x00 24. "  A3V        ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported"
bitfld.long 0x00 19.--23. "  IDBITS        ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
textline "                          "
bitfld.long 0x00 17. " LPIS         ,Indicates whether the implementation supports LPIs" "Not supported,Supported"
bitfld.long 0x00 16. "  MBIS       ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported"
bitfld.long 0x00 10. "  SECURITYEXTN  ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER    ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 0.--4. "              ITLN       ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved"
rgroup.long 0x0008++0x03
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. " PRODID       ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "        VAR        ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                          "
bitfld.long 0x00 12.--15. " REV          ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "             IMP        ,Implementer"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000)
wgroup.long 0x40++0x03
line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
wgroup.long 0x48++0x03
line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50))
wgroup.long 0x50++0x03
line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58))
wgroup.long 0x58++0x03
line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)"
endif
else
hgroup.long 0x40++0x03
hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hgroup.long 0x48++0x03
hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register"
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register"
endif
width 17.
tree "Group Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080))
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30  ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29  ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27  ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26  ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24  ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23  ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21  ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20  ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18  ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17  ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15  ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14  ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12  ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11  ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9   ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8   ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6   ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5   ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3   ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2   ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0   ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30  ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29  ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27  ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26  ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24  ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23  ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21  ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20  ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18  ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17  ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15  ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14  ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12  ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11  ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9   ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8   ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6   ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5   ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3   ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2   ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0   ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x0080++0x03
hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)"
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB62  ,Group Status Bit 62" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB61  ,Group Status Bit 61" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB59  ,Group Status Bit 59" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB58  ,Group Status Bit 58" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB56  ,Group Status Bit 56" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB55  ,Group Status Bit 55" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB53  ,Group Status Bit 53" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB52  ,Group Status Bit 52" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB50  ,Group Status Bit 50" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB49  ,Group Status Bit 49" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB47  ,Group Status Bit 47" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB46  ,Group Status Bit 46" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB44  ,Group Status Bit 44" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB43  ,Group Status Bit 43" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB41  ,Group Status Bit 41" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB40  ,Group Status Bit 40" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB38  ,Group Status Bit 38" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB37  ,Group Status Bit 37" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB35  ,Group Status Bit 35" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB34  ,Group Status Bit 34" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB32  ,Group Status Bit 32" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB62  ,Group Status Bit 62" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB61  ,Group Status Bit 61" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB59  ,Group Status Bit 59" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB58  ,Group Status Bit 58" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB56  ,Group Status Bit 56" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB55  ,Group Status Bit 55" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB53  ,Group Status Bit 53" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB52  ,Group Status Bit 52" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB50  ,Group Status Bit 50" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB49  ,Group Status Bit 49" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB47  ,Group Status Bit 47" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB46  ,Group Status Bit 46" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB44  ,Group Status Bit 44" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB43  ,Group Status Bit 43" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB41  ,Group Status Bit 41" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB40  ,Group Status Bit 40" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB38  ,Group Status Bit 38" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB37  ,Group Status Bit 37" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB35  ,Group Status Bit 35" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB34  ,Group Status Bit 34" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB32  ,Group Status Bit 32" "Group 0,Group 1"
else
hgroup.long 0x0084++0x03
hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)"
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB94  ,Group Status Bit 94" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB93  ,Group Status Bit 93" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB91  ,Group Status Bit 91" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB90  ,Group Status Bit 90" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB88  ,Group Status Bit 88" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB87  ,Group Status Bit 87" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB85  ,Group Status Bit 85" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB84  ,Group Status Bit 84" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB82  ,Group Status Bit 82" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB81  ,Group Status Bit 81" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB79  ,Group Status Bit 79" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB78  ,Group Status Bit 78" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB76  ,Group Status Bit 76" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB75  ,Group Status Bit 75" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB73  ,Group Status Bit 73" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB72  ,Group Status Bit 72" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB70  ,Group Status Bit 70" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB69  ,Group Status Bit 69" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB67  ,Group Status Bit 67" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB66  ,Group Status Bit 66" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB64  ,Group Status Bit 64" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB94  ,Group Status Bit 94" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB93  ,Group Status Bit 93" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB91  ,Group Status Bit 91" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB90  ,Group Status Bit 90" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB88  ,Group Status Bit 88" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB87  ,Group Status Bit 87" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB85  ,Group Status Bit 85" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB84  ,Group Status Bit 84" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB82  ,Group Status Bit 82" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB81  ,Group Status Bit 81" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB79  ,Group Status Bit 79" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB78  ,Group Status Bit 78" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB76  ,Group Status Bit 76" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB75  ,Group Status Bit 75" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB73  ,Group Status Bit 73" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB72  ,Group Status Bit 72" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB70  ,Group Status Bit 70" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB69  ,Group Status Bit 69" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB67  ,Group Status Bit 67" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB66  ,Group Status Bit 66" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB64  ,Group Status Bit 64" "Group 0,Group 1"
else
hgroup.long 0x0088++0x03
hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)"
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB99  ,Group Status Bit 99" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB98  ,Group Status Bit 98" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB96  ,Group Status Bit 96" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB126 ,Group Status Bit 126" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB125 ,Group Status Bit 125" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB123 ,Group Status Bit 123" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB122 ,Group Status Bit 122" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB120 ,Group Status Bit 120" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB119 ,Group Status Bit 119" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB117 ,Group Status Bit 117" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB116 ,Group Status Bit 116" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB114 ,Group Status Bit 114" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB113 ,Group Status Bit 113" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB111 ,Group Status Bit 111" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB110 ,Group Status Bit 110" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB108 ,Group Status Bit 108" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB107 ,Group Status Bit 107" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB105 ,Group Status Bit 105" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB104 ,Group Status Bit 104" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB102 ,Group Status Bit 102" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB101 ,Group Status Bit 101" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB99  ,Group Status Bit 99" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB98  ,Group Status Bit 98" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB96  ,Group Status Bit 96" "Group 0,Group 1"
else
hgroup.long 0x008C++0x03
hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)"
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB158 ,Group Status Bit 158" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB157 ,Group Status Bit 157" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB155 ,Group Status Bit 155" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB154 ,Group Status Bit 154" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB152 ,Group Status Bit 152" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB151 ,Group Status Bit 151" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB149 ,Group Status Bit 149" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB148 ,Group Status Bit 148" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB146 ,Group Status Bit 146" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB145 ,Group Status Bit 145" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB143 ,Group Status Bit 143" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB142 ,Group Status Bit 142" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB140 ,Group Status Bit 140" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB139 ,Group Status Bit 139" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB137 ,Group Status Bit 137" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB136 ,Group Status Bit 136" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB134 ,Group Status Bit 134" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB133 ,Group Status Bit 133" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB131 ,Group Status Bit 131" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB130 ,Group Status Bit 130" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB128 ,Group Status Bit 128" "Group 0,Group 1"
else
hgroup.long 0x0090++0x03
hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)"
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB190 ,Group Status Bit 190" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB189 ,Group Status Bit 189" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB187 ,Group Status Bit 187" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB186 ,Group Status Bit 186" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB184 ,Group Status Bit 184" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB183 ,Group Status Bit 183" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB181 ,Group Status Bit 181" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB180 ,Group Status Bit 180" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB178 ,Group Status Bit 178" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB177 ,Group Status Bit 177" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB175 ,Group Status Bit 175" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB174 ,Group Status Bit 174" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB172 ,Group Status Bit 172" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB171 ,Group Status Bit 171" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB169 ,Group Status Bit 169" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB168 ,Group Status Bit 168" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB166 ,Group Status Bit 166" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB165 ,Group Status Bit 165" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB163 ,Group Status Bit 163" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB162 ,Group Status Bit 162" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB160 ,Group Status Bit 160" "Group 0,Group 1"
else
hgroup.long 0x0094++0x03
hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)"
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB222 ,Group Status Bit 222" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB221 ,Group Status Bit 221" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB219 ,Group Status Bit 219" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB218 ,Group Status Bit 218" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB216 ,Group Status Bit 216" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB215 ,Group Status Bit 215" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB213 ,Group Status Bit 213" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB212 ,Group Status Bit 212" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB210 ,Group Status Bit 210" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB209 ,Group Status Bit 209" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB207 ,Group Status Bit 207" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB206 ,Group Status Bit 206" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB204 ,Group Status Bit 204" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB203 ,Group Status Bit 203" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB201 ,Group Status Bit 201" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB200 ,Group Status Bit 200" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB198 ,Group Status Bit 198" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB197 ,Group Status Bit 197" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB195 ,Group Status Bit 195" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB194 ,Group Status Bit 194" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB192 ,Group Status Bit 192" "Group 0,Group 1"
else
hgroup.long 0x0098++0x03
hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)"
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB254 ,Group Status Bit 254" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB253 ,Group Status Bit 253" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB251 ,Group Status Bit 251" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB250 ,Group Status Bit 250" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB248 ,Group Status Bit 248" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB247 ,Group Status Bit 247" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB245 ,Group Status Bit 245" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB244 ,Group Status Bit 244" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB242 ,Group Status Bit 242" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB241 ,Group Status Bit 241" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB239 ,Group Status Bit 239" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB238 ,Group Status Bit 238" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB236 ,Group Status Bit 236" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB235 ,Group Status Bit 235" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB233 ,Group Status Bit 233" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB232 ,Group Status Bit 232" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB230 ,Group Status Bit 230" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB229 ,Group Status Bit 229" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB227 ,Group Status Bit 227" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB226 ,Group Status Bit 226" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB224 ,Group Status Bit 224" "Group 0,Group 1"
else
hgroup.long 0x009C++0x03
hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)"
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB286 ,Group Status Bit 286" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB285 ,Group Status Bit 285" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB283 ,Group Status Bit 283" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB282 ,Group Status Bit 282" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB280 ,Group Status Bit 280" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB279 ,Group Status Bit 279" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB277 ,Group Status Bit 277" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB276 ,Group Status Bit 276" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB274 ,Group Status Bit 274" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB273 ,Group Status Bit 273" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB271 ,Group Status Bit 271" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB270 ,Group Status Bit 270" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB268 ,Group Status Bit 268" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB267 ,Group Status Bit 267" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB265 ,Group Status Bit 265" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB264 ,Group Status Bit 264" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB262 ,Group Status Bit 262" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB261 ,Group Status Bit 261" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB259 ,Group Status Bit 259" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB258 ,Group Status Bit 258" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB256 ,Group Status Bit 256" "Group 0,Group 1"
else
hgroup.long 0x00A0++0x03
hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)"
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB318 ,Group Status Bit 318" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB317 ,Group Status Bit 317" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB315 ,Group Status Bit 315" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB314 ,Group Status Bit 314" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB312 ,Group Status Bit 312" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB311 ,Group Status Bit 311" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB309 ,Group Status Bit 309" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB308 ,Group Status Bit 308" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB306 ,Group Status Bit 306" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB305 ,Group Status Bit 305" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB303 ,Group Status Bit 303" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB302 ,Group Status Bit 302" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB300 ,Group Status Bit 300" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB299 ,Group Status Bit 299" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB297 ,Group Status Bit 297" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB296 ,Group Status Bit 296" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB294 ,Group Status Bit 294" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB293 ,Group Status Bit 293" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB291 ,Group Status Bit 291" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB290 ,Group Status Bit 290" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB288 ,Group Status Bit 288" "Group 0,Group 1"
else
hgroup.long 0x00A4++0x03
hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB350 ,Group Status Bit 350" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB349 ,Group Status Bit 349" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB347 ,Group Status Bit 347" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB346 ,Group Status Bit 346" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB344 ,Group Status Bit 344" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB343 ,Group Status Bit 343" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB341 ,Group Status Bit 341" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB340 ,Group Status Bit 340" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB338 ,Group Status Bit 338" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB337 ,Group Status Bit 337" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB335 ,Group Status Bit 335" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB334 ,Group Status Bit 334" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB332 ,Group Status Bit 332" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB331 ,Group Status Bit 331" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB329 ,Group Status Bit 329" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB328 ,Group Status Bit 328" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB326 ,Group Status Bit 326" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB325 ,Group Status Bit 325" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB323 ,Group Status Bit 323" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB322 ,Group Status Bit 322" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB320 ,Group Status Bit 320" "Group 0,Group 1"
else
hgroup.long 0x00A8++0x03
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB382 ,Group Status Bit 382" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB381 ,Group Status Bit 381" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB379 ,Group Status Bit 379" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB378 ,Group Status Bit 378" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB376 ,Group Status Bit 376" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB375 ,Group Status Bit 375" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB373 ,Group Status Bit 373" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB372 ,Group Status Bit 372" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB370 ,Group Status Bit 370" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB369 ,Group Status Bit 369" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB367 ,Group Status Bit 367" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB366 ,Group Status Bit 366" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB364 ,Group Status Bit 364" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB363 ,Group Status Bit 363" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB361 ,Group Status Bit 361" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB360 ,Group Status Bit 360" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB358 ,Group Status Bit 358" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB357 ,Group Status Bit 357" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB355 ,Group Status Bit 355" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB354 ,Group Status Bit 354" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB352 ,Group Status Bit 352" "Group 0,Group 1"
else
hgroup.long 0x00AC++0x03
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB414 ,Group Status Bit 414" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB413 ,Group Status Bit 413" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB411 ,Group Status Bit 411" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB410 ,Group Status Bit 410" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB408 ,Group Status Bit 408" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB407 ,Group Status Bit 407" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB405 ,Group Status Bit 405" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB404 ,Group Status Bit 404" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB402 ,Group Status Bit 402" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB401 ,Group Status Bit 401" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB399 ,Group Status Bit 399" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB398 ,Group Status Bit 398" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB396 ,Group Status Bit 396" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB395 ,Group Status Bit 395" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB393 ,Group Status Bit 393" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB392 ,Group Status Bit 392" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB390 ,Group Status Bit 390" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB389 ,Group Status Bit 389" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB387 ,Group Status Bit 387" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB386 ,Group Status Bit 386" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB384 ,Group Status Bit 384" "Group 0,Group 1"
else
hgroup.long 0x00B0++0x03
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB446 ,Group Status Bit 446" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB445 ,Group Status Bit 445" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB443 ,Group Status Bit 443" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB442 ,Group Status Bit 442" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB440 ,Group Status Bit 440" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB439 ,Group Status Bit 439" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB437 ,Group Status Bit 437" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB436 ,Group Status Bit 436" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB434 ,Group Status Bit 434" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB433 ,Group Status Bit 433" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB431 ,Group Status Bit 431" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB430 ,Group Status Bit 430" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB428 ,Group Status Bit 428" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB427 ,Group Status Bit 427" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB425 ,Group Status Bit 425" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB424 ,Group Status Bit 424" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB422 ,Group Status Bit 422" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB421 ,Group Status Bit 421" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB419 ,Group Status Bit 419" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB418 ,Group Status Bit 418" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB416 ,Group Status Bit 416" "Group 0,Group 1"
else
hgroup.long 0x00B4++0x03
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB478 ,Group Status Bit 478" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB477 ,Group Status Bit 477" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB475 ,Group Status Bit 475" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB474 ,Group Status Bit 474" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB472 ,Group Status Bit 472" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB471 ,Group Status Bit 471" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB469 ,Group Status Bit 469" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB468 ,Group Status Bit 468" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB466 ,Group Status Bit 466" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB465 ,Group Status Bit 465" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB463 ,Group Status Bit 463" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB462 ,Group Status Bit 462" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB460 ,Group Status Bit 460" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB459 ,Group Status Bit 459" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB457 ,Group Status Bit 457" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB456 ,Group Status Bit 456" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB454 ,Group Status Bit 454" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB453 ,Group Status Bit 453" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB451 ,Group Status Bit 451" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB450 ,Group Status Bit 450" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB448 ,Group Status Bit 448" "Group 0,Group 1"
else
hgroup.long 0x00B8++0x03
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB510 ,Group Status Bit 510" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB509 ,Group Status Bit 509" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB507 ,Group Status Bit 507" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB506 ,Group Status Bit 506" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB504 ,Group Status Bit 504" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB503 ,Group Status Bit 503" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB501 ,Group Status Bit 501" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB500 ,Group Status Bit 500" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB498 ,Group Status Bit 498" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB497 ,Group Status Bit 497" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB495 ,Group Status Bit 495" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB494 ,Group Status Bit 494" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB492 ,Group Status Bit 492" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB491 ,Group Status Bit 491" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB489 ,Group Status Bit 489" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB488 ,Group Status Bit 488" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB486 ,Group Status Bit 486" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB485 ,Group Status Bit 485" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB483 ,Group Status Bit 483" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB482 ,Group Status Bit 482" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB480 ,Group Status Bit 480" "Group 0,Group 1"
else
hgroup.long 0x00BC++0x03
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB542 ,Group Status Bit 542" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB541 ,Group Status Bit 541" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB539 ,Group Status Bit 539" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB538 ,Group Status Bit 538" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB536 ,Group Status Bit 536" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB535 ,Group Status Bit 535" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB533 ,Group Status Bit 533" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB532 ,Group Status Bit 532" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB530 ,Group Status Bit 530" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB529 ,Group Status Bit 529" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB527 ,Group Status Bit 527" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB526 ,Group Status Bit 526" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB524 ,Group Status Bit 524" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB523 ,Group Status Bit 523" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB521 ,Group Status Bit 521" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB520 ,Group Status Bit 520" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB518 ,Group Status Bit 518" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB517 ,Group Status Bit 517" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB515 ,Group Status Bit 515" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB514 ,Group Status Bit 514" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB512 ,Group Status Bit 512" "Group 0,Group 1"
else
hgroup.long 0x00C0++0x03
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB574 ,Group Status Bit 574" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB573 ,Group Status Bit 573" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB571 ,Group Status Bit 571" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB570 ,Group Status Bit 570" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB568 ,Group Status Bit 568" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB567 ,Group Status Bit 567" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB565 ,Group Status Bit 565" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB564 ,Group Status Bit 564" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB562 ,Group Status Bit 562" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB561 ,Group Status Bit 561" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB559 ,Group Status Bit 559" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB558 ,Group Status Bit 558" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB556 ,Group Status Bit 556" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB555 ,Group Status Bit 555" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB553 ,Group Status Bit 553" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB552 ,Group Status Bit 552" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB550 ,Group Status Bit 550" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB549 ,Group Status Bit 549" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB547 ,Group Status Bit 547" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB546 ,Group Status Bit 546" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB544 ,Group Status Bit 544" "Group 0,Group 1"
else
hgroup.long 0x00C4++0x03
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB606 ,Group Status Bit 606" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB605 ,Group Status Bit 605" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB603 ,Group Status Bit 603" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB602 ,Group Status Bit 602" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB600 ,Group Status Bit 600" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB599 ,Group Status Bit 599" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB597 ,Group Status Bit 597" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB596 ,Group Status Bit 596" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB594 ,Group Status Bit 594" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB593 ,Group Status Bit 593" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB591 ,Group Status Bit 591" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB590 ,Group Status Bit 590" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB588 ,Group Status Bit 588" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB587 ,Group Status Bit 587" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB585 ,Group Status Bit 585" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB584 ,Group Status Bit 584" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB582 ,Group Status Bit 582" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB581 ,Group Status Bit 581" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB579 ,Group Status Bit 579" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB578 ,Group Status Bit 578" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB576 ,Group Status Bit 576" "Group 0,Group 1"
else
hgroup.long 0x00C8++0x03
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB638 ,Group Status Bit 638" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB637 ,Group Status Bit 637" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB635 ,Group Status Bit 635" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB634 ,Group Status Bit 634" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB632 ,Group Status Bit 632" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB631 ,Group Status Bit 631" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB629 ,Group Status Bit 629" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB628 ,Group Status Bit 628" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB626 ,Group Status Bit 626" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB625 ,Group Status Bit 625" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB623 ,Group Status Bit 623" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB622 ,Group Status Bit 622" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB620 ,Group Status Bit 620" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB619 ,Group Status Bit 619" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB617 ,Group Status Bit 617" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB616 ,Group Status Bit 616" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB614 ,Group Status Bit 614" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB613 ,Group Status Bit 613" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB611 ,Group Status Bit 611" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB610 ,Group Status Bit 610" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB608 ,Group Status Bit 608" "Group 0,Group 1"
else
hgroup.long 0x00CC++0x03
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB670 ,Group Status Bit 670" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB669 ,Group Status Bit 669" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB667 ,Group Status Bit 667" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB666 ,Group Status Bit 666" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB664 ,Group Status Bit 664" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB663 ,Group Status Bit 663" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB661 ,Group Status Bit 661" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB660 ,Group Status Bit 660" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB658 ,Group Status Bit 658" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB657 ,Group Status Bit 657" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB655 ,Group Status Bit 655" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB654 ,Group Status Bit 654" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB652 ,Group Status Bit 652" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB651 ,Group Status Bit 651" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB649 ,Group Status Bit 649" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB648 ,Group Status Bit 648" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB646 ,Group Status Bit 646" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB645 ,Group Status Bit 645" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB643 ,Group Status Bit 643" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB642 ,Group Status Bit 642" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB640 ,Group Status Bit 640" "Group 0,Group 1"
else
hgroup.long 0x00D0++0x03
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB702 ,Group Status Bit 702" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB701 ,Group Status Bit 701" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB699 ,Group Status Bit 699" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB698 ,Group Status Bit 698" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB696 ,Group Status Bit 696" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB695 ,Group Status Bit 695" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB693 ,Group Status Bit 693" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB692 ,Group Status Bit 692" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB690 ,Group Status Bit 690" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB689 ,Group Status Bit 689" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB687 ,Group Status Bit 687" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB686 ,Group Status Bit 686" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB684 ,Group Status Bit 684" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB683 ,Group Status Bit 683" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB681 ,Group Status Bit 681" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB680 ,Group Status Bit 680" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB678 ,Group Status Bit 678" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB677 ,Group Status Bit 677" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB675 ,Group Status Bit 675" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB674 ,Group Status Bit 674" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB672 ,Group Status Bit 672" "Group 0,Group 1"
else
hgroup.long 0x00D4++0x03
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB734 ,Group Status Bit 734" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB733 ,Group Status Bit 733" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB731 ,Group Status Bit 731" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB730 ,Group Status Bit 730" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB728 ,Group Status Bit 728" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB727 ,Group Status Bit 727" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB725 ,Group Status Bit 725" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB724 ,Group Status Bit 724" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB722 ,Group Status Bit 722" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB721 ,Group Status Bit 721" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB719 ,Group Status Bit 719" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB718 ,Group Status Bit 718" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB716 ,Group Status Bit 716" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB715 ,Group Status Bit 715" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB713 ,Group Status Bit 713" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB712 ,Group Status Bit 712" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB710 ,Group Status Bit 710" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB709 ,Group Status Bit 709" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB707 ,Group Status Bit 707" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB706 ,Group Status Bit 706" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB704 ,Group Status Bit 704" "Group 0,Group 1"
else
hgroup.long 0x00D8++0x03
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB766 ,Group Status Bit 766" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB765 ,Group Status Bit 765" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB763 ,Group Status Bit 763" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB762 ,Group Status Bit 762" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB760 ,Group Status Bit 760" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB759 ,Group Status Bit 759" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB757 ,Group Status Bit 757" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB756 ,Group Status Bit 756" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB754 ,Group Status Bit 754" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB753 ,Group Status Bit 753" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB751 ,Group Status Bit 751" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB750 ,Group Status Bit 750" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB748 ,Group Status Bit 748" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB747 ,Group Status Bit 747" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB745 ,Group Status Bit 745" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB744 ,Group Status Bit 744" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB742 ,Group Status Bit 742" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB741 ,Group Status Bit 741" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB739 ,Group Status Bit 739" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB738 ,Group Status Bit 738" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB736 ,Group Status Bit 736" "Group 0,Group 1"
else
hgroup.long 0x00DC++0x03
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB798 ,Group Status Bit 798" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB797 ,Group Status Bit 797" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB795 ,Group Status Bit 795" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB794 ,Group Status Bit 794" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB792 ,Group Status Bit 792" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB791 ,Group Status Bit 791" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB789 ,Group Status Bit 789" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB788 ,Group Status Bit 788" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB786 ,Group Status Bit 786" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB785 ,Group Status Bit 785" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB783 ,Group Status Bit 783" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB782 ,Group Status Bit 782" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB780 ,Group Status Bit 780" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB779 ,Group Status Bit 779" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB777 ,Group Status Bit 777" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB776 ,Group Status Bit 776" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB774 ,Group Status Bit 774" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB773 ,Group Status Bit 773" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB771 ,Group Status Bit 771" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB770 ,Group Status Bit 770" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB768 ,Group Status Bit 768" "Group 0,Group 1"
else
hgroup.long 0x00E0++0x03
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB830 ,Group Status Bit 830" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB829 ,Group Status Bit 829" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB827 ,Group Status Bit 827" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB826 ,Group Status Bit 826" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB824 ,Group Status Bit 824" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB823 ,Group Status Bit 823" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB821 ,Group Status Bit 821" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB820 ,Group Status Bit 820" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB818 ,Group Status Bit 818" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB817 ,Group Status Bit 817" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB815 ,Group Status Bit 815" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB814 ,Group Status Bit 814" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB812 ,Group Status Bit 812" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB811 ,Group Status Bit 811" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB809 ,Group Status Bit 809" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB808 ,Group Status Bit 808" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB806 ,Group Status Bit 806" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB805 ,Group Status Bit 805" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB803 ,Group Status Bit 803" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB802 ,Group Status Bit 802" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB800 ,Group Status Bit 800" "Group 0,Group 1"
else
hgroup.long 0x00E4++0x03
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB862 ,Group Status Bit 862" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB861 ,Group Status Bit 861" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB859 ,Group Status Bit 859" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB858 ,Group Status Bit 858" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB856 ,Group Status Bit 856" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB855 ,Group Status Bit 855" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB853 ,Group Status Bit 853" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB852 ,Group Status Bit 852" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB850 ,Group Status Bit 850" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB849 ,Group Status Bit 849" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB847 ,Group Status Bit 847" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB846 ,Group Status Bit 846" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB844 ,Group Status Bit 844" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB843 ,Group Status Bit 843" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB841 ,Group Status Bit 841" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB840 ,Group Status Bit 840" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB838 ,Group Status Bit 838" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB837 ,Group Status Bit 837" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB835 ,Group Status Bit 835" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB834 ,Group Status Bit 834" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB832 ,Group Status Bit 832" "Group 0,Group 1"
else
hgroup.long 0x00E8++0x03
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB894 ,Group Status Bit 894" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB893 ,Group Status Bit 893" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB891 ,Group Status Bit 891" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB890 ,Group Status Bit 890" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB888 ,Group Status Bit 888" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB887 ,Group Status Bit 887" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB885 ,Group Status Bit 885" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB884 ,Group Status Bit 884" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB882 ,Group Status Bit 882" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB881 ,Group Status Bit 881" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB879 ,Group Status Bit 879" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB878 ,Group Status Bit 878" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB876 ,Group Status Bit 876" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB875 ,Group Status Bit 875" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB873 ,Group Status Bit 873" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB872 ,Group Status Bit 872" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB870 ,Group Status Bit 870" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB869 ,Group Status Bit 869" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB867 ,Group Status Bit 867" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB866 ,Group Status Bit 866" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB864 ,Group Status Bit 864" "Group 0,Group 1"
else
hgroup.long 0x00EC++0x03
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB926 ,Group Status Bit 926" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB925 ,Group Status Bit 925" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB923 ,Group Status Bit 923" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB922 ,Group Status Bit 922" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB920 ,Group Status Bit 920" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB919 ,Group Status Bit 919" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB917 ,Group Status Bit 917" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB916 ,Group Status Bit 916" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB914 ,Group Status Bit 914" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB913 ,Group Status Bit 913" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB911 ,Group Status Bit 911" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB910 ,Group Status Bit 910" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB908 ,Group Status Bit 908" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB907 ,Group Status Bit 907" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB905 ,Group Status Bit 905" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB904 ,Group Status Bit 904" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB902 ,Group Status Bit 902" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB901 ,Group Status Bit 901" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB899 ,Group Status Bit 899" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB898 ,Group Status Bit 898" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB896 ,Group Status Bit 896" "Group 0,Group 1"
else
hgroup.long 0x00F0++0x03
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB958 ,Group Status Bit 958" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB957 ,Group Status Bit 957" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB955 ,Group Status Bit 955" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB954 ,Group Status Bit 954" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB952 ,Group Status Bit 952" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB951 ,Group Status Bit 951" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB949 ,Group Status Bit 949" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB948 ,Group Status Bit 948" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB946 ,Group Status Bit 946" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB945 ,Group Status Bit 945" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB943 ,Group Status Bit 943" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB942 ,Group Status Bit 942" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB940 ,Group Status Bit 940" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB939 ,Group Status Bit 939" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB937 ,Group Status Bit 937" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB936 ,Group Status Bit 936" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB934 ,Group Status Bit 934" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB933 ,Group Status Bit 933" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB931 ,Group Status Bit 931" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB930 ,Group Status Bit 930" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB928 ,Group Status Bit 928" "Group 0,Group 1"
else
hgroup.long 0x00F4++0x03
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB990 ,Group Status Bit 990" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB989 ,Group Status Bit 989" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB987 ,Group Status Bit 987" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB986 ,Group Status Bit 986" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB984 ,Group Status Bit 984" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB983 ,Group Status Bit 983" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB981 ,Group Status Bit 981" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB980 ,Group Status Bit 980" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB978 ,Group Status Bit 978" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB977 ,Group Status Bit 977" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB975 ,Group Status Bit 975" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB974 ,Group Status Bit 974" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB972 ,Group Status Bit 972" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB971 ,Group Status Bit 971" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB969 ,Group Status Bit 969" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB968 ,Group Status Bit 968" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB966 ,Group Status Bit 966" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB965 ,Group Status Bit 965" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB963 ,Group Status Bit 963" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB962 ,Group Status Bit 962" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB960 ,Group Status Bit 960" "Group 0,Group 1"
else
hgroup.long 0x00F8++0x03
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
endif
tree.end
width 24.
tree "Set/Clear Enable Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0100++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0100++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31   ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB30   ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB29   ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28   ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB27   ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB26   ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25   ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB24   ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB23   ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22   ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB21   ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB20   ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19   ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB18   ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB17   ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16   ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB15   ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB14   ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13   ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB12   ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB11   ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10   ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB9    ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB8    ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7    ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB6    ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB5    ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4    ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB3    ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB2    ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1    ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB0    ,Set/Clear Enable Bit 0" "Disabled,Enabled"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63   ,Set/Clear Enable Bit 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB62   ,Set/Clear Enable Bit 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB61   ,Set/Clear Enable Bit 61" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60   ,Set/Clear Enable Bit 60" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB59   ,Set/Clear Enable Bit 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB58   ,Set/Clear Enable Bit 58" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57   ,Set/Clear Enable Bit 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB56   ,Set/Clear Enable Bit 56" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB55   ,Set/Clear Enable Bit 55" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54   ,Set/Clear Enable Bit 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB53   ,Set/Clear Enable Bit 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB52   ,Set/Clear Enable Bit 52" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51   ,Set/Clear Enable Bit 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB50   ,Set/Clear Enable Bit 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB49   ,Set/Clear Enable Bit 49" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48   ,Set/Clear Enable Bit 48" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB47   ,Set/Clear Enable Bit 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB46   ,Set/Clear Enable Bit 46" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45   ,Set/Clear Enable Bit 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB44   ,Set/Clear Enable Bit 44" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB43   ,Set/Clear Enable Bit 43" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42   ,Set/Clear Enable Bit 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB41   ,Set/Clear Enable Bit 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB40   ,Set/Clear Enable Bit 40" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39   ,Set/Clear Enable Bit 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB38   ,Set/Clear Enable Bit 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB37   ,Set/Clear Enable Bit 37" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36   ,Set/Clear Enable Bit 36" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB35   ,Set/Clear Enable Bit 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB34   ,Set/Clear Enable Bit 34" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33   ,Set/Clear Enable Bit 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB32   ,Set/Clear Enable Bit 32" "Disabled,Enabled"
else
hgroup.long 0x0104++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95   ,Set/Clear Enable Bit 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB94   ,Set/Clear Enable Bit 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB93   ,Set/Clear Enable Bit 93" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92   ,Set/Clear Enable Bit 92" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB91   ,Set/Clear Enable Bit 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB90   ,Set/Clear Enable Bit 90" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89   ,Set/Clear Enable Bit 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB88   ,Set/Clear Enable Bit 88" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB87   ,Set/Clear Enable Bit 87" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86   ,Set/Clear Enable Bit 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB85   ,Set/Clear Enable Bit 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB84   ,Set/Clear Enable Bit 84" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83   ,Set/Clear Enable Bit 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB82   ,Set/Clear Enable Bit 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB81   ,Set/Clear Enable Bit 81" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80   ,Set/Clear Enable Bit 80" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB79   ,Set/Clear Enable Bit 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB78   ,Set/Clear Enable Bit 78" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77   ,Set/Clear Enable Bit 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB76   ,Set/Clear Enable Bit 76" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB75   ,Set/Clear Enable Bit 75" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74   ,Set/Clear Enable Bit 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB73   ,Set/Clear Enable Bit 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB72   ,Set/Clear Enable Bit 72" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71   ,Set/Clear Enable Bit 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB70   ,Set/Clear Enable Bit 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB69   ,Set/Clear Enable Bit 69" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68   ,Set/Clear Enable Bit 68" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB67   ,Set/Clear Enable Bit 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB66   ,Set/Clear Enable Bit 66" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65   ,Set/Clear Enable Bit 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB64   ,Set/Clear Enable Bit 64" "Disabled,Enabled"
else
hgroup.long 0x0108++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127  ,Set/Clear Enable Bit 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB126  ,Set/Clear Enable Bit 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB125  ,Set/Clear Enable Bit 125" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124  ,Set/Clear Enable Bit 124" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB123  ,Set/Clear Enable Bit 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB122  ,Set/Clear Enable Bit 122" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121  ,Set/Clear Enable Bit 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB120  ,Set/Clear Enable Bit 120" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB119  ,Set/Clear Enable Bit 119" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118  ,Set/Clear Enable Bit 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB117  ,Set/Clear Enable Bit 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB116  ,Set/Clear Enable Bit 116" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115  ,Set/Clear Enable Bit 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB114  ,Set/Clear Enable Bit 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB113  ,Set/Clear Enable Bit 113" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112  ,Set/Clear Enable Bit 112" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB111  ,Set/Clear Enable Bit 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB110  ,Set/Clear Enable Bit 110" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109  ,Set/Clear Enable Bit 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB108  ,Set/Clear Enable Bit 108" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB107  ,Set/Clear Enable Bit 107" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106  ,Set/Clear Enable Bit 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB105  ,Set/Clear Enable Bit 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB104  ,Set/Clear Enable Bit 104" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103  ,Set/Clear Enable Bit 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB102  ,Set/Clear Enable Bit 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB101  ,Set/Clear Enable Bit 101" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100  ,Set/Clear Enable Bit 100" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB99   ,Set/Clear Enable Bit 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB98   ,Set/Clear Enable Bit 98" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97   ,Set/Clear Enable Bit 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB96   ,Set/Clear Enable Bit 96" "Disabled,Enabled"
else
hgroup.long 0x010C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159  ,Set/Clear Enable Bit 159" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB158  ,Set/Clear Enable Bit 158" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB157  ,Set/Clear Enable Bit 157" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156  ,Set/Clear Enable Bit 156" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB155  ,Set/Clear Enable Bit 155" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB154  ,Set/Clear Enable Bit 154" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153  ,Set/Clear Enable Bit 153" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB152  ,Set/Clear Enable Bit 152" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB151  ,Set/Clear Enable Bit 151" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150  ,Set/Clear Enable Bit 150" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB149  ,Set/Clear Enable Bit 149" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB148  ,Set/Clear Enable Bit 148" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147  ,Set/Clear Enable Bit 147" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB146  ,Set/Clear Enable Bit 146" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB145  ,Set/Clear Enable Bit 145" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144  ,Set/Clear Enable Bit 144" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB143  ,Set/Clear Enable Bit 143" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB142  ,Set/Clear Enable Bit 142" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141  ,Set/Clear Enable Bit 141" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB140  ,Set/Clear Enable Bit 140" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB139  ,Set/Clear Enable Bit 139" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138  ,Set/Clear Enable Bit 138" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB137  ,Set/Clear Enable Bit 137" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB136  ,Set/Clear Enable Bit 136" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135  ,Set/Clear Enable Bit 135" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB134  ,Set/Clear Enable Bit 134" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB133  ,Set/Clear Enable Bit 133" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132  ,Set/Clear Enable Bit 132" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB131  ,Set/Clear Enable Bit 131" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB130  ,Set/Clear Enable Bit 130" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129  ,Set/Clear Enable Bit 129" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB128  ,Set/Clear Enable Bit 128" "Disabled,Enabled"
else
hgroup.long 0x0110++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191  ,Set/Clear Enable Bit 191" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB190  ,Set/Clear Enable Bit 190" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB189  ,Set/Clear Enable Bit 189" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188  ,Set/Clear Enable Bit 188" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB187  ,Set/Clear Enable Bit 187" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB186  ,Set/Clear Enable Bit 186" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185  ,Set/Clear Enable Bit 185" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB184  ,Set/Clear Enable Bit 184" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB183  ,Set/Clear Enable Bit 183" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182  ,Set/Clear Enable Bit 182" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB181  ,Set/Clear Enable Bit 181" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB180  ,Set/Clear Enable Bit 180" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179  ,Set/Clear Enable Bit 179" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB178  ,Set/Clear Enable Bit 178" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB177  ,Set/Clear Enable Bit 177" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176  ,Set/Clear Enable Bit 176" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB175  ,Set/Clear Enable Bit 175" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB174  ,Set/Clear Enable Bit 174" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173  ,Set/Clear Enable Bit 173" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB172  ,Set/Clear Enable Bit 172" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB171  ,Set/Clear Enable Bit 171" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170  ,Set/Clear Enable Bit 170" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB169  ,Set/Clear Enable Bit 169" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB168  ,Set/Clear Enable Bit 168" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167  ,Set/Clear Enable Bit 167" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB166  ,Set/Clear Enable Bit 166" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB165  ,Set/Clear Enable Bit 165" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164  ,Set/Clear Enable Bit 164" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB163  ,Set/Clear Enable Bit 163" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB162  ,Set/Clear Enable Bit 162" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161  ,Set/Clear Enable Bit 161" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB160  ,Set/Clear Enable Bit 160" "Disabled,Enabled"
else
hgroup.long 0x0114++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223  ,Set/Clear Enable Bit 223" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB222  ,Set/Clear Enable Bit 222" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB221  ,Set/Clear Enable Bit 221" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220  ,Set/Clear Enable Bit 220" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB219  ,Set/Clear Enable Bit 219" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB218  ,Set/Clear Enable Bit 218" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217  ,Set/Clear Enable Bit 217" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB216  ,Set/Clear Enable Bit 216" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB215  ,Set/Clear Enable Bit 215" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214  ,Set/Clear Enable Bit 214" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB213  ,Set/Clear Enable Bit 213" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB212  ,Set/Clear Enable Bit 212" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211  ,Set/Clear Enable Bit 211" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB210  ,Set/Clear Enable Bit 210" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB209  ,Set/Clear Enable Bit 209" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208  ,Set/Clear Enable Bit 208" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB207  ,Set/Clear Enable Bit 207" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB206  ,Set/Clear Enable Bit 206" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205  ,Set/Clear Enable Bit 205" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB204  ,Set/Clear Enable Bit 204" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB203  ,Set/Clear Enable Bit 203" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202  ,Set/Clear Enable Bit 202" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB201  ,Set/Clear Enable Bit 201" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB200  ,Set/Clear Enable Bit 200" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199  ,Set/Clear Enable Bit 199" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB198  ,Set/Clear Enable Bit 198" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB197  ,Set/Clear Enable Bit 197" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196  ,Set/Clear Enable Bit 196" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB195  ,Set/Clear Enable Bit 195" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB194  ,Set/Clear Enable Bit 194" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193  ,Set/Clear Enable Bit 193" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB192  ,Set/Clear Enable Bit 192" "Disabled,Enabled"
else
hgroup.long 0x0118++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255  ,Set/Clear Enable Bit 255" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB254  ,Set/Clear Enable Bit 254" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB253  ,Set/Clear Enable Bit 253" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252  ,Set/Clear Enable Bit 252" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB251  ,Set/Clear Enable Bit 251" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB250  ,Set/Clear Enable Bit 250" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249  ,Set/Clear Enable Bit 249" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB248  ,Set/Clear Enable Bit 248" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB247  ,Set/Clear Enable Bit 247" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246  ,Set/Clear Enable Bit 246" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB245  ,Set/Clear Enable Bit 245" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB244  ,Set/Clear Enable Bit 244" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243  ,Set/Clear Enable Bit 243" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB242  ,Set/Clear Enable Bit 242" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB241  ,Set/Clear Enable Bit 241" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240  ,Set/Clear Enable Bit 240" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB239  ,Set/Clear Enable Bit 239" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB238  ,Set/Clear Enable Bit 238" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237  ,Set/Clear Enable Bit 237" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB236  ,Set/Clear Enable Bit 236" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB235  ,Set/Clear Enable Bit 235" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234  ,Set/Clear Enable Bit 234" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB233  ,Set/Clear Enable Bit 233" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB232  ,Set/Clear Enable Bit 232" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231  ,Set/Clear Enable Bit 231" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB230  ,Set/Clear Enable Bit 230" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB229  ,Set/Clear Enable Bit 229" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228  ,Set/Clear Enable Bit 228" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB227  ,Set/Clear Enable Bit 227" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB226  ,Set/Clear Enable Bit 226" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225  ,Set/Clear Enable Bit 225" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB224  ,Set/Clear Enable Bit 224" "Disabled,Enabled"
else
hgroup.long 0x011C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287  ,Set/Clear Enable Bit 287" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB286  ,Set/Clear Enable Bit 286" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB285  ,Set/Clear Enable Bit 285" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284  ,Set/Clear Enable Bit 284" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB283  ,Set/Clear Enable Bit 283" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB282  ,Set/Clear Enable Bit 282" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281  ,Set/Clear Enable Bit 281" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB280  ,Set/Clear Enable Bit 280" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB279  ,Set/Clear Enable Bit 279" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278  ,Set/Clear Enable Bit 278" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB277  ,Set/Clear Enable Bit 277" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB276  ,Set/Clear Enable Bit 276" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275  ,Set/Clear Enable Bit 275" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB274  ,Set/Clear Enable Bit 274" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB273  ,Set/Clear Enable Bit 273" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272  ,Set/Clear Enable Bit 272" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB271  ,Set/Clear Enable Bit 271" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB270  ,Set/Clear Enable Bit 270" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269  ,Set/Clear Enable Bit 269" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB268  ,Set/Clear Enable Bit 268" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB267  ,Set/Clear Enable Bit 267" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266  ,Set/Clear Enable Bit 266" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB265  ,Set/Clear Enable Bit 265" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB264  ,Set/Clear Enable Bit 264" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263  ,Set/Clear Enable Bit 263" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB262  ,Set/Clear Enable Bit 262" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB261  ,Set/Clear Enable Bit 261" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260  ,Set/Clear Enable Bit 260" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB259  ,Set/Clear Enable Bit 259" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB258  ,Set/Clear Enable Bit 258" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257  ,Set/Clear Enable Bit 257" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB256  ,Set/Clear Enable Bit 256" "Disabled,Enabled"
else
hgroup.long 0x0120++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319  ,Set/Clear Enable Bit 319" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB318  ,Set/Clear Enable Bit 318" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB317  ,Set/Clear Enable Bit 317" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316  ,Set/Clear Enable Bit 316" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB315  ,Set/Clear Enable Bit 315" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB314  ,Set/Clear Enable Bit 314" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313  ,Set/Clear Enable Bit 313" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB312  ,Set/Clear Enable Bit 312" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB311  ,Set/Clear Enable Bit 311" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310  ,Set/Clear Enable Bit 310" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB309  ,Set/Clear Enable Bit 309" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB308  ,Set/Clear Enable Bit 308" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307  ,Set/Clear Enable Bit 307" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB306  ,Set/Clear Enable Bit 306" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB305  ,Set/Clear Enable Bit 305" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304  ,Set/Clear Enable Bit 304" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB303  ,Set/Clear Enable Bit 303" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB302  ,Set/Clear Enable Bit 302" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301  ,Set/Clear Enable Bit 301" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB300  ,Set/Clear Enable Bit 300" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB299  ,Set/Clear Enable Bit 299" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298  ,Set/Clear Enable Bit 298" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB297  ,Set/Clear Enable Bit 297" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB296  ,Set/Clear Enable Bit 296" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295  ,Set/Clear Enable Bit 295" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB294  ,Set/Clear Enable Bit 294" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB293  ,Set/Clear Enable Bit 293" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292  ,Set/Clear Enable Bit 292" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB291  ,Set/Clear Enable Bit 291" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB290  ,Set/Clear Enable Bit 290" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289  ,Set/Clear Enable Bit 289" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB288  ,Set/Clear Enable Bit 288" "Disabled,Enabled"
else
hgroup.long 0x0124++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351  ,Set/Clear Enable Bit 351" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB350  ,Set/Clear Enable Bit 350" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB349  ,Set/Clear Enable Bit 349" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348  ,Set/Clear Enable Bit 348" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB347  ,Set/Clear Enable Bit 347" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB346  ,Set/Clear Enable Bit 346" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345  ,Set/Clear Enable Bit 345" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB344  ,Set/Clear Enable Bit 344" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB343  ,Set/Clear Enable Bit 343" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342  ,Set/Clear Enable Bit 342" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB341  ,Set/Clear Enable Bit 341" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB340  ,Set/Clear Enable Bit 340" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339  ,Set/Clear Enable Bit 339" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB338  ,Set/Clear Enable Bit 338" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB337  ,Set/Clear Enable Bit 337" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336  ,Set/Clear Enable Bit 336" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB335  ,Set/Clear Enable Bit 335" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB334  ,Set/Clear Enable Bit 334" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333  ,Set/Clear Enable Bit 333" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB332  ,Set/Clear Enable Bit 332" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB331  ,Set/Clear Enable Bit 331" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330  ,Set/Clear Enable Bit 330" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB329  ,Set/Clear Enable Bit 329" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB328  ,Set/Clear Enable Bit 328" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327  ,Set/Clear Enable Bit 327" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB326  ,Set/Clear Enable Bit 326" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB325  ,Set/Clear Enable Bit 325" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324  ,Set/Clear Enable Bit 324" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB323  ,Set/Clear Enable Bit 323" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB322  ,Set/Clear Enable Bit 322" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321  ,Set/Clear Enable Bit 321" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB320  ,Set/Clear Enable Bit 320" "Disabled,Enabled"
else
hgroup.long 0x0128++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383  ,Set/Clear Enable Bit 383" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB382  ,Set/Clear Enable Bit 382" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB381  ,Set/Clear Enable Bit 381" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380  ,Set/Clear Enable Bit 380" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB379  ,Set/Clear Enable Bit 379" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB378  ,Set/Clear Enable Bit 378" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377  ,Set/Clear Enable Bit 377" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB376  ,Set/Clear Enable Bit 376" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB375  ,Set/Clear Enable Bit 375" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374  ,Set/Clear Enable Bit 374" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB373  ,Set/Clear Enable Bit 373" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB372  ,Set/Clear Enable Bit 372" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371  ,Set/Clear Enable Bit 371" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB370  ,Set/Clear Enable Bit 370" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB369  ,Set/Clear Enable Bit 369" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368  ,Set/Clear Enable Bit 368" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB367  ,Set/Clear Enable Bit 367" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB366  ,Set/Clear Enable Bit 366" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365  ,Set/Clear Enable Bit 365" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB364  ,Set/Clear Enable Bit 364" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB363  ,Set/Clear Enable Bit 363" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362  ,Set/Clear Enable Bit 362" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB361  ,Set/Clear Enable Bit 361" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB360  ,Set/Clear Enable Bit 360" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359  ,Set/Clear Enable Bit 359" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB358  ,Set/Clear Enable Bit 358" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB357  ,Set/Clear Enable Bit 357" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356  ,Set/Clear Enable Bit 356" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB355  ,Set/Clear Enable Bit 355" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB354  ,Set/Clear Enable Bit 354" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353  ,Set/Clear Enable Bit 353" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB352  ,Set/Clear Enable Bit 352" "Disabled,Enabled"
else
hgroup.long 0x012C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415  ,Set/Clear Enable Bit 415" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB414  ,Set/Clear Enable Bit 414" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB413  ,Set/Clear Enable Bit 413" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412  ,Set/Clear Enable Bit 412" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB411  ,Set/Clear Enable Bit 411" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB410  ,Set/Clear Enable Bit 410" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409  ,Set/Clear Enable Bit 409" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB408  ,Set/Clear Enable Bit 408" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB407  ,Set/Clear Enable Bit 407" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406  ,Set/Clear Enable Bit 406" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB405  ,Set/Clear Enable Bit 405" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB404  ,Set/Clear Enable Bit 404" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403  ,Set/Clear Enable Bit 403" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB402  ,Set/Clear Enable Bit 402" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB401  ,Set/Clear Enable Bit 401" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400  ,Set/Clear Enable Bit 400" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB399  ,Set/Clear Enable Bit 399" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB398  ,Set/Clear Enable Bit 398" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397  ,Set/Clear Enable Bit 397" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB396  ,Set/Clear Enable Bit 396" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB395  ,Set/Clear Enable Bit 395" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394  ,Set/Clear Enable Bit 394" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB393  ,Set/Clear Enable Bit 393" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB392  ,Set/Clear Enable Bit 392" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391  ,Set/Clear Enable Bit 391" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB390  ,Set/Clear Enable Bit 390" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB389  ,Set/Clear Enable Bit 389" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388  ,Set/Clear Enable Bit 388" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB387  ,Set/Clear Enable Bit 387" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB386  ,Set/Clear Enable Bit 386" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385  ,Set/Clear Enable Bit 385" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB384  ,Set/Clear Enable Bit 384" "Disabled,Enabled"
else
hgroup.long 0x0130++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447  ,Set/Clear Enable Bit 447" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB446  ,Set/Clear Enable Bit 446" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB445  ,Set/Clear Enable Bit 445" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444  ,Set/Clear Enable Bit 444" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB443  ,Set/Clear Enable Bit 443" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB442  ,Set/Clear Enable Bit 442" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441  ,Set/Clear Enable Bit 441" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB440  ,Set/Clear Enable Bit 440" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB439  ,Set/Clear Enable Bit 439" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438  ,Set/Clear Enable Bit 438" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB437  ,Set/Clear Enable Bit 437" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB436  ,Set/Clear Enable Bit 436" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435  ,Set/Clear Enable Bit 435" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB434  ,Set/Clear Enable Bit 434" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB433  ,Set/Clear Enable Bit 433" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432  ,Set/Clear Enable Bit 432" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB431  ,Set/Clear Enable Bit 431" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB430  ,Set/Clear Enable Bit 430" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429  ,Set/Clear Enable Bit 429" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB428  ,Set/Clear Enable Bit 428" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB427  ,Set/Clear Enable Bit 427" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426  ,Set/Clear Enable Bit 426" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB425  ,Set/Clear Enable Bit 425" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB424  ,Set/Clear Enable Bit 424" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423  ,Set/Clear Enable Bit 423" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB422  ,Set/Clear Enable Bit 422" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB421  ,Set/Clear Enable Bit 421" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420  ,Set/Clear Enable Bit 420" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB419  ,Set/Clear Enable Bit 419" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB418  ,Set/Clear Enable Bit 418" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417  ,Set/Clear Enable Bit 417" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB416  ,Set/Clear Enable Bit 416" "Disabled,Enabled"
else
hgroup.long 0x0134++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479  ,Set/Clear Enable Bit 479" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB478  ,Set/Clear Enable Bit 478" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB477  ,Set/Clear Enable Bit 477" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476  ,Set/Clear Enable Bit 476" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB475  ,Set/Clear Enable Bit 475" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB474  ,Set/Clear Enable Bit 474" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473  ,Set/Clear Enable Bit 473" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB472  ,Set/Clear Enable Bit 472" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB471  ,Set/Clear Enable Bit 471" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470  ,Set/Clear Enable Bit 470" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB469  ,Set/Clear Enable Bit 469" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB468  ,Set/Clear Enable Bit 468" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467  ,Set/Clear Enable Bit 467" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB466  ,Set/Clear Enable Bit 466" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB465  ,Set/Clear Enable Bit 465" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464  ,Set/Clear Enable Bit 464" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB463  ,Set/Clear Enable Bit 463" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB462  ,Set/Clear Enable Bit 462" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461  ,Set/Clear Enable Bit 461" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB460  ,Set/Clear Enable Bit 460" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB459  ,Set/Clear Enable Bit 459" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458  ,Set/Clear Enable Bit 458" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB457  ,Set/Clear Enable Bit 457" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB456  ,Set/Clear Enable Bit 456" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455  ,Set/Clear Enable Bit 455" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB454  ,Set/Clear Enable Bit 454" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB453  ,Set/Clear Enable Bit 453" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452  ,Set/Clear Enable Bit 452" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB451  ,Set/Clear Enable Bit 451" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB450  ,Set/Clear Enable Bit 450" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449  ,Set/Clear Enable Bit 449" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB448  ,Set/Clear Enable Bit 448" "Disabled,Enabled"
else
hgroup.long 0x0138++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511  ,Set/Clear Enable Bit 511" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB510  ,Set/Clear Enable Bit 510" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB509  ,Set/Clear Enable Bit 509" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508  ,Set/Clear Enable Bit 508" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB507  ,Set/Clear Enable Bit 507" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB506  ,Set/Clear Enable Bit 506" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505  ,Set/Clear Enable Bit 505" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB504  ,Set/Clear Enable Bit 504" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB503  ,Set/Clear Enable Bit 503" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502  ,Set/Clear Enable Bit 502" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB501  ,Set/Clear Enable Bit 501" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB500  ,Set/Clear Enable Bit 500" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499  ,Set/Clear Enable Bit 499" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB498  ,Set/Clear Enable Bit 498" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB497  ,Set/Clear Enable Bit 497" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496  ,Set/Clear Enable Bit 496" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB495  ,Set/Clear Enable Bit 495" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB494  ,Set/Clear Enable Bit 494" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493  ,Set/Clear Enable Bit 493" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB492  ,Set/Clear Enable Bit 492" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB491  ,Set/Clear Enable Bit 491" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490  ,Set/Clear Enable Bit 490" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB489  ,Set/Clear Enable Bit 489" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB488  ,Set/Clear Enable Bit 488" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487  ,Set/Clear Enable Bit 487" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB486  ,Set/Clear Enable Bit 486" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB485  ,Set/Clear Enable Bit 485" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484  ,Set/Clear Enable Bit 484" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB483  ,Set/Clear Enable Bit 483" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB482  ,Set/Clear Enable Bit 482" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481  ,Set/Clear Enable Bit 481" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB480  ,Set/Clear Enable Bit 480" "Disabled,Enabled"
else
hgroup.long 0x013C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543  ,Set/Clear Enable Bit 543" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB542  ,Set/Clear Enable Bit 542" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB541  ,Set/Clear Enable Bit 541" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540  ,Set/Clear Enable Bit 540" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB539  ,Set/Clear Enable Bit 539" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB538  ,Set/Clear Enable Bit 538" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537  ,Set/Clear Enable Bit 537" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB536  ,Set/Clear Enable Bit 536" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB535  ,Set/Clear Enable Bit 535" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534  ,Set/Clear Enable Bit 534" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB533  ,Set/Clear Enable Bit 533" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB532  ,Set/Clear Enable Bit 532" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531  ,Set/Clear Enable Bit 531" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB530  ,Set/Clear Enable Bit 530" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB529  ,Set/Clear Enable Bit 529" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528  ,Set/Clear Enable Bit 528" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB527  ,Set/Clear Enable Bit 527" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB526  ,Set/Clear Enable Bit 526" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525  ,Set/Clear Enable Bit 525" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB524  ,Set/Clear Enable Bit 524" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB523  ,Set/Clear Enable Bit 523" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522  ,Set/Clear Enable Bit 522" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB521  ,Set/Clear Enable Bit 521" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB520  ,Set/Clear Enable Bit 520" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519  ,Set/Clear Enable Bit 519" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB518  ,Set/Clear Enable Bit 518" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB517  ,Set/Clear Enable Bit 517" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516  ,Set/Clear Enable Bit 516" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB515  ,Set/Clear Enable Bit 515" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB514  ,Set/Clear Enable Bit 514" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513  ,Set/Clear Enable Bit 513" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB512  ,Set/Clear Enable Bit 512" "Disabled,Enabled"
else
hgroup.long 0x0140++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575  ,Set/Clear Enable Bit 575" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB574  ,Set/Clear Enable Bit 574" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB573  ,Set/Clear Enable Bit 573" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572  ,Set/Clear Enable Bit 572" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB571  ,Set/Clear Enable Bit 571" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB570  ,Set/Clear Enable Bit 570" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569  ,Set/Clear Enable Bit 569" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB568  ,Set/Clear Enable Bit 568" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB567  ,Set/Clear Enable Bit 567" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566  ,Set/Clear Enable Bit 566" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB565  ,Set/Clear Enable Bit 565" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB564  ,Set/Clear Enable Bit 564" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563  ,Set/Clear Enable Bit 563" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB562  ,Set/Clear Enable Bit 562" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB561  ,Set/Clear Enable Bit 561" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560  ,Set/Clear Enable Bit 560" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB559  ,Set/Clear Enable Bit 559" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB558  ,Set/Clear Enable Bit 558" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557  ,Set/Clear Enable Bit 557" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB556  ,Set/Clear Enable Bit 556" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB555  ,Set/Clear Enable Bit 555" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554  ,Set/Clear Enable Bit 554" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB553  ,Set/Clear Enable Bit 553" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB552  ,Set/Clear Enable Bit 552" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551  ,Set/Clear Enable Bit 551" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB550  ,Set/Clear Enable Bit 550" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB549  ,Set/Clear Enable Bit 549" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548  ,Set/Clear Enable Bit 548" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB547  ,Set/Clear Enable Bit 547" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB546  ,Set/Clear Enable Bit 546" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545  ,Set/Clear Enable Bit 545" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB544  ,Set/Clear Enable Bit 544" "Disabled,Enabled"
else
hgroup.long 0x0144++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607  ,Set/Clear Enable Bit 607" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB606  ,Set/Clear Enable Bit 606" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB605  ,Set/Clear Enable Bit 605" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604  ,Set/Clear Enable Bit 604" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB603  ,Set/Clear Enable Bit 603" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB602  ,Set/Clear Enable Bit 602" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601  ,Set/Clear Enable Bit 601" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB600  ,Set/Clear Enable Bit 600" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB599  ,Set/Clear Enable Bit 599" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598  ,Set/Clear Enable Bit 598" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB597  ,Set/Clear Enable Bit 597" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB596  ,Set/Clear Enable Bit 596" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595  ,Set/Clear Enable Bit 595" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB594  ,Set/Clear Enable Bit 594" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB593  ,Set/Clear Enable Bit 593" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592  ,Set/Clear Enable Bit 592" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB591  ,Set/Clear Enable Bit 591" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB590  ,Set/Clear Enable Bit 590" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589  ,Set/Clear Enable Bit 589" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB588  ,Set/Clear Enable Bit 588" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB587  ,Set/Clear Enable Bit 587" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586  ,Set/Clear Enable Bit 586" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB585  ,Set/Clear Enable Bit 585" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB584  ,Set/Clear Enable Bit 584" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583  ,Set/Clear Enable Bit 583" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB582  ,Set/Clear Enable Bit 582" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB581  ,Set/Clear Enable Bit 581" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580  ,Set/Clear Enable Bit 580" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB579  ,Set/Clear Enable Bit 579" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB578  ,Set/Clear Enable Bit 578" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577  ,Set/Clear Enable Bit 577" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB576  ,Set/Clear Enable Bit 576" "Disabled,Enabled"
else
hgroup.long 0x0148++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639  ,Set/Clear Enable Bit 639" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB638  ,Set/Clear Enable Bit 638" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB637  ,Set/Clear Enable Bit 637" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636  ,Set/Clear Enable Bit 636" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB635  ,Set/Clear Enable Bit 635" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB634  ,Set/Clear Enable Bit 634" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633  ,Set/Clear Enable Bit 633" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB632  ,Set/Clear Enable Bit 632" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB631  ,Set/Clear Enable Bit 631" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630  ,Set/Clear Enable Bit 630" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB629  ,Set/Clear Enable Bit 629" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB628  ,Set/Clear Enable Bit 628" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627  ,Set/Clear Enable Bit 627" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB626  ,Set/Clear Enable Bit 626" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB625  ,Set/Clear Enable Bit 625" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624  ,Set/Clear Enable Bit 624" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB623  ,Set/Clear Enable Bit 623" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB622  ,Set/Clear Enable Bit 622" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621  ,Set/Clear Enable Bit 621" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB620  ,Set/Clear Enable Bit 620" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB619  ,Set/Clear Enable Bit 619" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618  ,Set/Clear Enable Bit 618" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB617  ,Set/Clear Enable Bit 617" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB616  ,Set/Clear Enable Bit 616" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615  ,Set/Clear Enable Bit 615" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB614  ,Set/Clear Enable Bit 614" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB613  ,Set/Clear Enable Bit 613" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612  ,Set/Clear Enable Bit 612" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB611  ,Set/Clear Enable Bit 611" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB610  ,Set/Clear Enable Bit 610" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609  ,Set/Clear Enable Bit 609" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB608  ,Set/Clear Enable Bit 608" "Disabled,Enabled"
else
hgroup.long 0x014C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671  ,Set/Clear Enable Bit 671" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB670  ,Set/Clear Enable Bit 670" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB669  ,Set/Clear Enable Bit 669" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668  ,Set/Clear Enable Bit 668" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB667  ,Set/Clear Enable Bit 667" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB666  ,Set/Clear Enable Bit 666" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665  ,Set/Clear Enable Bit 665" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB664  ,Set/Clear Enable Bit 664" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB663  ,Set/Clear Enable Bit 663" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662  ,Set/Clear Enable Bit 662" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB661  ,Set/Clear Enable Bit 661" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB660  ,Set/Clear Enable Bit 660" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659  ,Set/Clear Enable Bit 659" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB658  ,Set/Clear Enable Bit 658" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB657  ,Set/Clear Enable Bit 657" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656  ,Set/Clear Enable Bit 656" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB655  ,Set/Clear Enable Bit 655" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB654  ,Set/Clear Enable Bit 654" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653  ,Set/Clear Enable Bit 653" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB652  ,Set/Clear Enable Bit 652" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB651  ,Set/Clear Enable Bit 651" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650  ,Set/Clear Enable Bit 650" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB649  ,Set/Clear Enable Bit 649" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB648  ,Set/Clear Enable Bit 648" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647  ,Set/Clear Enable Bit 647" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB646  ,Set/Clear Enable Bit 646" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB645  ,Set/Clear Enable Bit 645" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644  ,Set/Clear Enable Bit 644" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB643  ,Set/Clear Enable Bit 643" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB642  ,Set/Clear Enable Bit 642" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641  ,Set/Clear Enable Bit 641" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB640  ,Set/Clear Enable Bit 640" "Disabled,Enabled"
else
hgroup.long 0x0150++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703  ,Set/Clear Enable Bit 703" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB702  ,Set/Clear Enable Bit 702" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB701  ,Set/Clear Enable Bit 701" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700  ,Set/Clear Enable Bit 700" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB699  ,Set/Clear Enable Bit 699" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB698  ,Set/Clear Enable Bit 698" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697  ,Set/Clear Enable Bit 697" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB696  ,Set/Clear Enable Bit 696" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB695  ,Set/Clear Enable Bit 695" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694  ,Set/Clear Enable Bit 694" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB693  ,Set/Clear Enable Bit 693" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB692  ,Set/Clear Enable Bit 692" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691  ,Set/Clear Enable Bit 691" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB690  ,Set/Clear Enable Bit 690" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB689  ,Set/Clear Enable Bit 689" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688  ,Set/Clear Enable Bit 688" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB687  ,Set/Clear Enable Bit 687" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB686  ,Set/Clear Enable Bit 686" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685  ,Set/Clear Enable Bit 685" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB684  ,Set/Clear Enable Bit 684" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB683  ,Set/Clear Enable Bit 683" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682  ,Set/Clear Enable Bit 682" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB681  ,Set/Clear Enable Bit 681" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB680  ,Set/Clear Enable Bit 680" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679  ,Set/Clear Enable Bit 679" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB678  ,Set/Clear Enable Bit 678" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB677  ,Set/Clear Enable Bit 677" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676  ,Set/Clear Enable Bit 676" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB675  ,Set/Clear Enable Bit 675" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB674  ,Set/Clear Enable Bit 674" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673  ,Set/Clear Enable Bit 673" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB672  ,Set/Clear Enable Bit 672" "Disabled,Enabled"
else
hgroup.long 0x0154++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735  ,Set/Clear Enable Bit 735" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB734  ,Set/Clear Enable Bit 734" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB733  ,Set/Clear Enable Bit 733" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732  ,Set/Clear Enable Bit 732" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB731  ,Set/Clear Enable Bit 731" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB730  ,Set/Clear Enable Bit 730" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729  ,Set/Clear Enable Bit 729" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB728  ,Set/Clear Enable Bit 728" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB727  ,Set/Clear Enable Bit 727" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726  ,Set/Clear Enable Bit 726" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB725  ,Set/Clear Enable Bit 725" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB724  ,Set/Clear Enable Bit 724" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723  ,Set/Clear Enable Bit 723" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB722  ,Set/Clear Enable Bit 722" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB721  ,Set/Clear Enable Bit 721" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720  ,Set/Clear Enable Bit 720" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB719  ,Set/Clear Enable Bit 719" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB718  ,Set/Clear Enable Bit 718" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717  ,Set/Clear Enable Bit 717" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB716  ,Set/Clear Enable Bit 716" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB715  ,Set/Clear Enable Bit 715" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714  ,Set/Clear Enable Bit 714" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB713  ,Set/Clear Enable Bit 713" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB712  ,Set/Clear Enable Bit 712" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711  ,Set/Clear Enable Bit 711" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB710  ,Set/Clear Enable Bit 710" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB709  ,Set/Clear Enable Bit 709" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708  ,Set/Clear Enable Bit 708" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB707  ,Set/Clear Enable Bit 707" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB706  ,Set/Clear Enable Bit 706" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705  ,Set/Clear Enable Bit 705" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB704  ,Set/Clear Enable Bit 704" "Disabled,Enabled"
else
hgroup.long 0x0158++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767  ,Set/Clear Enable Bit 767" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB766  ,Set/Clear Enable Bit 766" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB765  ,Set/Clear Enable Bit 765" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764  ,Set/Clear Enable Bit 764" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB763  ,Set/Clear Enable Bit 763" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB762  ,Set/Clear Enable Bit 762" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761  ,Set/Clear Enable Bit 761" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB760  ,Set/Clear Enable Bit 760" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB759  ,Set/Clear Enable Bit 759" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758  ,Set/Clear Enable Bit 758" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB757  ,Set/Clear Enable Bit 757" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB756  ,Set/Clear Enable Bit 756" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755  ,Set/Clear Enable Bit 755" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB754  ,Set/Clear Enable Bit 754" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB753  ,Set/Clear Enable Bit 753" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752  ,Set/Clear Enable Bit 752" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB751  ,Set/Clear Enable Bit 751" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB750  ,Set/Clear Enable Bit 750" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749  ,Set/Clear Enable Bit 749" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB748  ,Set/Clear Enable Bit 748" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB747  ,Set/Clear Enable Bit 747" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746  ,Set/Clear Enable Bit 746" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB745  ,Set/Clear Enable Bit 745" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB744  ,Set/Clear Enable Bit 744" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743  ,Set/Clear Enable Bit 743" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB742  ,Set/Clear Enable Bit 742" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB741  ,Set/Clear Enable Bit 741" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740  ,Set/Clear Enable Bit 740" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB739  ,Set/Clear Enable Bit 739" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB738  ,Set/Clear Enable Bit 738" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737  ,Set/Clear Enable Bit 737" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB736  ,Set/Clear Enable Bit 736" "Disabled,Enabled"
else
hgroup.long 0x015C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799  ,Set/Clear Enable Bit 799" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB798  ,Set/Clear Enable Bit 798" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB797  ,Set/Clear Enable Bit 797" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796  ,Set/Clear Enable Bit 796" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB795  ,Set/Clear Enable Bit 795" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB794  ,Set/Clear Enable Bit 794" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793  ,Set/Clear Enable Bit 793" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB792  ,Set/Clear Enable Bit 792" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB791  ,Set/Clear Enable Bit 791" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790  ,Set/Clear Enable Bit 790" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB789  ,Set/Clear Enable Bit 789" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB788  ,Set/Clear Enable Bit 788" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787  ,Set/Clear Enable Bit 787" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB786  ,Set/Clear Enable Bit 786" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB785  ,Set/Clear Enable Bit 785" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784  ,Set/Clear Enable Bit 784" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB783  ,Set/Clear Enable Bit 783" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB782  ,Set/Clear Enable Bit 782" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781  ,Set/Clear Enable Bit 781" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB780  ,Set/Clear Enable Bit 780" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB779  ,Set/Clear Enable Bit 779" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778  ,Set/Clear Enable Bit 778" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB777  ,Set/Clear Enable Bit 777" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB776  ,Set/Clear Enable Bit 776" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775  ,Set/Clear Enable Bit 775" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB774  ,Set/Clear Enable Bit 774" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB773  ,Set/Clear Enable Bit 773" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772  ,Set/Clear Enable Bit 772" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB771  ,Set/Clear Enable Bit 771" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB770  ,Set/Clear Enable Bit 770" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769  ,Set/Clear Enable Bit 769" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB768  ,Set/Clear Enable Bit 768" "Disabled,Enabled"
else
hgroup.long 0x0160++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831  ,Set/Clear Enable Bit 831" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB830  ,Set/Clear Enable Bit 830" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB829  ,Set/Clear Enable Bit 829" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828  ,Set/Clear Enable Bit 828" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB827  ,Set/Clear Enable Bit 827" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB826  ,Set/Clear Enable Bit 826" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825  ,Set/Clear Enable Bit 825" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB824  ,Set/Clear Enable Bit 824" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB823  ,Set/Clear Enable Bit 823" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822  ,Set/Clear Enable Bit 822" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB821  ,Set/Clear Enable Bit 821" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB820  ,Set/Clear Enable Bit 820" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819  ,Set/Clear Enable Bit 819" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB818  ,Set/Clear Enable Bit 818" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB817  ,Set/Clear Enable Bit 817" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816  ,Set/Clear Enable Bit 816" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB815  ,Set/Clear Enable Bit 815" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB814  ,Set/Clear Enable Bit 814" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813  ,Set/Clear Enable Bit 813" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB812  ,Set/Clear Enable Bit 812" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB811  ,Set/Clear Enable Bit 811" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810  ,Set/Clear Enable Bit 810" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB809  ,Set/Clear Enable Bit 809" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB808  ,Set/Clear Enable Bit 808" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807  ,Set/Clear Enable Bit 807" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB806  ,Set/Clear Enable Bit 806" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB805  ,Set/Clear Enable Bit 805" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804  ,Set/Clear Enable Bit 804" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB803  ,Set/Clear Enable Bit 803" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB802  ,Set/Clear Enable Bit 802" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801  ,Set/Clear Enable Bit 801" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB800  ,Set/Clear Enable Bit 800" "Disabled,Enabled"
else
hgroup.long 0x0164++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863  ,Set/Clear Enable Bit 863" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB862  ,Set/Clear Enable Bit 862" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB861  ,Set/Clear Enable Bit 861" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860  ,Set/Clear Enable Bit 860" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB859  ,Set/Clear Enable Bit 859" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB858  ,Set/Clear Enable Bit 858" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857  ,Set/Clear Enable Bit 857" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB856  ,Set/Clear Enable Bit 856" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB855  ,Set/Clear Enable Bit 855" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854  ,Set/Clear Enable Bit 854" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB853  ,Set/Clear Enable Bit 853" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB852  ,Set/Clear Enable Bit 852" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851  ,Set/Clear Enable Bit 851" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB850  ,Set/Clear Enable Bit 850" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB849  ,Set/Clear Enable Bit 849" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848  ,Set/Clear Enable Bit 848" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB847  ,Set/Clear Enable Bit 847" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB846  ,Set/Clear Enable Bit 846" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845  ,Set/Clear Enable Bit 845" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB844  ,Set/Clear Enable Bit 844" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB843  ,Set/Clear Enable Bit 843" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842  ,Set/Clear Enable Bit 842" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB841  ,Set/Clear Enable Bit 841" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB840  ,Set/Clear Enable Bit 840" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839  ,Set/Clear Enable Bit 839" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB838  ,Set/Clear Enable Bit 838" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB837  ,Set/Clear Enable Bit 837" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836  ,Set/Clear Enable Bit 836" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB835  ,Set/Clear Enable Bit 835" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB834  ,Set/Clear Enable Bit 834" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833  ,Set/Clear Enable Bit 833" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB832  ,Set/Clear Enable Bit 832" "Disabled,Enabled"
else
hgroup.long 0x0168++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895  ,Set/Clear Enable Bit 895" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB894  ,Set/Clear Enable Bit 894" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB893  ,Set/Clear Enable Bit 893" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892  ,Set/Clear Enable Bit 892" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB891  ,Set/Clear Enable Bit 891" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB890  ,Set/Clear Enable Bit 890" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889  ,Set/Clear Enable Bit 889" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB888  ,Set/Clear Enable Bit 888" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB887  ,Set/Clear Enable Bit 887" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886  ,Set/Clear Enable Bit 886" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB885  ,Set/Clear Enable Bit 885" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB884  ,Set/Clear Enable Bit 884" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883  ,Set/Clear Enable Bit 883" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB882  ,Set/Clear Enable Bit 882" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB881  ,Set/Clear Enable Bit 881" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880  ,Set/Clear Enable Bit 880" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB879  ,Set/Clear Enable Bit 879" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB878  ,Set/Clear Enable Bit 878" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877  ,Set/Clear Enable Bit 877" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB876  ,Set/Clear Enable Bit 876" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB875  ,Set/Clear Enable Bit 875" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874  ,Set/Clear Enable Bit 874" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB873  ,Set/Clear Enable Bit 873" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB872  ,Set/Clear Enable Bit 872" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871  ,Set/Clear Enable Bit 871" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB870  ,Set/Clear Enable Bit 870" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB869  ,Set/Clear Enable Bit 869" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868  ,Set/Clear Enable Bit 868" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB867  ,Set/Clear Enable Bit 867" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB866  ,Set/Clear Enable Bit 866" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865  ,Set/Clear Enable Bit 865" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB864  ,Set/Clear Enable Bit 864" "Disabled,Enabled"
else
hgroup.long 0x016C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927  ,Set/Clear Enable Bit 927" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB926  ,Set/Clear Enable Bit 926" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB925  ,Set/Clear Enable Bit 925" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924  ,Set/Clear Enable Bit 924" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB923  ,Set/Clear Enable Bit 923" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB922  ,Set/Clear Enable Bit 922" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921  ,Set/Clear Enable Bit 921" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB920  ,Set/Clear Enable Bit 920" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB919  ,Set/Clear Enable Bit 919" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918  ,Set/Clear Enable Bit 918" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB917  ,Set/Clear Enable Bit 917" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB916  ,Set/Clear Enable Bit 916" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915  ,Set/Clear Enable Bit 915" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB914  ,Set/Clear Enable Bit 914" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB913  ,Set/Clear Enable Bit 913" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912  ,Set/Clear Enable Bit 912" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB911  ,Set/Clear Enable Bit 911" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB910  ,Set/Clear Enable Bit 910" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909  ,Set/Clear Enable Bit 909" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB908  ,Set/Clear Enable Bit 908" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB907  ,Set/Clear Enable Bit 907" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906  ,Set/Clear Enable Bit 906" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB905  ,Set/Clear Enable Bit 905" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB904  ,Set/Clear Enable Bit 904" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903  ,Set/Clear Enable Bit 903" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB902  ,Set/Clear Enable Bit 902" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB901  ,Set/Clear Enable Bit 901" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900  ,Set/Clear Enable Bit 900" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB899  ,Set/Clear Enable Bit 899" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB898  ,Set/Clear Enable Bit 898" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897  ,Set/Clear Enable Bit 897" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB896  ,Set/Clear Enable Bit 896" "Disabled,Enabled"
else
hgroup.long 0x0170++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959  ,Set/Clear Enable Bit 959" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB958  ,Set/Clear Enable Bit 958" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB957  ,Set/Clear Enable Bit 957" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956  ,Set/Clear Enable Bit 956" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB955  ,Set/Clear Enable Bit 955" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB954  ,Set/Clear Enable Bit 954" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953  ,Set/Clear Enable Bit 953" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB952  ,Set/Clear Enable Bit 952" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB951  ,Set/Clear Enable Bit 951" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950  ,Set/Clear Enable Bit 950" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB949  ,Set/Clear Enable Bit 949" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB948  ,Set/Clear Enable Bit 948" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947  ,Set/Clear Enable Bit 947" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB946  ,Set/Clear Enable Bit 946" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB945  ,Set/Clear Enable Bit 945" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944  ,Set/Clear Enable Bit 944" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB943  ,Set/Clear Enable Bit 943" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB942  ,Set/Clear Enable Bit 942" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941  ,Set/Clear Enable Bit 941" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB940  ,Set/Clear Enable Bit 940" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB939  ,Set/Clear Enable Bit 939" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938  ,Set/Clear Enable Bit 938" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB937  ,Set/Clear Enable Bit 937" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB936  ,Set/Clear Enable Bit 936" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935  ,Set/Clear Enable Bit 935" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB934  ,Set/Clear Enable Bit 934" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB933  ,Set/Clear Enable Bit 933" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932  ,Set/Clear Enable Bit 932" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB931  ,Set/Clear Enable Bit 931" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB930  ,Set/Clear Enable Bit 930" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929  ,Set/Clear Enable Bit 929" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB928  ,Set/Clear Enable Bit 928" "Disabled,Enabled"
else
hgroup.long 0x0174++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991  ,Set/Clear Enable Bit 991" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB990  ,Set/Clear Enable Bit 990" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB989  ,Set/Clear Enable Bit 989" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988  ,Set/Clear Enable Bit 988" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB987  ,Set/Clear Enable Bit 987" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB986  ,Set/Clear Enable Bit 986" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985  ,Set/Clear Enable Bit 985" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB984  ,Set/Clear Enable Bit 984" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB983  ,Set/Clear Enable Bit 983" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982  ,Set/Clear Enable Bit 982" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB981  ,Set/Clear Enable Bit 981" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB980  ,Set/Clear Enable Bit 980" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979  ,Set/Clear Enable Bit 979" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB978  ,Set/Clear Enable Bit 978" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB977  ,Set/Clear Enable Bit 977" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976  ,Set/Clear Enable Bit 976" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB975  ,Set/Clear Enable Bit 975" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB974  ,Set/Clear Enable Bit 974" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973  ,Set/Clear Enable Bit 973" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB972  ,Set/Clear Enable Bit 972" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB971  ,Set/Clear Enable Bit 971" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970  ,Set/Clear Enable Bit 970" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB969  ,Set/Clear Enable Bit 969" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB968  ,Set/Clear Enable Bit 968" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967  ,Set/Clear Enable Bit 967" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB966  ,Set/Clear Enable Bit 966" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB965  ,Set/Clear Enable Bit 965" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964  ,Set/Clear Enable Bit 964" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB963  ,Set/Clear Enable Bit 963" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB962  ,Set/Clear Enable Bit 962" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961  ,Set/Clear Enable Bit 961" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB960  ,Set/Clear Enable Bit 960" "Disabled,Enabled"
else
hgroup.long 0x0178++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
endif
tree.end
width 22.
tree "Set/Clear Pending Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0200++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0200++0x03
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63   ,Set/Clear Pending Bit 63" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND62   ,Set/Clear Pending Bit 62" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND61   ,Set/Clear Pending Bit 61" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60   ,Set/Clear Pending Bit 60" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND59   ,Set/Clear Pending Bit 59" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND58   ,Set/Clear Pending Bit 58" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57   ,Set/Clear Pending Bit 57" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND56   ,Set/Clear Pending Bit 56" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND55   ,Set/Clear Pending Bit 55" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54   ,Set/Clear Pending Bit 54" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND53   ,Set/Clear Pending Bit 53" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND52   ,Set/Clear Pending Bit 52" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51   ,Set/Clear Pending Bit 51" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND50   ,Set/Clear Pending Bit 50" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND49   ,Set/Clear Pending Bit 49" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48   ,Set/Clear Pending Bit 48" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND47   ,Set/Clear Pending Bit 47" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND46   ,Set/Clear Pending Bit 46" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45   ,Set/Clear Pending Bit 45" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND44   ,Set/Clear Pending Bit 44" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND43   ,Set/Clear Pending Bit 43" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42   ,Set/Clear Pending Bit 42" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND41   ,Set/Clear Pending Bit 41" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND40   ,Set/Clear Pending Bit 40" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39   ,Set/Clear Pending Bit 39" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND38   ,Set/Clear Pending Bit 38" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND37   ,Set/Clear Pending Bit 37" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36   ,Set/Clear Pending Bit 36" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND35   ,Set/Clear Pending Bit 35" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND34   ,Set/Clear Pending Bit 34" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33   ,Set/Clear Pending Bit 33" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND32   ,Set/Clear Pending Bit 32" "Not pending,Pending"
else
hgroup.long 0x0204++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95   ,Set/Clear Pending Bit 95" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND94   ,Set/Clear Pending Bit 94" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND93   ,Set/Clear Pending Bit 93" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92   ,Set/Clear Pending Bit 92" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND91   ,Set/Clear Pending Bit 91" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND90   ,Set/Clear Pending Bit 90" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89   ,Set/Clear Pending Bit 89" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND88   ,Set/Clear Pending Bit 88" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND87   ,Set/Clear Pending Bit 87" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86   ,Set/Clear Pending Bit 86" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND85   ,Set/Clear Pending Bit 85" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND84   ,Set/Clear Pending Bit 84" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83   ,Set/Clear Pending Bit 83" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND82   ,Set/Clear Pending Bit 82" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND81   ,Set/Clear Pending Bit 81" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80   ,Set/Clear Pending Bit 80" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND79   ,Set/Clear Pending Bit 79" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND78   ,Set/Clear Pending Bit 78" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77   ,Set/Clear Pending Bit 77" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND76   ,Set/Clear Pending Bit 76" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND75   ,Set/Clear Pending Bit 75" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74   ,Set/Clear Pending Bit 74" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND73   ,Set/Clear Pending Bit 73" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND72   ,Set/Clear Pending Bit 72" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71   ,Set/Clear Pending Bit 71" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND70   ,Set/Clear Pending Bit 70" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND69   ,Set/Clear Pending Bit 69" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68   ,Set/Clear Pending Bit 68" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND67   ,Set/Clear Pending Bit 67" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND66   ,Set/Clear Pending Bit 66" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65   ,Set/Clear Pending Bit 65" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND64   ,Set/Clear Pending Bit 64" "Not pending,Pending"
else
hgroup.long 0x0208++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127  ,Set/Clear Pending Bit 127" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND126  ,Set/Clear Pending Bit 126" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND125  ,Set/Clear Pending Bit 125" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124  ,Set/Clear Pending Bit 124" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND123  ,Set/Clear Pending Bit 123" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND122  ,Set/Clear Pending Bit 122" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121  ,Set/Clear Pending Bit 121" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND120  ,Set/Clear Pending Bit 120" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND119  ,Set/Clear Pending Bit 119" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118  ,Set/Clear Pending Bit 118" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND117  ,Set/Clear Pending Bit 117" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND116  ,Set/Clear Pending Bit 116" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115  ,Set/Clear Pending Bit 115" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND114  ,Set/Clear Pending Bit 114" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND113  ,Set/Clear Pending Bit 113" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112  ,Set/Clear Pending Bit 112" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND111  ,Set/Clear Pending Bit 111" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND110  ,Set/Clear Pending Bit 110" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109  ,Set/Clear Pending Bit 109" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND108  ,Set/Clear Pending Bit 108" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND107  ,Set/Clear Pending Bit 107" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106  ,Set/Clear Pending Bit 106" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND105  ,Set/Clear Pending Bit 105" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND104  ,Set/Clear Pending Bit 104" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103  ,Set/Clear Pending Bit 103" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND102  ,Set/Clear Pending Bit 102" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND101  ,Set/Clear Pending Bit 101" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100  ,Set/Clear Pending Bit 100" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND99   ,Set/Clear Pending Bit 99" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND98   ,Set/Clear Pending Bit 98" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97   ,Set/Clear Pending Bit 97" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND96   ,Set/Clear Pending Bit 96" "Not pending,Pending"
else
hgroup.long 0x020C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159  ,Set/Clear Pending Bit 159" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND158  ,Set/Clear Pending Bit 158" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND157  ,Set/Clear Pending Bit 157" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156  ,Set/Clear Pending Bit 156" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND155  ,Set/Clear Pending Bit 155" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND154  ,Set/Clear Pending Bit 154" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153  ,Set/Clear Pending Bit 153" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND152  ,Set/Clear Pending Bit 152" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND151  ,Set/Clear Pending Bit 151" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150  ,Set/Clear Pending Bit 150" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND149  ,Set/Clear Pending Bit 149" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND148  ,Set/Clear Pending Bit 148" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147  ,Set/Clear Pending Bit 147" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND146  ,Set/Clear Pending Bit 146" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND145  ,Set/Clear Pending Bit 145" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144  ,Set/Clear Pending Bit 144" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND143  ,Set/Clear Pending Bit 143" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND142  ,Set/Clear Pending Bit 142" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141  ,Set/Clear Pending Bit 141" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND140  ,Set/Clear Pending Bit 140" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND139  ,Set/Clear Pending Bit 139" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138  ,Set/Clear Pending Bit 138" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND137  ,Set/Clear Pending Bit 137" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND136  ,Set/Clear Pending Bit 136" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135  ,Set/Clear Pending Bit 135" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND134  ,Set/Clear Pending Bit 134" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND133  ,Set/Clear Pending Bit 133" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132  ,Set/Clear Pending Bit 132" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND131  ,Set/Clear Pending Bit 131" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND130  ,Set/Clear Pending Bit 130" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129  ,Set/Clear Pending Bit 129" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND128  ,Set/Clear Pending Bit 128" "Not pending,Pending"
else
hgroup.long 0x0210++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191  ,Set/Clear Pending Bit 191" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND190  ,Set/Clear Pending Bit 190" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND189  ,Set/Clear Pending Bit 189" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188  ,Set/Clear Pending Bit 188" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND187  ,Set/Clear Pending Bit 187" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND186  ,Set/Clear Pending Bit 186" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185  ,Set/Clear Pending Bit 185" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND184  ,Set/Clear Pending Bit 184" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND183  ,Set/Clear Pending Bit 183" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182  ,Set/Clear Pending Bit 182" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND181  ,Set/Clear Pending Bit 181" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND180  ,Set/Clear Pending Bit 180" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179  ,Set/Clear Pending Bit 179" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND178  ,Set/Clear Pending Bit 178" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND177  ,Set/Clear Pending Bit 177" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176  ,Set/Clear Pending Bit 176" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND175  ,Set/Clear Pending Bit 175" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND174  ,Set/Clear Pending Bit 174" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173  ,Set/Clear Pending Bit 173" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND172  ,Set/Clear Pending Bit 172" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND171  ,Set/Clear Pending Bit 171" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170  ,Set/Clear Pending Bit 170" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND169  ,Set/Clear Pending Bit 169" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND168  ,Set/Clear Pending Bit 168" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167  ,Set/Clear Pending Bit 167" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND166  ,Set/Clear Pending Bit 166" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND165  ,Set/Clear Pending Bit 165" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164  ,Set/Clear Pending Bit 164" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND163  ,Set/Clear Pending Bit 163" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND162  ,Set/Clear Pending Bit 162" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161  ,Set/Clear Pending Bit 161" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND160  ,Set/Clear Pending Bit 160" "Not pending,Pending"
else
hgroup.long 0x0214++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223  ,Set/Clear Pending Bit 223" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND222  ,Set/Clear Pending Bit 222" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND221  ,Set/Clear Pending Bit 221" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220  ,Set/Clear Pending Bit 220" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND219  ,Set/Clear Pending Bit 219" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND218  ,Set/Clear Pending Bit 218" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217  ,Set/Clear Pending Bit 217" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND216  ,Set/Clear Pending Bit 216" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND215  ,Set/Clear Pending Bit 215" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214  ,Set/Clear Pending Bit 214" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND213  ,Set/Clear Pending Bit 213" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND212  ,Set/Clear Pending Bit 212" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211  ,Set/Clear Pending Bit 211" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND210  ,Set/Clear Pending Bit 210" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND209  ,Set/Clear Pending Bit 209" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208  ,Set/Clear Pending Bit 208" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND207  ,Set/Clear Pending Bit 207" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND206  ,Set/Clear Pending Bit 206" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205  ,Set/Clear Pending Bit 205" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND204  ,Set/Clear Pending Bit 204" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND203  ,Set/Clear Pending Bit 203" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202  ,Set/Clear Pending Bit 202" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND201  ,Set/Clear Pending Bit 201" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND200  ,Set/Clear Pending Bit 200" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199  ,Set/Clear Pending Bit 199" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND198  ,Set/Clear Pending Bit 198" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND197  ,Set/Clear Pending Bit 197" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196  ,Set/Clear Pending Bit 196" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND195  ,Set/Clear Pending Bit 195" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND194  ,Set/Clear Pending Bit 194" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193  ,Set/Clear Pending Bit 193" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND192  ,Set/Clear Pending Bit 192" "Not pending,Pending"
else
hgroup.long 0x0218++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255  ,Set/Clear Pending Bit 255" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND254  ,Set/Clear Pending Bit 254" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND253  ,Set/Clear Pending Bit 253" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252  ,Set/Clear Pending Bit 252" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND251  ,Set/Clear Pending Bit 251" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND250  ,Set/Clear Pending Bit 250" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249  ,Set/Clear Pending Bit 249" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND248  ,Set/Clear Pending Bit 248" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND247  ,Set/Clear Pending Bit 247" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246  ,Set/Clear Pending Bit 246" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND245  ,Set/Clear Pending Bit 245" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND244  ,Set/Clear Pending Bit 244" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243  ,Set/Clear Pending Bit 243" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND242  ,Set/Clear Pending Bit 242" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND241  ,Set/Clear Pending Bit 241" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240  ,Set/Clear Pending Bit 240" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND239  ,Set/Clear Pending Bit 239" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND238  ,Set/Clear Pending Bit 238" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237  ,Set/Clear Pending Bit 237" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND236  ,Set/Clear Pending Bit 236" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND235  ,Set/Clear Pending Bit 235" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234  ,Set/Clear Pending Bit 234" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND233  ,Set/Clear Pending Bit 233" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND232  ,Set/Clear Pending Bit 232" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231  ,Set/Clear Pending Bit 231" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND230  ,Set/Clear Pending Bit 230" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND229  ,Set/Clear Pending Bit 229" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228  ,Set/Clear Pending Bit 228" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND227  ,Set/Clear Pending Bit 227" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND226  ,Set/Clear Pending Bit 226" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225  ,Set/Clear Pending Bit 225" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND224  ,Set/Clear Pending Bit 224" "Not pending,Pending"
else
hgroup.long 0x021C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287  ,Set/Clear Pending Bit 287" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND286  ,Set/Clear Pending Bit 286" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND285  ,Set/Clear Pending Bit 285" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284  ,Set/Clear Pending Bit 284" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND283  ,Set/Clear Pending Bit 283" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND282  ,Set/Clear Pending Bit 282" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281  ,Set/Clear Pending Bit 281" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND280  ,Set/Clear Pending Bit 280" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND279  ,Set/Clear Pending Bit 279" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278  ,Set/Clear Pending Bit 278" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND277  ,Set/Clear Pending Bit 277" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND276  ,Set/Clear Pending Bit 276" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275  ,Set/Clear Pending Bit 275" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND274  ,Set/Clear Pending Bit 274" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND273  ,Set/Clear Pending Bit 273" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272  ,Set/Clear Pending Bit 272" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND271  ,Set/Clear Pending Bit 271" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND270  ,Set/Clear Pending Bit 270" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269  ,Set/Clear Pending Bit 269" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND268  ,Set/Clear Pending Bit 268" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND267  ,Set/Clear Pending Bit 267" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266  ,Set/Clear Pending Bit 266" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND265  ,Set/Clear Pending Bit 265" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND264  ,Set/Clear Pending Bit 264" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263  ,Set/Clear Pending Bit 263" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND262  ,Set/Clear Pending Bit 262" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND261  ,Set/Clear Pending Bit 261" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260  ,Set/Clear Pending Bit 260" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND259  ,Set/Clear Pending Bit 259" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND258  ,Set/Clear Pending Bit 258" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257  ,Set/Clear Pending Bit 257" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND256  ,Set/Clear Pending Bit 256" "Not pending,Pending"
else
hgroup.long 0x0220++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319  ,Set/Clear Pending Bit 319" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND318  ,Set/Clear Pending Bit 318" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND317  ,Set/Clear Pending Bit 317" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316  ,Set/Clear Pending Bit 316" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND315  ,Set/Clear Pending Bit 315" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND314  ,Set/Clear Pending Bit 314" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313  ,Set/Clear Pending Bit 313" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND312  ,Set/Clear Pending Bit 312" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND311  ,Set/Clear Pending Bit 311" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310  ,Set/Clear Pending Bit 310" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND309  ,Set/Clear Pending Bit 309" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND308  ,Set/Clear Pending Bit 308" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307  ,Set/Clear Pending Bit 307" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND306  ,Set/Clear Pending Bit 306" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND305  ,Set/Clear Pending Bit 305" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304  ,Set/Clear Pending Bit 304" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND303  ,Set/Clear Pending Bit 303" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND302  ,Set/Clear Pending Bit 302" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301  ,Set/Clear Pending Bit 301" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND300  ,Set/Clear Pending Bit 300" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND299  ,Set/Clear Pending Bit 299" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298  ,Set/Clear Pending Bit 298" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND297  ,Set/Clear Pending Bit 297" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND296  ,Set/Clear Pending Bit 296" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295  ,Set/Clear Pending Bit 295" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND294  ,Set/Clear Pending Bit 294" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND293  ,Set/Clear Pending Bit 293" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292  ,Set/Clear Pending Bit 292" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND291  ,Set/Clear Pending Bit 291" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND290  ,Set/Clear Pending Bit 290" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289  ,Set/Clear Pending Bit 289" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND288  ,Set/Clear Pending Bit 288" "Not pending,Pending"
else
hgroup.long 0x0224++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351  ,Set/Clear Pending Bit 351" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND350  ,Set/Clear Pending Bit 350" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND349  ,Set/Clear Pending Bit 349" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348  ,Set/Clear Pending Bit 348" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND347  ,Set/Clear Pending Bit 347" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND346  ,Set/Clear Pending Bit 346" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345  ,Set/Clear Pending Bit 345" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND344  ,Set/Clear Pending Bit 344" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND343  ,Set/Clear Pending Bit 343" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342  ,Set/Clear Pending Bit 342" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND341  ,Set/Clear Pending Bit 341" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND340  ,Set/Clear Pending Bit 340" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339  ,Set/Clear Pending Bit 339" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND338  ,Set/Clear Pending Bit 338" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND337  ,Set/Clear Pending Bit 337" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336  ,Set/Clear Pending Bit 336" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND335  ,Set/Clear Pending Bit 335" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND334  ,Set/Clear Pending Bit 334" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333  ,Set/Clear Pending Bit 333" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND332  ,Set/Clear Pending Bit 332" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND331  ,Set/Clear Pending Bit 331" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330  ,Set/Clear Pending Bit 330" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND329  ,Set/Clear Pending Bit 329" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND328  ,Set/Clear Pending Bit 328" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327  ,Set/Clear Pending Bit 327" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND326  ,Set/Clear Pending Bit 326" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND325  ,Set/Clear Pending Bit 325" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324  ,Set/Clear Pending Bit 324" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND323  ,Set/Clear Pending Bit 323" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND322  ,Set/Clear Pending Bit 322" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321  ,Set/Clear Pending Bit 321" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND320  ,Set/Clear Pending Bit 320" "Not pending,Pending"
else
hgroup.long 0x0228++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383  ,Set/Clear Pending Bit 383" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND382  ,Set/Clear Pending Bit 382" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND381  ,Set/Clear Pending Bit 381" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380  ,Set/Clear Pending Bit 380" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND379  ,Set/Clear Pending Bit 379" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND378  ,Set/Clear Pending Bit 378" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377  ,Set/Clear Pending Bit 377" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND376  ,Set/Clear Pending Bit 376" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND375  ,Set/Clear Pending Bit 375" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374  ,Set/Clear Pending Bit 374" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND373  ,Set/Clear Pending Bit 373" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND372  ,Set/Clear Pending Bit 372" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371  ,Set/Clear Pending Bit 371" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND370  ,Set/Clear Pending Bit 370" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND369  ,Set/Clear Pending Bit 369" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368  ,Set/Clear Pending Bit 368" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND367  ,Set/Clear Pending Bit 367" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND366  ,Set/Clear Pending Bit 366" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365  ,Set/Clear Pending Bit 365" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND364  ,Set/Clear Pending Bit 364" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND363  ,Set/Clear Pending Bit 363" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362  ,Set/Clear Pending Bit 362" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND361  ,Set/Clear Pending Bit 361" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND360  ,Set/Clear Pending Bit 360" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359  ,Set/Clear Pending Bit 359" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND358  ,Set/Clear Pending Bit 358" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND357  ,Set/Clear Pending Bit 357" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356  ,Set/Clear Pending Bit 356" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND355  ,Set/Clear Pending Bit 355" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND354  ,Set/Clear Pending Bit 354" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353  ,Set/Clear Pending Bit 353" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND352  ,Set/Clear Pending Bit 352" "Not pending,Pending"
else
hgroup.long 0x022C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415  ,Set/Clear Pending Bit 415" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND414  ,Set/Clear Pending Bit 414" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND413  ,Set/Clear Pending Bit 413" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412  ,Set/Clear Pending Bit 412" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND411  ,Set/Clear Pending Bit 411" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND410  ,Set/Clear Pending Bit 410" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409  ,Set/Clear Pending Bit 409" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND408  ,Set/Clear Pending Bit 408" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND407  ,Set/Clear Pending Bit 407" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406  ,Set/Clear Pending Bit 406" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND405  ,Set/Clear Pending Bit 405" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND404  ,Set/Clear Pending Bit 404" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403  ,Set/Clear Pending Bit 403" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND402  ,Set/Clear Pending Bit 402" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND401  ,Set/Clear Pending Bit 401" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400  ,Set/Clear Pending Bit 400" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND399  ,Set/Clear Pending Bit 399" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND398  ,Set/Clear Pending Bit 398" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397  ,Set/Clear Pending Bit 397" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND396  ,Set/Clear Pending Bit 396" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND395  ,Set/Clear Pending Bit 395" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394  ,Set/Clear Pending Bit 394" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND393  ,Set/Clear Pending Bit 393" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND392  ,Set/Clear Pending Bit 392" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391  ,Set/Clear Pending Bit 391" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND390  ,Set/Clear Pending Bit 390" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND389  ,Set/Clear Pending Bit 389" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388  ,Set/Clear Pending Bit 388" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND387  ,Set/Clear Pending Bit 387" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND386  ,Set/Clear Pending Bit 386" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385  ,Set/Clear Pending Bit 385" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND384  ,Set/Clear Pending Bit 384" "Not pending,Pending"
else
hgroup.long 0x0230++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447  ,Set/Clear Pending Bit 447" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND446  ,Set/Clear Pending Bit 446" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND445  ,Set/Clear Pending Bit 445" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444  ,Set/Clear Pending Bit 444" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND443  ,Set/Clear Pending Bit 443" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND442  ,Set/Clear Pending Bit 442" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441  ,Set/Clear Pending Bit 441" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND440  ,Set/Clear Pending Bit 440" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND439  ,Set/Clear Pending Bit 439" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438  ,Set/Clear Pending Bit 438" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND437  ,Set/Clear Pending Bit 437" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND436  ,Set/Clear Pending Bit 436" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435  ,Set/Clear Pending Bit 435" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND434  ,Set/Clear Pending Bit 434" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND433  ,Set/Clear Pending Bit 433" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432  ,Set/Clear Pending Bit 432" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND431  ,Set/Clear Pending Bit 431" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND430  ,Set/Clear Pending Bit 430" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429  ,Set/Clear Pending Bit 429" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND428  ,Set/Clear Pending Bit 428" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND427  ,Set/Clear Pending Bit 427" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426  ,Set/Clear Pending Bit 426" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND425  ,Set/Clear Pending Bit 425" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND424  ,Set/Clear Pending Bit 424" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423  ,Set/Clear Pending Bit 423" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND422  ,Set/Clear Pending Bit 422" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND421  ,Set/Clear Pending Bit 421" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420  ,Set/Clear Pending Bit 420" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND419  ,Set/Clear Pending Bit 419" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND418  ,Set/Clear Pending Bit 418" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417  ,Set/Clear Pending Bit 417" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND416  ,Set/Clear Pending Bit 416" "Not pending,Pending"
else
hgroup.long 0x0234++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479  ,Set/Clear Pending Bit 479" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND478  ,Set/Clear Pending Bit 478" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND477  ,Set/Clear Pending Bit 477" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476  ,Set/Clear Pending Bit 476" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND475  ,Set/Clear Pending Bit 475" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND474  ,Set/Clear Pending Bit 474" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473  ,Set/Clear Pending Bit 473" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND472  ,Set/Clear Pending Bit 472" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND471  ,Set/Clear Pending Bit 471" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470  ,Set/Clear Pending Bit 470" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND469  ,Set/Clear Pending Bit 469" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND468  ,Set/Clear Pending Bit 468" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467  ,Set/Clear Pending Bit 467" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND466  ,Set/Clear Pending Bit 466" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND465  ,Set/Clear Pending Bit 465" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464  ,Set/Clear Pending Bit 464" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND463  ,Set/Clear Pending Bit 463" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND462  ,Set/Clear Pending Bit 462" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461  ,Set/Clear Pending Bit 461" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND460  ,Set/Clear Pending Bit 460" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND459  ,Set/Clear Pending Bit 459" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458  ,Set/Clear Pending Bit 458" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND457  ,Set/Clear Pending Bit 457" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND456  ,Set/Clear Pending Bit 456" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455  ,Set/Clear Pending Bit 455" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND454  ,Set/Clear Pending Bit 454" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND453  ,Set/Clear Pending Bit 453" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452  ,Set/Clear Pending Bit 452" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND451  ,Set/Clear Pending Bit 451" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND450  ,Set/Clear Pending Bit 450" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449  ,Set/Clear Pending Bit 449" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND448  ,Set/Clear Pending Bit 448" "Not pending,Pending"
else
hgroup.long 0x0238++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511  ,Set/Clear Pending Bit 511" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND510  ,Set/Clear Pending Bit 510" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND509  ,Set/Clear Pending Bit 509" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508  ,Set/Clear Pending Bit 508" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND507  ,Set/Clear Pending Bit 507" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND506  ,Set/Clear Pending Bit 506" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505  ,Set/Clear Pending Bit 505" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND504  ,Set/Clear Pending Bit 504" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND503  ,Set/Clear Pending Bit 503" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502  ,Set/Clear Pending Bit 502" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND501  ,Set/Clear Pending Bit 501" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND500  ,Set/Clear Pending Bit 500" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499  ,Set/Clear Pending Bit 499" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND498  ,Set/Clear Pending Bit 498" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND497  ,Set/Clear Pending Bit 497" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496  ,Set/Clear Pending Bit 496" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND495  ,Set/Clear Pending Bit 495" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND494  ,Set/Clear Pending Bit 494" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493  ,Set/Clear Pending Bit 493" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND492  ,Set/Clear Pending Bit 492" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND491  ,Set/Clear Pending Bit 491" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490  ,Set/Clear Pending Bit 490" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND489  ,Set/Clear Pending Bit 489" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND488  ,Set/Clear Pending Bit 488" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487  ,Set/Clear Pending Bit 487" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND486  ,Set/Clear Pending Bit 486" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND485  ,Set/Clear Pending Bit 485" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484  ,Set/Clear Pending Bit 484" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND483  ,Set/Clear Pending Bit 483" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND482  ,Set/Clear Pending Bit 482" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481  ,Set/Clear Pending Bit 481" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND480  ,Set/Clear Pending Bit 480" "Not pending,Pending"
else
hgroup.long 0x023C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543  ,Set/Clear Pending Bit 543" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND542  ,Set/Clear Pending Bit 542" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND541  ,Set/Clear Pending Bit 541" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540  ,Set/Clear Pending Bit 540" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND539  ,Set/Clear Pending Bit 539" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND538  ,Set/Clear Pending Bit 538" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537  ,Set/Clear Pending Bit 537" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND536  ,Set/Clear Pending Bit 536" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND535  ,Set/Clear Pending Bit 535" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534  ,Set/Clear Pending Bit 534" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND533  ,Set/Clear Pending Bit 533" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND532  ,Set/Clear Pending Bit 532" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531  ,Set/Clear Pending Bit 531" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND530  ,Set/Clear Pending Bit 530" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND529  ,Set/Clear Pending Bit 529" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528  ,Set/Clear Pending Bit 528" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND527  ,Set/Clear Pending Bit 527" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND526  ,Set/Clear Pending Bit 526" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525  ,Set/Clear Pending Bit 525" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND524  ,Set/Clear Pending Bit 524" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND523  ,Set/Clear Pending Bit 523" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522  ,Set/Clear Pending Bit 522" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND521  ,Set/Clear Pending Bit 521" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND520  ,Set/Clear Pending Bit 520" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519  ,Set/Clear Pending Bit 519" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND518  ,Set/Clear Pending Bit 518" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND517  ,Set/Clear Pending Bit 517" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516  ,Set/Clear Pending Bit 516" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND515  ,Set/Clear Pending Bit 515" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND514  ,Set/Clear Pending Bit 514" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513  ,Set/Clear Pending Bit 513" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND512  ,Set/Clear Pending Bit 512" "Not pending,Pending"
else
hgroup.long 0x0240++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575  ,Set/Clear Pending Bit 575" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND574  ,Set/Clear Pending Bit 574" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND573  ,Set/Clear Pending Bit 573" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572  ,Set/Clear Pending Bit 572" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND571  ,Set/Clear Pending Bit 571" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND570  ,Set/Clear Pending Bit 570" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569  ,Set/Clear Pending Bit 569" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND568  ,Set/Clear Pending Bit 568" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND567  ,Set/Clear Pending Bit 567" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566  ,Set/Clear Pending Bit 566" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND565  ,Set/Clear Pending Bit 565" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND564  ,Set/Clear Pending Bit 564" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563  ,Set/Clear Pending Bit 563" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND562  ,Set/Clear Pending Bit 562" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND561  ,Set/Clear Pending Bit 561" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560  ,Set/Clear Pending Bit 560" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND559  ,Set/Clear Pending Bit 559" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND558  ,Set/Clear Pending Bit 558" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557  ,Set/Clear Pending Bit 557" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND556  ,Set/Clear Pending Bit 556" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND555  ,Set/Clear Pending Bit 555" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554  ,Set/Clear Pending Bit 554" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND553  ,Set/Clear Pending Bit 553" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND552  ,Set/Clear Pending Bit 552" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551  ,Set/Clear Pending Bit 551" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND550  ,Set/Clear Pending Bit 550" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND549  ,Set/Clear Pending Bit 549" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548  ,Set/Clear Pending Bit 548" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND547  ,Set/Clear Pending Bit 547" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND546  ,Set/Clear Pending Bit 546" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545  ,Set/Clear Pending Bit 545" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND544  ,Set/Clear Pending Bit 544" "Not pending,Pending"
else
hgroup.long 0x0244++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607  ,Set/Clear Pending Bit 607" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND606  ,Set/Clear Pending Bit 606" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND605  ,Set/Clear Pending Bit 605" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604  ,Set/Clear Pending Bit 604" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND603  ,Set/Clear Pending Bit 603" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND602  ,Set/Clear Pending Bit 602" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601  ,Set/Clear Pending Bit 601" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND600  ,Set/Clear Pending Bit 600" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND599  ,Set/Clear Pending Bit 599" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598  ,Set/Clear Pending Bit 598" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND597  ,Set/Clear Pending Bit 597" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND596  ,Set/Clear Pending Bit 596" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595  ,Set/Clear Pending Bit 595" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND594  ,Set/Clear Pending Bit 594" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND593  ,Set/Clear Pending Bit 593" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592  ,Set/Clear Pending Bit 592" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND591  ,Set/Clear Pending Bit 591" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND590  ,Set/Clear Pending Bit 590" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589  ,Set/Clear Pending Bit 589" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND588  ,Set/Clear Pending Bit 588" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND587  ,Set/Clear Pending Bit 587" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586  ,Set/Clear Pending Bit 586" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND585  ,Set/Clear Pending Bit 585" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND584  ,Set/Clear Pending Bit 584" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583  ,Set/Clear Pending Bit 583" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND582  ,Set/Clear Pending Bit 582" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND581  ,Set/Clear Pending Bit 581" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580  ,Set/Clear Pending Bit 580" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND579  ,Set/Clear Pending Bit 579" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND578  ,Set/Clear Pending Bit 578" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577  ,Set/Clear Pending Bit 577" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND576  ,Set/Clear Pending Bit 576" "Not pending,Pending"
else
hgroup.long 0x0248++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639  ,Set/Clear Pending Bit 639" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND638  ,Set/Clear Pending Bit 638" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND637  ,Set/Clear Pending Bit 637" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636  ,Set/Clear Pending Bit 636" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND635  ,Set/Clear Pending Bit 635" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND634  ,Set/Clear Pending Bit 634" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633  ,Set/Clear Pending Bit 633" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND632  ,Set/Clear Pending Bit 632" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND631  ,Set/Clear Pending Bit 631" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630  ,Set/Clear Pending Bit 630" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND629  ,Set/Clear Pending Bit 629" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND628  ,Set/Clear Pending Bit 628" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627  ,Set/Clear Pending Bit 627" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND626  ,Set/Clear Pending Bit 626" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND625  ,Set/Clear Pending Bit 625" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624  ,Set/Clear Pending Bit 624" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND623  ,Set/Clear Pending Bit 623" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND622  ,Set/Clear Pending Bit 622" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621  ,Set/Clear Pending Bit 621" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND620  ,Set/Clear Pending Bit 620" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND619  ,Set/Clear Pending Bit 619" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618  ,Set/Clear Pending Bit 618" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND617  ,Set/Clear Pending Bit 617" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND616  ,Set/Clear Pending Bit 616" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615  ,Set/Clear Pending Bit 615" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND614  ,Set/Clear Pending Bit 614" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND613  ,Set/Clear Pending Bit 613" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612  ,Set/Clear Pending Bit 612" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND611  ,Set/Clear Pending Bit 611" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND610  ,Set/Clear Pending Bit 610" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609  ,Set/Clear Pending Bit 609" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND608  ,Set/Clear Pending Bit 608" "Not pending,Pending"
else
hgroup.long 0x024C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671  ,Set/Clear Pending Bit 671" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND670  ,Set/Clear Pending Bit 670" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND669  ,Set/Clear Pending Bit 669" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668  ,Set/Clear Pending Bit 668" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND667  ,Set/Clear Pending Bit 667" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND666  ,Set/Clear Pending Bit 666" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665  ,Set/Clear Pending Bit 665" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND664  ,Set/Clear Pending Bit 664" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND663  ,Set/Clear Pending Bit 663" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662  ,Set/Clear Pending Bit 662" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND661  ,Set/Clear Pending Bit 661" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND660  ,Set/Clear Pending Bit 660" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659  ,Set/Clear Pending Bit 659" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND658  ,Set/Clear Pending Bit 658" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND657  ,Set/Clear Pending Bit 657" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656  ,Set/Clear Pending Bit 656" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND655  ,Set/Clear Pending Bit 655" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND654  ,Set/Clear Pending Bit 654" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653  ,Set/Clear Pending Bit 653" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND652  ,Set/Clear Pending Bit 652" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND651  ,Set/Clear Pending Bit 651" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650  ,Set/Clear Pending Bit 650" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND649  ,Set/Clear Pending Bit 649" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND648  ,Set/Clear Pending Bit 648" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647  ,Set/Clear Pending Bit 647" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND646  ,Set/Clear Pending Bit 646" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND645  ,Set/Clear Pending Bit 645" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644  ,Set/Clear Pending Bit 644" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND643  ,Set/Clear Pending Bit 643" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND642  ,Set/Clear Pending Bit 642" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641  ,Set/Clear Pending Bit 641" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND640  ,Set/Clear Pending Bit 640" "Not pending,Pending"
else
hgroup.long 0x0250++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703  ,Set/Clear Pending Bit 703" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND702  ,Set/Clear Pending Bit 702" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND701  ,Set/Clear Pending Bit 701" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700  ,Set/Clear Pending Bit 700" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND699  ,Set/Clear Pending Bit 699" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND698  ,Set/Clear Pending Bit 698" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697  ,Set/Clear Pending Bit 697" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND696  ,Set/Clear Pending Bit 696" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND695  ,Set/Clear Pending Bit 695" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694  ,Set/Clear Pending Bit 694" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND693  ,Set/Clear Pending Bit 693" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND692  ,Set/Clear Pending Bit 692" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691  ,Set/Clear Pending Bit 691" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND690  ,Set/Clear Pending Bit 690" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND689  ,Set/Clear Pending Bit 689" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688  ,Set/Clear Pending Bit 688" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND687  ,Set/Clear Pending Bit 687" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND686  ,Set/Clear Pending Bit 686" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685  ,Set/Clear Pending Bit 685" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND684  ,Set/Clear Pending Bit 684" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND683  ,Set/Clear Pending Bit 683" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682  ,Set/Clear Pending Bit 682" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND681  ,Set/Clear Pending Bit 681" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND680  ,Set/Clear Pending Bit 680" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679  ,Set/Clear Pending Bit 679" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND678  ,Set/Clear Pending Bit 678" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND677  ,Set/Clear Pending Bit 677" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676  ,Set/Clear Pending Bit 676" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND675  ,Set/Clear Pending Bit 675" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND674  ,Set/Clear Pending Bit 674" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673  ,Set/Clear Pending Bit 673" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND672  ,Set/Clear Pending Bit 672" "Not pending,Pending"
else
hgroup.long 0x0254++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735  ,Set/Clear Pending Bit 735" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND734  ,Set/Clear Pending Bit 734" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND733  ,Set/Clear Pending Bit 733" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732  ,Set/Clear Pending Bit 732" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND731  ,Set/Clear Pending Bit 731" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND730  ,Set/Clear Pending Bit 730" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729  ,Set/Clear Pending Bit 729" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND728  ,Set/Clear Pending Bit 728" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND727  ,Set/Clear Pending Bit 727" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726  ,Set/Clear Pending Bit 726" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND725  ,Set/Clear Pending Bit 725" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND724  ,Set/Clear Pending Bit 724" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723  ,Set/Clear Pending Bit 723" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND722  ,Set/Clear Pending Bit 722" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND721  ,Set/Clear Pending Bit 721" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720  ,Set/Clear Pending Bit 720" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND719  ,Set/Clear Pending Bit 719" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND718  ,Set/Clear Pending Bit 718" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717  ,Set/Clear Pending Bit 717" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND716  ,Set/Clear Pending Bit 716" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND715  ,Set/Clear Pending Bit 715" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714  ,Set/Clear Pending Bit 714" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND713  ,Set/Clear Pending Bit 713" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND712  ,Set/Clear Pending Bit 712" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711  ,Set/Clear Pending Bit 711" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND710  ,Set/Clear Pending Bit 710" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND709  ,Set/Clear Pending Bit 709" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708  ,Set/Clear Pending Bit 708" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND707  ,Set/Clear Pending Bit 707" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND706  ,Set/Clear Pending Bit 706" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705  ,Set/Clear Pending Bit 705" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND704  ,Set/Clear Pending Bit 704" "Not pending,Pending"
else
hgroup.long 0x0258++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767  ,Set/Clear Pending Bit 767" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND766  ,Set/Clear Pending Bit 766" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND765  ,Set/Clear Pending Bit 765" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764  ,Set/Clear Pending Bit 764" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND763  ,Set/Clear Pending Bit 763" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND762  ,Set/Clear Pending Bit 762" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761  ,Set/Clear Pending Bit 761" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND760  ,Set/Clear Pending Bit 760" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND759  ,Set/Clear Pending Bit 759" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758  ,Set/Clear Pending Bit 758" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND757  ,Set/Clear Pending Bit 757" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND756  ,Set/Clear Pending Bit 756" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755  ,Set/Clear Pending Bit 755" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND754  ,Set/Clear Pending Bit 754" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND753  ,Set/Clear Pending Bit 753" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752  ,Set/Clear Pending Bit 752" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND751  ,Set/Clear Pending Bit 751" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND750  ,Set/Clear Pending Bit 750" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749  ,Set/Clear Pending Bit 749" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND748  ,Set/Clear Pending Bit 748" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND747  ,Set/Clear Pending Bit 747" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746  ,Set/Clear Pending Bit 746" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND745  ,Set/Clear Pending Bit 745" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND744  ,Set/Clear Pending Bit 744" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743  ,Set/Clear Pending Bit 743" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND742  ,Set/Clear Pending Bit 742" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND741  ,Set/Clear Pending Bit 741" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740  ,Set/Clear Pending Bit 740" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND739  ,Set/Clear Pending Bit 739" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND738  ,Set/Clear Pending Bit 738" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737  ,Set/Clear Pending Bit 737" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND736  ,Set/Clear Pending Bit 736" "Not pending,Pending"
else
hgroup.long 0x025C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799  ,Set/Clear Pending Bit 799" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND798  ,Set/Clear Pending Bit 798" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND797  ,Set/Clear Pending Bit 797" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796  ,Set/Clear Pending Bit 796" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND795  ,Set/Clear Pending Bit 795" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND794  ,Set/Clear Pending Bit 794" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793  ,Set/Clear Pending Bit 793" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND792  ,Set/Clear Pending Bit 792" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND791  ,Set/Clear Pending Bit 791" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790  ,Set/Clear Pending Bit 790" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND789  ,Set/Clear Pending Bit 789" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND788  ,Set/Clear Pending Bit 788" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787  ,Set/Clear Pending Bit 787" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND786  ,Set/Clear Pending Bit 786" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND785  ,Set/Clear Pending Bit 785" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784  ,Set/Clear Pending Bit 784" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND783  ,Set/Clear Pending Bit 783" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND782  ,Set/Clear Pending Bit 782" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781  ,Set/Clear Pending Bit 781" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND780  ,Set/Clear Pending Bit 780" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND779  ,Set/Clear Pending Bit 779" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778  ,Set/Clear Pending Bit 778" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND777  ,Set/Clear Pending Bit 777" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND776  ,Set/Clear Pending Bit 776" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775  ,Set/Clear Pending Bit 775" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND774  ,Set/Clear Pending Bit 774" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND773  ,Set/Clear Pending Bit 773" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772  ,Set/Clear Pending Bit 772" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND771  ,Set/Clear Pending Bit 771" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND770  ,Set/Clear Pending Bit 770" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769  ,Set/Clear Pending Bit 769" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND768  ,Set/Clear Pending Bit 768" "Not pending,Pending"
else
hgroup.long 0x0260++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831  ,Set/Clear Pending Bit 831" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND830  ,Set/Clear Pending Bit 830" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND829  ,Set/Clear Pending Bit 829" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828  ,Set/Clear Pending Bit 828" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND827  ,Set/Clear Pending Bit 827" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND826  ,Set/Clear Pending Bit 826" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825  ,Set/Clear Pending Bit 825" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND824  ,Set/Clear Pending Bit 824" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND823  ,Set/Clear Pending Bit 823" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822  ,Set/Clear Pending Bit 822" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND821  ,Set/Clear Pending Bit 821" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND820  ,Set/Clear Pending Bit 820" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819  ,Set/Clear Pending Bit 819" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND818  ,Set/Clear Pending Bit 818" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND817  ,Set/Clear Pending Bit 817" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816  ,Set/Clear Pending Bit 816" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND815  ,Set/Clear Pending Bit 815" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND814  ,Set/Clear Pending Bit 814" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813  ,Set/Clear Pending Bit 813" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND812  ,Set/Clear Pending Bit 812" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND811  ,Set/Clear Pending Bit 811" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810  ,Set/Clear Pending Bit 810" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND809  ,Set/Clear Pending Bit 809" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND808  ,Set/Clear Pending Bit 808" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807  ,Set/Clear Pending Bit 807" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND806  ,Set/Clear Pending Bit 806" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND805  ,Set/Clear Pending Bit 805" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804  ,Set/Clear Pending Bit 804" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND803  ,Set/Clear Pending Bit 803" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND802  ,Set/Clear Pending Bit 802" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801  ,Set/Clear Pending Bit 801" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND800  ,Set/Clear Pending Bit 800" "Not pending,Pending"
else
hgroup.long 0x0264++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863  ,Set/Clear Pending Bit 863" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND862  ,Set/Clear Pending Bit 862" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND861  ,Set/Clear Pending Bit 861" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860  ,Set/Clear Pending Bit 860" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND859  ,Set/Clear Pending Bit 859" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND858  ,Set/Clear Pending Bit 858" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857  ,Set/Clear Pending Bit 857" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND856  ,Set/Clear Pending Bit 856" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND855  ,Set/Clear Pending Bit 855" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854  ,Set/Clear Pending Bit 854" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND853  ,Set/Clear Pending Bit 853" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND852  ,Set/Clear Pending Bit 852" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851  ,Set/Clear Pending Bit 851" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND850  ,Set/Clear Pending Bit 850" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND849  ,Set/Clear Pending Bit 849" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848  ,Set/Clear Pending Bit 848" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND847  ,Set/Clear Pending Bit 847" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND846  ,Set/Clear Pending Bit 846" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845  ,Set/Clear Pending Bit 845" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND844  ,Set/Clear Pending Bit 844" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND843  ,Set/Clear Pending Bit 843" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842  ,Set/Clear Pending Bit 842" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND841  ,Set/Clear Pending Bit 841" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND840  ,Set/Clear Pending Bit 840" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839  ,Set/Clear Pending Bit 839" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND838  ,Set/Clear Pending Bit 838" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND837  ,Set/Clear Pending Bit 837" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836  ,Set/Clear Pending Bit 836" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND835  ,Set/Clear Pending Bit 835" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND834  ,Set/Clear Pending Bit 834" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833  ,Set/Clear Pending Bit 833" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND832  ,Set/Clear Pending Bit 832" "Not pending,Pending"
else
hgroup.long 0x0268++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895  ,Set/Clear Pending Bit 895" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND894  ,Set/Clear Pending Bit 894" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND893  ,Set/Clear Pending Bit 893" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892  ,Set/Clear Pending Bit 892" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND891  ,Set/Clear Pending Bit 891" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND890  ,Set/Clear Pending Bit 890" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889  ,Set/Clear Pending Bit 889" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND888  ,Set/Clear Pending Bit 888" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND887  ,Set/Clear Pending Bit 887" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886  ,Set/Clear Pending Bit 886" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND885  ,Set/Clear Pending Bit 885" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND884  ,Set/Clear Pending Bit 884" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883  ,Set/Clear Pending Bit 883" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND882  ,Set/Clear Pending Bit 882" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND881  ,Set/Clear Pending Bit 881" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880  ,Set/Clear Pending Bit 880" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND879  ,Set/Clear Pending Bit 879" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND878  ,Set/Clear Pending Bit 878" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877  ,Set/Clear Pending Bit 877" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND876  ,Set/Clear Pending Bit 876" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND875  ,Set/Clear Pending Bit 875" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874  ,Set/Clear Pending Bit 874" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND873  ,Set/Clear Pending Bit 873" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND872  ,Set/Clear Pending Bit 872" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871  ,Set/Clear Pending Bit 871" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND870  ,Set/Clear Pending Bit 870" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND869  ,Set/Clear Pending Bit 869" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868  ,Set/Clear Pending Bit 868" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND867  ,Set/Clear Pending Bit 867" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND866  ,Set/Clear Pending Bit 866" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865  ,Set/Clear Pending Bit 865" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND864  ,Set/Clear Pending Bit 864" "Not pending,Pending"
else
hgroup.long 0x026C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927  ,Set/Clear Pending Bit 927" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND926  ,Set/Clear Pending Bit 926" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND925  ,Set/Clear Pending Bit 925" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924  ,Set/Clear Pending Bit 924" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND923  ,Set/Clear Pending Bit 923" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND922  ,Set/Clear Pending Bit 922" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921  ,Set/Clear Pending Bit 921" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND920  ,Set/Clear Pending Bit 920" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND919  ,Set/Clear Pending Bit 919" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918  ,Set/Clear Pending Bit 918" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND917  ,Set/Clear Pending Bit 917" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND916  ,Set/Clear Pending Bit 916" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915  ,Set/Clear Pending Bit 915" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND914  ,Set/Clear Pending Bit 914" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND913  ,Set/Clear Pending Bit 913" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912  ,Set/Clear Pending Bit 912" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND911  ,Set/Clear Pending Bit 911" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND910  ,Set/Clear Pending Bit 910" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909  ,Set/Clear Pending Bit 909" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND908  ,Set/Clear Pending Bit 908" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND907  ,Set/Clear Pending Bit 907" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906  ,Set/Clear Pending Bit 906" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND905  ,Set/Clear Pending Bit 905" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND904  ,Set/Clear Pending Bit 904" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903  ,Set/Clear Pending Bit 903" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND902  ,Set/Clear Pending Bit 902" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND901  ,Set/Clear Pending Bit 901" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900  ,Set/Clear Pending Bit 900" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND899  ,Set/Clear Pending Bit 899" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND898  ,Set/Clear Pending Bit 898" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897  ,Set/Clear Pending Bit 897" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND896  ,Set/Clear Pending Bit 896" "Not pending,Pending"
else
hgroup.long 0x0270++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959  ,Set/Clear Pending Bit 959" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND958  ,Set/Clear Pending Bit 958" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND957  ,Set/Clear Pending Bit 957" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956  ,Set/Clear Pending Bit 956" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND955  ,Set/Clear Pending Bit 955" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND954  ,Set/Clear Pending Bit 954" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953  ,Set/Clear Pending Bit 953" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND952  ,Set/Clear Pending Bit 952" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND951  ,Set/Clear Pending Bit 951" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950  ,Set/Clear Pending Bit 950" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND949  ,Set/Clear Pending Bit 949" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND948  ,Set/Clear Pending Bit 948" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947  ,Set/Clear Pending Bit 947" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND946  ,Set/Clear Pending Bit 946" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND945  ,Set/Clear Pending Bit 945" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944  ,Set/Clear Pending Bit 944" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND943  ,Set/Clear Pending Bit 943" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND942  ,Set/Clear Pending Bit 942" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941  ,Set/Clear Pending Bit 941" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND940  ,Set/Clear Pending Bit 940" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND939  ,Set/Clear Pending Bit 939" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938  ,Set/Clear Pending Bit 938" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND937  ,Set/Clear Pending Bit 937" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND936  ,Set/Clear Pending Bit 936" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935  ,Set/Clear Pending Bit 935" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND934  ,Set/Clear Pending Bit 934" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND933  ,Set/Clear Pending Bit 933" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932  ,Set/Clear Pending Bit 932" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND931  ,Set/Clear Pending Bit 931" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND930  ,Set/Clear Pending Bit 930" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929  ,Set/Clear Pending Bit 929" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND928  ,Set/Clear Pending Bit 928" "Not pending,Pending"
else
hgroup.long 0x0274++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991  ,Set/Clear Pending Bit 991" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND990  ,Set/Clear Pending Bit 990" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND989  ,Set/Clear Pending Bit 989" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988  ,Set/Clear Pending Bit 988" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND987  ,Set/Clear Pending Bit 987" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND986  ,Set/Clear Pending Bit 986" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985  ,Set/Clear Pending Bit 985" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND984  ,Set/Clear Pending Bit 984" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND983  ,Set/Clear Pending Bit 983" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982  ,Set/Clear Pending Bit 982" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND981  ,Set/Clear Pending Bit 981" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND980  ,Set/Clear Pending Bit 980" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979  ,Set/Clear Pending Bit 979" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND978  ,Set/Clear Pending Bit 978" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND977  ,Set/Clear Pending Bit 977" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976  ,Set/Clear Pending Bit 976" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND975  ,Set/Clear Pending Bit 975" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND974  ,Set/Clear Pending Bit 974" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973  ,Set/Clear Pending Bit 973" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND972  ,Set/Clear Pending Bit 972" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND971  ,Set/Clear Pending Bit 971" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970  ,Set/Clear Pending Bit 970" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND969  ,Set/Clear Pending Bit 969" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND968  ,Set/Clear Pending Bit 968" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967  ,Set/Clear Pending Bit 967" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND966  ,Set/Clear Pending Bit 966" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND965  ,Set/Clear Pending Bit 965" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964  ,Set/Clear Pending Bit 964" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND963  ,Set/Clear Pending Bit 963" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND962  ,Set/Clear Pending Bit 962" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961  ,Set/Clear Pending Bit 961" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND960  ,Set/Clear Pending Bit 960" "Not pending,Pending"
else
hgroup.long 0x0278++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
endif
tree.end
width 24.
tree "Set/Clear Active Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0300++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0300++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31  ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30  ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29  ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28  ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27  ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26  ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25  ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24  ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23  ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22  ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21  ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20  ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19  ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18  ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17  ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16  ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15  ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14  ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13  ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12  ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11  ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10  ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9   ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8   ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7   ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6   ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5   ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4   ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3   ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2   ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1   ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0   ,Set/Clear Active Bit 0" "Not active,Active"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63  ,Set/Clear Active Bit 63" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE62  ,Set/Clear Active Bit 62" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE61  ,Set/Clear Active Bit 61" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60  ,Set/Clear Active Bit 60" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE59  ,Set/Clear Active Bit 59" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE58  ,Set/Clear Active Bit 58" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57  ,Set/Clear Active Bit 57" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE56  ,Set/Clear Active Bit 56" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE55  ,Set/Clear Active Bit 55" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54  ,Set/Clear Active Bit 54" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE53  ,Set/Clear Active Bit 53" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE52  ,Set/Clear Active Bit 52" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51  ,Set/Clear Active Bit 51" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE50  ,Set/Clear Active Bit 50" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE49  ,Set/Clear Active Bit 49" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48  ,Set/Clear Active Bit 48" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE47  ,Set/Clear Active Bit 47" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE46  ,Set/Clear Active Bit 46" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45  ,Set/Clear Active Bit 45" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE44  ,Set/Clear Active Bit 44" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE43  ,Set/Clear Active Bit 43" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42  ,Set/Clear Active Bit 42" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE41  ,Set/Clear Active Bit 41" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE40  ,Set/Clear Active Bit 40" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39  ,Set/Clear Active Bit 39" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE38  ,Set/Clear Active Bit 38" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE37  ,Set/Clear Active Bit 37" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36  ,Set/Clear Active Bit 36" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE35  ,Set/Clear Active Bit 35" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE34  ,Set/Clear Active Bit 34" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33  ,Set/Clear Active Bit 33" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE32  ,Set/Clear Active Bit 32" "Not active,Active"
else
hgroup.long 0x0304++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95  ,Set/Clear Active Bit 95" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE94  ,Set/Clear Active Bit 94" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE93  ,Set/Clear Active Bit 93" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92  ,Set/Clear Active Bit 92" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE91  ,Set/Clear Active Bit 91" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE90  ,Set/Clear Active Bit 90" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89  ,Set/Clear Active Bit 89" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE88  ,Set/Clear Active Bit 88" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE87  ,Set/Clear Active Bit 87" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86  ,Set/Clear Active Bit 86" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE85  ,Set/Clear Active Bit 85" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE84  ,Set/Clear Active Bit 84" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83  ,Set/Clear Active Bit 83" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE82  ,Set/Clear Active Bit 82" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE81  ,Set/Clear Active Bit 81" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80  ,Set/Clear Active Bit 80" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE79  ,Set/Clear Active Bit 79" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE78  ,Set/Clear Active Bit 78" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77  ,Set/Clear Active Bit 77" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE76  ,Set/Clear Active Bit 76" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE75  ,Set/Clear Active Bit 75" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74  ,Set/Clear Active Bit 74" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE73  ,Set/Clear Active Bit 73" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE72  ,Set/Clear Active Bit 72" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71  ,Set/Clear Active Bit 71" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE70  ,Set/Clear Active Bit 70" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE69  ,Set/Clear Active Bit 69" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68  ,Set/Clear Active Bit 68" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE67  ,Set/Clear Active Bit 67" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE66  ,Set/Clear Active Bit 66" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65  ,Set/Clear Active Bit 65" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE64  ,Set/Clear Active Bit 64" "Not active,Active"
else
hgroup.long 0x0308++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE99  ,Set/Clear Active Bit 99" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE98  ,Set/Clear Active Bit 98" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97  ,Set/Clear Active Bit 97" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE96  ,Set/Clear Active Bit 96" "Not active,Active"
else
hgroup.long 0x030C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
else
hgroup.long 0x0310++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
else
hgroup.long 0x0314++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
else
hgroup.long 0x0318++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
else
hgroup.long 0x031C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
else
hgroup.long 0x0320++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
else
hgroup.long 0x0324++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
else
hgroup.long 0x0328++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
else
hgroup.long 0x032C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
else
hgroup.long 0x0330++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
else
hgroup.long 0x0334++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
else
hgroup.long 0x0338++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
else
hgroup.long 0x033C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0340++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active"
else
hgroup.long 0x0340++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0344++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active"
else
hgroup.long 0x0344++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0348++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active"
else
hgroup.long 0x0348++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x034C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active"
else
hgroup.long 0x034C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0350++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active"
else
hgroup.long 0x0350++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0354++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active"
else
hgroup.long 0x0354++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0358++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active"
else
hgroup.long 0x0358++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x035C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active"
else
hgroup.long 0x035C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0360++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active"
else
hgroup.long 0x0360++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0364++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active"
else
hgroup.long 0x0364++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0368++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active"
else
hgroup.long 0x0368++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x036C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active"
else
hgroup.long 0x036C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0370++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active"
else
hgroup.long 0x0370++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0374++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active"
else
hgroup.long 0x0374++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0378++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active"
else
hgroup.long 0x0378++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
endif
tree.end
width 20.
tree "Priority Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x400++0x03
hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hgroup.long 0x404++0x03
hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hgroup.long 0x408++0x03
hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hgroup.long 0x40C++0x03
hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hgroup.long 0x410++0x03
hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hgroup.long 0x414++0x03
hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hgroup.long 0x418++0x03
hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hgroup.long 0x41C++0x03
hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
else
group.long 0x400++0x03
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID2    ,Interrupt ID2     Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID0    ,Interrupt ID0     Priority/Priority Byte Offset 0   "
group.long 0x404++0x03
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID6    ,Interrupt ID6     Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID4    ,Interrupt ID4     Priority/Priority Byte Offset 4   "
group.long 0x408++0x03
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID10   ,Interrupt ID10    Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID8    ,Interrupt ID8     Priority/Priority Byte Offset 8   "
group.long 0x40C++0x03
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID14   ,Interrupt ID14    Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID12   ,Interrupt ID12    Priority/Priority Byte Offset 12  "
group.long 0x410++0x03
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID18   ,Interrupt ID18    Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID16   ,Interrupt ID16    Priority/Priority Byte Offset 16  "
group.long 0x414++0x03
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID22   ,Interrupt ID22    Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID20   ,Interrupt ID20    Priority/Priority Byte Offset 20  "
group.long 0x418++0x03
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID26   ,Interrupt ID26    Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID24   ,Interrupt ID24    Priority/Priority Byte Offset 24  "
group.long 0x41C++0x03
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID30   ,Interrupt ID30    Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID28   ,Interrupt ID28    Priority/Priority Byte Offset 28  "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hexmask.long.byte 0x00 24.--31. 1. " INTID35   ,Interrupt ID35   Priority/Priority Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID34   ,Interrupt ID34    Priority/Priority Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID33   ,Interrupt ID33   Priority/Priority Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID32   ,Interrupt ID32    Priority/Priority Byte Offset 32  "
group.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hexmask.long.byte 0x00 24.--31. 1. " INTID39   ,Interrupt ID39   Priority/Priority Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID38   ,Interrupt ID38    Priority/Priority Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID37   ,Interrupt ID37   Priority/Priority Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID36   ,Interrupt ID36    Priority/Priority Byte Offset 36  "
group.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hexmask.long.byte 0x00 24.--31. 1. " INTID43   ,Interrupt ID43   Priority/Priority Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID42   ,Interrupt ID42    Priority/Priority Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID41   ,Interrupt ID41   Priority/Priority Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID40   ,Interrupt ID40    Priority/Priority Byte Offset 40  "
group.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hexmask.long.byte 0x00 24.--31. 1. " INTID47   ,Interrupt ID47   Priority/Priority Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID46   ,Interrupt ID46    Priority/Priority Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID45   ,Interrupt ID45   Priority/Priority Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID44   ,Interrupt ID44    Priority/Priority Byte Offset 44  "
group.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hexmask.long.byte 0x00 24.--31. 1. " INTID51   ,Interrupt ID51   Priority/Priority Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID50   ,Interrupt ID50    Priority/Priority Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID49   ,Interrupt ID49   Priority/Priority Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID48   ,Interrupt ID48    Priority/Priority Byte Offset 48  "
group.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hexmask.long.byte 0x00 24.--31. 1. " INTID55   ,Interrupt ID55   Priority/Priority Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID54   ,Interrupt ID54    Priority/Priority Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID53   ,Interrupt ID53   Priority/Priority Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID52   ,Interrupt ID52    Priority/Priority Byte Offset 52  "
group.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hexmask.long.byte 0x00 24.--31. 1. " INTID59   ,Interrupt ID59   Priority/Priority Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID58   ,Interrupt ID58    Priority/Priority Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID57   ,Interrupt ID57   Priority/Priority Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID56   ,Interrupt ID56    Priority/Priority Byte Offset 56  "
group.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
hexmask.long.byte 0x00 24.--31. 1. " INTID63   ,Interrupt ID63   Priority/Priority Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID62   ,Interrupt ID62    Priority/Priority Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID61   ,Interrupt ID61   Priority/Priority Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID60   ,Interrupt ID60    Priority/Priority Byte Offset 60  "
else
hgroup.long 0x420++0x03
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hgroup.long 0x424++0x03
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hgroup.long 0x428++0x03
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hgroup.long 0x42C++0x03
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hgroup.long 0x430++0x03
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hgroup.long 0x434++0x03
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hgroup.long 0x438++0x03
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hgroup.long 0x43C++0x03
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hexmask.long.byte 0x00 24.--31. 1. " INTID67   ,Interrupt ID67   Priority/Priority Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID66   ,Interrupt ID66    Priority/Priority Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID65   ,Interrupt ID65   Priority/Priority Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID64   ,Interrupt ID64    Priority/Priority Byte Offset 64  "
group.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hexmask.long.byte 0x00 24.--31. 1. " INTID71   ,Interrupt ID71   Priority/Priority Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID70   ,Interrupt ID70    Priority/Priority Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID69   ,Interrupt ID69   Priority/Priority Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID68   ,Interrupt ID68    Priority/Priority Byte Offset 68  "
group.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hexmask.long.byte 0x00 24.--31. 1. " INTID75   ,Interrupt ID75   Priority/Priority Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID74   ,Interrupt ID74    Priority/Priority Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID73   ,Interrupt ID73   Priority/Priority Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID72   ,Interrupt ID72    Priority/Priority Byte Offset 72  "
group.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hexmask.long.byte 0x00 24.--31. 1. " INTID79   ,Interrupt ID79   Priority/Priority Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID78   ,Interrupt ID78    Priority/Priority Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID77   ,Interrupt ID77   Priority/Priority Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID76   ,Interrupt ID76    Priority/Priority Byte Offset 76  "
group.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hexmask.long.byte 0x00 24.--31. 1. " INTID83   ,Interrupt ID83   Priority/Priority Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID82   ,Interrupt ID82    Priority/Priority Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID81   ,Interrupt ID81   Priority/Priority Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID80   ,Interrupt ID80    Priority/Priority Byte Offset 80  "
group.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hexmask.long.byte 0x00 24.--31. 1. " INTID87   ,Interrupt ID87   Priority/Priority Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID86   ,Interrupt ID86    Priority/Priority Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID85   ,Interrupt ID85   Priority/Priority Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID84   ,Interrupt ID84    Priority/Priority Byte Offset 84  "
group.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hexmask.long.byte 0x00 24.--31. 1. " INTID91   ,Interrupt ID91   Priority/Priority Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID90   ,Interrupt ID90    Priority/Priority Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID89   ,Interrupt ID89   Priority/Priority Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID88   ,Interrupt ID88    Priority/Priority Byte Offset 88  "
group.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
hexmask.long.byte 0x00 24.--31. 1. " INTID95   ,Interrupt ID95   Priority/Priority Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID94   ,Interrupt ID94    Priority/Priority Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID93   ,Interrupt ID93   Priority/Priority Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID92   ,Interrupt ID92    Priority/Priority Byte Offset 92  "
else
hgroup.long 0x440++0x03
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hgroup.long 0x444++0x03
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hgroup.long 0x448++0x03
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hgroup.long 0x44C++0x03
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hgroup.long 0x450++0x03
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hgroup.long 0x454++0x03
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hgroup.long 0x458++0x03
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hgroup.long 0x45C++0x03
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hexmask.long.byte 0x00 24.--31. 1. " INTID99   ,Interrupt ID99   Priority/Priority Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID98   ,Interrupt ID98    Priority/Priority Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID97   ,Interrupt ID97   Priority/Priority Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID96   ,Interrupt ID96    Priority/Priority Byte Offset 96  "
group.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hexmask.long.byte 0x00 24.--31. 1. " INTID103  ,Interrupt ID103  Priority/Priority Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID102  ,Interrupt ID102   Priority/Priority Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID101  ,Interrupt ID101  Priority/Priority Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID100  ,Interrupt ID100   Priority/Priority Byte Offset 100 "
group.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hexmask.long.byte 0x00 24.--31. 1. " INTID107  ,Interrupt ID107  Priority/Priority Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID106  ,Interrupt ID106   Priority/Priority Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID105  ,Interrupt ID105  Priority/Priority Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID104  ,Interrupt ID104   Priority/Priority Byte Offset 104 "
group.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hexmask.long.byte 0x00 24.--31. 1. " INTID111  ,Interrupt ID111  Priority/Priority Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID110  ,Interrupt ID110   Priority/Priority Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID109  ,Interrupt ID109  Priority/Priority Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID108  ,Interrupt ID108   Priority/Priority Byte Offset 108 "
group.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hexmask.long.byte 0x00 24.--31. 1. " INTID115  ,Interrupt ID115  Priority/Priority Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID114  ,Interrupt ID114   Priority/Priority Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID113  ,Interrupt ID113  Priority/Priority Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID112  ,Interrupt ID112   Priority/Priority Byte Offset 112 "
group.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hexmask.long.byte 0x00 24.--31. 1. " INTID119  ,Interrupt ID119  Priority/Priority Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID118  ,Interrupt ID118   Priority/Priority Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID117  ,Interrupt ID117  Priority/Priority Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID116  ,Interrupt ID116   Priority/Priority Byte Offset 116 "
group.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hexmask.long.byte 0x00 24.--31. 1. " INTID123  ,Interrupt ID123  Priority/Priority Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID122  ,Interrupt ID122   Priority/Priority Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID121  ,Interrupt ID121  Priority/Priority Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID120  ,Interrupt ID120   Priority/Priority Byte Offset 120 "
group.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
hexmask.long.byte 0x00 24.--31. 1. " INTID127  ,Interrupt ID127  Priority/Priority Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID126  ,Interrupt ID126   Priority/Priority Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID125  ,Interrupt ID125  Priority/Priority Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID124  ,Interrupt ID124   Priority/Priority Byte Offset 124 "
else
hgroup.long 0x460++0x03
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hgroup.long 0x464++0x03
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hgroup.long 0x468++0x03
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hgroup.long 0x46C++0x03
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hgroup.long 0x470++0x03
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hgroup.long 0x474++0x03
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hgroup.long 0x478++0x03
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hgroup.long 0x47C++0x03
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hexmask.long.byte 0x00 24.--31. 1. " INTID131  ,Interrupt ID131  Priority/Priority Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID130  ,Interrupt ID130   Priority/Priority Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID129  ,Interrupt ID129  Priority/Priority Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID128  ,Interrupt ID128   Priority/Priority Byte Offset 128 "
group.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hexmask.long.byte 0x00 24.--31. 1. " INTID135  ,Interrupt ID135  Priority/Priority Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID134  ,Interrupt ID134   Priority/Priority Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID133  ,Interrupt ID133  Priority/Priority Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID132  ,Interrupt ID132   Priority/Priority Byte Offset 132 "
group.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hexmask.long.byte 0x00 24.--31. 1. " INTID139  ,Interrupt ID139  Priority/Priority Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID138  ,Interrupt ID138   Priority/Priority Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID137  ,Interrupt ID137  Priority/Priority Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID136  ,Interrupt ID136   Priority/Priority Byte Offset 136 "
group.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hexmask.long.byte 0x00 24.--31. 1. " INTID143  ,Interrupt ID143  Priority/Priority Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID142  ,Interrupt ID142   Priority/Priority Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID141  ,Interrupt ID141  Priority/Priority Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID140  ,Interrupt ID140   Priority/Priority Byte Offset 140 "
group.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hexmask.long.byte 0x00 24.--31. 1. " INTID147  ,Interrupt ID147  Priority/Priority Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID146  ,Interrupt ID146   Priority/Priority Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID145  ,Interrupt ID145  Priority/Priority Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID144  ,Interrupt ID144   Priority/Priority Byte Offset 144 "
group.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hexmask.long.byte 0x00 24.--31. 1. " INTID151  ,Interrupt ID151  Priority/Priority Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID150  ,Interrupt ID150   Priority/Priority Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID149  ,Interrupt ID149  Priority/Priority Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID148  ,Interrupt ID148   Priority/Priority Byte Offset 148 "
group.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hexmask.long.byte 0x00 24.--31. 1. " INTID155  ,Interrupt ID155  Priority/Priority Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID154  ,Interrupt ID154   Priority/Priority Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID153  ,Interrupt ID153  Priority/Priority Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID152  ,Interrupt ID152   Priority/Priority Byte Offset 152 "
group.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
hexmask.long.byte 0x00 24.--31. 1. " INTID159  ,Interrupt ID159  Priority/Priority Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID158  ,Interrupt ID158   Priority/Priority Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID157  ,Interrupt ID157  Priority/Priority Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID156  ,Interrupt ID156   Priority/Priority Byte Offset 156 "
else
hgroup.long 0x480++0x03
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hgroup.long 0x484++0x03
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hgroup.long 0x488++0x03
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hgroup.long 0x48C++0x03
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hgroup.long 0x490++0x03
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hgroup.long 0x494++0x03
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hgroup.long 0x498++0x03
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hgroup.long 0x49C++0x03
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hexmask.long.byte 0x00 24.--31. 1. " INTID163  ,Interrupt ID163  Priority/Priority Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID162  ,Interrupt ID162   Priority/Priority Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID161  ,Interrupt ID161  Priority/Priority Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID160  ,Interrupt ID160   Priority/Priority Byte Offset 160 "
group.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hexmask.long.byte 0x00 24.--31. 1. " INTID167  ,Interrupt ID167  Priority/Priority Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID166  ,Interrupt ID166   Priority/Priority Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID165  ,Interrupt ID165  Priority/Priority Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID164  ,Interrupt ID164   Priority/Priority Byte Offset 164 "
group.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hexmask.long.byte 0x00 24.--31. 1. " INTID171  ,Interrupt ID171  Priority/Priority Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID170  ,Interrupt ID170   Priority/Priority Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID169  ,Interrupt ID169  Priority/Priority Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID168  ,Interrupt ID168   Priority/Priority Byte Offset 168 "
group.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hexmask.long.byte 0x00 24.--31. 1. " INTID175  ,Interrupt ID175  Priority/Priority Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID174  ,Interrupt ID174   Priority/Priority Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID173  ,Interrupt ID173  Priority/Priority Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID172  ,Interrupt ID172   Priority/Priority Byte Offset 172 "
group.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hexmask.long.byte 0x00 24.--31. 1. " INTID179  ,Interrupt ID179  Priority/Priority Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID178  ,Interrupt ID178   Priority/Priority Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID177  ,Interrupt ID177  Priority/Priority Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID176  ,Interrupt ID176   Priority/Priority Byte Offset 176 "
group.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hexmask.long.byte 0x00 24.--31. 1. " INTID183  ,Interrupt ID183  Priority/Priority Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID182  ,Interrupt ID182   Priority/Priority Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID181  ,Interrupt ID181  Priority/Priority Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID180  ,Interrupt ID180   Priority/Priority Byte Offset 180 "
group.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hexmask.long.byte 0x00 24.--31. 1. " INTID187  ,Interrupt ID187  Priority/Priority Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID186  ,Interrupt ID186   Priority/Priority Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID185  ,Interrupt ID185  Priority/Priority Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID184  ,Interrupt ID184   Priority/Priority Byte Offset 184 "
group.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
hexmask.long.byte 0x00 24.--31. 1. " INTID191  ,Interrupt ID191  Priority/Priority Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID190  ,Interrupt ID190   Priority/Priority Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID189  ,Interrupt ID189  Priority/Priority Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID188  ,Interrupt ID188   Priority/Priority Byte Offset 188 "
else
hgroup.long 0x4A0++0x03
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hgroup.long 0x4A4++0x03
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hgroup.long 0x4A8++0x03
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hgroup.long 0x4AC++0x03
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hgroup.long 0x4B0++0x03
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hgroup.long 0x4B4++0x03
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hgroup.long 0x4B8++0x03
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hgroup.long 0x4BC++0x03
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hexmask.long.byte 0x00 24.--31. 1. " INTID195  ,Interrupt ID195  Priority/Priority Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID194  ,Interrupt ID194   Priority/Priority Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID193  ,Interrupt ID193  Priority/Priority Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID192  ,Interrupt ID192   Priority/Priority Byte Offset 192 "
group.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hexmask.long.byte 0x00 24.--31. 1. " INTID199  ,Interrupt ID199  Priority/Priority Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID198  ,Interrupt ID198   Priority/Priority Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID197  ,Interrupt ID197  Priority/Priority Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID196  ,Interrupt ID196   Priority/Priority Byte Offset 196 "
group.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hexmask.long.byte 0x00 24.--31. 1. " INTID203  ,Interrupt ID203  Priority/Priority Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID202  ,Interrupt ID202   Priority/Priority Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID201  ,Interrupt ID201  Priority/Priority Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID200  ,Interrupt ID200   Priority/Priority Byte Offset 200 "
group.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hexmask.long.byte 0x00 24.--31. 1. " INTID207  ,Interrupt ID207  Priority/Priority Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID206  ,Interrupt ID206   Priority/Priority Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID205  ,Interrupt ID205  Priority/Priority Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID204  ,Interrupt ID204   Priority/Priority Byte Offset 204 "
group.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hexmask.long.byte 0x00 24.--31. 1. " INTID211  ,Interrupt ID211  Priority/Priority Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID210  ,Interrupt ID210   Priority/Priority Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID209  ,Interrupt ID209  Priority/Priority Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID208  ,Interrupt ID208   Priority/Priority Byte Offset 208 "
group.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hexmask.long.byte 0x00 24.--31. 1. " INTID215  ,Interrupt ID215  Priority/Priority Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID214  ,Interrupt ID214   Priority/Priority Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID213  ,Interrupt ID213  Priority/Priority Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID212  ,Interrupt ID212   Priority/Priority Byte Offset 212 "
group.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hexmask.long.byte 0x00 24.--31. 1. " INTID219  ,Interrupt ID219  Priority/Priority Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID218  ,Interrupt ID218   Priority/Priority Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID217  ,Interrupt ID217  Priority/Priority Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID216  ,Interrupt ID216   Priority/Priority Byte Offset 216 "
group.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
hexmask.long.byte 0x00 24.--31. 1. " INTID223  ,Interrupt ID223  Priority/Priority Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID222  ,Interrupt ID222   Priority/Priority Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID221  ,Interrupt ID221  Priority/Priority Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID220  ,Interrupt ID220   Priority/Priority Byte Offset 220 "
else
hgroup.long 0x4C0++0x03
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hgroup.long 0x4C4++0x03
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hgroup.long 0x4C8++0x03
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hgroup.long 0x4CC++0x03
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hgroup.long 0x4D0++0x03
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hgroup.long 0x4D4++0x03
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hgroup.long 0x4D8++0x03
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hgroup.long 0x4DC++0x03
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hexmask.long.byte 0x00 24.--31. 1. " INTID227  ,Interrupt ID227  Priority/Priority Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID226  ,Interrupt ID226   Priority/Priority Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID225  ,Interrupt ID225  Priority/Priority Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID224  ,Interrupt ID224   Priority/Priority Byte Offset 224 "
group.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hexmask.long.byte 0x00 24.--31. 1. " INTID231  ,Interrupt ID231  Priority/Priority Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID230  ,Interrupt ID230   Priority/Priority Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID229  ,Interrupt ID229  Priority/Priority Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID228  ,Interrupt ID228   Priority/Priority Byte Offset 228 "
group.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hexmask.long.byte 0x00 24.--31. 1. " INTID235  ,Interrupt ID235  Priority/Priority Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID234  ,Interrupt ID234   Priority/Priority Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID233  ,Interrupt ID233  Priority/Priority Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID232  ,Interrupt ID232   Priority/Priority Byte Offset 232 "
group.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hexmask.long.byte 0x00 24.--31. 1. " INTID239  ,Interrupt ID239  Priority/Priority Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID238  ,Interrupt ID238   Priority/Priority Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID237  ,Interrupt ID237  Priority/Priority Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID236  ,Interrupt ID236   Priority/Priority Byte Offset 236 "
group.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hexmask.long.byte 0x00 24.--31. 1. " INTID243  ,Interrupt ID243  Priority/Priority Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID242  ,Interrupt ID242   Priority/Priority Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID241  ,Interrupt ID241  Priority/Priority Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID240  ,Interrupt ID240   Priority/Priority Byte Offset 240 "
group.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hexmask.long.byte 0x00 24.--31. 1. " INTID247  ,Interrupt ID247  Priority/Priority Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID246  ,Interrupt ID246   Priority/Priority Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID245  ,Interrupt ID245  Priority/Priority Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID244  ,Interrupt ID244   Priority/Priority Byte Offset 244 "
group.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hexmask.long.byte 0x00 24.--31. 1. " INTID251  ,Interrupt ID251  Priority/Priority Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID250  ,Interrupt ID250   Priority/Priority Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID249  ,Interrupt ID249  Priority/Priority Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID248  ,Interrupt ID248   Priority/Priority Byte Offset 248 "
group.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
hexmask.long.byte 0x00 24.--31. 1. " INTID255  ,Interrupt ID255  Priority/Priority Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID254  ,Interrupt ID254   Priority/Priority Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID253  ,Interrupt ID253  Priority/Priority Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID252  ,Interrupt ID252   Priority/Priority Byte Offset 252 "
else
hgroup.long 0x4E0++0x03
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hgroup.long 0x4E4++0x03
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hgroup.long 0x4E8++0x03
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hgroup.long 0x4EC++0x03
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hgroup.long 0x4F0++0x03
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hgroup.long 0x4F4++0x03
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hgroup.long 0x4F8++0x03
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hgroup.long 0x4FC++0x03
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hexmask.long.byte 0x00 24.--31. 1. " INTID259  ,Interrupt ID259  Priority/Priority Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID258  ,Interrupt ID258   Priority/Priority Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID257  ,Interrupt ID257  Priority/Priority Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID256  ,Interrupt ID256   Priority/Priority Byte Offset 256 "
group.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hexmask.long.byte 0x00 24.--31. 1. " INTID263  ,Interrupt ID263  Priority/Priority Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID262  ,Interrupt ID262   Priority/Priority Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID261  ,Interrupt ID261  Priority/Priority Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID260  ,Interrupt ID260   Priority/Priority Byte Offset 260 "
group.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hexmask.long.byte 0x00 24.--31. 1. " INTID267  ,Interrupt ID267  Priority/Priority Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID266  ,Interrupt ID266   Priority/Priority Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID265  ,Interrupt ID265  Priority/Priority Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID264  ,Interrupt ID264   Priority/Priority Byte Offset 264 "
group.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hexmask.long.byte 0x00 24.--31. 1. " INTID271  ,Interrupt ID271  Priority/Priority Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID270  ,Interrupt ID270   Priority/Priority Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID269  ,Interrupt ID269  Priority/Priority Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID268  ,Interrupt ID268   Priority/Priority Byte Offset 268 "
group.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hexmask.long.byte 0x00 24.--31. 1. " INTID275  ,Interrupt ID275  Priority/Priority Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID274  ,Interrupt ID274   Priority/Priority Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID273  ,Interrupt ID273  Priority/Priority Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID272  ,Interrupt ID272   Priority/Priority Byte Offset 272 "
group.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hexmask.long.byte 0x00 24.--31. 1. " INTID279  ,Interrupt ID279  Priority/Priority Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID278  ,Interrupt ID278   Priority/Priority Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID277  ,Interrupt ID277  Priority/Priority Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID276  ,Interrupt ID276   Priority/Priority Byte Offset 276 "
group.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hexmask.long.byte 0x00 24.--31. 1. " INTID283  ,Interrupt ID283  Priority/Priority Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID282  ,Interrupt ID282   Priority/Priority Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID281  ,Interrupt ID281  Priority/Priority Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID280  ,Interrupt ID280   Priority/Priority Byte Offset 280 "
group.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
hexmask.long.byte 0x00 24.--31. 1. " INTID287  ,Interrupt ID287  Priority/Priority Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID286  ,Interrupt ID286   Priority/Priority Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID285  ,Interrupt ID285  Priority/Priority Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID284  ,Interrupt ID284   Priority/Priority Byte Offset 284 "
else
hgroup.long 0x500++0x03
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hgroup.long 0x504++0x03
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hgroup.long 0x508++0x03
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hgroup.long 0x50C++0x03
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hgroup.long 0x510++0x03
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hgroup.long 0x514++0x03
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hgroup.long 0x518++0x03
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hgroup.long 0x51C++0x03
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hexmask.long.byte 0x00 24.--31. 1. " INTID291  ,Interrupt ID291  Priority/Priority Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID290  ,Interrupt ID290   Priority/Priority Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID289  ,Interrupt ID289  Priority/Priority Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID288  ,Interrupt ID288   Priority/Priority Byte Offset 288 "
group.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hexmask.long.byte 0x00 24.--31. 1. " INTID295  ,Interrupt ID295  Priority/Priority Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID294  ,Interrupt ID294   Priority/Priority Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID293  ,Interrupt ID293  Priority/Priority Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID292  ,Interrupt ID292   Priority/Priority Byte Offset 292 "
group.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hexmask.long.byte 0x00 24.--31. 1. " INTID299  ,Interrupt ID299  Priority/Priority Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID298  ,Interrupt ID298   Priority/Priority Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID297  ,Interrupt ID297  Priority/Priority Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID296  ,Interrupt ID296   Priority/Priority Byte Offset 296 "
group.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hexmask.long.byte 0x00 24.--31. 1. " INTID303  ,Interrupt ID303  Priority/Priority Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID302  ,Interrupt ID302   Priority/Priority Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID301  ,Interrupt ID301  Priority/Priority Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID300  ,Interrupt ID300   Priority/Priority Byte Offset 300 "
group.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hexmask.long.byte 0x00 24.--31. 1. " INTID307  ,Interrupt ID307  Priority/Priority Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID306  ,Interrupt ID306   Priority/Priority Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID305  ,Interrupt ID305  Priority/Priority Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID304  ,Interrupt ID304   Priority/Priority Byte Offset 304 "
group.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hexmask.long.byte 0x00 24.--31. 1. " INTID311  ,Interrupt ID311  Priority/Priority Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID310  ,Interrupt ID310   Priority/Priority Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID309  ,Interrupt ID309  Priority/Priority Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID308  ,Interrupt ID308   Priority/Priority Byte Offset 308 "
group.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hexmask.long.byte 0x00 24.--31. 1. " INTID315  ,Interrupt ID315  Priority/Priority Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID314  ,Interrupt ID314   Priority/Priority Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID313  ,Interrupt ID313  Priority/Priority Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID312  ,Interrupt ID312   Priority/Priority Byte Offset 312 "
group.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
hexmask.long.byte 0x00 24.--31. 1. " INTID319  ,Interrupt ID319  Priority/Priority Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID318  ,Interrupt ID318   Priority/Priority Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID317  ,Interrupt ID317  Priority/Priority Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID316  ,Interrupt ID316   Priority/Priority Byte Offset 316 "
else
hgroup.long 0x520++0x03
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hgroup.long 0x524++0x03
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hgroup.long 0x528++0x03
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hgroup.long 0x52C++0x03
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hgroup.long 0x530++0x03
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hgroup.long 0x534++0x03
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hgroup.long 0x538++0x03
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hgroup.long 0x53C++0x03
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hexmask.long.byte 0x00 24.--31. 1. " INTID323  ,Interrupt ID323  Priority/Priority Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID322  ,Interrupt ID322   Priority/Priority Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID321  ,Interrupt ID321  Priority/Priority Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID320  ,Interrupt ID320   Priority/Priority Byte Offset 320 "
group.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hexmask.long.byte 0x00 24.--31. 1. " INTID327  ,Interrupt ID327  Priority/Priority Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID326  ,Interrupt ID326   Priority/Priority Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID325  ,Interrupt ID325  Priority/Priority Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID324  ,Interrupt ID324   Priority/Priority Byte Offset 324 "
group.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hexmask.long.byte 0x00 24.--31. 1. " INTID331  ,Interrupt ID331  Priority/Priority Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID330  ,Interrupt ID330   Priority/Priority Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID329  ,Interrupt ID329  Priority/Priority Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID328  ,Interrupt ID328   Priority/Priority Byte Offset 328 "
group.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hexmask.long.byte 0x00 24.--31. 1. " INTID335  ,Interrupt ID335  Priority/Priority Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID334  ,Interrupt ID334   Priority/Priority Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID333  ,Interrupt ID333  Priority/Priority Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID332  ,Interrupt ID332   Priority/Priority Byte Offset 332 "
group.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hexmask.long.byte 0x00 24.--31. 1. " INTID339  ,Interrupt ID339  Priority/Priority Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID338  ,Interrupt ID338   Priority/Priority Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID337  ,Interrupt ID337  Priority/Priority Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID336  ,Interrupt ID336   Priority/Priority Byte Offset 336 "
group.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hexmask.long.byte 0x00 24.--31. 1. " INTID343  ,Interrupt ID343  Priority/Priority Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID342  ,Interrupt ID342   Priority/Priority Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID341  ,Interrupt ID341  Priority/Priority Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID340  ,Interrupt ID340   Priority/Priority Byte Offset 340 "
group.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hexmask.long.byte 0x00 24.--31. 1. " INTID347  ,Interrupt ID347  Priority/Priority Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID346  ,Interrupt ID346   Priority/Priority Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID345  ,Interrupt ID345  Priority/Priority Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID344  ,Interrupt ID344   Priority/Priority Byte Offset 344 "
group.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
hexmask.long.byte 0x00 24.--31. 1. " INTID351  ,Interrupt ID351  Priority/Priority Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID350  ,Interrupt ID350   Priority/Priority Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID349  ,Interrupt ID349  Priority/Priority Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID348  ,Interrupt ID348   Priority/Priority Byte Offset 348 "
else
hgroup.long 0x540++0x03
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hgroup.long 0x544++0x03
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hgroup.long 0x548++0x03
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hgroup.long 0x54C++0x03
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hgroup.long 0x550++0x03
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hgroup.long 0x554++0x03
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hgroup.long 0x558++0x03
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hgroup.long 0x55C++0x03
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hexmask.long.byte 0x00 24.--31. 1. " INTID355  ,Interrupt ID355  Priority/Priority Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID354  ,Interrupt ID354   Priority/Priority Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID353  ,Interrupt ID353  Priority/Priority Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID352  ,Interrupt ID352   Priority/Priority Byte Offset 352 "
group.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hexmask.long.byte 0x00 24.--31. 1. " INTID359  ,Interrupt ID359  Priority/Priority Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID358  ,Interrupt ID358   Priority/Priority Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID357  ,Interrupt ID357  Priority/Priority Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID356  ,Interrupt ID356   Priority/Priority Byte Offset 356 "
group.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hexmask.long.byte 0x00 24.--31. 1. " INTID363  ,Interrupt ID363  Priority/Priority Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID362  ,Interrupt ID362   Priority/Priority Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID361  ,Interrupt ID361  Priority/Priority Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID360  ,Interrupt ID360   Priority/Priority Byte Offset 360 "
group.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hexmask.long.byte 0x00 24.--31. 1. " INTID367  ,Interrupt ID367  Priority/Priority Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID366  ,Interrupt ID366   Priority/Priority Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID365  ,Interrupt ID365  Priority/Priority Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID364  ,Interrupt ID364   Priority/Priority Byte Offset 364 "
group.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hexmask.long.byte 0x00 24.--31. 1. " INTID371  ,Interrupt ID371  Priority/Priority Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID370  ,Interrupt ID370   Priority/Priority Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID369  ,Interrupt ID369  Priority/Priority Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID368  ,Interrupt ID368   Priority/Priority Byte Offset 368 "
group.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hexmask.long.byte 0x00 24.--31. 1. " INTID375  ,Interrupt ID375  Priority/Priority Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID374  ,Interrupt ID374   Priority/Priority Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID373  ,Interrupt ID373  Priority/Priority Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID372  ,Interrupt ID372   Priority/Priority Byte Offset 372 "
group.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hexmask.long.byte 0x00 24.--31. 1. " INTID379  ,Interrupt ID379  Priority/Priority Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID378  ,Interrupt ID378   Priority/Priority Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID377  ,Interrupt ID377  Priority/Priority Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID376  ,Interrupt ID376   Priority/Priority Byte Offset 376 "
group.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
hexmask.long.byte 0x00 24.--31. 1. " INTID383  ,Interrupt ID383  Priority/Priority Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID382  ,Interrupt ID382   Priority/Priority Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID381  ,Interrupt ID381  Priority/Priority Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID380  ,Interrupt ID380   Priority/Priority Byte Offset 380 "
else
hgroup.long 0x560++0x03
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hgroup.long 0x564++0x03
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hgroup.long 0x568++0x03
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hgroup.long 0x56C++0x03
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hgroup.long 0x570++0x03
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hgroup.long 0x574++0x03
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hgroup.long 0x578++0x03
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hgroup.long 0x57C++0x03
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hexmask.long.byte 0x00 24.--31. 1. " INTID387  ,Interrupt ID387  Priority/Priority Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID386  ,Interrupt ID386   Priority/Priority Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID385  ,Interrupt ID385  Priority/Priority Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID384  ,Interrupt ID384   Priority/Priority Byte Offset 384 "
group.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hexmask.long.byte 0x00 24.--31. 1. " INTID391  ,Interrupt ID391  Priority/Priority Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID390  ,Interrupt ID390   Priority/Priority Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID389  ,Interrupt ID389  Priority/Priority Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID388  ,Interrupt ID388   Priority/Priority Byte Offset 388 "
group.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hexmask.long.byte 0x00 24.--31. 1. " INTID395  ,Interrupt ID395  Priority/Priority Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID394  ,Interrupt ID394   Priority/Priority Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID393  ,Interrupt ID393  Priority/Priority Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID392  ,Interrupt ID392   Priority/Priority Byte Offset 392 "
group.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hexmask.long.byte 0x00 24.--31. 1. " INTID399  ,Interrupt ID399  Priority/Priority Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID398  ,Interrupt ID398   Priority/Priority Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID397  ,Interrupt ID397  Priority/Priority Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID396  ,Interrupt ID396   Priority/Priority Byte Offset 396 "
group.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hexmask.long.byte 0x00 24.--31. 1. " INTID403  ,Interrupt ID403  Priority/Priority Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID402  ,Interrupt ID402   Priority/Priority Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID401  ,Interrupt ID401  Priority/Priority Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID400  ,Interrupt ID400   Priority/Priority Byte Offset 400 "
group.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hexmask.long.byte 0x00 24.--31. 1. " INTID407  ,Interrupt ID407  Priority/Priority Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID406  ,Interrupt ID406   Priority/Priority Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID405  ,Interrupt ID405  Priority/Priority Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID404  ,Interrupt ID404   Priority/Priority Byte Offset 404 "
group.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hexmask.long.byte 0x00 24.--31. 1. " INTID411  ,Interrupt ID411  Priority/Priority Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID410  ,Interrupt ID410   Priority/Priority Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID409  ,Interrupt ID409  Priority/Priority Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID408  ,Interrupt ID408   Priority/Priority Byte Offset 408 "
group.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
hexmask.long.byte 0x00 24.--31. 1. " INTID415  ,Interrupt ID415  Priority/Priority Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID414  ,Interrupt ID414   Priority/Priority Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID413  ,Interrupt ID413  Priority/Priority Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID412  ,Interrupt ID412   Priority/Priority Byte Offset 412 "
else
hgroup.long 0x580++0x03
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hgroup.long 0x584++0x03
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hgroup.long 0x588++0x03
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hgroup.long 0x58C++0x03
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hgroup.long 0x590++0x03
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hgroup.long 0x594++0x03
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hgroup.long 0x598++0x03
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hgroup.long 0x59C++0x03
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hexmask.long.byte 0x00 24.--31. 1. " INTID419  ,Interrupt ID419  Priority/Priority Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID418  ,Interrupt ID418   Priority/Priority Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID417  ,Interrupt ID417  Priority/Priority Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID416  ,Interrupt ID416   Priority/Priority Byte Offset 416 "
group.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hexmask.long.byte 0x00 24.--31. 1. " INTID423  ,Interrupt ID423  Priority/Priority Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID422  ,Interrupt ID422   Priority/Priority Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID421  ,Interrupt ID421  Priority/Priority Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID420  ,Interrupt ID420   Priority/Priority Byte Offset 420 "
group.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hexmask.long.byte 0x00 24.--31. 1. " INTID427  ,Interrupt ID427  Priority/Priority Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID426  ,Interrupt ID426   Priority/Priority Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID425  ,Interrupt ID425  Priority/Priority Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID424  ,Interrupt ID424   Priority/Priority Byte Offset 424 "
group.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hexmask.long.byte 0x00 24.--31. 1. " INTID431  ,Interrupt ID431  Priority/Priority Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID430  ,Interrupt ID430   Priority/Priority Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID429  ,Interrupt ID429  Priority/Priority Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID428  ,Interrupt ID428   Priority/Priority Byte Offset 428 "
group.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hexmask.long.byte 0x00 24.--31. 1. " INTID435  ,Interrupt ID435  Priority/Priority Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID434  ,Interrupt ID434   Priority/Priority Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID433  ,Interrupt ID433  Priority/Priority Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID432  ,Interrupt ID432   Priority/Priority Byte Offset 432 "
group.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hexmask.long.byte 0x00 24.--31. 1. " INTID439  ,Interrupt ID439  Priority/Priority Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID438  ,Interrupt ID438   Priority/Priority Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID437  ,Interrupt ID437  Priority/Priority Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID436  ,Interrupt ID436   Priority/Priority Byte Offset 436 "
group.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hexmask.long.byte 0x00 24.--31. 1. " INTID443  ,Interrupt ID443  Priority/Priority Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID442  ,Interrupt ID442   Priority/Priority Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID441  ,Interrupt ID441  Priority/Priority Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID440  ,Interrupt ID440   Priority/Priority Byte Offset 440 "
group.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
hexmask.long.byte 0x00 24.--31. 1. " INTID447  ,Interrupt ID447  Priority/Priority Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID446  ,Interrupt ID446   Priority/Priority Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID445  ,Interrupt ID445  Priority/Priority Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID444  ,Interrupt ID444   Priority/Priority Byte Offset 444 "
else
hgroup.long 0x5A0++0x03
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hgroup.long 0x5A4++0x03
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hgroup.long 0x5A8++0x03
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hgroup.long 0x5AC++0x03
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hgroup.long 0x5B0++0x03
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hgroup.long 0x5B4++0x03
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hgroup.long 0x5B8++0x03
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hgroup.long 0x5BC++0x03
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hexmask.long.byte 0x00 24.--31. 1. " INTID451  ,Interrupt ID451  Priority/Priority Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID450  ,Interrupt ID450   Priority/Priority Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID449  ,Interrupt ID449  Priority/Priority Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID448  ,Interrupt ID448   Priority/Priority Byte Offset 448 "
group.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hexmask.long.byte 0x00 24.--31. 1. " INTID455  ,Interrupt ID455  Priority/Priority Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID454  ,Interrupt ID454   Priority/Priority Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID453  ,Interrupt ID453  Priority/Priority Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID452  ,Interrupt ID452   Priority/Priority Byte Offset 452 "
group.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hexmask.long.byte 0x00 24.--31. 1. " INTID459  ,Interrupt ID459  Priority/Priority Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID458  ,Interrupt ID458   Priority/Priority Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID457  ,Interrupt ID457  Priority/Priority Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID456  ,Interrupt ID456   Priority/Priority Byte Offset 456 "
group.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hexmask.long.byte 0x00 24.--31. 1. " INTID463  ,Interrupt ID463  Priority/Priority Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID462  ,Interrupt ID462   Priority/Priority Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID461  ,Interrupt ID461  Priority/Priority Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID460  ,Interrupt ID460   Priority/Priority Byte Offset 460 "
group.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hexmask.long.byte 0x00 24.--31. 1. " INTID467  ,Interrupt ID467  Priority/Priority Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID466  ,Interrupt ID466   Priority/Priority Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID465  ,Interrupt ID465  Priority/Priority Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID464  ,Interrupt ID464   Priority/Priority Byte Offset 464 "
group.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hexmask.long.byte 0x00 24.--31. 1. " INTID471  ,Interrupt ID471  Priority/Priority Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID470  ,Interrupt ID470   Priority/Priority Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID469  ,Interrupt ID469  Priority/Priority Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID468  ,Interrupt ID468   Priority/Priority Byte Offset 468 "
group.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hexmask.long.byte 0x00 24.--31. 1. " INTID475  ,Interrupt ID475  Priority/Priority Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID474  ,Interrupt ID474   Priority/Priority Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID473  ,Interrupt ID473  Priority/Priority Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID472  ,Interrupt ID472   Priority/Priority Byte Offset 472 "
group.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
hexmask.long.byte 0x00 24.--31. 1. " INTID479  ,Interrupt ID479  Priority/Priority Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID478  ,Interrupt ID478   Priority/Priority Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID477  ,Interrupt ID477  Priority/Priority Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID476  ,Interrupt ID476   Priority/Priority Byte Offset 476 "
else
hgroup.long 0x5C0++0x03
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hgroup.long 0x5C4++0x03
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hgroup.long 0x5C8++0x03
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hgroup.long 0x5CC++0x03
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hgroup.long 0x5D0++0x03
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hgroup.long 0x5D4++0x03
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hgroup.long 0x5D8++0x03
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hgroup.long 0x5DC++0x03
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hexmask.long.byte 0x00 24.--31. 1. " INTID483  ,Interrupt ID483  Priority/Priority Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID482  ,Interrupt ID482   Priority/Priority Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID481  ,Interrupt ID481  Priority/Priority Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID480  ,Interrupt ID480   Priority/Priority Byte Offset 480 "
group.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hexmask.long.byte 0x00 24.--31. 1. " INTID487  ,Interrupt ID487  Priority/Priority Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID486  ,Interrupt ID486   Priority/Priority Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID485  ,Interrupt ID485  Priority/Priority Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID484  ,Interrupt ID484   Priority/Priority Byte Offset 484 "
group.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hexmask.long.byte 0x00 24.--31. 1. " INTID491  ,Interrupt ID491  Priority/Priority Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID490  ,Interrupt ID490   Priority/Priority Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID489  ,Interrupt ID489  Priority/Priority Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID488  ,Interrupt ID488   Priority/Priority Byte Offset 488 "
group.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hexmask.long.byte 0x00 24.--31. 1. " INTID495  ,Interrupt ID495  Priority/Priority Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID494  ,Interrupt ID494   Priority/Priority Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID493  ,Interrupt ID493  Priority/Priority Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID492  ,Interrupt ID492   Priority/Priority Byte Offset 492 "
group.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hexmask.long.byte 0x00 24.--31. 1. " INTID499  ,Interrupt ID499  Priority/Priority Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID498  ,Interrupt ID498   Priority/Priority Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID497  ,Interrupt ID497  Priority/Priority Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID496  ,Interrupt ID496   Priority/Priority Byte Offset 496 "
group.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hexmask.long.byte 0x00 24.--31. 1. " INTID503  ,Interrupt ID503  Priority/Priority Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID502  ,Interrupt ID502   Priority/Priority Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID501  ,Interrupt ID501  Priority/Priority Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID500  ,Interrupt ID500   Priority/Priority Byte Offset 500 "
group.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hexmask.long.byte 0x00 24.--31. 1. " INTID507  ,Interrupt ID507  Priority/Priority Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID506  ,Interrupt ID506   Priority/Priority Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID505  ,Interrupt ID505  Priority/Priority Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID504  ,Interrupt ID504   Priority/Priority Byte Offset 504 "
group.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
hexmask.long.byte 0x00 24.--31. 1. " INTID511  ,Interrupt ID511  Priority/Priority Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID510  ,Interrupt ID510   Priority/Priority Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID509  ,Interrupt ID509  Priority/Priority Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID508  ,Interrupt ID508   Priority/Priority Byte Offset 508 "
else
hgroup.long 0x5E0++0x03
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hgroup.long 0x5E4++0x03
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hgroup.long 0x5E8++0x03
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hgroup.long 0x5EC++0x03
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hgroup.long 0x5F0++0x03
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hgroup.long 0x5F4++0x03
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hgroup.long 0x5F8++0x03
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hgroup.long 0x5FC++0x03
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hexmask.long.byte 0x00 24.--31. 1. " INTID515  ,Interrupt ID515  Priority/Priority Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID514  ,Interrupt ID514   Priority/Priority Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID513  ,Interrupt ID513  Priority/Priority Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID512  ,Interrupt ID512   Priority/Priority Byte Offset 512 "
group.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hexmask.long.byte 0x00 24.--31. 1. " INTID519  ,Interrupt ID519  Priority/Priority Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID518  ,Interrupt ID518   Priority/Priority Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID517  ,Interrupt ID517  Priority/Priority Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID516  ,Interrupt ID516   Priority/Priority Byte Offset 516 "
group.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hexmask.long.byte 0x00 24.--31. 1. " INTID523  ,Interrupt ID523  Priority/Priority Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID522  ,Interrupt ID522   Priority/Priority Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID521  ,Interrupt ID521  Priority/Priority Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID520  ,Interrupt ID520   Priority/Priority Byte Offset 520 "
group.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hexmask.long.byte 0x00 24.--31. 1. " INTID527  ,Interrupt ID527  Priority/Priority Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID526  ,Interrupt ID526   Priority/Priority Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID525  ,Interrupt ID525  Priority/Priority Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID524  ,Interrupt ID524   Priority/Priority Byte Offset 524 "
group.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hexmask.long.byte 0x00 24.--31. 1. " INTID531  ,Interrupt ID531  Priority/Priority Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID530  ,Interrupt ID530   Priority/Priority Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID529  ,Interrupt ID529  Priority/Priority Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID528  ,Interrupt ID528   Priority/Priority Byte Offset 528 "
group.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hexmask.long.byte 0x00 24.--31. 1. " INTID535  ,Interrupt ID535  Priority/Priority Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID534  ,Interrupt ID534   Priority/Priority Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID533  ,Interrupt ID533  Priority/Priority Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID532  ,Interrupt ID532   Priority/Priority Byte Offset 532 "
group.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hexmask.long.byte 0x00 24.--31. 1. " INTID539  ,Interrupt ID539  Priority/Priority Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID538  ,Interrupt ID538   Priority/Priority Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID537  ,Interrupt ID537  Priority/Priority Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID536  ,Interrupt ID536   Priority/Priority Byte Offset 536 "
group.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
hexmask.long.byte 0x00 24.--31. 1. " INTID543  ,Interrupt ID543  Priority/Priority Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID542  ,Interrupt ID542   Priority/Priority Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID541  ,Interrupt ID541  Priority/Priority Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID540  ,Interrupt ID540   Priority/Priority Byte Offset 540 "
else
hgroup.long 0x600++0x03
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hgroup.long 0x604++0x03
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hgroup.long 0x608++0x03
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hgroup.long 0x60C++0x03
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hgroup.long 0x610++0x03
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hgroup.long 0x614++0x03
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hgroup.long 0x618++0x03
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hgroup.long 0x61C++0x03
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hexmask.long.byte 0x00 24.--31. 1. " INTID547  ,Interrupt ID547  Priority/Priority Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID546  ,Interrupt ID546   Priority/Priority Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID545  ,Interrupt ID545  Priority/Priority Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID544  ,Interrupt ID544   Priority/Priority Byte Offset 544 "
group.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hexmask.long.byte 0x00 24.--31. 1. " INTID551  ,Interrupt ID551  Priority/Priority Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID550  ,Interrupt ID550   Priority/Priority Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID549  ,Interrupt ID549  Priority/Priority Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID548  ,Interrupt ID548   Priority/Priority Byte Offset 548 "
group.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hexmask.long.byte 0x00 24.--31. 1. " INTID555  ,Interrupt ID555  Priority/Priority Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID554  ,Interrupt ID554   Priority/Priority Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID553  ,Interrupt ID553  Priority/Priority Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID552  ,Interrupt ID552   Priority/Priority Byte Offset 552 "
group.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hexmask.long.byte 0x00 24.--31. 1. " INTID559  ,Interrupt ID559  Priority/Priority Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID558  ,Interrupt ID558   Priority/Priority Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID557  ,Interrupt ID557  Priority/Priority Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID556  ,Interrupt ID556   Priority/Priority Byte Offset 556 "
group.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hexmask.long.byte 0x00 24.--31. 1. " INTID563  ,Interrupt ID563  Priority/Priority Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID562  ,Interrupt ID562   Priority/Priority Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID561  ,Interrupt ID561  Priority/Priority Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID560  ,Interrupt ID560   Priority/Priority Byte Offset 560 "
group.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hexmask.long.byte 0x00 24.--31. 1. " INTID567  ,Interrupt ID567  Priority/Priority Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID566  ,Interrupt ID566   Priority/Priority Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID565  ,Interrupt ID565  Priority/Priority Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID564  ,Interrupt ID564   Priority/Priority Byte Offset 564 "
group.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hexmask.long.byte 0x00 24.--31. 1. " INTID571  ,Interrupt ID571  Priority/Priority Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID570  ,Interrupt ID570   Priority/Priority Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID569  ,Interrupt ID569  Priority/Priority Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID568  ,Interrupt ID568   Priority/Priority Byte Offset 568 "
group.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
hexmask.long.byte 0x00 24.--31. 1. " INTID575  ,Interrupt ID575  Priority/Priority Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID574  ,Interrupt ID574   Priority/Priority Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID573  ,Interrupt ID573  Priority/Priority Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID572  ,Interrupt ID572   Priority/Priority Byte Offset 572 "
else
hgroup.long 0x620++0x03
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hgroup.long 0x624++0x03
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hgroup.long 0x628++0x03
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hgroup.long 0x62C++0x03
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hgroup.long 0x630++0x03
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hgroup.long 0x634++0x03
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hgroup.long 0x638++0x03
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hgroup.long 0x63C++0x03
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hexmask.long.byte 0x00 24.--31. 1. " INTID579  ,Interrupt ID579  Priority/Priority Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID578  ,Interrupt ID578   Priority/Priority Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID577  ,Interrupt ID577  Priority/Priority Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID576  ,Interrupt ID576   Priority/Priority Byte Offset 576 "
group.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hexmask.long.byte 0x00 24.--31. 1. " INTID583  ,Interrupt ID583  Priority/Priority Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID582  ,Interrupt ID582   Priority/Priority Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID581  ,Interrupt ID581  Priority/Priority Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID580  ,Interrupt ID580   Priority/Priority Byte Offset 580 "
group.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hexmask.long.byte 0x00 24.--31. 1. " INTID587  ,Interrupt ID587  Priority/Priority Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID586  ,Interrupt ID586   Priority/Priority Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID585  ,Interrupt ID585  Priority/Priority Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID584  ,Interrupt ID584   Priority/Priority Byte Offset 584 "
group.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hexmask.long.byte 0x00 24.--31. 1. " INTID591  ,Interrupt ID591  Priority/Priority Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID590  ,Interrupt ID590   Priority/Priority Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID589  ,Interrupt ID589  Priority/Priority Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID588  ,Interrupt ID588   Priority/Priority Byte Offset 588 "
group.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hexmask.long.byte 0x00 24.--31. 1. " INTID595  ,Interrupt ID595  Priority/Priority Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID594  ,Interrupt ID594   Priority/Priority Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID593  ,Interrupt ID593  Priority/Priority Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID592  ,Interrupt ID592   Priority/Priority Byte Offset 592 "
group.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hexmask.long.byte 0x00 24.--31. 1. " INTID599  ,Interrupt ID599  Priority/Priority Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID598  ,Interrupt ID598   Priority/Priority Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID597  ,Interrupt ID597  Priority/Priority Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID596  ,Interrupt ID596   Priority/Priority Byte Offset 596 "
group.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hexmask.long.byte 0x00 24.--31. 1. " INTID603  ,Interrupt ID603  Priority/Priority Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID602  ,Interrupt ID602   Priority/Priority Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID601  ,Interrupt ID601  Priority/Priority Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID600  ,Interrupt ID600   Priority/Priority Byte Offset 600 "
group.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
hexmask.long.byte 0x00 24.--31. 1. " INTID607  ,Interrupt ID607  Priority/Priority Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID606  ,Interrupt ID606   Priority/Priority Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID605  ,Interrupt ID605  Priority/Priority Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID604  ,Interrupt ID604   Priority/Priority Byte Offset 604 "
else
hgroup.long 0x640++0x03
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hgroup.long 0x644++0x03
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hgroup.long 0x648++0x03
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hgroup.long 0x64C++0x03
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hgroup.long 0x650++0x03
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hgroup.long 0x654++0x03
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hgroup.long 0x658++0x03
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hgroup.long 0x65C++0x03
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hexmask.long.byte 0x00 24.--31. 1. " INTID611  ,Interrupt ID611  Priority/Priority Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID610  ,Interrupt ID610   Priority/Priority Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID609  ,Interrupt ID609  Priority/Priority Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID608  ,Interrupt ID608   Priority/Priority Byte Offset 608 "
group.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hexmask.long.byte 0x00 24.--31. 1. " INTID615  ,Interrupt ID615  Priority/Priority Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID614  ,Interrupt ID614   Priority/Priority Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID613  ,Interrupt ID613  Priority/Priority Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID612  ,Interrupt ID612   Priority/Priority Byte Offset 612 "
group.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hexmask.long.byte 0x00 24.--31. 1. " INTID619  ,Interrupt ID619  Priority/Priority Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID618  ,Interrupt ID618   Priority/Priority Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID617  ,Interrupt ID617  Priority/Priority Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID616  ,Interrupt ID616   Priority/Priority Byte Offset 616 "
group.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hexmask.long.byte 0x00 24.--31. 1. " INTID623  ,Interrupt ID623  Priority/Priority Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID622  ,Interrupt ID622   Priority/Priority Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID621  ,Interrupt ID621  Priority/Priority Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID620  ,Interrupt ID620   Priority/Priority Byte Offset 620 "
group.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hexmask.long.byte 0x00 24.--31. 1. " INTID627  ,Interrupt ID627  Priority/Priority Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID626  ,Interrupt ID626   Priority/Priority Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID625  ,Interrupt ID625  Priority/Priority Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID624  ,Interrupt ID624   Priority/Priority Byte Offset 624 "
group.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hexmask.long.byte 0x00 24.--31. 1. " INTID631  ,Interrupt ID631  Priority/Priority Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID630  ,Interrupt ID630   Priority/Priority Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID629  ,Interrupt ID629  Priority/Priority Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID628  ,Interrupt ID628   Priority/Priority Byte Offset 628 "
group.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hexmask.long.byte 0x00 24.--31. 1. " INTID635  ,Interrupt ID635  Priority/Priority Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID634  ,Interrupt ID634   Priority/Priority Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID633  ,Interrupt ID633  Priority/Priority Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID632  ,Interrupt ID632   Priority/Priority Byte Offset 632 "
group.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
hexmask.long.byte 0x00 24.--31. 1. " INTID639  ,Interrupt ID639  Priority/Priority Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID638  ,Interrupt ID638   Priority/Priority Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID637  ,Interrupt ID637  Priority/Priority Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID636  ,Interrupt ID636   Priority/Priority Byte Offset 636 "
else
hgroup.long 0x660++0x03
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hgroup.long 0x664++0x03
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hgroup.long 0x668++0x03
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hgroup.long 0x66C++0x03
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hgroup.long 0x670++0x03
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hgroup.long 0x674++0x03
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hgroup.long 0x678++0x03
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hgroup.long 0x67C++0x03
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hexmask.long.byte 0x00 24.--31. 1. " INTID643  ,Interrupt ID643  Priority/Priority Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID642  ,Interrupt ID642   Priority/Priority Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID641  ,Interrupt ID641  Priority/Priority Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID640  ,Interrupt ID640   Priority/Priority Byte Offset 640 "
group.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hexmask.long.byte 0x00 24.--31. 1. " INTID647  ,Interrupt ID647  Priority/Priority Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID646  ,Interrupt ID646   Priority/Priority Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID645  ,Interrupt ID645  Priority/Priority Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID644  ,Interrupt ID644   Priority/Priority Byte Offset 644 "
group.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hexmask.long.byte 0x00 24.--31. 1. " INTID651  ,Interrupt ID651  Priority/Priority Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID650  ,Interrupt ID650   Priority/Priority Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID649  ,Interrupt ID649  Priority/Priority Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID648  ,Interrupt ID648   Priority/Priority Byte Offset 648 "
group.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hexmask.long.byte 0x00 24.--31. 1. " INTID655  ,Interrupt ID655  Priority/Priority Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID654  ,Interrupt ID654   Priority/Priority Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID653  ,Interrupt ID653  Priority/Priority Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID652  ,Interrupt ID652   Priority/Priority Byte Offset 652 "
group.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hexmask.long.byte 0x00 24.--31. 1. " INTID659  ,Interrupt ID659  Priority/Priority Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID658  ,Interrupt ID658   Priority/Priority Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID657  ,Interrupt ID657  Priority/Priority Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID656  ,Interrupt ID656   Priority/Priority Byte Offset 656 "
group.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hexmask.long.byte 0x00 24.--31. 1. " INTID663  ,Interrupt ID663  Priority/Priority Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID662  ,Interrupt ID662   Priority/Priority Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID661  ,Interrupt ID661  Priority/Priority Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID660  ,Interrupt ID660   Priority/Priority Byte Offset 660 "
group.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hexmask.long.byte 0x00 24.--31. 1. " INTID667  ,Interrupt ID667  Priority/Priority Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID666  ,Interrupt ID666   Priority/Priority Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID665  ,Interrupt ID665  Priority/Priority Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID664  ,Interrupt ID664   Priority/Priority Byte Offset 664 "
group.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
hexmask.long.byte 0x00 24.--31. 1. " INTID671  ,Interrupt ID671  Priority/Priority Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID670  ,Interrupt ID670   Priority/Priority Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID669  ,Interrupt ID669  Priority/Priority Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID668  ,Interrupt ID668   Priority/Priority Byte Offset 668 "
else
hgroup.long 0x680++0x03
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hgroup.long 0x684++0x03
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hgroup.long 0x688++0x03
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hgroup.long 0x68C++0x03
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hgroup.long 0x690++0x03
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hgroup.long 0x694++0x03
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hgroup.long 0x698++0x03
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hgroup.long 0x69C++0x03
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hexmask.long.byte 0x00 24.--31. 1. " INTID675  ,Interrupt ID675  Priority/Priority Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID674  ,Interrupt ID674   Priority/Priority Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID673  ,Interrupt ID673  Priority/Priority Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID672  ,Interrupt ID672   Priority/Priority Byte Offset 672 "
group.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hexmask.long.byte 0x00 24.--31. 1. " INTID679  ,Interrupt ID679  Priority/Priority Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID678  ,Interrupt ID678   Priority/Priority Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID677  ,Interrupt ID677  Priority/Priority Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID676  ,Interrupt ID676   Priority/Priority Byte Offset 676 "
group.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hexmask.long.byte 0x00 24.--31. 1. " INTID683  ,Interrupt ID683  Priority/Priority Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID682  ,Interrupt ID682   Priority/Priority Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID681  ,Interrupt ID681  Priority/Priority Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID680  ,Interrupt ID680   Priority/Priority Byte Offset 680 "
group.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hexmask.long.byte 0x00 24.--31. 1. " INTID687  ,Interrupt ID687  Priority/Priority Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID686  ,Interrupt ID686   Priority/Priority Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID685  ,Interrupt ID685  Priority/Priority Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID684  ,Interrupt ID684   Priority/Priority Byte Offset 684 "
group.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hexmask.long.byte 0x00 24.--31. 1. " INTID691  ,Interrupt ID691  Priority/Priority Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID690  ,Interrupt ID690   Priority/Priority Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID689  ,Interrupt ID689  Priority/Priority Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID688  ,Interrupt ID688   Priority/Priority Byte Offset 688 "
group.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hexmask.long.byte 0x00 24.--31. 1. " INTID695  ,Interrupt ID695  Priority/Priority Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID694  ,Interrupt ID694   Priority/Priority Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID693  ,Interrupt ID693  Priority/Priority Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID692  ,Interrupt ID692   Priority/Priority Byte Offset 692 "
group.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hexmask.long.byte 0x00 24.--31. 1. " INTID699  ,Interrupt ID699  Priority/Priority Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID698  ,Interrupt ID698   Priority/Priority Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID697  ,Interrupt ID697  Priority/Priority Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID696  ,Interrupt ID696   Priority/Priority Byte Offset 696 "
group.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
hexmask.long.byte 0x00 24.--31. 1. " INTID703  ,Interrupt ID703  Priority/Priority Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID702  ,Interrupt ID702   Priority/Priority Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID701  ,Interrupt ID701  Priority/Priority Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID700  ,Interrupt ID700   Priority/Priority Byte Offset 700 "
else
hgroup.long 0x6A0++0x03
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hgroup.long 0x6A4++0x03
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hgroup.long 0x6A8++0x03
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hgroup.long 0x6AC++0x03
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hgroup.long 0x6B0++0x03
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hgroup.long 0x6B4++0x03
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hgroup.long 0x6B8++0x03
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hgroup.long 0x6BC++0x03
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hexmask.long.byte 0x00 24.--31. 1. " INTID707  ,Interrupt ID707  Priority/Priority Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID706  ,Interrupt ID706   Priority/Priority Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID705  ,Interrupt ID705  Priority/Priority Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID704  ,Interrupt ID704   Priority/Priority Byte Offset 704 "
group.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hexmask.long.byte 0x00 24.--31. 1. " INTID711  ,Interrupt ID711  Priority/Priority Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID710  ,Interrupt ID710   Priority/Priority Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID709  ,Interrupt ID709  Priority/Priority Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID708  ,Interrupt ID708   Priority/Priority Byte Offset 708 "
group.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hexmask.long.byte 0x00 24.--31. 1. " INTID715  ,Interrupt ID715  Priority/Priority Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID714  ,Interrupt ID714   Priority/Priority Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID713  ,Interrupt ID713  Priority/Priority Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID712  ,Interrupt ID712   Priority/Priority Byte Offset 712 "
group.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hexmask.long.byte 0x00 24.--31. 1. " INTID719  ,Interrupt ID719  Priority/Priority Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID718  ,Interrupt ID718   Priority/Priority Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID717  ,Interrupt ID717  Priority/Priority Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID716  ,Interrupt ID716   Priority/Priority Byte Offset 716 "
group.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hexmask.long.byte 0x00 24.--31. 1. " INTID723  ,Interrupt ID723  Priority/Priority Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID722  ,Interrupt ID722   Priority/Priority Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID721  ,Interrupt ID721  Priority/Priority Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID720  ,Interrupt ID720   Priority/Priority Byte Offset 720 "
group.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hexmask.long.byte 0x00 24.--31. 1. " INTID727  ,Interrupt ID727  Priority/Priority Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID726  ,Interrupt ID726   Priority/Priority Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID725  ,Interrupt ID725  Priority/Priority Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID724  ,Interrupt ID724   Priority/Priority Byte Offset 724 "
group.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hexmask.long.byte 0x00 24.--31. 1. " INTID731  ,Interrupt ID731  Priority/Priority Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID730  ,Interrupt ID730   Priority/Priority Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID729  ,Interrupt ID729  Priority/Priority Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID728  ,Interrupt ID728   Priority/Priority Byte Offset 728 "
group.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
hexmask.long.byte 0x00 24.--31. 1. " INTID735  ,Interrupt ID735  Priority/Priority Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID734  ,Interrupt ID734   Priority/Priority Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID733  ,Interrupt ID733  Priority/Priority Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID732  ,Interrupt ID732   Priority/Priority Byte Offset 732 "
else
hgroup.long 0x6C0++0x03
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hgroup.long 0x6C4++0x03
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hgroup.long 0x6C8++0x03
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hgroup.long 0x6CC++0x03
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hgroup.long 0x6D0++0x03
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hgroup.long 0x6D4++0x03
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hgroup.long 0x6D8++0x03
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hgroup.long 0x6DC++0x03
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hexmask.long.byte 0x00 24.--31. 1. " INTID739  ,Interrupt ID739  Priority/Priority Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID738  ,Interrupt ID738   Priority/Priority Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID737  ,Interrupt ID737  Priority/Priority Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID736  ,Interrupt ID736   Priority/Priority Byte Offset 736 "
group.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hexmask.long.byte 0x00 24.--31. 1. " INTID743  ,Interrupt ID743  Priority/Priority Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID742  ,Interrupt ID742   Priority/Priority Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID741  ,Interrupt ID741  Priority/Priority Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID740  ,Interrupt ID740   Priority/Priority Byte Offset 740 "
group.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hexmask.long.byte 0x00 24.--31. 1. " INTID747  ,Interrupt ID747  Priority/Priority Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID746  ,Interrupt ID746   Priority/Priority Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID745  ,Interrupt ID745  Priority/Priority Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID744  ,Interrupt ID744   Priority/Priority Byte Offset 744 "
group.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hexmask.long.byte 0x00 24.--31. 1. " INTID751  ,Interrupt ID751  Priority/Priority Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID750  ,Interrupt ID750   Priority/Priority Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID749  ,Interrupt ID749  Priority/Priority Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID748  ,Interrupt ID748   Priority/Priority Byte Offset 748 "
group.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hexmask.long.byte 0x00 24.--31. 1. " INTID755  ,Interrupt ID755  Priority/Priority Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID754  ,Interrupt ID754   Priority/Priority Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID753  ,Interrupt ID753  Priority/Priority Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID752  ,Interrupt ID752   Priority/Priority Byte Offset 752 "
group.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hexmask.long.byte 0x00 24.--31. 1. " INTID759  ,Interrupt ID759  Priority/Priority Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID758  ,Interrupt ID758   Priority/Priority Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID757  ,Interrupt ID757  Priority/Priority Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID756  ,Interrupt ID756   Priority/Priority Byte Offset 756 "
group.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hexmask.long.byte 0x00 24.--31. 1. " INTID763  ,Interrupt ID763  Priority/Priority Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID762  ,Interrupt ID762   Priority/Priority Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID761  ,Interrupt ID761  Priority/Priority Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID760  ,Interrupt ID760   Priority/Priority Byte Offset 760 "
group.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
hexmask.long.byte 0x00 24.--31. 1. " INTID767  ,Interrupt ID767  Priority/Priority Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID766  ,Interrupt ID766   Priority/Priority Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID765  ,Interrupt ID765  Priority/Priority Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID764  ,Interrupt ID764   Priority/Priority Byte Offset 764 "
else
hgroup.long 0x6E0++0x03
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hgroup.long 0x6E4++0x03
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hgroup.long 0x6E8++0x03
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hgroup.long 0x6EC++0x03
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hgroup.long 0x6F0++0x03
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hgroup.long 0x6F4++0x03
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hgroup.long 0x6F8++0x03
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hgroup.long 0x6FC++0x03
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hexmask.long.byte 0x00 24.--31. 1. " INTID771  ,Interrupt ID771  Priority/Priority Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID770  ,Interrupt ID770   Priority/Priority Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID769  ,Interrupt ID769  Priority/Priority Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID768  ,Interrupt ID768   Priority/Priority Byte Offset 768 "
group.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hexmask.long.byte 0x00 24.--31. 1. " INTID775  ,Interrupt ID775  Priority/Priority Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID774  ,Interrupt ID774   Priority/Priority Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID773  ,Interrupt ID773  Priority/Priority Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID772  ,Interrupt ID772   Priority/Priority Byte Offset 772 "
group.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hexmask.long.byte 0x00 24.--31. 1. " INTID779  ,Interrupt ID779  Priority/Priority Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID778  ,Interrupt ID778   Priority/Priority Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID777  ,Interrupt ID777  Priority/Priority Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID776  ,Interrupt ID776   Priority/Priority Byte Offset 776 "
group.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hexmask.long.byte 0x00 24.--31. 1. " INTID783  ,Interrupt ID783  Priority/Priority Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID782  ,Interrupt ID782   Priority/Priority Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID781  ,Interrupt ID781  Priority/Priority Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID780  ,Interrupt ID780   Priority/Priority Byte Offset 780 "
group.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hexmask.long.byte 0x00 24.--31. 1. " INTID787  ,Interrupt ID787  Priority/Priority Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID786  ,Interrupt ID786   Priority/Priority Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID785  ,Interrupt ID785  Priority/Priority Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID784  ,Interrupt ID784   Priority/Priority Byte Offset 784 "
group.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hexmask.long.byte 0x00 24.--31. 1. " INTID791  ,Interrupt ID791  Priority/Priority Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID790  ,Interrupt ID790   Priority/Priority Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID789  ,Interrupt ID789  Priority/Priority Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID788  ,Interrupt ID788   Priority/Priority Byte Offset 788 "
group.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hexmask.long.byte 0x00 24.--31. 1. " INTID795  ,Interrupt ID795  Priority/Priority Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID794  ,Interrupt ID794   Priority/Priority Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID793  ,Interrupt ID793  Priority/Priority Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID792  ,Interrupt ID792   Priority/Priority Byte Offset 792 "
group.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
hexmask.long.byte 0x00 24.--31. 1. " INTID799  ,Interrupt ID799  Priority/Priority Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID798  ,Interrupt ID798   Priority/Priority Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID797  ,Interrupt ID797  Priority/Priority Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID796  ,Interrupt ID796   Priority/Priority Byte Offset 796 "
else
hgroup.long 0x700++0x03
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hgroup.long 0x704++0x03
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hgroup.long 0x708++0x03
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hgroup.long 0x70C++0x03
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hgroup.long 0x710++0x03
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hgroup.long 0x714++0x03
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hgroup.long 0x718++0x03
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hgroup.long 0x71C++0x03
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hexmask.long.byte 0x00 24.--31. 1. " INTID803  ,Interrupt ID803  Priority/Priority Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID802  ,Interrupt ID802   Priority/Priority Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID801  ,Interrupt ID801  Priority/Priority Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID800  ,Interrupt ID800   Priority/Priority Byte Offset 800 "
group.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hexmask.long.byte 0x00 24.--31. 1. " INTID807  ,Interrupt ID807  Priority/Priority Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID806  ,Interrupt ID806   Priority/Priority Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID805  ,Interrupt ID805  Priority/Priority Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID804  ,Interrupt ID804   Priority/Priority Byte Offset 804 "
group.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hexmask.long.byte 0x00 24.--31. 1. " INTID811  ,Interrupt ID811  Priority/Priority Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID810  ,Interrupt ID810   Priority/Priority Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID809  ,Interrupt ID809  Priority/Priority Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID808  ,Interrupt ID808   Priority/Priority Byte Offset 808 "
group.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hexmask.long.byte 0x00 24.--31. 1. " INTID815  ,Interrupt ID815  Priority/Priority Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID814  ,Interrupt ID814   Priority/Priority Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID813  ,Interrupt ID813  Priority/Priority Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID812  ,Interrupt ID812   Priority/Priority Byte Offset 812 "
group.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hexmask.long.byte 0x00 24.--31. 1. " INTID819  ,Interrupt ID819  Priority/Priority Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID818  ,Interrupt ID818   Priority/Priority Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID817  ,Interrupt ID817  Priority/Priority Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID816  ,Interrupt ID816   Priority/Priority Byte Offset 816 "
group.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hexmask.long.byte 0x00 24.--31. 1. " INTID823  ,Interrupt ID823  Priority/Priority Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID822  ,Interrupt ID822   Priority/Priority Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID821  ,Interrupt ID821  Priority/Priority Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID820  ,Interrupt ID820   Priority/Priority Byte Offset 820 "
group.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hexmask.long.byte 0x00 24.--31. 1. " INTID827  ,Interrupt ID827  Priority/Priority Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID826  ,Interrupt ID826   Priority/Priority Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID825  ,Interrupt ID825  Priority/Priority Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID824  ,Interrupt ID824   Priority/Priority Byte Offset 824 "
group.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
hexmask.long.byte 0x00 24.--31. 1. " INTID831  ,Interrupt ID831  Priority/Priority Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID830  ,Interrupt ID830   Priority/Priority Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID829  ,Interrupt ID829  Priority/Priority Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID828  ,Interrupt ID828   Priority/Priority Byte Offset 828 "
else
hgroup.long 0x720++0x03
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hgroup.long 0x724++0x03
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hgroup.long 0x728++0x03
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hgroup.long 0x72C++0x03
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hgroup.long 0x730++0x03
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hgroup.long 0x734++0x03
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hgroup.long 0x738++0x03
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hgroup.long 0x73C++0x03
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hexmask.long.byte 0x00 24.--31. 1. " INTID835  ,Interrupt ID835  Priority/Priority Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID834  ,Interrupt ID834   Priority/Priority Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID833  ,Interrupt ID833  Priority/Priority Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID832  ,Interrupt ID832   Priority/Priority Byte Offset 832 "
group.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hexmask.long.byte 0x00 24.--31. 1. " INTID839  ,Interrupt ID839  Priority/Priority Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID838  ,Interrupt ID838   Priority/Priority Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID837  ,Interrupt ID837  Priority/Priority Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID836  ,Interrupt ID836   Priority/Priority Byte Offset 836 "
group.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hexmask.long.byte 0x00 24.--31. 1. " INTID843  ,Interrupt ID843  Priority/Priority Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID842  ,Interrupt ID842   Priority/Priority Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID841  ,Interrupt ID841  Priority/Priority Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID840  ,Interrupt ID840   Priority/Priority Byte Offset 840 "
group.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hexmask.long.byte 0x00 24.--31. 1. " INTID847  ,Interrupt ID847  Priority/Priority Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID846  ,Interrupt ID846   Priority/Priority Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID845  ,Interrupt ID845  Priority/Priority Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID844  ,Interrupt ID844   Priority/Priority Byte Offset 844 "
group.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hexmask.long.byte 0x00 24.--31. 1. " INTID851  ,Interrupt ID851  Priority/Priority Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID850  ,Interrupt ID850   Priority/Priority Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID849  ,Interrupt ID849  Priority/Priority Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID848  ,Interrupt ID848   Priority/Priority Byte Offset 848 "
group.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hexmask.long.byte 0x00 24.--31. 1. " INTID855  ,Interrupt ID855  Priority/Priority Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID854  ,Interrupt ID854   Priority/Priority Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID853  ,Interrupt ID853  Priority/Priority Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID852  ,Interrupt ID852   Priority/Priority Byte Offset 852 "
group.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hexmask.long.byte 0x00 24.--31. 1. " INTID859  ,Interrupt ID859  Priority/Priority Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID858  ,Interrupt ID858   Priority/Priority Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID857  ,Interrupt ID857  Priority/Priority Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID856  ,Interrupt ID856   Priority/Priority Byte Offset 856 "
group.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
hexmask.long.byte 0x00 24.--31. 1. " INTID863  ,Interrupt ID863  Priority/Priority Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID862  ,Interrupt ID862   Priority/Priority Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID861  ,Interrupt ID861  Priority/Priority Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID860  ,Interrupt ID860   Priority/Priority Byte Offset 860 "
else
hgroup.long 0x740++0x03
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hgroup.long 0x744++0x03
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hgroup.long 0x748++0x03
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hgroup.long 0x74C++0x03
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hgroup.long 0x750++0x03
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hgroup.long 0x754++0x03
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hgroup.long 0x758++0x03
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hgroup.long 0x75C++0x03
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hexmask.long.byte 0x00 24.--31. 1. " INTID867  ,Interrupt ID867  Priority/Priority Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID866  ,Interrupt ID866   Priority/Priority Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID865  ,Interrupt ID865  Priority/Priority Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID864  ,Interrupt ID864   Priority/Priority Byte Offset 864 "
group.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hexmask.long.byte 0x00 24.--31. 1. " INTID871  ,Interrupt ID871  Priority/Priority Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID870  ,Interrupt ID870   Priority/Priority Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID869  ,Interrupt ID869  Priority/Priority Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID868  ,Interrupt ID868   Priority/Priority Byte Offset 868 "
group.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hexmask.long.byte 0x00 24.--31. 1. " INTID875  ,Interrupt ID875  Priority/Priority Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID874  ,Interrupt ID874   Priority/Priority Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID873  ,Interrupt ID873  Priority/Priority Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID872  ,Interrupt ID872   Priority/Priority Byte Offset 872 "
group.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hexmask.long.byte 0x00 24.--31. 1. " INTID879  ,Interrupt ID879  Priority/Priority Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID878  ,Interrupt ID878   Priority/Priority Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID877  ,Interrupt ID877  Priority/Priority Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID876  ,Interrupt ID876   Priority/Priority Byte Offset 876 "
group.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hexmask.long.byte 0x00 24.--31. 1. " INTID883  ,Interrupt ID883  Priority/Priority Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID882  ,Interrupt ID882   Priority/Priority Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID881  ,Interrupt ID881  Priority/Priority Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID880  ,Interrupt ID880   Priority/Priority Byte Offset 880 "
group.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hexmask.long.byte 0x00 24.--31. 1. " INTID887  ,Interrupt ID887  Priority/Priority Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID886  ,Interrupt ID886   Priority/Priority Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID885  ,Interrupt ID885  Priority/Priority Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID884  ,Interrupt ID884   Priority/Priority Byte Offset 884 "
group.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hexmask.long.byte 0x00 24.--31. 1. " INTID891  ,Interrupt ID891  Priority/Priority Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID890  ,Interrupt ID890   Priority/Priority Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID889  ,Interrupt ID889  Priority/Priority Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID888  ,Interrupt ID888   Priority/Priority Byte Offset 888 "
group.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
hexmask.long.byte 0x00 24.--31. 1. " INTID895  ,Interrupt ID895  Priority/Priority Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID894  ,Interrupt ID894   Priority/Priority Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID893  ,Interrupt ID893  Priority/Priority Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID892  ,Interrupt ID892   Priority/Priority Byte Offset 892 "
else
hgroup.long 0x760++0x03
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hgroup.long 0x764++0x03
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hgroup.long 0x768++0x03
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hgroup.long 0x76C++0x03
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hgroup.long 0x770++0x03
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hgroup.long 0x774++0x03
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hgroup.long 0x778++0x03
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hgroup.long 0x77C++0x03
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hexmask.long.byte 0x00 24.--31. 1. " INTID899  ,Interrupt ID899  Priority/Priority Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID898  ,Interrupt ID898   Priority/Priority Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID897  ,Interrupt ID897  Priority/Priority Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID896  ,Interrupt ID896   Priority/Priority Byte Offset 896 "
group.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hexmask.long.byte 0x00 24.--31. 1. " INTID903  ,Interrupt ID903  Priority/Priority Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID902  ,Interrupt ID902   Priority/Priority Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID901  ,Interrupt ID901  Priority/Priority Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID900  ,Interrupt ID900   Priority/Priority Byte Offset 900 "
group.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hexmask.long.byte 0x00 24.--31. 1. " INTID907  ,Interrupt ID907  Priority/Priority Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID906  ,Interrupt ID906   Priority/Priority Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID905  ,Interrupt ID905  Priority/Priority Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID904  ,Interrupt ID904   Priority/Priority Byte Offset 904 "
group.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hexmask.long.byte 0x00 24.--31. 1. " INTID911  ,Interrupt ID911  Priority/Priority Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID910  ,Interrupt ID910   Priority/Priority Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID909  ,Interrupt ID909  Priority/Priority Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID908  ,Interrupt ID908   Priority/Priority Byte Offset 908 "
group.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hexmask.long.byte 0x00 24.--31. 1. " INTID915  ,Interrupt ID915  Priority/Priority Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID914  ,Interrupt ID914   Priority/Priority Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID913  ,Interrupt ID913  Priority/Priority Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID912  ,Interrupt ID912   Priority/Priority Byte Offset 912 "
group.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hexmask.long.byte 0x00 24.--31. 1. " INTID919  ,Interrupt ID919  Priority/Priority Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID918  ,Interrupt ID918   Priority/Priority Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID917  ,Interrupt ID917  Priority/Priority Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID916  ,Interrupt ID916   Priority/Priority Byte Offset 916 "
group.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hexmask.long.byte 0x00 24.--31. 1. " INTID923  ,Interrupt ID923  Priority/Priority Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID922  ,Interrupt ID922   Priority/Priority Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID921  ,Interrupt ID921  Priority/Priority Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID920  ,Interrupt ID920   Priority/Priority Byte Offset 920 "
group.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
hexmask.long.byte 0x00 24.--31. 1. " INTID927  ,Interrupt ID927  Priority/Priority Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID926  ,Interrupt ID926   Priority/Priority Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID925  ,Interrupt ID925  Priority/Priority Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID924  ,Interrupt ID924   Priority/Priority Byte Offset 924 "
else
hgroup.long 0x780++0x03
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hgroup.long 0x784++0x03
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hgroup.long 0x788++0x03
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hgroup.long 0x78C++0x03
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hgroup.long 0x790++0x03
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hgroup.long 0x794++0x03
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hgroup.long 0x798++0x03
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hgroup.long 0x79C++0x03
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hexmask.long.byte 0x00 24.--31. 1. " INTID931  ,Interrupt ID931  Priority/Priority Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID930  ,Interrupt ID930   Priority/Priority Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID929  ,Interrupt ID929  Priority/Priority Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID928  ,Interrupt ID928   Priority/Priority Byte Offset 928 "
group.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hexmask.long.byte 0x00 24.--31. 1. " INTID935  ,Interrupt ID935  Priority/Priority Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID934  ,Interrupt ID934   Priority/Priority Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID933  ,Interrupt ID933  Priority/Priority Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID932  ,Interrupt ID932   Priority/Priority Byte Offset 932 "
group.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hexmask.long.byte 0x00 24.--31. 1. " INTID939  ,Interrupt ID939  Priority/Priority Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID938  ,Interrupt ID938   Priority/Priority Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID937  ,Interrupt ID937  Priority/Priority Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID936  ,Interrupt ID936   Priority/Priority Byte Offset 936 "
group.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hexmask.long.byte 0x00 24.--31. 1. " INTID943  ,Interrupt ID943  Priority/Priority Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID942  ,Interrupt ID942   Priority/Priority Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID941  ,Interrupt ID941  Priority/Priority Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID940  ,Interrupt ID940   Priority/Priority Byte Offset 940 "
group.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hexmask.long.byte 0x00 24.--31. 1. " INTID947  ,Interrupt ID947  Priority/Priority Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID946  ,Interrupt ID946   Priority/Priority Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID945  ,Interrupt ID945  Priority/Priority Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID944  ,Interrupt ID944   Priority/Priority Byte Offset 944 "
group.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hexmask.long.byte 0x00 24.--31. 1. " INTID951  ,Interrupt ID951  Priority/Priority Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID950  ,Interrupt ID950   Priority/Priority Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID949  ,Interrupt ID949  Priority/Priority Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID948  ,Interrupt ID948   Priority/Priority Byte Offset 948 "
group.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hexmask.long.byte 0x00 24.--31. 1. " INTID955  ,Interrupt ID955  Priority/Priority Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID954  ,Interrupt ID954   Priority/Priority Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID953  ,Interrupt ID953  Priority/Priority Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID952  ,Interrupt ID952   Priority/Priority Byte Offset 952 "
group.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
hexmask.long.byte 0x00 24.--31. 1. " INTID959  ,Interrupt ID959  Priority/Priority Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID958  ,Interrupt ID958   Priority/Priority Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID957  ,Interrupt ID957  Priority/Priority Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID956  ,Interrupt ID956   Priority/Priority Byte Offset 956 "
else
hgroup.long 0x7A0++0x03
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hgroup.long 0x7A4++0x03
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hgroup.long 0x7A8++0x03
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hgroup.long 0x7AC++0x03
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hgroup.long 0x7B0++0x03
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hgroup.long 0x7B4++0x03
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hgroup.long 0x7B8++0x03
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hgroup.long 0x7BC++0x03
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hexmask.long.byte 0x00 24.--31. 1. " INTID963  ,Interrupt ID963  Priority/Priority Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID962  ,Interrupt ID962   Priority/Priority Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID961  ,Interrupt ID961  Priority/Priority Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID960  ,Interrupt ID960   Priority/Priority Byte Offset 960 "
group.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hexmask.long.byte 0x00 24.--31. 1. " INTID967  ,Interrupt ID967  Priority/Priority Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID966  ,Interrupt ID966   Priority/Priority Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID965  ,Interrupt ID965  Priority/Priority Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID964  ,Interrupt ID964   Priority/Priority Byte Offset 964 "
group.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hexmask.long.byte 0x00 24.--31. 1. " INTID971  ,Interrupt ID971  Priority/Priority Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID970  ,Interrupt ID970   Priority/Priority Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID969  ,Interrupt ID969  Priority/Priority Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID968  ,Interrupt ID968   Priority/Priority Byte Offset 968 "
group.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hexmask.long.byte 0x00 24.--31. 1. " INTID975  ,Interrupt ID975  Priority/Priority Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID974  ,Interrupt ID974   Priority/Priority Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID973  ,Interrupt ID973  Priority/Priority Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID972  ,Interrupt ID972   Priority/Priority Byte Offset 972 "
group.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hexmask.long.byte 0x00 24.--31. 1. " INTID979  ,Interrupt ID979  Priority/Priority Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID978  ,Interrupt ID978   Priority/Priority Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID977  ,Interrupt ID977  Priority/Priority Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID976  ,Interrupt ID976   Priority/Priority Byte Offset 976 "
group.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hexmask.long.byte 0x00 24.--31. 1. " INTID983  ,Interrupt ID983  Priority/Priority Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID982  ,Interrupt ID982   Priority/Priority Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID981  ,Interrupt ID981  Priority/Priority Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID980  ,Interrupt ID980   Priority/Priority Byte Offset 980 "
group.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hexmask.long.byte 0x00 24.--31. 1. " INTID987  ,Interrupt ID987  Priority/Priority Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID986  ,Interrupt ID986   Priority/Priority Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID985  ,Interrupt ID985  Priority/Priority Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID984  ,Interrupt ID984   Priority/Priority Byte Offset 984 "
group.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
hexmask.long.byte 0x00 24.--31. 1. " INTID991  ,Interrupt ID991  Priority/Priority Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID990  ,Interrupt ID990   Priority/Priority Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID989  ,Interrupt ID989  Priority/Priority Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID988  ,Interrupt ID988   Priority/Priority Byte Offset 988 "
else
hgroup.long 0x7C0++0x03
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hgroup.long 0x7C4++0x03
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hgroup.long 0x7C8++0x03
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hgroup.long 0x7CC++0x03
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hgroup.long 0x7D0++0x03
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hgroup.long 0x7D4++0x03
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hgroup.long 0x7D8++0x03
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hgroup.long 0x7DC++0x03
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
endif
tree.end
width 19.
tree "Interrupt Targets Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1)
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35   ,CPU Targets Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO34   ,CPU Targets Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO33   ,CPU Targets Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO32   ,CPU Targets Byte Offset 32  "
group.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39   ,CPU Targets Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO38   ,CPU Targets Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO37   ,CPU Targets Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO36   ,CPU Targets Byte Offset 36  "
group.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43   ,CPU Targets Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO42   ,CPU Targets Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO41   ,CPU Targets Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO40   ,CPU Targets Byte Offset 40  "
group.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47   ,CPU Targets Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO46   ,CPU Targets Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO45   ,CPU Targets Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO44   ,CPU Targets Byte Offset 44  "
group.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51   ,CPU Targets Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO50   ,CPU Targets Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO49   ,CPU Targets Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO48   ,CPU Targets Byte Offset 48  "
group.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55   ,CPU Targets Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO54   ,CPU Targets Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO53   ,CPU Targets Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO52   ,CPU Targets Byte Offset 52  "
group.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59   ,CPU Targets Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO58   ,CPU Targets Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO57   ,CPU Targets Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO56   ,CPU Targets Byte Offset 56  "
group.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63   ,CPU Targets Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO62   ,CPU Targets Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO61   ,CPU Targets Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO60   ,CPU Targets Byte Offset 60  "
else
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67   ,CPU Targets Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO66   ,CPU Targets Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO65   ,CPU Targets Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO64   ,CPU Targets Byte Offset 64  "
group.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71   ,CPU Targets Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO70   ,CPU Targets Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO69   ,CPU Targets Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO68   ,CPU Targets Byte Offset 68  "
group.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75   ,CPU Targets Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO74   ,CPU Targets Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO73   ,CPU Targets Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO72   ,CPU Targets Byte Offset 72  "
group.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79   ,CPU Targets Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO78   ,CPU Targets Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO77   ,CPU Targets Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO76   ,CPU Targets Byte Offset 76  "
group.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83   ,CPU Targets Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO82   ,CPU Targets Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO81   ,CPU Targets Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO80   ,CPU Targets Byte Offset 80  "
group.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87   ,CPU Targets Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO86   ,CPU Targets Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO85   ,CPU Targets Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO84   ,CPU Targets Byte Offset 84  "
group.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91   ,CPU Targets Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO90   ,CPU Targets Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO89   ,CPU Targets Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO88   ,CPU Targets Byte Offset 88  "
group.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95   ,CPU Targets Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO94   ,CPU Targets Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO93   ,CPU Targets Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO92   ,CPU Targets Byte Offset 92  "
else
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99   ,CPU Targets Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO98   ,CPU Targets Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO97   ,CPU Targets Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO96   ,CPU Targets Byte Offset 96  "
group.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103  ,CPU Targets Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO102  ,CPU Targets Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO101  ,CPU Targets Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO100  ,CPU Targets Byte Offset 100 "
group.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107  ,CPU Targets Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO106  ,CPU Targets Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO105  ,CPU Targets Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO104  ,CPU Targets Byte Offset 104 "
group.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111  ,CPU Targets Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO110  ,CPU Targets Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO109  ,CPU Targets Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO108  ,CPU Targets Byte Offset 108 "
group.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115  ,CPU Targets Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO114  ,CPU Targets Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO113  ,CPU Targets Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO112  ,CPU Targets Byte Offset 112 "
group.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119  ,CPU Targets Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO118  ,CPU Targets Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO117  ,CPU Targets Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO116  ,CPU Targets Byte Offset 116 "
group.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123  ,CPU Targets Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO122  ,CPU Targets Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO121  ,CPU Targets Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO120  ,CPU Targets Byte Offset 120 "
group.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127  ,CPU Targets Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO126  ,CPU Targets Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO125  ,CPU Targets Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO124  ,CPU Targets Byte Offset 124 "
else
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131  ,CPU Targets Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO130  ,CPU Targets Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO129  ,CPU Targets Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO128  ,CPU Targets Byte Offset 128 "
group.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135  ,CPU Targets Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO134  ,CPU Targets Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO133  ,CPU Targets Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO132  ,CPU Targets Byte Offset 132 "
group.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139  ,CPU Targets Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO138  ,CPU Targets Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO137  ,CPU Targets Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO136  ,CPU Targets Byte Offset 136 "
group.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143  ,CPU Targets Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO142  ,CPU Targets Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO141  ,CPU Targets Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO140  ,CPU Targets Byte Offset 140 "
group.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147  ,CPU Targets Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO146  ,CPU Targets Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO145  ,CPU Targets Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO144  ,CPU Targets Byte Offset 144 "
group.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151  ,CPU Targets Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO150  ,CPU Targets Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO149  ,CPU Targets Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO148  ,CPU Targets Byte Offset 148 "
group.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155  ,CPU Targets Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO154  ,CPU Targets Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO153  ,CPU Targets Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO152  ,CPU Targets Byte Offset 152 "
group.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159  ,CPU Targets Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO158  ,CPU Targets Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO157  ,CPU Targets Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO156  ,CPU Targets Byte Offset 156 "
else
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163  ,CPU Targets Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO162  ,CPU Targets Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO161  ,CPU Targets Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO160  ,CPU Targets Byte Offset 160 "
group.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167  ,CPU Targets Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO166  ,CPU Targets Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO165  ,CPU Targets Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO164  ,CPU Targets Byte Offset 164 "
group.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171  ,CPU Targets Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO170  ,CPU Targets Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO169  ,CPU Targets Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO168  ,CPU Targets Byte Offset 168 "
group.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175  ,CPU Targets Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO174  ,CPU Targets Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO173  ,CPU Targets Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO172  ,CPU Targets Byte Offset 172 "
group.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179  ,CPU Targets Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO178  ,CPU Targets Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO177  ,CPU Targets Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO176  ,CPU Targets Byte Offset 176 "
group.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183  ,CPU Targets Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO182  ,CPU Targets Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO181  ,CPU Targets Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO180  ,CPU Targets Byte Offset 180 "
group.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187  ,CPU Targets Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO186  ,CPU Targets Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO185  ,CPU Targets Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO184  ,CPU Targets Byte Offset 184 "
group.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191  ,CPU Targets Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO190  ,CPU Targets Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO189  ,CPU Targets Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO188  ,CPU Targets Byte Offset 188 "
else
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195  ,CPU Targets Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO194  ,CPU Targets Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO193  ,CPU Targets Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO192  ,CPU Targets Byte Offset 192 "
group.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199  ,CPU Targets Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO198  ,CPU Targets Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO197  ,CPU Targets Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO196  ,CPU Targets Byte Offset 196 "
group.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203  ,CPU Targets Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO202  ,CPU Targets Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO201  ,CPU Targets Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO200  ,CPU Targets Byte Offset 200 "
group.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207  ,CPU Targets Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO206  ,CPU Targets Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO205  ,CPU Targets Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO204  ,CPU Targets Byte Offset 204 "
group.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211  ,CPU Targets Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO210  ,CPU Targets Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO209  ,CPU Targets Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO208  ,CPU Targets Byte Offset 208 "
group.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215  ,CPU Targets Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO214  ,CPU Targets Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO213  ,CPU Targets Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO212  ,CPU Targets Byte Offset 212 "
group.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219  ,CPU Targets Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO218  ,CPU Targets Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO217  ,CPU Targets Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO216  ,CPU Targets Byte Offset 216 "
group.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223  ,CPU Targets Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO222  ,CPU Targets Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO221  ,CPU Targets Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO220  ,CPU Targets Byte Offset 220 "
else
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227  ,CPU Targets Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO226  ,CPU Targets Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO225  ,CPU Targets Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO224  ,CPU Targets Byte Offset 224 "
group.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231  ,CPU Targets Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO230  ,CPU Targets Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO229  ,CPU Targets Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO228  ,CPU Targets Byte Offset 228 "
group.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235  ,CPU Targets Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO234  ,CPU Targets Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO233  ,CPU Targets Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO232  ,CPU Targets Byte Offset 232 "
group.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239  ,CPU Targets Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO238  ,CPU Targets Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO237  ,CPU Targets Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO236  ,CPU Targets Byte Offset 236 "
group.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243  ,CPU Targets Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO242  ,CPU Targets Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO241  ,CPU Targets Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO240  ,CPU Targets Byte Offset 240 "
group.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247  ,CPU Targets Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO246  ,CPU Targets Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO245  ,CPU Targets Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO244  ,CPU Targets Byte Offset 244 "
group.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251  ,CPU Targets Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO250  ,CPU Targets Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO249  ,CPU Targets Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO248  ,CPU Targets Byte Offset 248 "
group.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255  ,CPU Targets Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO254  ,CPU Targets Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO253  ,CPU Targets Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO252  ,CPU Targets Byte Offset 252 "
else
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259  ,CPU Targets Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO258  ,CPU Targets Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO257  ,CPU Targets Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO256  ,CPU Targets Byte Offset 256 "
group.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263  ,CPU Targets Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO262  ,CPU Targets Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO261  ,CPU Targets Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO260  ,CPU Targets Byte Offset 260 "
group.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267  ,CPU Targets Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO266  ,CPU Targets Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO265  ,CPU Targets Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO264  ,CPU Targets Byte Offset 264 "
group.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271  ,CPU Targets Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO270  ,CPU Targets Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO269  ,CPU Targets Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO268  ,CPU Targets Byte Offset 268 "
group.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275  ,CPU Targets Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO274  ,CPU Targets Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO273  ,CPU Targets Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO272  ,CPU Targets Byte Offset 272 "
group.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279  ,CPU Targets Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO278  ,CPU Targets Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO277  ,CPU Targets Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO276  ,CPU Targets Byte Offset 276 "
group.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283  ,CPU Targets Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO282  ,CPU Targets Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO281  ,CPU Targets Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO280  ,CPU Targets Byte Offset 280 "
group.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287  ,CPU Targets Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO286  ,CPU Targets Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO285  ,CPU Targets Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO284  ,CPU Targets Byte Offset 284 "
else
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291  ,CPU Targets Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO290  ,CPU Targets Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO289  ,CPU Targets Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO288  ,CPU Targets Byte Offset 288 "
group.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295  ,CPU Targets Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO294  ,CPU Targets Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO293  ,CPU Targets Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO292  ,CPU Targets Byte Offset 292 "
group.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299  ,CPU Targets Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO298  ,CPU Targets Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO297  ,CPU Targets Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO296  ,CPU Targets Byte Offset 296 "
group.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303  ,CPU Targets Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO302  ,CPU Targets Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO301  ,CPU Targets Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO300  ,CPU Targets Byte Offset 300 "
group.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307  ,CPU Targets Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO306  ,CPU Targets Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO305  ,CPU Targets Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO304  ,CPU Targets Byte Offset 304 "
group.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311  ,CPU Targets Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO310  ,CPU Targets Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO309  ,CPU Targets Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO308  ,CPU Targets Byte Offset 308 "
group.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315  ,CPU Targets Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO314  ,CPU Targets Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO313  ,CPU Targets Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO312  ,CPU Targets Byte Offset 312 "
group.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319  ,CPU Targets Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO318  ,CPU Targets Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO317  ,CPU Targets Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO316  ,CPU Targets Byte Offset 316 "
else
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323  ,CPU Targets Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO322  ,CPU Targets Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO321  ,CPU Targets Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO320  ,CPU Targets Byte Offset 320 "
group.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327  ,CPU Targets Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO326  ,CPU Targets Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO325  ,CPU Targets Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO324  ,CPU Targets Byte Offset 324 "
group.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331  ,CPU Targets Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO330  ,CPU Targets Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO329  ,CPU Targets Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO328  ,CPU Targets Byte Offset 328 "
group.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335  ,CPU Targets Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO334  ,CPU Targets Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO333  ,CPU Targets Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO332  ,CPU Targets Byte Offset 332 "
group.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339  ,CPU Targets Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO338  ,CPU Targets Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO337  ,CPU Targets Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO336  ,CPU Targets Byte Offset 336 "
group.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343  ,CPU Targets Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO342  ,CPU Targets Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO341  ,CPU Targets Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO340  ,CPU Targets Byte Offset 340 "
group.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347  ,CPU Targets Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO346  ,CPU Targets Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO345  ,CPU Targets Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO344  ,CPU Targets Byte Offset 344 "
group.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351  ,CPU Targets Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO350  ,CPU Targets Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO349  ,CPU Targets Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO348  ,CPU Targets Byte Offset 348 "
else
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355  ,CPU Targets Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO354  ,CPU Targets Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO353  ,CPU Targets Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO352  ,CPU Targets Byte Offset 352 "
group.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359  ,CPU Targets Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO358  ,CPU Targets Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO357  ,CPU Targets Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO356  ,CPU Targets Byte Offset 356 "
group.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363  ,CPU Targets Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO362  ,CPU Targets Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO361  ,CPU Targets Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO360  ,CPU Targets Byte Offset 360 "
group.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367  ,CPU Targets Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO366  ,CPU Targets Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO365  ,CPU Targets Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO364  ,CPU Targets Byte Offset 364 "
group.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371  ,CPU Targets Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO370  ,CPU Targets Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO369  ,CPU Targets Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO368  ,CPU Targets Byte Offset 368 "
group.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375  ,CPU Targets Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO374  ,CPU Targets Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO373  ,CPU Targets Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO372  ,CPU Targets Byte Offset 372 "
group.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379  ,CPU Targets Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO378  ,CPU Targets Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO377  ,CPU Targets Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO376  ,CPU Targets Byte Offset 376 "
group.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383  ,CPU Targets Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO382  ,CPU Targets Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO381  ,CPU Targets Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO380  ,CPU Targets Byte Offset 380 "
else
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387  ,CPU Targets Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO386  ,CPU Targets Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO385  ,CPU Targets Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO384  ,CPU Targets Byte Offset 384 "
group.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391  ,CPU Targets Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO390  ,CPU Targets Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO389  ,CPU Targets Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO388  ,CPU Targets Byte Offset 388 "
group.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395  ,CPU Targets Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO394  ,CPU Targets Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO393  ,CPU Targets Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO392  ,CPU Targets Byte Offset 392 "
group.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399  ,CPU Targets Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO398  ,CPU Targets Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO397  ,CPU Targets Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO396  ,CPU Targets Byte Offset 396 "
group.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403  ,CPU Targets Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO402  ,CPU Targets Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO401  ,CPU Targets Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO400  ,CPU Targets Byte Offset 400 "
group.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407  ,CPU Targets Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO406  ,CPU Targets Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO405  ,CPU Targets Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO404  ,CPU Targets Byte Offset 404 "
group.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411  ,CPU Targets Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO410  ,CPU Targets Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO409  ,CPU Targets Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO408  ,CPU Targets Byte Offset 408 "
group.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415  ,CPU Targets Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO414  ,CPU Targets Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO413  ,CPU Targets Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO412  ,CPU Targets Byte Offset 412 "
else
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419  ,CPU Targets Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO418  ,CPU Targets Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO417  ,CPU Targets Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO416  ,CPU Targets Byte Offset 416 "
group.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423  ,CPU Targets Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO422  ,CPU Targets Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO421  ,CPU Targets Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO420  ,CPU Targets Byte Offset 420 "
group.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427  ,CPU Targets Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO426  ,CPU Targets Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO425  ,CPU Targets Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO424  ,CPU Targets Byte Offset 424 "
group.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431  ,CPU Targets Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO430  ,CPU Targets Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO429  ,CPU Targets Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO428  ,CPU Targets Byte Offset 428 "
group.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435  ,CPU Targets Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO434  ,CPU Targets Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO433  ,CPU Targets Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO432  ,CPU Targets Byte Offset 432 "
group.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439  ,CPU Targets Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO438  ,CPU Targets Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO437  ,CPU Targets Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO436  ,CPU Targets Byte Offset 436 "
group.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443  ,CPU Targets Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO442  ,CPU Targets Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO441  ,CPU Targets Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO440  ,CPU Targets Byte Offset 440 "
group.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447  ,CPU Targets Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO446  ,CPU Targets Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO445  ,CPU Targets Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO444  ,CPU Targets Byte Offset 444 "
else
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451  ,CPU Targets Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO450  ,CPU Targets Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO449  ,CPU Targets Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO448  ,CPU Targets Byte Offset 448 "
group.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455  ,CPU Targets Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO454  ,CPU Targets Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO453  ,CPU Targets Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO452  ,CPU Targets Byte Offset 452 "
group.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459  ,CPU Targets Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO458  ,CPU Targets Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO457  ,CPU Targets Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO456  ,CPU Targets Byte Offset 456 "
group.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463  ,CPU Targets Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO462  ,CPU Targets Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO461  ,CPU Targets Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO460  ,CPU Targets Byte Offset 460 "
group.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467  ,CPU Targets Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO466  ,CPU Targets Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO465  ,CPU Targets Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO464  ,CPU Targets Byte Offset 464 "
group.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471  ,CPU Targets Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO470  ,CPU Targets Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO469  ,CPU Targets Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO468  ,CPU Targets Byte Offset 468 "
group.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475  ,CPU Targets Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO474  ,CPU Targets Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO473  ,CPU Targets Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO472  ,CPU Targets Byte Offset 472 "
group.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479  ,CPU Targets Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO478  ,CPU Targets Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO477  ,CPU Targets Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO476  ,CPU Targets Byte Offset 476 "
else
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483  ,CPU Targets Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO482  ,CPU Targets Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO481  ,CPU Targets Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO480  ,CPU Targets Byte Offset 480 "
group.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487  ,CPU Targets Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO486  ,CPU Targets Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO485  ,CPU Targets Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO484  ,CPU Targets Byte Offset 484 "
group.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491  ,CPU Targets Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO490  ,CPU Targets Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO489  ,CPU Targets Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO488  ,CPU Targets Byte Offset 488 "
group.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495  ,CPU Targets Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO494  ,CPU Targets Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO493  ,CPU Targets Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO492  ,CPU Targets Byte Offset 492 "
group.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499  ,CPU Targets Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO498  ,CPU Targets Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO497  ,CPU Targets Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO496  ,CPU Targets Byte Offset 496 "
group.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503  ,CPU Targets Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO502  ,CPU Targets Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO501  ,CPU Targets Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO500  ,CPU Targets Byte Offset 500 "
group.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507  ,CPU Targets Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO506  ,CPU Targets Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO505  ,CPU Targets Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO504  ,CPU Targets Byte Offset 504 "
group.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511  ,CPU Targets Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO510  ,CPU Targets Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO509  ,CPU Targets Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO508  ,CPU Targets Byte Offset 508 "
else
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515  ,CPU Targets Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO514  ,CPU Targets Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO513  ,CPU Targets Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO512  ,CPU Targets Byte Offset 512 "
group.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519  ,CPU Targets Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO518  ,CPU Targets Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO517  ,CPU Targets Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO516  ,CPU Targets Byte Offset 516 "
group.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523  ,CPU Targets Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO522  ,CPU Targets Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO521  ,CPU Targets Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO520  ,CPU Targets Byte Offset 520 "
group.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527  ,CPU Targets Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO526  ,CPU Targets Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO525  ,CPU Targets Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO524  ,CPU Targets Byte Offset 524 "
group.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531  ,CPU Targets Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO530  ,CPU Targets Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO529  ,CPU Targets Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO528  ,CPU Targets Byte Offset 528 "
group.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535  ,CPU Targets Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO534  ,CPU Targets Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO533  ,CPU Targets Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO532  ,CPU Targets Byte Offset 532 "
group.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539  ,CPU Targets Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO538  ,CPU Targets Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO537  ,CPU Targets Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO536  ,CPU Targets Byte Offset 536 "
group.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543  ,CPU Targets Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO542  ,CPU Targets Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO541  ,CPU Targets Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO540  ,CPU Targets Byte Offset 540 "
else
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547  ,CPU Targets Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO546  ,CPU Targets Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO545  ,CPU Targets Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO544  ,CPU Targets Byte Offset 544 "
group.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551  ,CPU Targets Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO550  ,CPU Targets Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO549  ,CPU Targets Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO548  ,CPU Targets Byte Offset 548 "
group.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555  ,CPU Targets Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO554  ,CPU Targets Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO553  ,CPU Targets Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO552  ,CPU Targets Byte Offset 552 "
group.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559  ,CPU Targets Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO558  ,CPU Targets Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO557  ,CPU Targets Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO556  ,CPU Targets Byte Offset 556 "
group.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563  ,CPU Targets Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO562  ,CPU Targets Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO561  ,CPU Targets Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO560  ,CPU Targets Byte Offset 560 "
group.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567  ,CPU Targets Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO566  ,CPU Targets Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO565  ,CPU Targets Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO564  ,CPU Targets Byte Offset 564 "
group.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571  ,CPU Targets Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO570  ,CPU Targets Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO569  ,CPU Targets Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO568  ,CPU Targets Byte Offset 568 "
group.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575  ,CPU Targets Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO574  ,CPU Targets Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO573  ,CPU Targets Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO572  ,CPU Targets Byte Offset 572 "
else
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579  ,CPU Targets Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO578  ,CPU Targets Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO577  ,CPU Targets Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO576  ,CPU Targets Byte Offset 576 "
group.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583  ,CPU Targets Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO582  ,CPU Targets Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO581  ,CPU Targets Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO580  ,CPU Targets Byte Offset 580 "
group.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587  ,CPU Targets Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO586  ,CPU Targets Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO585  ,CPU Targets Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO584  ,CPU Targets Byte Offset 584 "
group.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591  ,CPU Targets Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO590  ,CPU Targets Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO589  ,CPU Targets Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO588  ,CPU Targets Byte Offset 588 "
group.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595  ,CPU Targets Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO594  ,CPU Targets Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO593  ,CPU Targets Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO592  ,CPU Targets Byte Offset 592 "
group.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599  ,CPU Targets Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO598  ,CPU Targets Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO597  ,CPU Targets Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO596  ,CPU Targets Byte Offset 596 "
group.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603  ,CPU Targets Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO602  ,CPU Targets Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO601  ,CPU Targets Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO600  ,CPU Targets Byte Offset 600 "
group.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607  ,CPU Targets Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO606  ,CPU Targets Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO605  ,CPU Targets Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO604  ,CPU Targets Byte Offset 604 "
else
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611  ,CPU Targets Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO610  ,CPU Targets Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO609  ,CPU Targets Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO608  ,CPU Targets Byte Offset 608 "
group.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615  ,CPU Targets Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO614  ,CPU Targets Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO613  ,CPU Targets Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO612  ,CPU Targets Byte Offset 612 "
group.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619  ,CPU Targets Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO618  ,CPU Targets Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO617  ,CPU Targets Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO616  ,CPU Targets Byte Offset 616 "
group.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623  ,CPU Targets Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO622  ,CPU Targets Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO621  ,CPU Targets Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO620  ,CPU Targets Byte Offset 620 "
group.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627  ,CPU Targets Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO626  ,CPU Targets Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO625  ,CPU Targets Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO624  ,CPU Targets Byte Offset 624 "
group.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631  ,CPU Targets Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO630  ,CPU Targets Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO629  ,CPU Targets Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO628  ,CPU Targets Byte Offset 628 "
group.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635  ,CPU Targets Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO634  ,CPU Targets Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO633  ,CPU Targets Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO632  ,CPU Targets Byte Offset 632 "
group.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639  ,CPU Targets Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO638  ,CPU Targets Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO637  ,CPU Targets Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO636  ,CPU Targets Byte Offset 636 "
else
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643  ,CPU Targets Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO642  ,CPU Targets Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO641  ,CPU Targets Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO640  ,CPU Targets Byte Offset 640 "
group.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647  ,CPU Targets Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO646  ,CPU Targets Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO645  ,CPU Targets Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO644  ,CPU Targets Byte Offset 644 "
group.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651  ,CPU Targets Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO650  ,CPU Targets Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO649  ,CPU Targets Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO648  ,CPU Targets Byte Offset 648 "
group.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655  ,CPU Targets Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO654  ,CPU Targets Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO653  ,CPU Targets Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO652  ,CPU Targets Byte Offset 652 "
group.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659  ,CPU Targets Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO658  ,CPU Targets Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO657  ,CPU Targets Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO656  ,CPU Targets Byte Offset 656 "
group.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663  ,CPU Targets Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO662  ,CPU Targets Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO661  ,CPU Targets Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO660  ,CPU Targets Byte Offset 660 "
group.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667  ,CPU Targets Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO666  ,CPU Targets Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO665  ,CPU Targets Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO664  ,CPU Targets Byte Offset 664 "
group.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671  ,CPU Targets Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO670  ,CPU Targets Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO669  ,CPU Targets Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO668  ,CPU Targets Byte Offset 668 "
else
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675  ,CPU Targets Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO674  ,CPU Targets Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO673  ,CPU Targets Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO672  ,CPU Targets Byte Offset 672 "
group.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679  ,CPU Targets Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO678  ,CPU Targets Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO677  ,CPU Targets Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO676  ,CPU Targets Byte Offset 676 "
group.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683  ,CPU Targets Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO682  ,CPU Targets Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO681  ,CPU Targets Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO680  ,CPU Targets Byte Offset 680 "
group.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687  ,CPU Targets Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO686  ,CPU Targets Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO685  ,CPU Targets Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO684  ,CPU Targets Byte Offset 684 "
group.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691  ,CPU Targets Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO690  ,CPU Targets Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO689  ,CPU Targets Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO688  ,CPU Targets Byte Offset 688 "
group.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695  ,CPU Targets Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO694  ,CPU Targets Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO693  ,CPU Targets Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO692  ,CPU Targets Byte Offset 692 "
group.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699  ,CPU Targets Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO698  ,CPU Targets Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO697  ,CPU Targets Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO696  ,CPU Targets Byte Offset 696 "
group.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703  ,CPU Targets Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO702  ,CPU Targets Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO701  ,CPU Targets Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO700  ,CPU Targets Byte Offset 700 "
else
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707  ,CPU Targets Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO706  ,CPU Targets Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO705  ,CPU Targets Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO704  ,CPU Targets Byte Offset 704 "
group.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711  ,CPU Targets Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO710  ,CPU Targets Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO709  ,CPU Targets Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO708  ,CPU Targets Byte Offset 708 "
group.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715  ,CPU Targets Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO714  ,CPU Targets Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO713  ,CPU Targets Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO712  ,CPU Targets Byte Offset 712 "
group.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719  ,CPU Targets Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO718  ,CPU Targets Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO717  ,CPU Targets Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO716  ,CPU Targets Byte Offset 716 "
group.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723  ,CPU Targets Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO722  ,CPU Targets Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO721  ,CPU Targets Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO720  ,CPU Targets Byte Offset 720 "
group.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727  ,CPU Targets Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO726  ,CPU Targets Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO725  ,CPU Targets Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO724  ,CPU Targets Byte Offset 724 "
group.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731  ,CPU Targets Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO730  ,CPU Targets Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO729  ,CPU Targets Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO728  ,CPU Targets Byte Offset 728 "
group.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735  ,CPU Targets Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO734  ,CPU Targets Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO733  ,CPU Targets Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO732  ,CPU Targets Byte Offset 732 "
else
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739  ,CPU Targets Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO738  ,CPU Targets Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO737  ,CPU Targets Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO736  ,CPU Targets Byte Offset 736 "
group.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743  ,CPU Targets Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO742  ,CPU Targets Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO741  ,CPU Targets Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO740  ,CPU Targets Byte Offset 740 "
group.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747  ,CPU Targets Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO746  ,CPU Targets Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO745  ,CPU Targets Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO744  ,CPU Targets Byte Offset 744 "
group.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751  ,CPU Targets Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO750  ,CPU Targets Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO749  ,CPU Targets Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO748  ,CPU Targets Byte Offset 748 "
group.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755  ,CPU Targets Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO754  ,CPU Targets Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO753  ,CPU Targets Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO752  ,CPU Targets Byte Offset 752 "
group.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759  ,CPU Targets Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO758  ,CPU Targets Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO757  ,CPU Targets Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO756  ,CPU Targets Byte Offset 756 "
group.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763  ,CPU Targets Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO762  ,CPU Targets Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO761  ,CPU Targets Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO760  ,CPU Targets Byte Offset 760 "
group.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767  ,CPU Targets Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO766  ,CPU Targets Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO765  ,CPU Targets Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO764  ,CPU Targets Byte Offset 764 "
else
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771  ,CPU Targets Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO770  ,CPU Targets Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO769  ,CPU Targets Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO768  ,CPU Targets Byte Offset 768 "
group.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775  ,CPU Targets Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO774  ,CPU Targets Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO773  ,CPU Targets Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO772  ,CPU Targets Byte Offset 772 "
group.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779  ,CPU Targets Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO778  ,CPU Targets Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO777  ,CPU Targets Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO776  ,CPU Targets Byte Offset 776 "
group.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783  ,CPU Targets Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO782  ,CPU Targets Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO781  ,CPU Targets Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO780  ,CPU Targets Byte Offset 780 "
group.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787  ,CPU Targets Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO786  ,CPU Targets Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO785  ,CPU Targets Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO784  ,CPU Targets Byte Offset 784 "
group.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791  ,CPU Targets Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO790  ,CPU Targets Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO789  ,CPU Targets Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO788  ,CPU Targets Byte Offset 788 "
group.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795  ,CPU Targets Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO794  ,CPU Targets Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO793  ,CPU Targets Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO792  ,CPU Targets Byte Offset 792 "
group.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799  ,CPU Targets Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO798  ,CPU Targets Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO797  ,CPU Targets Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO796  ,CPU Targets Byte Offset 796 "
else
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803  ,CPU Targets Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO802  ,CPU Targets Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO801  ,CPU Targets Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO800  ,CPU Targets Byte Offset 800 "
group.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807  ,CPU Targets Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO806  ,CPU Targets Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO805  ,CPU Targets Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO804  ,CPU Targets Byte Offset 804 "
group.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811  ,CPU Targets Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO810  ,CPU Targets Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO809  ,CPU Targets Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO808  ,CPU Targets Byte Offset 808 "
group.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815  ,CPU Targets Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO814  ,CPU Targets Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO813  ,CPU Targets Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO812  ,CPU Targets Byte Offset 812 "
group.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819  ,CPU Targets Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO818  ,CPU Targets Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO817  ,CPU Targets Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO816  ,CPU Targets Byte Offset 816 "
group.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823  ,CPU Targets Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO822  ,CPU Targets Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO821  ,CPU Targets Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO820  ,CPU Targets Byte Offset 820 "
group.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827  ,CPU Targets Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO826  ,CPU Targets Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO825  ,CPU Targets Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO824  ,CPU Targets Byte Offset 824 "
group.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831  ,CPU Targets Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO830  ,CPU Targets Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO829  ,CPU Targets Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO828  ,CPU Targets Byte Offset 828 "
else
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835  ,CPU Targets Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO834  ,CPU Targets Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO833  ,CPU Targets Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO832  ,CPU Targets Byte Offset 832 "
group.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839  ,CPU Targets Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO838  ,CPU Targets Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO837  ,CPU Targets Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO836  ,CPU Targets Byte Offset 836 "
group.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843  ,CPU Targets Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO842  ,CPU Targets Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO841  ,CPU Targets Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO840  ,CPU Targets Byte Offset 840 "
group.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847  ,CPU Targets Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO846  ,CPU Targets Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO845  ,CPU Targets Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO844  ,CPU Targets Byte Offset 844 "
group.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851  ,CPU Targets Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO850  ,CPU Targets Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO849  ,CPU Targets Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO848  ,CPU Targets Byte Offset 848 "
group.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855  ,CPU Targets Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO854  ,CPU Targets Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO853  ,CPU Targets Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO852  ,CPU Targets Byte Offset 852 "
group.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859  ,CPU Targets Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO858  ,CPU Targets Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO857  ,CPU Targets Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO856  ,CPU Targets Byte Offset 856 "
group.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863  ,CPU Targets Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO862  ,CPU Targets Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO861  ,CPU Targets Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO860  ,CPU Targets Byte Offset 860 "
else
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867  ,CPU Targets Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO866  ,CPU Targets Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO865  ,CPU Targets Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO864  ,CPU Targets Byte Offset 864 "
group.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871  ,CPU Targets Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO870  ,CPU Targets Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO869  ,CPU Targets Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO868  ,CPU Targets Byte Offset 868 "
group.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875  ,CPU Targets Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO874  ,CPU Targets Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO873  ,CPU Targets Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO872  ,CPU Targets Byte Offset 872 "
group.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879  ,CPU Targets Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO878  ,CPU Targets Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO877  ,CPU Targets Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO876  ,CPU Targets Byte Offset 876 "
group.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883  ,CPU Targets Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO882  ,CPU Targets Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO881  ,CPU Targets Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO880  ,CPU Targets Byte Offset 880 "
group.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887  ,CPU Targets Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO886  ,CPU Targets Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO885  ,CPU Targets Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO884  ,CPU Targets Byte Offset 884 "
group.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891  ,CPU Targets Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO890  ,CPU Targets Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO889  ,CPU Targets Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO888  ,CPU Targets Byte Offset 888 "
group.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895  ,CPU Targets Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO894  ,CPU Targets Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO893  ,CPU Targets Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO892  ,CPU Targets Byte Offset 892 "
else
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899  ,CPU Targets Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO898  ,CPU Targets Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO897  ,CPU Targets Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO896  ,CPU Targets Byte Offset 896 "
group.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903  ,CPU Targets Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO902  ,CPU Targets Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO901  ,CPU Targets Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO900  ,CPU Targets Byte Offset 900 "
group.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907  ,CPU Targets Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO906  ,CPU Targets Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO905  ,CPU Targets Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO904  ,CPU Targets Byte Offset 904 "
group.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911  ,CPU Targets Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO910  ,CPU Targets Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO909  ,CPU Targets Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO908  ,CPU Targets Byte Offset 908 "
group.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915  ,CPU Targets Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO914  ,CPU Targets Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO913  ,CPU Targets Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO912  ,CPU Targets Byte Offset 912 "
group.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919  ,CPU Targets Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO918  ,CPU Targets Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO917  ,CPU Targets Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO916  ,CPU Targets Byte Offset 916 "
group.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923  ,CPU Targets Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO922  ,CPU Targets Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO921  ,CPU Targets Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO920  ,CPU Targets Byte Offset 920 "
group.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927  ,CPU Targets Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO926  ,CPU Targets Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO925  ,CPU Targets Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO924  ,CPU Targets Byte Offset 924 "
else
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931  ,CPU Targets Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO930  ,CPU Targets Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO929  ,CPU Targets Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO928  ,CPU Targets Byte Offset 928 "
group.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935  ,CPU Targets Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO934  ,CPU Targets Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO933  ,CPU Targets Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO932  ,CPU Targets Byte Offset 932 "
group.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939  ,CPU Targets Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO938  ,CPU Targets Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO937  ,CPU Targets Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO936  ,CPU Targets Byte Offset 936 "
group.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943  ,CPU Targets Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO942  ,CPU Targets Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO941  ,CPU Targets Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO940  ,CPU Targets Byte Offset 940 "
group.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947  ,CPU Targets Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO946  ,CPU Targets Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO945  ,CPU Targets Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO944  ,CPU Targets Byte Offset 944 "
group.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951  ,CPU Targets Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO950  ,CPU Targets Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO949  ,CPU Targets Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO948  ,CPU Targets Byte Offset 948 "
group.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955  ,CPU Targets Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO954  ,CPU Targets Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO953  ,CPU Targets Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO952  ,CPU Targets Byte Offset 952 "
group.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959  ,CPU Targets Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO958  ,CPU Targets Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO957  ,CPU Targets Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO956  ,CPU Targets Byte Offset 956 "
else
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963  ,CPU Targets Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO962  ,CPU Targets Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO961  ,CPU Targets Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO960  ,CPU Targets Byte Offset 960 "
group.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967  ,CPU Targets Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO966  ,CPU Targets Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO965  ,CPU Targets Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO964  ,CPU Targets Byte Offset 964 "
group.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971  ,CPU Targets Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO970  ,CPU Targets Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO969  ,CPU Targets Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO968  ,CPU Targets Byte Offset 968 "
group.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975  ,CPU Targets Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO974  ,CPU Targets Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO973  ,CPU Targets Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO972  ,CPU Targets Byte Offset 972 "
group.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979  ,CPU Targets Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO978  ,CPU Targets Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO977  ,CPU Targets Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO976  ,CPU Targets Byte Offset 976 "
group.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983  ,CPU Targets Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO982  ,CPU Targets Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO981  ,CPU Targets Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO980  ,CPU Targets Byte Offset 980 "
group.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987  ,CPU Targets Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO986  ,CPU Targets Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO985  ,CPU Targets Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO984  ,CPU Targets Byte Offset 984 "
group.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991  ,CPU Targets Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO990  ,CPU Targets Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO989  ,CPU Targets Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO988  ,CPU Targets Byte Offset 988 "
else
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
else
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0  ,Interrupt Processor Targets Register 0  "
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1  ,Interrupt Processor Targets Register 1  "
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2  ,Interrupt Processor Targets Register 2  "
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3  ,Interrupt Processor Targets Register 3  "
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4  ,Interrupt Processor Targets Register 4  "
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5  ,Interrupt Processor Targets Register 5  "
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6  ,Interrupt Processor Targets Register 6  "
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7  ,Interrupt Processor Targets Register 7  "
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8  ,Interrupt Processor Targets Register 8  "
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9  ,Interrupt Processor Targets Register 9  "
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
tree.end
width 14.
tree "Configuration Registers"
rgroup.long 0xC00++0x03
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SGI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SGI)" "Level,Edge"
group.long 0xC04++0x03
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (PPI)" "Level,Edge"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)
group.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC08++0x03
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
hgroup.long 0xC0C++0x03
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)
group.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC10++0x03
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
hgroup.long 0xC14++0x03
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)
group.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC18++0x03
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
hgroup.long 0xC1C++0x03
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)
group.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC20++0x03
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
hgroup.long 0xC24++0x03
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)
group.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC28++0x03
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
hgroup.long 0xC2C++0x03
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)
group.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC30++0x03
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
hgroup.long 0xC34++0x03
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)
group.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC38++0x03
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
hgroup.long 0xC3C++0x03
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)
group.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC40++0x03
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
hgroup.long 0xC44++0x03
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)
group.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC48++0x03
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
hgroup.long 0xC4C++0x03
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)
group.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC50++0x03
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
hgroup.long 0xC54++0x03
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)
group.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC58++0x03
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
hgroup.long 0xC5C++0x03
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)
group.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC60++0x03
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
hgroup.long 0xC64++0x03
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)
group.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC68++0x03
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
hgroup.long 0xC6C++0x03
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)
group.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC70++0x03
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
hgroup.long 0xC74++0x03
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)
group.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC78++0x03
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
hgroup.long 0xC7C++0x03
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC80++0x03
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
hgroup.long 0xC84++0x03
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC88++0x03
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
hgroup.long 0xC8C++0x03
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC90++0x03
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
hgroup.long 0xC94++0x03
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC98++0x03
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
hgroup.long 0xC9C++0x03
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA0++0x03
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
hgroup.long 0xCA4++0x03
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA8++0x03
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
hgroup.long 0xCAC++0x03
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB0++0x03
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
hgroup.long 0xCB4++0x03
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB8++0x03
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
hgroup.long 0xCBC++0x03
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC0++0x03
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
hgroup.long 0xCC4++0x03
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC8++0x03
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
hgroup.long 0xCCC++0x03
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD0++0x03
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
hgroup.long 0xCD4++0x03
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD8++0x03
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
hgroup.long 0xCDC++0x03
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE0++0x03
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
hgroup.long 0xCE4++0x03
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE8++0x03
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
hgroup.long 0xCEC++0x03
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCF0++0x03
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
hgroup.long 0xCF4++0x03
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
endif
tree.end
width 17.
tree "Interrupt Group Modifier Registers"
hgroup.long 0x0D00++0x03
hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01))
group.long 0x0D04++0x03
line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
bitfld.long 0x00 31. " GMB63  ,Group Modifier Bit 63" "0,1"
bitfld.long 0x00 30. "  GMB62  ,Group Modifier Bit 62" "0,1"
bitfld.long 0x00 29. "  GMB61  ,Group Modifier Bit 61" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB60  ,Group Modifier Bit 60" "0,1"
bitfld.long 0x00 27. "  GMB59  ,Group Modifier Bit 59" "0,1"
bitfld.long 0x00 26. "  GMB58  ,Group Modifier Bit 58" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB57  ,Group Modifier Bit 57" "0,1"
bitfld.long 0x00 24. "  GMB56  ,Group Modifier Bit 56" "0,1"
bitfld.long 0x00 23. "  GMB55  ,Group Modifier Bit 55" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB54  ,Group Modifier Bit 54" "0,1"
bitfld.long 0x00 21. "  GMB53  ,Group Modifier Bit 53" "0,1"
bitfld.long 0x00 20. "  GMB52  ,Group Modifier Bit 52" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB51  ,Group Modifier Bit 51" "0,1"
bitfld.long 0x00 18. "  GMB50  ,Group Modifier Bit 50" "0,1"
bitfld.long 0x00 17. "  GMB49  ,Group Modifier Bit 49" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB48  ,Group Modifier Bit 48" "0,1"
bitfld.long 0x00 15. "  GMB47  ,Group Modifier Bit 47" "0,1"
bitfld.long 0x00 14. "  GMB46  ,Group Modifier Bit 46" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB45  ,Group Modifier Bit 45" "0,1"
bitfld.long 0x00 12. "  GMB44  ,Group Modifier Bit 44" "0,1"
bitfld.long 0x00 11. "  GMB43  ,Group Modifier Bit 43" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB42  ,Group Modifier Bit 42" "0,1"
bitfld.long 0x00 9. "  GMB41  ,Group Modifier Bit 41" "0,1"
bitfld.long 0x00 8. "  GMB40  ,Group Modifier Bit 40" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB39  ,Group Modifier Bit 39" "0,1"
bitfld.long 0x00 6. "  GMB38  ,Group Modifier Bit 38" "0,1"
bitfld.long 0x00 5. "  GMB37  ,Group Modifier Bit 37" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB36  ,Group Modifier Bit 36" "0,1"
bitfld.long 0x00 3. "  GMB35  ,Group Modifier Bit 35" "0,1"
bitfld.long 0x00 2. "  GMB34  ,Group Modifier Bit 34" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB33  ,Group Modifier Bit 33" "0,1"
bitfld.long 0x00 0. "  GMB32  ,Group Modifier Bit 32" "0,1"
else
hgroup.long 0x0D04++0x03
hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02))
group.long 0x0D08++0x03
line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
bitfld.long 0x00 31. " GMB95  ,Group Modifier Bit 95" "0,1"
bitfld.long 0x00 30. "  GMB94  ,Group Modifier Bit 94" "0,1"
bitfld.long 0x00 29. "  GMB93  ,Group Modifier Bit 93" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB92  ,Group Modifier Bit 92" "0,1"
bitfld.long 0x00 27. "  GMB91  ,Group Modifier Bit 91" "0,1"
bitfld.long 0x00 26. "  GMB90  ,Group Modifier Bit 90" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB89  ,Group Modifier Bit 89" "0,1"
bitfld.long 0x00 24. "  GMB88  ,Group Modifier Bit 88" "0,1"
bitfld.long 0x00 23. "  GMB87  ,Group Modifier Bit 87" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB86  ,Group Modifier Bit 86" "0,1"
bitfld.long 0x00 21. "  GMB85  ,Group Modifier Bit 85" "0,1"
bitfld.long 0x00 20. "  GMB84  ,Group Modifier Bit 84" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB83  ,Group Modifier Bit 83" "0,1"
bitfld.long 0x00 18. "  GMB82  ,Group Modifier Bit 82" "0,1"
bitfld.long 0x00 17. "  GMB81  ,Group Modifier Bit 81" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB80  ,Group Modifier Bit 80" "0,1"
bitfld.long 0x00 15. "  GMB79  ,Group Modifier Bit 79" "0,1"
bitfld.long 0x00 14. "  GMB78  ,Group Modifier Bit 78" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB77  ,Group Modifier Bit 77" "0,1"
bitfld.long 0x00 12. "  GMB76  ,Group Modifier Bit 76" "0,1"
bitfld.long 0x00 11. "  GMB75  ,Group Modifier Bit 75" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB74  ,Group Modifier Bit 74" "0,1"
bitfld.long 0x00 9. "  GMB73  ,Group Modifier Bit 73" "0,1"
bitfld.long 0x00 8. "  GMB72  ,Group Modifier Bit 72" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB71  ,Group Modifier Bit 71" "0,1"
bitfld.long 0x00 6. "  GMB70  ,Group Modifier Bit 70" "0,1"
bitfld.long 0x00 5. "  GMB69  ,Group Modifier Bit 69" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB68  ,Group Modifier Bit 68" "0,1"
bitfld.long 0x00 3. "  GMB67  ,Group Modifier Bit 67" "0,1"
bitfld.long 0x00 2. "  GMB66  ,Group Modifier Bit 66" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB65  ,Group Modifier Bit 65" "0,1"
bitfld.long 0x00 0. "  GMB64  ,Group Modifier Bit 64" "0,1"
else
hgroup.long 0x0D08++0x03
hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03))
group.long 0x0D0C++0x03
line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1"
bitfld.long 0x00 30. "  GMB126 ,Group Modifier Bit 126" "0,1"
bitfld.long 0x00 29. "  GMB125 ,Group Modifier Bit 125" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1"
bitfld.long 0x00 27. "  GMB123 ,Group Modifier Bit 123" "0,1"
bitfld.long 0x00 26. "  GMB122 ,Group Modifier Bit 122" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1"
bitfld.long 0x00 24. "  GMB120 ,Group Modifier Bit 120" "0,1"
bitfld.long 0x00 23. "  GMB119 ,Group Modifier Bit 119" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1"
bitfld.long 0x00 21. "  GMB117 ,Group Modifier Bit 117" "0,1"
bitfld.long 0x00 20. "  GMB116 ,Group Modifier Bit 116" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1"
bitfld.long 0x00 18. "  GMB114 ,Group Modifier Bit 114" "0,1"
bitfld.long 0x00 17. "  GMB113 ,Group Modifier Bit 113" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1"
bitfld.long 0x00 15. "  GMB111 ,Group Modifier Bit 111" "0,1"
bitfld.long 0x00 14. "  GMB110 ,Group Modifier Bit 110" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1"
bitfld.long 0x00 12. "  GMB108 ,Group Modifier Bit 108" "0,1"
bitfld.long 0x00 11. "  GMB107 ,Group Modifier Bit 107" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1"
bitfld.long 0x00 9. "  GMB105 ,Group Modifier Bit 105" "0,1"
bitfld.long 0x00 8. "  GMB104 ,Group Modifier Bit 104" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1"
bitfld.long 0x00 6. "  GMB102 ,Group Modifier Bit 102" "0,1"
bitfld.long 0x00 5. "  GMB101 ,Group Modifier Bit 101" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1"
bitfld.long 0x00 3. "  GMB99  ,Group Modifier Bit 99" "0,1"
bitfld.long 0x00 2. "  GMB98  ,Group Modifier Bit 98" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB97  ,Group Modifier Bit 97" "0,1"
bitfld.long 0x00 0. "  GMB96  ,Group Modifier Bit 96" "0,1"
else
hgroup.long 0x0D0C++0x03
hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04))
group.long 0x0D10++0x03
line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1"
bitfld.long 0x00 30. "  GMB158 ,Group Modifier Bit 158" "0,1"
bitfld.long 0x00 29. "  GMB157 ,Group Modifier Bit 157" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1"
bitfld.long 0x00 27. "  GMB155 ,Group Modifier Bit 155" "0,1"
bitfld.long 0x00 26. "  GMB154 ,Group Modifier Bit 154" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1"
bitfld.long 0x00 24. "  GMB152 ,Group Modifier Bit 152" "0,1"
bitfld.long 0x00 23. "  GMB151 ,Group Modifier Bit 151" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1"
bitfld.long 0x00 21. "  GMB149 ,Group Modifier Bit 149" "0,1"
bitfld.long 0x00 20. "  GMB148 ,Group Modifier Bit 148" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1"
bitfld.long 0x00 18. "  GMB146 ,Group Modifier Bit 146" "0,1"
bitfld.long 0x00 17. "  GMB145 ,Group Modifier Bit 145" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1"
bitfld.long 0x00 15. "  GMB143 ,Group Modifier Bit 143" "0,1"
bitfld.long 0x00 14. "  GMB142 ,Group Modifier Bit 142" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1"
bitfld.long 0x00 12. "  GMB140 ,Group Modifier Bit 140" "0,1"
bitfld.long 0x00 11. "  GMB139 ,Group Modifier Bit 139" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1"
bitfld.long 0x00 9. "  GMB137 ,Group Modifier Bit 137" "0,1"
bitfld.long 0x00 8. "  GMB136 ,Group Modifier Bit 136" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1"
bitfld.long 0x00 6. "  GMB134 ,Group Modifier Bit 134" "0,1"
bitfld.long 0x00 5. "  GMB133 ,Group Modifier Bit 133" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1"
bitfld.long 0x00 3. "  GMB131 ,Group Modifier Bit 131" "0,1"
bitfld.long 0x00 2. "  GMB130 ,Group Modifier Bit 130" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1"
bitfld.long 0x00 0. "  GMB128 ,Group Modifier Bit 128" "0,1"
else
hgroup.long 0x0D10++0x03
hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05))
group.long 0x0D14++0x03
line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1"
bitfld.long 0x00 30. "  GMB190 ,Group Modifier Bit 190" "0,1"
bitfld.long 0x00 29. "  GMB189 ,Group Modifier Bit 189" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1"
bitfld.long 0x00 27. "  GMB187 ,Group Modifier Bit 187" "0,1"
bitfld.long 0x00 26. "  GMB186 ,Group Modifier Bit 186" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1"
bitfld.long 0x00 24. "  GMB184 ,Group Modifier Bit 184" "0,1"
bitfld.long 0x00 23. "  GMB183 ,Group Modifier Bit 183" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1"
bitfld.long 0x00 21. "  GMB181 ,Group Modifier Bit 181" "0,1"
bitfld.long 0x00 20. "  GMB180 ,Group Modifier Bit 180" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1"
bitfld.long 0x00 18. "  GMB178 ,Group Modifier Bit 178" "0,1"
bitfld.long 0x00 17. "  GMB177 ,Group Modifier Bit 177" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1"
bitfld.long 0x00 15. "  GMB175 ,Group Modifier Bit 175" "0,1"
bitfld.long 0x00 14. "  GMB174 ,Group Modifier Bit 174" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1"
bitfld.long 0x00 12. "  GMB172 ,Group Modifier Bit 172" "0,1"
bitfld.long 0x00 11. "  GMB171 ,Group Modifier Bit 171" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1"
bitfld.long 0x00 9. "  GMB169 ,Group Modifier Bit 169" "0,1"
bitfld.long 0x00 8. "  GMB168 ,Group Modifier Bit 168" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1"
bitfld.long 0x00 6. "  GMB166 ,Group Modifier Bit 166" "0,1"
bitfld.long 0x00 5. "  GMB165 ,Group Modifier Bit 165" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1"
bitfld.long 0x00 3. "  GMB163 ,Group Modifier Bit 163" "0,1"
bitfld.long 0x00 2. "  GMB162 ,Group Modifier Bit 162" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1"
bitfld.long 0x00 0. "  GMB160 ,Group Modifier Bit 160" "0,1"
else
hgroup.long 0x0D14++0x03
hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06))
group.long 0x0D18++0x03
line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1"
bitfld.long 0x00 30. "  GMB222 ,Group Modifier Bit 222" "0,1"
bitfld.long 0x00 29. "  GMB221 ,Group Modifier Bit 221" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1"
bitfld.long 0x00 27. "  GMB219 ,Group Modifier Bit 219" "0,1"
bitfld.long 0x00 26. "  GMB218 ,Group Modifier Bit 218" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1"
bitfld.long 0x00 24. "  GMB216 ,Group Modifier Bit 216" "0,1"
bitfld.long 0x00 23. "  GMB215 ,Group Modifier Bit 215" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1"
bitfld.long 0x00 21. "  GMB213 ,Group Modifier Bit 213" "0,1"
bitfld.long 0x00 20. "  GMB212 ,Group Modifier Bit 212" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1"
bitfld.long 0x00 18. "  GMB210 ,Group Modifier Bit 210" "0,1"
bitfld.long 0x00 17. "  GMB209 ,Group Modifier Bit 209" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1"
bitfld.long 0x00 15. "  GMB207 ,Group Modifier Bit 207" "0,1"
bitfld.long 0x00 14. "  GMB206 ,Group Modifier Bit 206" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1"
bitfld.long 0x00 12. "  GMB204 ,Group Modifier Bit 204" "0,1"
bitfld.long 0x00 11. "  GMB203 ,Group Modifier Bit 203" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1"
bitfld.long 0x00 9. "  GMB201 ,Group Modifier Bit 201" "0,1"
bitfld.long 0x00 8. "  GMB200 ,Group Modifier Bit 200" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1"
bitfld.long 0x00 6. "  GMB198 ,Group Modifier Bit 198" "0,1"
bitfld.long 0x00 5. "  GMB197 ,Group Modifier Bit 197" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1"
bitfld.long 0x00 3. "  GMB195 ,Group Modifier Bit 195" "0,1"
bitfld.long 0x00 2. "  GMB194 ,Group Modifier Bit 194" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1"
bitfld.long 0x00 0. "  GMB192 ,Group Modifier Bit 192" "0,1"
else
hgroup.long 0x0D18++0x03
hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07))
group.long 0x0D1C++0x03
line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1"
bitfld.long 0x00 30. "  GMB254 ,Group Modifier Bit 254" "0,1"
bitfld.long 0x00 29. "  GMB253 ,Group Modifier Bit 253" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1"
bitfld.long 0x00 27. "  GMB251 ,Group Modifier Bit 251" "0,1"
bitfld.long 0x00 26. "  GMB250 ,Group Modifier Bit 250" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1"
bitfld.long 0x00 24. "  GMB248 ,Group Modifier Bit 248" "0,1"
bitfld.long 0x00 23. "  GMB247 ,Group Modifier Bit 247" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1"
bitfld.long 0x00 21. "  GMB245 ,Group Modifier Bit 245" "0,1"
bitfld.long 0x00 20. "  GMB244 ,Group Modifier Bit 244" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1"
bitfld.long 0x00 18. "  GMB242 ,Group Modifier Bit 242" "0,1"
bitfld.long 0x00 17. "  GMB241 ,Group Modifier Bit 241" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1"
bitfld.long 0x00 15. "  GMB239 ,Group Modifier Bit 239" "0,1"
bitfld.long 0x00 14. "  GMB238 ,Group Modifier Bit 238" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1"
bitfld.long 0x00 12. "  GMB236 ,Group Modifier Bit 236" "0,1"
bitfld.long 0x00 11. "  GMB235 ,Group Modifier Bit 235" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1"
bitfld.long 0x00 9. "  GMB233 ,Group Modifier Bit 233" "0,1"
bitfld.long 0x00 8. "  GMB232 ,Group Modifier Bit 232" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1"
bitfld.long 0x00 6. "  GMB230 ,Group Modifier Bit 230" "0,1"
bitfld.long 0x00 5. "  GMB229 ,Group Modifier Bit 229" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1"
bitfld.long 0x00 3. "  GMB227 ,Group Modifier Bit 227" "0,1"
bitfld.long 0x00 2. "  GMB226 ,Group Modifier Bit 226" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1"
bitfld.long 0x00 0. "  GMB224 ,Group Modifier Bit 224" "0,1"
else
hgroup.long 0x0D1C++0x03
hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08))
group.long 0x0D20++0x03
line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1"
bitfld.long 0x00 30. "  GMB286 ,Group Modifier Bit 286" "0,1"
bitfld.long 0x00 29. "  GMB285 ,Group Modifier Bit 285" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1"
bitfld.long 0x00 27. "  GMB283 ,Group Modifier Bit 283" "0,1"
bitfld.long 0x00 26. "  GMB282 ,Group Modifier Bit 282" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1"
bitfld.long 0x00 24. "  GMB280 ,Group Modifier Bit 280" "0,1"
bitfld.long 0x00 23. "  GMB279 ,Group Modifier Bit 279" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1"
bitfld.long 0x00 21. "  GMB277 ,Group Modifier Bit 277" "0,1"
bitfld.long 0x00 20. "  GMB276 ,Group Modifier Bit 276" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1"
bitfld.long 0x00 18. "  GMB274 ,Group Modifier Bit 274" "0,1"
bitfld.long 0x00 17. "  GMB273 ,Group Modifier Bit 273" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1"
bitfld.long 0x00 15. "  GMB271 ,Group Modifier Bit 271" "0,1"
bitfld.long 0x00 14. "  GMB270 ,Group Modifier Bit 270" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1"
bitfld.long 0x00 12. "  GMB268 ,Group Modifier Bit 268" "0,1"
bitfld.long 0x00 11. "  GMB267 ,Group Modifier Bit 267" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1"
bitfld.long 0x00 9. "  GMB265 ,Group Modifier Bit 265" "0,1"
bitfld.long 0x00 8. "  GMB264 ,Group Modifier Bit 264" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1"
bitfld.long 0x00 6. "  GMB262 ,Group Modifier Bit 262" "0,1"
bitfld.long 0x00 5. "  GMB261 ,Group Modifier Bit 261" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1"
bitfld.long 0x00 3. "  GMB259 ,Group Modifier Bit 259" "0,1"
bitfld.long 0x00 2. "  GMB258 ,Group Modifier Bit 258" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1"
bitfld.long 0x00 0. "  GMB256 ,Group Modifier Bit 256" "0,1"
else
hgroup.long 0x0D20++0x03
hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09))
group.long 0x0D24++0x03
line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1"
bitfld.long 0x00 30. "  GMB318 ,Group Modifier Bit 318" "0,1"
bitfld.long 0x00 29. "  GMB317 ,Group Modifier Bit 317" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1"
bitfld.long 0x00 27. "  GMB315 ,Group Modifier Bit 315" "0,1"
bitfld.long 0x00 26. "  GMB314 ,Group Modifier Bit 314" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1"
bitfld.long 0x00 24. "  GMB312 ,Group Modifier Bit 312" "0,1"
bitfld.long 0x00 23. "  GMB311 ,Group Modifier Bit 311" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1"
bitfld.long 0x00 21. "  GMB309 ,Group Modifier Bit 309" "0,1"
bitfld.long 0x00 20. "  GMB308 ,Group Modifier Bit 308" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1"
bitfld.long 0x00 18. "  GMB306 ,Group Modifier Bit 306" "0,1"
bitfld.long 0x00 17. "  GMB305 ,Group Modifier Bit 305" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1"
bitfld.long 0x00 15. "  GMB303 ,Group Modifier Bit 303" "0,1"
bitfld.long 0x00 14. "  GMB302 ,Group Modifier Bit 302" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1"
bitfld.long 0x00 12. "  GMB300 ,Group Modifier Bit 300" "0,1"
bitfld.long 0x00 11. "  GMB299 ,Group Modifier Bit 299" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1"
bitfld.long 0x00 9. "  GMB297 ,Group Modifier Bit 297" "0,1"
bitfld.long 0x00 8. "  GMB296 ,Group Modifier Bit 296" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1"
bitfld.long 0x00 6. "  GMB294 ,Group Modifier Bit 294" "0,1"
bitfld.long 0x00 5. "  GMB293 ,Group Modifier Bit 293" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1"
bitfld.long 0x00 3. "  GMB291 ,Group Modifier Bit 291" "0,1"
bitfld.long 0x00 2. "  GMB290 ,Group Modifier Bit 290" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1"
bitfld.long 0x00 0. "  GMB288 ,Group Modifier Bit 288" "0,1"
else
hgroup.long 0x0D24++0x03
hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A))
group.long 0x0D28++0x03
line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1"
bitfld.long 0x00 30. "  GMB350 ,Group Modifier Bit 350" "0,1"
bitfld.long 0x00 29. "  GMB349 ,Group Modifier Bit 349" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1"
bitfld.long 0x00 27. "  GMB347 ,Group Modifier Bit 347" "0,1"
bitfld.long 0x00 26. "  GMB346 ,Group Modifier Bit 346" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1"
bitfld.long 0x00 24. "  GMB344 ,Group Modifier Bit 344" "0,1"
bitfld.long 0x00 23. "  GMB343 ,Group Modifier Bit 343" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1"
bitfld.long 0x00 21. "  GMB341 ,Group Modifier Bit 341" "0,1"
bitfld.long 0x00 20. "  GMB340 ,Group Modifier Bit 340" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1"
bitfld.long 0x00 18. "  GMB338 ,Group Modifier Bit 338" "0,1"
bitfld.long 0x00 17. "  GMB337 ,Group Modifier Bit 337" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1"
bitfld.long 0x00 15. "  GMB335 ,Group Modifier Bit 335" "0,1"
bitfld.long 0x00 14. "  GMB334 ,Group Modifier Bit 334" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1"
bitfld.long 0x00 12. "  GMB332 ,Group Modifier Bit 332" "0,1"
bitfld.long 0x00 11. "  GMB331 ,Group Modifier Bit 331" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1"
bitfld.long 0x00 9. "  GMB329 ,Group Modifier Bit 329" "0,1"
bitfld.long 0x00 8. "  GMB328 ,Group Modifier Bit 328" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1"
bitfld.long 0x00 6. "  GMB326 ,Group Modifier Bit 326" "0,1"
bitfld.long 0x00 5. "  GMB325 ,Group Modifier Bit 325" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1"
bitfld.long 0x00 3. "  GMB323 ,Group Modifier Bit 323" "0,1"
bitfld.long 0x00 2. "  GMB322 ,Group Modifier Bit 322" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1"
bitfld.long 0x00 0. "  GMB320 ,Group Modifier Bit 320" "0,1"
else
hgroup.long 0x0D28++0x03
hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B))
group.long 0x0D2C++0x03
line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1"
bitfld.long 0x00 30. "  GMB382 ,Group Modifier Bit 382" "0,1"
bitfld.long 0x00 29. "  GMB381 ,Group Modifier Bit 381" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1"
bitfld.long 0x00 27. "  GMB379 ,Group Modifier Bit 379" "0,1"
bitfld.long 0x00 26. "  GMB378 ,Group Modifier Bit 378" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1"
bitfld.long 0x00 24. "  GMB376 ,Group Modifier Bit 376" "0,1"
bitfld.long 0x00 23. "  GMB375 ,Group Modifier Bit 375" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1"
bitfld.long 0x00 21. "  GMB373 ,Group Modifier Bit 373" "0,1"
bitfld.long 0x00 20. "  GMB372 ,Group Modifier Bit 372" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1"
bitfld.long 0x00 18. "  GMB370 ,Group Modifier Bit 370" "0,1"
bitfld.long 0x00 17. "  GMB369 ,Group Modifier Bit 369" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1"
bitfld.long 0x00 15. "  GMB367 ,Group Modifier Bit 367" "0,1"
bitfld.long 0x00 14. "  GMB366 ,Group Modifier Bit 366" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1"
bitfld.long 0x00 12. "  GMB364 ,Group Modifier Bit 364" "0,1"
bitfld.long 0x00 11. "  GMB363 ,Group Modifier Bit 363" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1"
bitfld.long 0x00 9. "  GMB361 ,Group Modifier Bit 361" "0,1"
bitfld.long 0x00 8. "  GMB360 ,Group Modifier Bit 360" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1"
bitfld.long 0x00 6. "  GMB358 ,Group Modifier Bit 358" "0,1"
bitfld.long 0x00 5. "  GMB357 ,Group Modifier Bit 357" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1"
bitfld.long 0x00 3. "  GMB355 ,Group Modifier Bit 355" "0,1"
bitfld.long 0x00 2. "  GMB354 ,Group Modifier Bit 354" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1"
bitfld.long 0x00 0. "  GMB352 ,Group Modifier Bit 352" "0,1"
else
hgroup.long 0x0D2C++0x03
hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C))
group.long 0x0D30++0x03
line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1"
bitfld.long 0x00 30. "  GMB414 ,Group Modifier Bit 414" "0,1"
bitfld.long 0x00 29. "  GMB413 ,Group Modifier Bit 413" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1"
bitfld.long 0x00 27. "  GMB411 ,Group Modifier Bit 411" "0,1"
bitfld.long 0x00 26. "  GMB410 ,Group Modifier Bit 410" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1"
bitfld.long 0x00 24. "  GMB408 ,Group Modifier Bit 408" "0,1"
bitfld.long 0x00 23. "  GMB407 ,Group Modifier Bit 407" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1"
bitfld.long 0x00 21. "  GMB405 ,Group Modifier Bit 405" "0,1"
bitfld.long 0x00 20. "  GMB404 ,Group Modifier Bit 404" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1"
bitfld.long 0x00 18. "  GMB402 ,Group Modifier Bit 402" "0,1"
bitfld.long 0x00 17. "  GMB401 ,Group Modifier Bit 401" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1"
bitfld.long 0x00 15. "  GMB399 ,Group Modifier Bit 399" "0,1"
bitfld.long 0x00 14. "  GMB398 ,Group Modifier Bit 398" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1"
bitfld.long 0x00 12. "  GMB396 ,Group Modifier Bit 396" "0,1"
bitfld.long 0x00 11. "  GMB395 ,Group Modifier Bit 395" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1"
bitfld.long 0x00 9. "  GMB393 ,Group Modifier Bit 393" "0,1"
bitfld.long 0x00 8. "  GMB392 ,Group Modifier Bit 392" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1"
bitfld.long 0x00 6. "  GMB390 ,Group Modifier Bit 390" "0,1"
bitfld.long 0x00 5. "  GMB389 ,Group Modifier Bit 389" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1"
bitfld.long 0x00 3. "  GMB387 ,Group Modifier Bit 387" "0,1"
bitfld.long 0x00 2. "  GMB386 ,Group Modifier Bit 386" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1"
bitfld.long 0x00 0. "  GMB384 ,Group Modifier Bit 384" "0,1"
else
hgroup.long 0x0D30++0x03
hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D))
group.long 0x0D34++0x03
line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1"
bitfld.long 0x00 30. "  GMB446 ,Group Modifier Bit 446" "0,1"
bitfld.long 0x00 29. "  GMB445 ,Group Modifier Bit 445" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1"
bitfld.long 0x00 27. "  GMB443 ,Group Modifier Bit 443" "0,1"
bitfld.long 0x00 26. "  GMB442 ,Group Modifier Bit 442" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1"
bitfld.long 0x00 24. "  GMB440 ,Group Modifier Bit 440" "0,1"
bitfld.long 0x00 23. "  GMB439 ,Group Modifier Bit 439" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1"
bitfld.long 0x00 21. "  GMB437 ,Group Modifier Bit 437" "0,1"
bitfld.long 0x00 20. "  GMB436 ,Group Modifier Bit 436" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1"
bitfld.long 0x00 18. "  GMB434 ,Group Modifier Bit 434" "0,1"
bitfld.long 0x00 17. "  GMB433 ,Group Modifier Bit 433" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1"
bitfld.long 0x00 15. "  GMB431 ,Group Modifier Bit 431" "0,1"
bitfld.long 0x00 14. "  GMB430 ,Group Modifier Bit 430" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1"
bitfld.long 0x00 12. "  GMB428 ,Group Modifier Bit 428" "0,1"
bitfld.long 0x00 11. "  GMB427 ,Group Modifier Bit 427" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1"
bitfld.long 0x00 9. "  GMB425 ,Group Modifier Bit 425" "0,1"
bitfld.long 0x00 8. "  GMB424 ,Group Modifier Bit 424" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1"
bitfld.long 0x00 6. "  GMB422 ,Group Modifier Bit 422" "0,1"
bitfld.long 0x00 5. "  GMB421 ,Group Modifier Bit 421" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1"
bitfld.long 0x00 3. "  GMB419 ,Group Modifier Bit 419" "0,1"
bitfld.long 0x00 2. "  GMB418 ,Group Modifier Bit 418" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1"
bitfld.long 0x00 0. "  GMB416 ,Group Modifier Bit 416" "0,1"
else
hgroup.long 0x0D34++0x03
hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E))
group.long 0x0D38++0x03
line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1"
bitfld.long 0x00 30. "  GMB478 ,Group Modifier Bit 478" "0,1"
bitfld.long 0x00 29. "  GMB477 ,Group Modifier Bit 477" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1"
bitfld.long 0x00 27. "  GMB475 ,Group Modifier Bit 475" "0,1"
bitfld.long 0x00 26. "  GMB474 ,Group Modifier Bit 474" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1"
bitfld.long 0x00 24. "  GMB472 ,Group Modifier Bit 472" "0,1"
bitfld.long 0x00 23. "  GMB471 ,Group Modifier Bit 471" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1"
bitfld.long 0x00 21. "  GMB469 ,Group Modifier Bit 469" "0,1"
bitfld.long 0x00 20. "  GMB468 ,Group Modifier Bit 468" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1"
bitfld.long 0x00 18. "  GMB466 ,Group Modifier Bit 466" "0,1"
bitfld.long 0x00 17. "  GMB465 ,Group Modifier Bit 465" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1"
bitfld.long 0x00 15. "  GMB463 ,Group Modifier Bit 463" "0,1"
bitfld.long 0x00 14. "  GMB462 ,Group Modifier Bit 462" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1"
bitfld.long 0x00 12. "  GMB460 ,Group Modifier Bit 460" "0,1"
bitfld.long 0x00 11. "  GMB459 ,Group Modifier Bit 459" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1"
bitfld.long 0x00 9. "  GMB457 ,Group Modifier Bit 457" "0,1"
bitfld.long 0x00 8. "  GMB456 ,Group Modifier Bit 456" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1"
bitfld.long 0x00 6. "  GMB454 ,Group Modifier Bit 454" "0,1"
bitfld.long 0x00 5. "  GMB453 ,Group Modifier Bit 453" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1"
bitfld.long 0x00 3. "  GMB451 ,Group Modifier Bit 451" "0,1"
bitfld.long 0x00 2. "  GMB450 ,Group Modifier Bit 450" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1"
bitfld.long 0x00 0. "  GMB448 ,Group Modifier Bit 448" "0,1"
else
hgroup.long 0x0D38++0x03
hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F))
group.long 0x0D3C++0x03
line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1"
bitfld.long 0x00 30. "  GMB510 ,Group Modifier Bit 510" "0,1"
bitfld.long 0x00 29. "  GMB509 ,Group Modifier Bit 509" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1"
bitfld.long 0x00 27. "  GMB507 ,Group Modifier Bit 507" "0,1"
bitfld.long 0x00 26. "  GMB506 ,Group Modifier Bit 506" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1"
bitfld.long 0x00 24. "  GMB504 ,Group Modifier Bit 504" "0,1"
bitfld.long 0x00 23. "  GMB503 ,Group Modifier Bit 503" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1"
bitfld.long 0x00 21. "  GMB501 ,Group Modifier Bit 501" "0,1"
bitfld.long 0x00 20. "  GMB500 ,Group Modifier Bit 500" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1"
bitfld.long 0x00 18. "  GMB498 ,Group Modifier Bit 498" "0,1"
bitfld.long 0x00 17. "  GMB497 ,Group Modifier Bit 497" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1"
bitfld.long 0x00 15. "  GMB495 ,Group Modifier Bit 495" "0,1"
bitfld.long 0x00 14. "  GMB494 ,Group Modifier Bit 494" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1"
bitfld.long 0x00 12. "  GMB492 ,Group Modifier Bit 492" "0,1"
bitfld.long 0x00 11. "  GMB491 ,Group Modifier Bit 491" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1"
bitfld.long 0x00 9. "  GMB489 ,Group Modifier Bit 489" "0,1"
bitfld.long 0x00 8. "  GMB488 ,Group Modifier Bit 488" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1"
bitfld.long 0x00 6. "  GMB486 ,Group Modifier Bit 486" "0,1"
bitfld.long 0x00 5. "  GMB485 ,Group Modifier Bit 485" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1"
bitfld.long 0x00 3. "  GMB483 ,Group Modifier Bit 483" "0,1"
bitfld.long 0x00 2. "  GMB482 ,Group Modifier Bit 482" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1"
bitfld.long 0x00 0. "  GMB480 ,Group Modifier Bit 480" "0,1"
else
hgroup.long 0x0D3C++0x03
hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x0D40++0x03
line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1"
bitfld.long 0x00 30. "  GMB542 ,Group Modifier Bit 542" "0,1"
bitfld.long 0x00 29. "  GMB541 ,Group Modifier Bit 541" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1"
bitfld.long 0x00 27. "  GMB539 ,Group Modifier Bit 539" "0,1"
bitfld.long 0x00 26. "  GMB538 ,Group Modifier Bit 538" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1"
bitfld.long 0x00 24. "  GMB536 ,Group Modifier Bit 536" "0,1"
bitfld.long 0x00 23. "  GMB535 ,Group Modifier Bit 535" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1"
bitfld.long 0x00 21. "  GMB533 ,Group Modifier Bit 533" "0,1"
bitfld.long 0x00 20. "  GMB532 ,Group Modifier Bit 532" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1"
bitfld.long 0x00 18. "  GMB530 ,Group Modifier Bit 530" "0,1"
bitfld.long 0x00 17. "  GMB529 ,Group Modifier Bit 529" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1"
bitfld.long 0x00 15. "  GMB527 ,Group Modifier Bit 527" "0,1"
bitfld.long 0x00 14. "  GMB526 ,Group Modifier Bit 526" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1"
bitfld.long 0x00 12. "  GMB524 ,Group Modifier Bit 524" "0,1"
bitfld.long 0x00 11. "  GMB523 ,Group Modifier Bit 523" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1"
bitfld.long 0x00 9. "  GMB521 ,Group Modifier Bit 521" "0,1"
bitfld.long 0x00 8. "  GMB520 ,Group Modifier Bit 520" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1"
bitfld.long 0x00 6. "  GMB518 ,Group Modifier Bit 518" "0,1"
bitfld.long 0x00 5. "  GMB517 ,Group Modifier Bit 517" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1"
bitfld.long 0x00 3. "  GMB515 ,Group Modifier Bit 515" "0,1"
bitfld.long 0x00 2. "  GMB514 ,Group Modifier Bit 514" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1"
bitfld.long 0x00 0. "  GMB512 ,Group Modifier Bit 512" "0,1"
else
hgroup.long 0x0D40++0x03
hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x0D44++0x03
line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1"
bitfld.long 0x00 30. "  GMB574 ,Group Modifier Bit 574" "0,1"
bitfld.long 0x00 29. "  GMB573 ,Group Modifier Bit 573" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1"
bitfld.long 0x00 27. "  GMB571 ,Group Modifier Bit 571" "0,1"
bitfld.long 0x00 26. "  GMB570 ,Group Modifier Bit 570" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1"
bitfld.long 0x00 24. "  GMB568 ,Group Modifier Bit 568" "0,1"
bitfld.long 0x00 23. "  GMB567 ,Group Modifier Bit 567" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1"
bitfld.long 0x00 21. "  GMB565 ,Group Modifier Bit 565" "0,1"
bitfld.long 0x00 20. "  GMB564 ,Group Modifier Bit 564" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1"
bitfld.long 0x00 18. "  GMB562 ,Group Modifier Bit 562" "0,1"
bitfld.long 0x00 17. "  GMB561 ,Group Modifier Bit 561" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1"
bitfld.long 0x00 15. "  GMB559 ,Group Modifier Bit 559" "0,1"
bitfld.long 0x00 14. "  GMB558 ,Group Modifier Bit 558" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1"
bitfld.long 0x00 12. "  GMB556 ,Group Modifier Bit 556" "0,1"
bitfld.long 0x00 11. "  GMB555 ,Group Modifier Bit 555" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1"
bitfld.long 0x00 9. "  GMB553 ,Group Modifier Bit 553" "0,1"
bitfld.long 0x00 8. "  GMB552 ,Group Modifier Bit 552" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1"
bitfld.long 0x00 6. "  GMB550 ,Group Modifier Bit 550" "0,1"
bitfld.long 0x00 5. "  GMB549 ,Group Modifier Bit 549" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1"
bitfld.long 0x00 3. "  GMB547 ,Group Modifier Bit 547" "0,1"
bitfld.long 0x00 2. "  GMB546 ,Group Modifier Bit 546" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1"
bitfld.long 0x00 0. "  GMB544 ,Group Modifier Bit 544" "0,1"
else
hgroup.long 0x0D44++0x03
hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x0D48++0x03
line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1"
bitfld.long 0x00 30. "  GMB606 ,Group Modifier Bit 606" "0,1"
bitfld.long 0x00 29. "  GMB605 ,Group Modifier Bit 605" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1"
bitfld.long 0x00 27. "  GMB603 ,Group Modifier Bit 603" "0,1"
bitfld.long 0x00 26. "  GMB602 ,Group Modifier Bit 602" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1"
bitfld.long 0x00 24. "  GMB600 ,Group Modifier Bit 600" "0,1"
bitfld.long 0x00 23. "  GMB599 ,Group Modifier Bit 599" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1"
bitfld.long 0x00 21. "  GMB597 ,Group Modifier Bit 597" "0,1"
bitfld.long 0x00 20. "  GMB596 ,Group Modifier Bit 596" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1"
bitfld.long 0x00 18. "  GMB594 ,Group Modifier Bit 594" "0,1"
bitfld.long 0x00 17. "  GMB593 ,Group Modifier Bit 593" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1"
bitfld.long 0x00 15. "  GMB591 ,Group Modifier Bit 591" "0,1"
bitfld.long 0x00 14. "  GMB590 ,Group Modifier Bit 590" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1"
bitfld.long 0x00 12. "  GMB588 ,Group Modifier Bit 588" "0,1"
bitfld.long 0x00 11. "  GMB587 ,Group Modifier Bit 587" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1"
bitfld.long 0x00 9. "  GMB585 ,Group Modifier Bit 585" "0,1"
bitfld.long 0x00 8. "  GMB584 ,Group Modifier Bit 584" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1"
bitfld.long 0x00 6. "  GMB582 ,Group Modifier Bit 582" "0,1"
bitfld.long 0x00 5. "  GMB581 ,Group Modifier Bit 581" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1"
bitfld.long 0x00 3. "  GMB579 ,Group Modifier Bit 579" "0,1"
bitfld.long 0x00 2. "  GMB578 ,Group Modifier Bit 578" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1"
bitfld.long 0x00 0. "  GMB576 ,Group Modifier Bit 576" "0,1"
else
hgroup.long 0x0D48++0x03
hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x0D4C++0x03
line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1"
bitfld.long 0x00 30. "  GMB638 ,Group Modifier Bit 638" "0,1"
bitfld.long 0x00 29. "  GMB637 ,Group Modifier Bit 637" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1"
bitfld.long 0x00 27. "  GMB635 ,Group Modifier Bit 635" "0,1"
bitfld.long 0x00 26. "  GMB634 ,Group Modifier Bit 634" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1"
bitfld.long 0x00 24. "  GMB632 ,Group Modifier Bit 632" "0,1"
bitfld.long 0x00 23. "  GMB631 ,Group Modifier Bit 631" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1"
bitfld.long 0x00 21. "  GMB629 ,Group Modifier Bit 629" "0,1"
bitfld.long 0x00 20. "  GMB628 ,Group Modifier Bit 628" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1"
bitfld.long 0x00 18. "  GMB626 ,Group Modifier Bit 626" "0,1"
bitfld.long 0x00 17. "  GMB625 ,Group Modifier Bit 625" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1"
bitfld.long 0x00 15. "  GMB623 ,Group Modifier Bit 623" "0,1"
bitfld.long 0x00 14. "  GMB622 ,Group Modifier Bit 622" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1"
bitfld.long 0x00 12. "  GMB620 ,Group Modifier Bit 620" "0,1"
bitfld.long 0x00 11. "  GMB619 ,Group Modifier Bit 619" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1"
bitfld.long 0x00 9. "  GMB617 ,Group Modifier Bit 617" "0,1"
bitfld.long 0x00 8. "  GMB616 ,Group Modifier Bit 616" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1"
bitfld.long 0x00 6. "  GMB614 ,Group Modifier Bit 614" "0,1"
bitfld.long 0x00 5. "  GMB613 ,Group Modifier Bit 613" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1"
bitfld.long 0x00 3. "  GMB611 ,Group Modifier Bit 611" "0,1"
bitfld.long 0x00 2. "  GMB610 ,Group Modifier Bit 610" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1"
bitfld.long 0x00 0. "  GMB608 ,Group Modifier Bit 608" "0,1"
else
hgroup.long 0x0D4C++0x03
hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x0D50++0x03
line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1"
bitfld.long 0x00 30. "  GMB670 ,Group Modifier Bit 670" "0,1"
bitfld.long 0x00 29. "  GMB669 ,Group Modifier Bit 669" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1"
bitfld.long 0x00 27. "  GMB667 ,Group Modifier Bit 667" "0,1"
bitfld.long 0x00 26. "  GMB666 ,Group Modifier Bit 666" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1"
bitfld.long 0x00 24. "  GMB664 ,Group Modifier Bit 664" "0,1"
bitfld.long 0x00 23. "  GMB663 ,Group Modifier Bit 663" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1"
bitfld.long 0x00 21. "  GMB661 ,Group Modifier Bit 661" "0,1"
bitfld.long 0x00 20. "  GMB660 ,Group Modifier Bit 660" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1"
bitfld.long 0x00 18. "  GMB658 ,Group Modifier Bit 658" "0,1"
bitfld.long 0x00 17. "  GMB657 ,Group Modifier Bit 657" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1"
bitfld.long 0x00 15. "  GMB655 ,Group Modifier Bit 655" "0,1"
bitfld.long 0x00 14. "  GMB654 ,Group Modifier Bit 654" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1"
bitfld.long 0x00 12. "  GMB652 ,Group Modifier Bit 652" "0,1"
bitfld.long 0x00 11. "  GMB651 ,Group Modifier Bit 651" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1"
bitfld.long 0x00 9. "  GMB649 ,Group Modifier Bit 649" "0,1"
bitfld.long 0x00 8. "  GMB648 ,Group Modifier Bit 648" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1"
bitfld.long 0x00 6. "  GMB646 ,Group Modifier Bit 646" "0,1"
bitfld.long 0x00 5. "  GMB645 ,Group Modifier Bit 645" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1"
bitfld.long 0x00 3. "  GMB643 ,Group Modifier Bit 643" "0,1"
bitfld.long 0x00 2. "  GMB642 ,Group Modifier Bit 642" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1"
bitfld.long 0x00 0. "  GMB640 ,Group Modifier Bit 640" "0,1"
else
hgroup.long 0x0D50++0x03
hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x0D54++0x03
line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1"
bitfld.long 0x00 30. "  GMB702 ,Group Modifier Bit 702" "0,1"
bitfld.long 0x00 29. "  GMB701 ,Group Modifier Bit 701" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1"
bitfld.long 0x00 27. "  GMB699 ,Group Modifier Bit 699" "0,1"
bitfld.long 0x00 26. "  GMB698 ,Group Modifier Bit 698" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1"
bitfld.long 0x00 24. "  GMB696 ,Group Modifier Bit 696" "0,1"
bitfld.long 0x00 23. "  GMB695 ,Group Modifier Bit 695" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1"
bitfld.long 0x00 21. "  GMB693 ,Group Modifier Bit 693" "0,1"
bitfld.long 0x00 20. "  GMB692 ,Group Modifier Bit 692" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1"
bitfld.long 0x00 18. "  GMB690 ,Group Modifier Bit 690" "0,1"
bitfld.long 0x00 17. "  GMB689 ,Group Modifier Bit 689" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1"
bitfld.long 0x00 15. "  GMB687 ,Group Modifier Bit 687" "0,1"
bitfld.long 0x00 14. "  GMB686 ,Group Modifier Bit 686" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1"
bitfld.long 0x00 12. "  GMB684 ,Group Modifier Bit 684" "0,1"
bitfld.long 0x00 11. "  GMB683 ,Group Modifier Bit 683" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1"
bitfld.long 0x00 9. "  GMB681 ,Group Modifier Bit 681" "0,1"
bitfld.long 0x00 8. "  GMB680 ,Group Modifier Bit 680" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1"
bitfld.long 0x00 6. "  GMB678 ,Group Modifier Bit 678" "0,1"
bitfld.long 0x00 5. "  GMB677 ,Group Modifier Bit 677" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1"
bitfld.long 0x00 3. "  GMB675 ,Group Modifier Bit 675" "0,1"
bitfld.long 0x00 2. "  GMB674 ,Group Modifier Bit 674" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1"
bitfld.long 0x00 0. "  GMB672 ,Group Modifier Bit 672" "0,1"
else
hgroup.long 0x0D54++0x03
hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x0D58++0x03
line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1"
bitfld.long 0x00 30. "  GMB734 ,Group Modifier Bit 734" "0,1"
bitfld.long 0x00 29. "  GMB733 ,Group Modifier Bit 733" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1"
bitfld.long 0x00 27. "  GMB731 ,Group Modifier Bit 731" "0,1"
bitfld.long 0x00 26. "  GMB730 ,Group Modifier Bit 730" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1"
bitfld.long 0x00 24. "  GMB728 ,Group Modifier Bit 728" "0,1"
bitfld.long 0x00 23. "  GMB727 ,Group Modifier Bit 727" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1"
bitfld.long 0x00 21. "  GMB725 ,Group Modifier Bit 725" "0,1"
bitfld.long 0x00 20. "  GMB724 ,Group Modifier Bit 724" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1"
bitfld.long 0x00 18. "  GMB722 ,Group Modifier Bit 722" "0,1"
bitfld.long 0x00 17. "  GMB721 ,Group Modifier Bit 721" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1"
bitfld.long 0x00 15. "  GMB719 ,Group Modifier Bit 719" "0,1"
bitfld.long 0x00 14. "  GMB718 ,Group Modifier Bit 718" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1"
bitfld.long 0x00 12. "  GMB716 ,Group Modifier Bit 716" "0,1"
bitfld.long 0x00 11. "  GMB715 ,Group Modifier Bit 715" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1"
bitfld.long 0x00 9. "  GMB713 ,Group Modifier Bit 713" "0,1"
bitfld.long 0x00 8. "  GMB712 ,Group Modifier Bit 712" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1"
bitfld.long 0x00 6. "  GMB710 ,Group Modifier Bit 710" "0,1"
bitfld.long 0x00 5. "  GMB709 ,Group Modifier Bit 709" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1"
bitfld.long 0x00 3. "  GMB707 ,Group Modifier Bit 707" "0,1"
bitfld.long 0x00 2. "  GMB706 ,Group Modifier Bit 706" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1"
bitfld.long 0x00 0. "  GMB704 ,Group Modifier Bit 704" "0,1"
else
hgroup.long 0x0D58++0x03
hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x0D5C++0x03
line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1"
bitfld.long 0x00 30. "  GMB766 ,Group Modifier Bit 766" "0,1"
bitfld.long 0x00 29. "  GMB765 ,Group Modifier Bit 765" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1"
bitfld.long 0x00 27. "  GMB763 ,Group Modifier Bit 763" "0,1"
bitfld.long 0x00 26. "  GMB762 ,Group Modifier Bit 762" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1"
bitfld.long 0x00 24. "  GMB760 ,Group Modifier Bit 760" "0,1"
bitfld.long 0x00 23. "  GMB759 ,Group Modifier Bit 759" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1"
bitfld.long 0x00 21. "  GMB757 ,Group Modifier Bit 757" "0,1"
bitfld.long 0x00 20. "  GMB756 ,Group Modifier Bit 756" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1"
bitfld.long 0x00 18. "  GMB754 ,Group Modifier Bit 754" "0,1"
bitfld.long 0x00 17. "  GMB753 ,Group Modifier Bit 753" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1"
bitfld.long 0x00 15. "  GMB751 ,Group Modifier Bit 751" "0,1"
bitfld.long 0x00 14. "  GMB750 ,Group Modifier Bit 750" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1"
bitfld.long 0x00 12. "  GMB748 ,Group Modifier Bit 748" "0,1"
bitfld.long 0x00 11. "  GMB747 ,Group Modifier Bit 747" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1"
bitfld.long 0x00 9. "  GMB745 ,Group Modifier Bit 745" "0,1"
bitfld.long 0x00 8. "  GMB744 ,Group Modifier Bit 744" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1"
bitfld.long 0x00 6. "  GMB742 ,Group Modifier Bit 742" "0,1"
bitfld.long 0x00 5. "  GMB741 ,Group Modifier Bit 741" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1"
bitfld.long 0x00 3. "  GMB739 ,Group Modifier Bit 739" "0,1"
bitfld.long 0x00 2. "  GMB738 ,Group Modifier Bit 738" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1"
bitfld.long 0x00 0. "  GMB736 ,Group Modifier Bit 736" "0,1"
else
hgroup.long 0x0D5C++0x03
hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x0D60++0x03
line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1"
bitfld.long 0x00 30. "  GMB798 ,Group Modifier Bit 798" "0,1"
bitfld.long 0x00 29. "  GMB797 ,Group Modifier Bit 797" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1"
bitfld.long 0x00 27. "  GMB795 ,Group Modifier Bit 795" "0,1"
bitfld.long 0x00 26. "  GMB794 ,Group Modifier Bit 794" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1"
bitfld.long 0x00 24. "  GMB792 ,Group Modifier Bit 792" "0,1"
bitfld.long 0x00 23. "  GMB791 ,Group Modifier Bit 791" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1"
bitfld.long 0x00 21. "  GMB789 ,Group Modifier Bit 789" "0,1"
bitfld.long 0x00 20. "  GMB788 ,Group Modifier Bit 788" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1"
bitfld.long 0x00 18. "  GMB786 ,Group Modifier Bit 786" "0,1"
bitfld.long 0x00 17. "  GMB785 ,Group Modifier Bit 785" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1"
bitfld.long 0x00 15. "  GMB783 ,Group Modifier Bit 783" "0,1"
bitfld.long 0x00 14. "  GMB782 ,Group Modifier Bit 782" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1"
bitfld.long 0x00 12. "  GMB780 ,Group Modifier Bit 780" "0,1"
bitfld.long 0x00 11. "  GMB779 ,Group Modifier Bit 779" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1"
bitfld.long 0x00 9. "  GMB777 ,Group Modifier Bit 777" "0,1"
bitfld.long 0x00 8. "  GMB776 ,Group Modifier Bit 776" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1"
bitfld.long 0x00 6. "  GMB774 ,Group Modifier Bit 774" "0,1"
bitfld.long 0x00 5. "  GMB773 ,Group Modifier Bit 773" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1"
bitfld.long 0x00 3. "  GMB771 ,Group Modifier Bit 771" "0,1"
bitfld.long 0x00 2. "  GMB770 ,Group Modifier Bit 770" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1"
bitfld.long 0x00 0. "  GMB768 ,Group Modifier Bit 768" "0,1"
else
hgroup.long 0x0D60++0x03
hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x0D64++0x03
line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1"
bitfld.long 0x00 30. "  GMB830 ,Group Modifier Bit 830" "0,1"
bitfld.long 0x00 29. "  GMB829 ,Group Modifier Bit 829" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1"
bitfld.long 0x00 27. "  GMB827 ,Group Modifier Bit 827" "0,1"
bitfld.long 0x00 26. "  GMB826 ,Group Modifier Bit 826" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1"
bitfld.long 0x00 24. "  GMB824 ,Group Modifier Bit 824" "0,1"
bitfld.long 0x00 23. "  GMB823 ,Group Modifier Bit 823" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1"
bitfld.long 0x00 21. "  GMB821 ,Group Modifier Bit 821" "0,1"
bitfld.long 0x00 20. "  GMB820 ,Group Modifier Bit 820" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1"
bitfld.long 0x00 18. "  GMB818 ,Group Modifier Bit 818" "0,1"
bitfld.long 0x00 17. "  GMB817 ,Group Modifier Bit 817" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1"
bitfld.long 0x00 15. "  GMB815 ,Group Modifier Bit 815" "0,1"
bitfld.long 0x00 14. "  GMB814 ,Group Modifier Bit 814" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1"
bitfld.long 0x00 12. "  GMB812 ,Group Modifier Bit 812" "0,1"
bitfld.long 0x00 11. "  GMB811 ,Group Modifier Bit 811" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1"
bitfld.long 0x00 9. "  GMB809 ,Group Modifier Bit 809" "0,1"
bitfld.long 0x00 8. "  GMB808 ,Group Modifier Bit 808" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1"
bitfld.long 0x00 6. "  GMB806 ,Group Modifier Bit 806" "0,1"
bitfld.long 0x00 5. "  GMB805 ,Group Modifier Bit 805" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1"
bitfld.long 0x00 3. "  GMB803 ,Group Modifier Bit 803" "0,1"
bitfld.long 0x00 2. "  GMB802 ,Group Modifier Bit 802" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1"
bitfld.long 0x00 0. "  GMB800 ,Group Modifier Bit 800" "0,1"
else
hgroup.long 0x0D64++0x03
hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A))
group.long 0x0D68++0x03
line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1"
bitfld.long 0x00 30. "  GMB862 ,Group Modifier Bit 862" "0,1"
bitfld.long 0x00 29. "  GMB861 ,Group Modifier Bit 861" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1"
bitfld.long 0x00 27. "  GMB859 ,Group Modifier Bit 859" "0,1"
bitfld.long 0x00 26. "  GMB858 ,Group Modifier Bit 858" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1"
bitfld.long 0x00 24. "  GMB856 ,Group Modifier Bit 856" "0,1"
bitfld.long 0x00 23. "  GMB855 ,Group Modifier Bit 855" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1"
bitfld.long 0x00 21. "  GMB853 ,Group Modifier Bit 853" "0,1"
bitfld.long 0x00 20. "  GMB852 ,Group Modifier Bit 852" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1"
bitfld.long 0x00 18. "  GMB850 ,Group Modifier Bit 850" "0,1"
bitfld.long 0x00 17. "  GMB849 ,Group Modifier Bit 849" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1"
bitfld.long 0x00 15. "  GMB847 ,Group Modifier Bit 847" "0,1"
bitfld.long 0x00 14. "  GMB846 ,Group Modifier Bit 846" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1"
bitfld.long 0x00 12. "  GMB844 ,Group Modifier Bit 844" "0,1"
bitfld.long 0x00 11. "  GMB843 ,Group Modifier Bit 843" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1"
bitfld.long 0x00 9. "  GMB841 ,Group Modifier Bit 841" "0,1"
bitfld.long 0x00 8. "  GMB840 ,Group Modifier Bit 840" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1"
bitfld.long 0x00 6. "  GMB838 ,Group Modifier Bit 838" "0,1"
bitfld.long 0x00 5. "  GMB837 ,Group Modifier Bit 837" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1"
bitfld.long 0x00 3. "  GMB835 ,Group Modifier Bit 835" "0,1"
bitfld.long 0x00 2. "  GMB834 ,Group Modifier Bit 834" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1"
bitfld.long 0x00 0. "  GMB832 ,Group Modifier Bit 832" "0,1"
else
hgroup.long 0x0D68++0x03
hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x0D6C++0x03
line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1"
bitfld.long 0x00 30. "  GMB894 ,Group Modifier Bit 894" "0,1"
bitfld.long 0x00 29. "  GMB893 ,Group Modifier Bit 893" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1"
bitfld.long 0x00 27. "  GMB891 ,Group Modifier Bit 891" "0,1"
bitfld.long 0x00 26. "  GMB890 ,Group Modifier Bit 890" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1"
bitfld.long 0x00 24. "  GMB888 ,Group Modifier Bit 888" "0,1"
bitfld.long 0x00 23. "  GMB887 ,Group Modifier Bit 887" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1"
bitfld.long 0x00 21. "  GMB885 ,Group Modifier Bit 885" "0,1"
bitfld.long 0x00 20. "  GMB884 ,Group Modifier Bit 884" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1"
bitfld.long 0x00 18. "  GMB882 ,Group Modifier Bit 882" "0,1"
bitfld.long 0x00 17. "  GMB881 ,Group Modifier Bit 881" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1"
bitfld.long 0x00 15. "  GMB879 ,Group Modifier Bit 879" "0,1"
bitfld.long 0x00 14. "  GMB878 ,Group Modifier Bit 878" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1"
bitfld.long 0x00 12. "  GMB876 ,Group Modifier Bit 876" "0,1"
bitfld.long 0x00 11. "  GMB875 ,Group Modifier Bit 875" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1"
bitfld.long 0x00 9. "  GMB873 ,Group Modifier Bit 873" "0,1"
bitfld.long 0x00 8. "  GMB872 ,Group Modifier Bit 872" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1"
bitfld.long 0x00 6. "  GMB870 ,Group Modifier Bit 870" "0,1"
bitfld.long 0x00 5. "  GMB869 ,Group Modifier Bit 869" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1"
bitfld.long 0x00 3. "  GMB867 ,Group Modifier Bit 867" "0,1"
bitfld.long 0x00 2. "  GMB866 ,Group Modifier Bit 866" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1"
bitfld.long 0x00 0. "  GMB864 ,Group Modifier Bit 864" "0,1"
else
hgroup.long 0x0D6C++0x03
hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x0D70++0x03
line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1"
bitfld.long 0x00 30. "  GMB926 ,Group Modifier Bit 926" "0,1"
bitfld.long 0x00 29. "  GMB925 ,Group Modifier Bit 925" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1"
bitfld.long 0x00 27. "  GMB923 ,Group Modifier Bit 923" "0,1"
bitfld.long 0x00 26. "  GMB922 ,Group Modifier Bit 922" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1"
bitfld.long 0x00 24. "  GMB920 ,Group Modifier Bit 920" "0,1"
bitfld.long 0x00 23. "  GMB919 ,Group Modifier Bit 919" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1"
bitfld.long 0x00 21. "  GMB917 ,Group Modifier Bit 917" "0,1"
bitfld.long 0x00 20. "  GMB916 ,Group Modifier Bit 916" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1"
bitfld.long 0x00 18. "  GMB914 ,Group Modifier Bit 914" "0,1"
bitfld.long 0x00 17. "  GMB913 ,Group Modifier Bit 913" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1"
bitfld.long 0x00 15. "  GMB911 ,Group Modifier Bit 911" "0,1"
bitfld.long 0x00 14. "  GMB910 ,Group Modifier Bit 910" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1"
bitfld.long 0x00 12. "  GMB908 ,Group Modifier Bit 908" "0,1"
bitfld.long 0x00 11. "  GMB907 ,Group Modifier Bit 907" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1"
bitfld.long 0x00 9. "  GMB905 ,Group Modifier Bit 905" "0,1"
bitfld.long 0x00 8. "  GMB904 ,Group Modifier Bit 904" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1"
bitfld.long 0x00 6. "  GMB902 ,Group Modifier Bit 902" "0,1"
bitfld.long 0x00 5. "  GMB901 ,Group Modifier Bit 901" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1"
bitfld.long 0x00 3. "  GMB899 ,Group Modifier Bit 899" "0,1"
bitfld.long 0x00 2. "  GMB898 ,Group Modifier Bit 898" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1"
bitfld.long 0x00 0. "  GMB896 ,Group Modifier Bit 896" "0,1"
else
hgroup.long 0x0D70++0x03
hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x0D74++0x03
line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1"
bitfld.long 0x00 30. "  GMB958 ,Group Modifier Bit 958" "0,1"
bitfld.long 0x00 29. "  GMB957 ,Group Modifier Bit 957" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1"
bitfld.long 0x00 27. "  GMB955 ,Group Modifier Bit 955" "0,1"
bitfld.long 0x00 26. "  GMB954 ,Group Modifier Bit 954" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1"
bitfld.long 0x00 24. "  GMB952 ,Group Modifier Bit 952" "0,1"
bitfld.long 0x00 23. "  GMB951 ,Group Modifier Bit 951" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1"
bitfld.long 0x00 21. "  GMB949 ,Group Modifier Bit 949" "0,1"
bitfld.long 0x00 20. "  GMB948 ,Group Modifier Bit 948" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1"
bitfld.long 0x00 18. "  GMB946 ,Group Modifier Bit 946" "0,1"
bitfld.long 0x00 17. "  GMB945 ,Group Modifier Bit 945" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1"
bitfld.long 0x00 15. "  GMB943 ,Group Modifier Bit 943" "0,1"
bitfld.long 0x00 14. "  GMB942 ,Group Modifier Bit 942" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1"
bitfld.long 0x00 12. "  GMB940 ,Group Modifier Bit 940" "0,1"
bitfld.long 0x00 11. "  GMB939 ,Group Modifier Bit 939" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1"
bitfld.long 0x00 9. "  GMB937 ,Group Modifier Bit 937" "0,1"
bitfld.long 0x00 8. "  GMB936 ,Group Modifier Bit 936" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1"
bitfld.long 0x00 6. "  GMB934 ,Group Modifier Bit 934" "0,1"
bitfld.long 0x00 5. "  GMB933 ,Group Modifier Bit 933" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1"
bitfld.long 0x00 3. "  GMB931 ,Group Modifier Bit 931" "0,1"
bitfld.long 0x00 2. "  GMB930 ,Group Modifier Bit 930" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1"
bitfld.long 0x00 0. "  GMB928 ,Group Modifier Bit 928" "0,1"
else
hgroup.long 0x0D74++0x03
hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x0D78++0x03
line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1"
bitfld.long 0x00 30. "  GMB990 ,Group Modifier Bit 990" "0,1"
bitfld.long 0x00 29. "  GMB989 ,Group Modifier Bit 989" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1"
bitfld.long 0x00 27. "  GMB987 ,Group Modifier Bit 987" "0,1"
bitfld.long 0x00 26. "  GMB986 ,Group Modifier Bit 986" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1"
bitfld.long 0x00 24. "  GMB984 ,Group Modifier Bit 984" "0,1"
bitfld.long 0x00 23. "  GMB983 ,Group Modifier Bit 983" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1"
bitfld.long 0x00 21. "  GMB981 ,Group Modifier Bit 981" "0,1"
bitfld.long 0x00 20. "  GMB980 ,Group Modifier Bit 980" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1"
bitfld.long 0x00 18. "  GMB978 ,Group Modifier Bit 978" "0,1"
bitfld.long 0x00 17. "  GMB977 ,Group Modifier Bit 977" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1"
bitfld.long 0x00 15. "  GMB975 ,Group Modifier Bit 975" "0,1"
bitfld.long 0x00 14. "  GMB974 ,Group Modifier Bit 974" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1"
bitfld.long 0x00 12. "  GMB972 ,Group Modifier Bit 972" "0,1"
bitfld.long 0x00 11. "  GMB971 ,Group Modifier Bit 971" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1"
bitfld.long 0x00 9. "  GMB969 ,Group Modifier Bit 969" "0,1"
bitfld.long 0x00 8. "  GMB968 ,Group Modifier Bit 968" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1"
bitfld.long 0x00 6. "  GMB966 ,Group Modifier Bit 966" "0,1"
bitfld.long 0x00 5. "  GMB965 ,Group Modifier Bit 965" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1"
bitfld.long 0x00 3. "  GMB963 ,Group Modifier Bit 963" "0,1"
bitfld.long 0x00 2. "  GMB962 ,Group Modifier Bit 962" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1"
bitfld.long 0x00 0. "  GMB960 ,Group Modifier Bit 960" "0,1"
else
hgroup.long 0x0D78++0x03
hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
endif
tree.end
width 14.
tree "Non-secure Access Control Registers"
hgroup.long 0x0E00++0x03
hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0"
hgroup.long 0xE04++0x03
hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08)))
group.long 0xE08++0x03
line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
bitfld.long 0x00 30.--31. " NS_ACCESS47  ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS46  ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS45  ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS44  ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS43  ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS42  ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS41  ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS40  ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS39  ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS38  ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS37  ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS36  ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS35  ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS34  ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS33  ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS32  ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE08++0x03
hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C)))
group.long 0xE0C++0x03
line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
bitfld.long 0x00 30.--31. " NS_ACCESS63  ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS62  ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS61  ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS60  ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS59  ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS58  ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS57  ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS56  ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS55  ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS54  ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS53  ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS52  ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS51  ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS50  ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS49  ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS48  ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE0C++0x03
hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10)))
group.long 0xE10++0x03
line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
bitfld.long 0x00 30.--31. " NS_ACCESS79  ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS78  ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS77  ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS76  ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS75  ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS74  ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS73  ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS72  ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS71  ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS70  ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS69  ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS68  ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS67  ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS66  ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS65  ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS64  ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE10++0x03
hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14)))
group.long 0xE14++0x03
line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
bitfld.long 0x00 30.--31. " NS_ACCESS95  ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS94  ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS93  ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS92  ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS91  ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS90  ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS89  ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS88  ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS87  ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS86  ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS85  ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS84  ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS83  ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS82  ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS81  ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS80  ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE14++0x03
hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18)))
group.long 0xE18++0x03
line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS99  ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS98  ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS97  ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS96  ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE18++0x03
hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C)))
group.long 0xE1C++0x03
line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE1C++0x03
hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20)))
group.long 0xE20++0x03
line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE20++0x03
hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24)))
group.long 0xE24++0x03
line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE24++0x03
hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28)))
group.long 0xE28++0x03
line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE28++0x03
hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C)))
group.long 0xE2C++0x03
line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE2C++0x03
hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30)))
group.long 0xE30++0x03
line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE30++0x03
hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34)))
group.long 0xE34++0x03
line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE34++0x03
hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38)))
group.long 0xE38++0x03
line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE38++0x03
hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C)))
group.long 0xE3C++0x03
line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE3C++0x03
hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40)))
group.long 0xE40++0x03
line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE40++0x03
hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44)))
group.long 0xE44++0x03
line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE44++0x03
hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48)))
group.long 0xE48++0x03
line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE48++0x03
hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C)))
group.long 0xE4C++0x03
line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE4C++0x03
hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50)))
group.long 0xE50++0x03
line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE50++0x03
hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54)))
group.long 0xE54++0x03
line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE54++0x03
hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58)))
group.long 0xE58++0x03
line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE58++0x03
hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C)))
group.long 0xE5C++0x03
line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE5C++0x03
hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60)))
group.long 0xE60++0x03
line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE60++0x03
hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64)))
group.long 0xE64++0x03
line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE64++0x03
hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68)))
group.long 0xE68++0x03
line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE68++0x03
hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C)))
group.long 0xE6C++0x03
line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE6C++0x03
hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70)))
group.long 0xE70++0x03
line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE70++0x03
hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74)))
group.long 0xE74++0x03
line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE74++0x03
hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78)))
group.long 0xE78++0x03
line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE78++0x03
hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C)))
group.long 0xE7C++0x03
line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE7C++0x03
hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80)))
group.long 0xE80++0x03
line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE80++0x03
hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84)))
group.long 0xE84++0x03
line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE84++0x03
hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88)))
group.long 0xE88++0x03
line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE88++0x03
hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C)))
group.long 0xE8C++0x03
line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE8C++0x03
hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90)))
group.long 0xE90++0x03
line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE90++0x03
hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94)))
group.long 0xE94++0x03
line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE94++0x03
hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98)))
group.long 0xE98++0x03
line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE98++0x03
hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C)))
group.long 0xE9C++0x03
line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE9C++0x03
hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0)))
group.long 0xEA0++0x03
line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA0++0x03
hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4)))
group.long 0xEA4++0x03
line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA4++0x03
hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8)))
group.long 0xEA8++0x03
line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA8++0x03
hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC)))
group.long 0xEAC++0x03
line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEAC++0x03
hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0)))
group.long 0xEB0++0x03
line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB0++0x03
hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4)))
group.long 0xEB4++0x03
line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB4++0x03
hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8)))
group.long 0xEB8++0x03
line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB8++0x03
hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC)))
group.long 0xEBC++0x03
line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEBC++0x03
hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0)))
group.long 0xEC0++0x03
line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC0++0x03
hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4)))
group.long 0xEC4++0x03
line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC4++0x03
hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8)))
group.long 0xEC8++0x03
line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC8++0x03
hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC)))
group.long 0xECC++0x03
line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xECC++0x03
hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0)))
group.long 0xED0++0x03
line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED0++0x03
hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4)))
group.long 0xED4++0x03
line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED4++0x03
hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8)))
group.long 0xED8++0x03
line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED8++0x03
hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC)))
group.long 0xEDC++0x03
line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEDC++0x03
hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0)))
group.long 0xEE0++0x03
line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE0++0x03
hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4)))
group.long 0xEE4++0x03
line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE4++0x03
hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8)))
group.long 0xEE8++0x03
line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE8++0x03
hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC)))
group.long 0xEEC++0x03
line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEEC++0x03
hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0)))
group.long 0xEF0++0x03
line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF0++0x03
hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4)))
group.long 0xEF4++0x03
line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF4++0x03
hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
endif
tree.end
width 25.
tree "Software Generated Interrupt"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0F00++0x03
hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
hgroup.long 0xF10++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
hgroup.long 0xF14++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
hgroup.long 0xF18++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
hgroup.long 0xF1C++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
hgroup.long 0xF20++0x03
hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
hgroup.long 0xF24++0x03
hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
hgroup.long 0xF28++0x03
hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
hgroup.long 0xF2C++0x03
hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
else
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
group.long 0xF10++0x03
line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
group.long 0xF14++0x03
line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
group.long 0xF18++0x03
line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
group.long 0xF1C++0x03
line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
group.long 0xF20++0x03
line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
group.long 0xF24++0x03
line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
group.long 0xF28++0x03
line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
group.long 0xF2C++0x03
line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
endif
tree.end
width 24.
tree "Interrupt Routing Registers"
group.quad 0x6100++0x07
line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6108++0x07
line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6110++0x07
line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6118++0x07
line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6120++0x07
line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6128++0x07
line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6130++0x07
line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6138++0x07
line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6140++0x07
line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6148++0x07
line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6150++0x07
line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6158++0x07
line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6160++0x07
line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6168++0x07
line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6170++0x07
line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6178++0x07
line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6180++0x07
line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6188++0x07
line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6190++0x07
line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6198++0x07
line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A0++0x07
line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A8++0x07
line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B0++0x07
line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B8++0x07
line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C0++0x07
line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C8++0x07
line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D0++0x07
line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D8++0x07
line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E0++0x07
line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E8++0x07
line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F0++0x07
line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F8++0x07
line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6200++0x07
line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6208++0x07
line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6210++0x07
line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6218++0x07
line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6220++0x07
line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6228++0x07
line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6230++0x07
line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6238++0x07
line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6240++0x07
line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6248++0x07
line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6250++0x07
line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6258++0x07
line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6260++0x07
line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6268++0x07
line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6270++0x07
line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6278++0x07
line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6280++0x07
line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6288++0x07
line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6290++0x07
line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6298++0x07
line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A0++0x07
line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A8++0x07
line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B0++0x07
line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B8++0x07
line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C0++0x07
line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C8++0x07
line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D0++0x07
line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D8++0x07
line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E0++0x07
line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E8++0x07
line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F0++0x07
line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F8++0x07
line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6300++0x07
line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6308++0x07
line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6310++0x07
line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6318++0x07
line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6320++0x07
line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6328++0x07
line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6330++0x07
line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6338++0x07
line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6340++0x07
line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6348++0x07
line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6350++0x07
line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6358++0x07
line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6360++0x07
line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6368++0x07
line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6370++0x07
line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6378++0x07
line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6380++0x07
line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6388++0x07
line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6390++0x07
line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6398++0x07
line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A0++0x07
line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A8++0x07
line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B0++0x07
line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B8++0x07
line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C0++0x07
line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C8++0x07
line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D0++0x07
line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D8++0x07
line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E0++0x07
line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E8++0x07
line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F0++0x07
line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F8++0x07
line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6400++0x07
line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6408++0x07
line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6410++0x07
line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6418++0x07
line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6420++0x07
line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6428++0x07
line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6430++0x07
line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6438++0x07
line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6440++0x07
line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6448++0x07
line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6450++0x07
line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6458++0x07
line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6460++0x07
line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6468++0x07
line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6470++0x07
line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6478++0x07
line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6480++0x07
line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6488++0x07
line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6490++0x07
line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6498++0x07
line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A0++0x07
line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A8++0x07
line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B0++0x07
line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B8++0x07
line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C0++0x07
line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C8++0x07
line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D0++0x07
line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D8++0x07
line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E0++0x07
line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E8++0x07
line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F0++0x07
line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F8++0x07
line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6500++0x07
line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6508++0x07
line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6510++0x07
line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6518++0x07
line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6520++0x07
line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6528++0x07
line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6530++0x07
line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6538++0x07
line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6540++0x07
line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6548++0x07
line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6550++0x07
line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6558++0x07
line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6560++0x07
line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6568++0x07
line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6570++0x07
line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6578++0x07
line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6580++0x07
line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6588++0x07
line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6590++0x07
line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6598++0x07
line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A0++0x07
line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A8++0x07
line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B0++0x07
line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B8++0x07
line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C0++0x07
line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C8++0x07
line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D0++0x07
line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D8++0x07
line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E0++0x07
line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E8++0x07
line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F0++0x07
line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F8++0x07
line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6600++0x07
line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6608++0x07
line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6610++0x07
line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6618++0x07
line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6620++0x07
line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6628++0x07
line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6630++0x07
line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6638++0x07
line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6640++0x07
line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6648++0x07
line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6650++0x07
line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6658++0x07
line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6660++0x07
line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6668++0x07
line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6670++0x07
line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6678++0x07
line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6680++0x07
line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6688++0x07
line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6690++0x07
line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6698++0x07
line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A0++0x07
line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A8++0x07
line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B0++0x07
line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B8++0x07
line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C0++0x07
line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C8++0x07
line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D0++0x07
line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D8++0x07
line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E0++0x07
line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E8++0x07
line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F0++0x07
line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F8++0x07
line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6700++0x07
line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6708++0x07
line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6710++0x07
line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6718++0x07
line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6720++0x07
line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6728++0x07
line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6730++0x07
line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6738++0x07
line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6740++0x07
line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6748++0x07
line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6750++0x07
line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6758++0x07
line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6760++0x07
line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6768++0x07
line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6770++0x07
line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6778++0x07
line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6780++0x07
line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6788++0x07
line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6790++0x07
line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6798++0x07
line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A0++0x07
line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A8++0x07
line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B0++0x07
line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B8++0x07
line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C0++0x07
line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C8++0x07
line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D0++0x07
line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D8++0x07
line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E0++0x07
line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E8++0x07
line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F0++0x07
line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F8++0x07
line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6800++0x07
line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6808++0x07
line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6810++0x07
line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6818++0x07
line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6820++0x07
line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6828++0x07
line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6830++0x07
line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6838++0x07
line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6840++0x07
line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6848++0x07
line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6850++0x07
line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6858++0x07
line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6860++0x07
line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6868++0x07
line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6870++0x07
line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6878++0x07
line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6880++0x07
line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6888++0x07
line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6890++0x07
line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6898++0x07
line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A0++0x07
line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A8++0x07
line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B0++0x07
line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B8++0x07
line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C0++0x07
line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C8++0x07
line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D0++0x07
line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D8++0x07
line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E0++0x07
line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E8++0x07
line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F0++0x07
line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F8++0x07
line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6900++0x07
line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6908++0x07
line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6910++0x07
line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6918++0x07
line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6920++0x07
line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6928++0x07
line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6930++0x07
line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6938++0x07
line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6940++0x07
line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6948++0x07
line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6950++0x07
line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6958++0x07
line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6960++0x07
line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6968++0x07
line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6970++0x07
line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6978++0x07
line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6980++0x07
line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6988++0x07
line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6990++0x07
line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6998++0x07
line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A0++0x07
line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A8++0x07
line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B0++0x07
line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B8++0x07
line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C0++0x07
line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C8++0x07
line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D0++0x07
line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D8++0x07
line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E0++0x07
line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E8++0x07
line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F0++0x07
line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F8++0x07
line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A00++0x07
line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A08++0x07
line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A10++0x07
line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A18++0x07
line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A20++0x07
line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A28++0x07
line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A30++0x07
line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A38++0x07
line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A40++0x07
line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A48++0x07
line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A50++0x07
line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A58++0x07
line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A60++0x07
line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A68++0x07
line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A70++0x07
line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A78++0x07
line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A80++0x07
line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A88++0x07
line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A90++0x07
line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A98++0x07
line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA0++0x07
line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA8++0x07
line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB0++0x07
line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB8++0x07
line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC0++0x07
line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC8++0x07
line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD0++0x07
line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD8++0x07
line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE0++0x07
line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE8++0x07
line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF0++0x07
line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF8++0x07
line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B00++0x07
line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B08++0x07
line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B10++0x07
line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B18++0x07
line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B20++0x07
line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B28++0x07
line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B30++0x07
line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B38++0x07
line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B40++0x07
line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B48++0x07
line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B50++0x07
line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B58++0x07
line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B60++0x07
line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B68++0x07
line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B70++0x07
line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B78++0x07
line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B80++0x07
line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B88++0x07
line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B90++0x07
line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B98++0x07
line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA0++0x07
line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA8++0x07
line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB0++0x07
line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB8++0x07
line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC0++0x07
line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC8++0x07
line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD0++0x07
line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD8++0x07
line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE0++0x07
line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE8++0x07
line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF0++0x07
line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF8++0x07
line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C00++0x07
line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C08++0x07
line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C10++0x07
line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C18++0x07
line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C20++0x07
line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C28++0x07
line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C30++0x07
line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C38++0x07
line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C40++0x07
line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C48++0x07
line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C50++0x07
line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C58++0x07
line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C60++0x07
line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C68++0x07
line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C70++0x07
line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C78++0x07
line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C80++0x07
line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C88++0x07
line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C90++0x07
line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C98++0x07
line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA0++0x07
line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA8++0x07
line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB0++0x07
line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB8++0x07
line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC0++0x07
line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC8++0x07
line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD0++0x07
line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD8++0x07
line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE0++0x07
line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE8++0x07
line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF0++0x07
line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF8++0x07
line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D00++0x07
line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D08++0x07
line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D10++0x07
line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D18++0x07
line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D20++0x07
line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D28++0x07
line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D30++0x07
line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D38++0x07
line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D40++0x07
line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D48++0x07
line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D50++0x07
line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D58++0x07
line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D60++0x07
line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D68++0x07
line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D70++0x07
line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D78++0x07
line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D80++0x07
line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D88++0x07
line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D90++0x07
line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D98++0x07
line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA0++0x07
line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA8++0x07
line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB0++0x07
line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB8++0x07
line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC0++0x07
line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC8++0x07
line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD0++0x07
line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD8++0x07
line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE0++0x07
line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE8++0x07
line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF0++0x07
line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF8++0x07
line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E00++0x07
line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E08++0x07
line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E10++0x07
line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E18++0x07
line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E20++0x07
line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E28++0x07
line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E30++0x07
line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E38++0x07
line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E40++0x07
line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E48++0x07
line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E50++0x07
line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E58++0x07
line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E60++0x07
line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E68++0x07
line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E70++0x07
line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E78++0x07
line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E80++0x07
line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E88++0x07
line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E90++0x07
line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E98++0x07
line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA0++0x07
line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA8++0x07
line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB0++0x07
line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB8++0x07
line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC0++0x07
line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC8++0x07
line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED0++0x07
line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED8++0x07
line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE0++0x07
line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE8++0x07
line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF0++0x07
line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF8++0x07
line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F00++0x07
line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F08++0x07
line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F10++0x07
line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F18++0x07
line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F20++0x07
line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F28++0x07
line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F30++0x07
line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F38++0x07
line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F40++0x07
line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F48++0x07
line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F50++0x07
line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F58++0x07
line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F60++0x07
line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F68++0x07
line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F70++0x07
line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F78++0x07
line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F80++0x07
line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F88++0x07
line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F90++0x07
line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F98++0x07
line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA0++0x07
line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA8++0x07
line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB0++0x07
line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB8++0x07
line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC0++0x07
line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC8++0x07
line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD0++0x07
line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD8++0x07
line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE0++0x07
line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE8++0x07
line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF0++0x07
line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF8++0x07
line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7000++0x07
line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7008++0x07
line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7010++0x07
line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7018++0x07
line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7020++0x07
line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7028++0x07
line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7030++0x07
line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7038++0x07
line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7040++0x07
line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7048++0x07
line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7050++0x07
line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7058++0x07
line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7060++0x07
line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7068++0x07
line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7070++0x07
line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7078++0x07
line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7080++0x07
line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7088++0x07
line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7090++0x07
line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7098++0x07
line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A0++0x07
line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A8++0x07
line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B0++0x07
line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B8++0x07
line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C0++0x07
line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C8++0x07
line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D0++0x07
line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D8++0x07
line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E0++0x07
line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E8++0x07
line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F0++0x07
line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F8++0x07
line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7100++0x07
line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7108++0x07
line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7110++0x07
line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7118++0x07
line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7120++0x07
line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7128++0x07
line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7130++0x07
line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7138++0x07
line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7140++0x07
line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7148++0x07
line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7150++0x07
line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7158++0x07
line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7160++0x07
line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7168++0x07
line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7170++0x07
line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7178++0x07
line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7180++0x07
line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7188++0x07
line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7190++0x07
line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7198++0x07
line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A0++0x07
line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A8++0x07
line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B0++0x07
line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B8++0x07
line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C0++0x07
line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C8++0x07
line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D0++0x07
line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D8++0x07
line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E0++0x07
line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E8++0x07
line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F0++0x07
line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F8++0x07
line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7200++0x07
line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7208++0x07
line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7210++0x07
line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7218++0x07
line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7220++0x07
line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7228++0x07
line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7230++0x07
line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7238++0x07
line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7240++0x07
line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7248++0x07
line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7250++0x07
line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7258++0x07
line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7260++0x07
line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7268++0x07
line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7270++0x07
line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7278++0x07
line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7280++0x07
line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7288++0x07
line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7290++0x07
line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7298++0x07
line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A0++0x07
line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A8++0x07
line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B0++0x07
line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B8++0x07
line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C0++0x07
line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C8++0x07
line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D0++0x07
line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D8++0x07
line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E0++0x07
line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E8++0x07
line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F0++0x07
line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F8++0x07
line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7300++0x07
line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7308++0x07
line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7310++0x07
line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7318++0x07
line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7320++0x07
line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7328++0x07
line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7330++0x07
line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7338++0x07
line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7340++0x07
line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7348++0x07
line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7350++0x07
line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7358++0x07
line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7360++0x07
line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7368++0x07
line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7370++0x07
line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7378++0x07
line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7380++0x07
line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7388++0x07
line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7390++0x07
line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7398++0x07
line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A0++0x07
line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A8++0x07
line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B0++0x07
line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B8++0x07
line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C0++0x07
line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C8++0x07
line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D0++0x07
line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D8++0x07
line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E0++0x07
line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E8++0x07
line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F0++0x07
line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F8++0x07
line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7400++0x07
line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7408++0x07
line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7410++0x07
line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7418++0x07
line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7420++0x07
line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7428++0x07
line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7430++0x07
line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7438++0x07
line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7440++0x07
line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7448++0x07
line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7450++0x07
line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7458++0x07
line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7460++0x07
line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7468++0x07
line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7470++0x07
line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7478++0x07
line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7480++0x07
line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7488++0x07
line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7490++0x07
line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7498++0x07
line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A0++0x07
line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A8++0x07
line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B0++0x07
line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B8++0x07
line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C0++0x07
line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C8++0x07
line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D0++0x07
line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D8++0x07
line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E0++0x07
line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E8++0x07
line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F0++0x07
line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F8++0x07
line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7500++0x07
line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7508++0x07
line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7510++0x07
line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7518++0x07
line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7520++0x07
line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7528++0x07
line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7530++0x07
line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7538++0x07
line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7540++0x07
line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7548++0x07
line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7550++0x07
line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7558++0x07
line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7560++0x07
line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7568++0x07
line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7570++0x07
line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7578++0x07
line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7580++0x07
line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7588++0x07
line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7590++0x07
line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7598++0x07
line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A0++0x07
line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A8++0x07
line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B0++0x07
line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B8++0x07
line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C0++0x07
line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C8++0x07
line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D0++0x07
line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D8++0x07
line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E0++0x07
line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E8++0x07
line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F0++0x07
line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F8++0x07
line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7600++0x07
line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7608++0x07
line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7610++0x07
line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7618++0x07
line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7620++0x07
line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7628++0x07
line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7630++0x07
line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7638++0x07
line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7640++0x07
line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7648++0x07
line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7650++0x07
line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7658++0x07
line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7660++0x07
line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7668++0x07
line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7670++0x07
line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7678++0x07
line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7680++0x07
line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7688++0x07
line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7690++0x07
line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7698++0x07
line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A0++0x07
line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A8++0x07
line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B0++0x07
line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B8++0x07
line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C0++0x07
line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C8++0x07
line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D0++0x07
line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D8++0x07
line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E0++0x07
line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E8++0x07
line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F0++0x07
line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F8++0x07
line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7700++0x07
line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7708++0x07
line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7710++0x07
line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7718++0x07
line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7720++0x07
line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7728++0x07
line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7730++0x07
line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7738++0x07
line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7740++0x07
line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7748++0x07
line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7750++0x07
line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7758++0x07
line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7760++0x07
line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7768++0x07
line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7770++0x07
line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7778++0x07
line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7780++0x07
line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7788++0x07
line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7790++0x07
line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7798++0x07
line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A0++0x07
line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A8++0x07
line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B0++0x07
line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B8++0x07
line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C0++0x07
line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C8++0x07
line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D0++0x07
line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D8++0x07
line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E0++0x07
line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E8++0x07
line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F0++0x07
line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F8++0x07
line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7800++0x07
line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7808++0x07
line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7810++0x07
line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7818++0x07
line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7820++0x07
line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7828++0x07
line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7830++0x07
line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7838++0x07
line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7840++0x07
line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7848++0x07
line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7850++0x07
line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7858++0x07
line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7860++0x07
line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7868++0x07
line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7870++0x07
line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7878++0x07
line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7880++0x07
line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7888++0x07
line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7890++0x07
line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7898++0x07
line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A0++0x07
line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A8++0x07
line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B0++0x07
line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B8++0x07
line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C0++0x07
line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C8++0x07
line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D0++0x07
line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D8++0x07
line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E0++0x07
line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E8++0x07
line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F0++0x07
line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F8++0x07
line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7900++0x07
line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7908++0x07
line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7910++0x07
line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7918++0x07
line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7920++0x07
line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7928++0x07
line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7930++0x07
line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7938++0x07
line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7940++0x07
line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7948++0x07
line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7950++0x07
line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7958++0x07
line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7960++0x07
line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7968++0x07
line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7970++0x07
line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7978++0x07
line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7980++0x07
line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7988++0x07
line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7990++0x07
line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7998++0x07
line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A0++0x07
line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A8++0x07
line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B0++0x07
line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B8++0x07
line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C0++0x07
line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C8++0x07
line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D0++0x07
line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D8++0x07
line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E0++0x07
line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E8++0x07
line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F0++0x07
line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F8++0x07
line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A00++0x07
line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A08++0x07
line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A10++0x07
line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A18++0x07
line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A20++0x07
line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A28++0x07
line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A30++0x07
line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A38++0x07
line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A40++0x07
line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A48++0x07
line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A50++0x07
line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A58++0x07
line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A60++0x07
line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A68++0x07
line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A70++0x07
line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A78++0x07
line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A80++0x07
line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A88++0x07
line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A90++0x07
line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A98++0x07
line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA0++0x07
line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA8++0x07
line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB0++0x07
line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB8++0x07
line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC0++0x07
line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC8++0x07
line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD0++0x07
line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD8++0x07
line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE0++0x07
line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE8++0x07
line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF0++0x07
line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF8++0x07
line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B00++0x07
line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B08++0x07
line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B10++0x07
line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B18++0x07
line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B20++0x07
line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B28++0x07
line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B30++0x07
line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B38++0x07
line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B40++0x07
line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B48++0x07
line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B50++0x07
line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B58++0x07
line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B60++0x07
line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B68++0x07
line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B70++0x07
line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B78++0x07
line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B80++0x07
line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B88++0x07
line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B90++0x07
line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B98++0x07
line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA0++0x07
line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA8++0x07
line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB0++0x07
line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB8++0x07
line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC0++0x07
line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC8++0x07
line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD0++0x07
line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD8++0x07
line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE0++0x07
line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE8++0x07
line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF0++0x07
line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF8++0x07
line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C00++0x07
line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C08++0x07
line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C10++0x07
line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C18++0x07
line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C20++0x07
line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C28++0x07
line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C30++0x07
line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C38++0x07
line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C40++0x07
line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C48++0x07
line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C50++0x07
line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C58++0x07
line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C60++0x07
line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C68++0x07
line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C70++0x07
line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C78++0x07
line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C80++0x07
line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C88++0x07
line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C90++0x07
line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C98++0x07
line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA0++0x07
line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA8++0x07
line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB0++0x07
line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB8++0x07
line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC0++0x07
line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC8++0x07
line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD0++0x07
line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD8++0x07
line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE0++0x07
line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE8++0x07
line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF0++0x07
line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF8++0x07
line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D00++0x07
line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D08++0x07
line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D10++0x07
line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D18++0x07
line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D20++0x07
line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D28++0x07
line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D30++0x07
line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D38++0x07
line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D40++0x07
line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D48++0x07
line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D50++0x07
line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D58++0x07
line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D60++0x07
line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D68++0x07
line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D70++0x07
line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D78++0x07
line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D80++0x07
line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D88++0x07
line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D90++0x07
line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D98++0x07
line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA0++0x07
line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA8++0x07
line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB0++0x07
line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB8++0x07
line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC0++0x07
line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC8++0x07
line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD0++0x07
line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD8++0x07
line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE0++0x07
line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE8++0x07
line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF0++0x07
line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF8++0x07
line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E00++0x07
line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E08++0x07
line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E10++0x07
line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E18++0x07
line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E20++0x07
line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E28++0x07
line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E30++0x07
line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E38++0x07
line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E40++0x07
line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E48++0x07
line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E50++0x07
line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E58++0x07
line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E60++0x07
line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E68++0x07
line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E70++0x07
line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E78++0x07
line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E80++0x07
line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E88++0x07
line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E90++0x07
line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E98++0x07
line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA0++0x07
line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA8++0x07
line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB0++0x07
line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB8++0x07
line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC0++0x07
line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC8++0x07
line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED0++0x07
line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED8++0x07
line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE0++0x07
line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE8++0x07
line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF0++0x07
line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF8++0x07
line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
tree.end
width 22.
tree "Implementation Defined Test Registers"
rgroup.long 0xC000++0x03
line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR"
bitfld.long 0x00 31. " SRWP     ,Super Register Write Pending" "Not pending,Pending"
wgroup.long 0xC004++0x03
line.long 0x00 "GICD_ERRTESTR,Error Test Register"
bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High"
bitfld.long 0x00 0. "         ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High"
textline "                               "
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
rgroup.long 0xC084++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
bitfld.long 0x00 31. " SPIS63  ,SPI Status Bit 63" "Low,High"
bitfld.long 0x00 30. "  SPIS62  ,SPI Status Bit 62" "Low,High"
bitfld.long 0x00 29. "  SPIS61  ,SPI Status Bit 61" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS60  ,SPI Status Bit 60" "Low,High"
bitfld.long 0x00 27. "  SPIS59  ,SPI Status Bit 59" "Low,High"
bitfld.long 0x00 26. "  SPIS58  ,SPI Status Bit 58" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS57  ,SPI Status Bit 57" "Low,High"
bitfld.long 0x00 24. "  SPIS56  ,SPI Status Bit 56" "Low,High"
bitfld.long 0x00 23. "  SPIS55  ,SPI Status Bit 55" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS54  ,SPI Status Bit 54" "Low,High"
bitfld.long 0x00 21. "  SPIS53  ,SPI Status Bit 53" "Low,High"
bitfld.long 0x00 20. "  SPIS52  ,SPI Status Bit 52" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS51  ,SPI Status Bit 51" "Low,High"
bitfld.long 0x00 18. "  SPIS50  ,SPI Status Bit 50" "Low,High"
bitfld.long 0x00 17. "  SPIS49  ,SPI Status Bit 49" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS48  ,SPI Status Bit 48" "Low,High"
bitfld.long 0x00 15. "  SPIS47  ,SPI Status Bit 47" "Low,High"
bitfld.long 0x00 14. "  SPIS46  ,SPI Status Bit 46" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS45  ,SPI Status Bit 45" "Low,High"
bitfld.long 0x00 12. "  SPIS44  ,SPI Status Bit 44" "Low,High"
bitfld.long 0x00 11. "  SPIS43  ,SPI Status Bit 43" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS42  ,SPI Status Bit 42" "Low,High"
bitfld.long 0x00 9. "  SPIS41  ,SPI Status Bit 41" "Low,High"
bitfld.long 0x00 8. "  SPIS40  ,SPI Status Bit 40" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS39  ,SPI Status Bit 39" "Low,High"
bitfld.long 0x00 6. "  SPIS38  ,SPI Status Bit 38" "Low,High"
bitfld.long 0x00 5. "  SPIS37  ,SPI Status Bit 37" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS36  ,SPI Status Bit 36" "Low,High"
bitfld.long 0x00 3. "  SPIS35  ,SPI Status Bit 35" "Low,High"
bitfld.long 0x00 2. "  SPIS34  ,SPI Status Bit 34" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS33  ,SPI Status Bit 33" "Low,High"
bitfld.long 0x00 0. "  SPIS32  ,SPI Status Bit 32" "Low,High"
else
hgroup.long 0xC084++0x03
hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
rgroup.long 0xC088++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
bitfld.long 0x00 31. " SPIS95  ,SPI Status Bit 95" "Low,High"
bitfld.long 0x00 30. "  SPIS94  ,SPI Status Bit 94" "Low,High"
bitfld.long 0x00 29. "  SPIS93  ,SPI Status Bit 93" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS92  ,SPI Status Bit 92" "Low,High"
bitfld.long 0x00 27. "  SPIS91  ,SPI Status Bit 91" "Low,High"
bitfld.long 0x00 26. "  SPIS90  ,SPI Status Bit 90" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS89  ,SPI Status Bit 89" "Low,High"
bitfld.long 0x00 24. "  SPIS88  ,SPI Status Bit 88" "Low,High"
bitfld.long 0x00 23. "  SPIS87  ,SPI Status Bit 87" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS86  ,SPI Status Bit 86" "Low,High"
bitfld.long 0x00 21. "  SPIS85  ,SPI Status Bit 85" "Low,High"
bitfld.long 0x00 20. "  SPIS84  ,SPI Status Bit 84" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS83  ,SPI Status Bit 83" "Low,High"
bitfld.long 0x00 18. "  SPIS82  ,SPI Status Bit 82" "Low,High"
bitfld.long 0x00 17. "  SPIS81  ,SPI Status Bit 81" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS80  ,SPI Status Bit 80" "Low,High"
bitfld.long 0x00 15. "  SPIS79  ,SPI Status Bit 79" "Low,High"
bitfld.long 0x00 14. "  SPIS78  ,SPI Status Bit 78" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS77  ,SPI Status Bit 77" "Low,High"
bitfld.long 0x00 12. "  SPIS76  ,SPI Status Bit 76" "Low,High"
bitfld.long 0x00 11. "  SPIS75  ,SPI Status Bit 75" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS74  ,SPI Status Bit 74" "Low,High"
bitfld.long 0x00 9. "  SPIS73  ,SPI Status Bit 73" "Low,High"
bitfld.long 0x00 8. "  SPIS72  ,SPI Status Bit 72" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS71  ,SPI Status Bit 71" "Low,High"
bitfld.long 0x00 6. "  SPIS70  ,SPI Status Bit 70" "Low,High"
bitfld.long 0x00 5. "  SPIS69  ,SPI Status Bit 69" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS68  ,SPI Status Bit 68" "Low,High"
bitfld.long 0x00 3. "  SPIS67  ,SPI Status Bit 67" "Low,High"
bitfld.long 0x00 2. "  SPIS66  ,SPI Status Bit 66" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS65  ,SPI Status Bit 65" "Low,High"
bitfld.long 0x00 0. "  SPIS64  ,SPI Status Bit 64" "Low,High"
else
hgroup.long 0xC088++0x03
hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
rgroup.long 0xC08C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High"
bitfld.long 0x00 30. "  SPIS126 ,SPI Status Bit 126" "Low,High"
bitfld.long 0x00 29. "  SPIS125 ,SPI Status Bit 125" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High"
bitfld.long 0x00 27. "  SPIS123 ,SPI Status Bit 123" "Low,High"
bitfld.long 0x00 26. "  SPIS122 ,SPI Status Bit 122" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High"
bitfld.long 0x00 24. "  SPIS120 ,SPI Status Bit 120" "Low,High"
bitfld.long 0x00 23. "  SPIS119 ,SPI Status Bit 119" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High"
bitfld.long 0x00 21. "  SPIS117 ,SPI Status Bit 117" "Low,High"
bitfld.long 0x00 20. "  SPIS116 ,SPI Status Bit 116" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High"
bitfld.long 0x00 18. "  SPIS114 ,SPI Status Bit 114" "Low,High"
bitfld.long 0x00 17. "  SPIS113 ,SPI Status Bit 113" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High"
bitfld.long 0x00 15. "  SPIS111 ,SPI Status Bit 111" "Low,High"
bitfld.long 0x00 14. "  SPIS110 ,SPI Status Bit 110" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High"
bitfld.long 0x00 12. "  SPIS108 ,SPI Status Bit 108" "Low,High"
bitfld.long 0x00 11. "  SPIS107 ,SPI Status Bit 107" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High"
bitfld.long 0x00 9. "  SPIS105 ,SPI Status Bit 105" "Low,High"
bitfld.long 0x00 8. "  SPIS104 ,SPI Status Bit 104" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High"
bitfld.long 0x00 6. "  SPIS102 ,SPI Status Bit 102" "Low,High"
bitfld.long 0x00 5. "  SPIS101 ,SPI Status Bit 101" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High"
bitfld.long 0x00 3. "  SPIS99  ,SPI Status Bit 99" "Low,High"
bitfld.long 0x00 2. "  SPIS98  ,SPI Status Bit 98" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS97  ,SPI Status Bit 97" "Low,High"
bitfld.long 0x00 0. "  SPIS96  ,SPI Status Bit 96" "Low,High"
else
hgroup.long 0xC08C++0x03
hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
rgroup.long 0xC090++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High"
bitfld.long 0x00 30. "  SPIS158 ,SPI Status Bit 158" "Low,High"
bitfld.long 0x00 29. "  SPIS157 ,SPI Status Bit 157" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High"
bitfld.long 0x00 27. "  SPIS155 ,SPI Status Bit 155" "Low,High"
bitfld.long 0x00 26. "  SPIS154 ,SPI Status Bit 154" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High"
bitfld.long 0x00 24. "  SPIS152 ,SPI Status Bit 152" "Low,High"
bitfld.long 0x00 23. "  SPIS151 ,SPI Status Bit 151" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High"
bitfld.long 0x00 21. "  SPIS149 ,SPI Status Bit 149" "Low,High"
bitfld.long 0x00 20. "  SPIS148 ,SPI Status Bit 148" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High"
bitfld.long 0x00 18. "  SPIS146 ,SPI Status Bit 146" "Low,High"
bitfld.long 0x00 17. "  SPIS145 ,SPI Status Bit 145" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High"
bitfld.long 0x00 15. "  SPIS143 ,SPI Status Bit 143" "Low,High"
bitfld.long 0x00 14. "  SPIS142 ,SPI Status Bit 142" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High"
bitfld.long 0x00 12. "  SPIS140 ,SPI Status Bit 140" "Low,High"
bitfld.long 0x00 11. "  SPIS139 ,SPI Status Bit 139" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High"
bitfld.long 0x00 9. "  SPIS137 ,SPI Status Bit 137" "Low,High"
bitfld.long 0x00 8. "  SPIS136 ,SPI Status Bit 136" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High"
bitfld.long 0x00 6. "  SPIS134 ,SPI Status Bit 134" "Low,High"
bitfld.long 0x00 5. "  SPIS133 ,SPI Status Bit 133" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High"
bitfld.long 0x00 3. "  SPIS131 ,SPI Status Bit 131" "Low,High"
bitfld.long 0x00 2. "  SPIS130 ,SPI Status Bit 130" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High"
bitfld.long 0x00 0. "  SPIS128 ,SPI Status Bit 128" "Low,High"
else
hgroup.long 0xC090++0x03
hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
rgroup.long 0xC094++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High"
bitfld.long 0x00 30. "  SPIS190 ,SPI Status Bit 190" "Low,High"
bitfld.long 0x00 29. "  SPIS189 ,SPI Status Bit 189" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High"
bitfld.long 0x00 27. "  SPIS187 ,SPI Status Bit 187" "Low,High"
bitfld.long 0x00 26. "  SPIS186 ,SPI Status Bit 186" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High"
bitfld.long 0x00 24. "  SPIS184 ,SPI Status Bit 184" "Low,High"
bitfld.long 0x00 23. "  SPIS183 ,SPI Status Bit 183" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High"
bitfld.long 0x00 21. "  SPIS181 ,SPI Status Bit 181" "Low,High"
bitfld.long 0x00 20. "  SPIS180 ,SPI Status Bit 180" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High"
bitfld.long 0x00 18. "  SPIS178 ,SPI Status Bit 178" "Low,High"
bitfld.long 0x00 17. "  SPIS177 ,SPI Status Bit 177" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High"
bitfld.long 0x00 15. "  SPIS175 ,SPI Status Bit 175" "Low,High"
bitfld.long 0x00 14. "  SPIS174 ,SPI Status Bit 174" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High"
bitfld.long 0x00 12. "  SPIS172 ,SPI Status Bit 172" "Low,High"
bitfld.long 0x00 11. "  SPIS171 ,SPI Status Bit 171" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High"
bitfld.long 0x00 9. "  SPIS169 ,SPI Status Bit 169" "Low,High"
bitfld.long 0x00 8. "  SPIS168 ,SPI Status Bit 168" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High"
bitfld.long 0x00 6. "  SPIS166 ,SPI Status Bit 166" "Low,High"
bitfld.long 0x00 5. "  SPIS165 ,SPI Status Bit 165" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High"
bitfld.long 0x00 3. "  SPIS163 ,SPI Status Bit 163" "Low,High"
bitfld.long 0x00 2. "  SPIS162 ,SPI Status Bit 162" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High"
bitfld.long 0x00 0. "  SPIS160 ,SPI Status Bit 160" "Low,High"
else
hgroup.long 0xC094++0x03
hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
rgroup.long 0xC098++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High"
bitfld.long 0x00 30. "  SPIS222 ,SPI Status Bit 222" "Low,High"
bitfld.long 0x00 29. "  SPIS221 ,SPI Status Bit 221" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High"
bitfld.long 0x00 27. "  SPIS219 ,SPI Status Bit 219" "Low,High"
bitfld.long 0x00 26. "  SPIS218 ,SPI Status Bit 218" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High"
bitfld.long 0x00 24. "  SPIS216 ,SPI Status Bit 216" "Low,High"
bitfld.long 0x00 23. "  SPIS215 ,SPI Status Bit 215" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High"
bitfld.long 0x00 21. "  SPIS213 ,SPI Status Bit 213" "Low,High"
bitfld.long 0x00 20. "  SPIS212 ,SPI Status Bit 212" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High"
bitfld.long 0x00 18. "  SPIS210 ,SPI Status Bit 210" "Low,High"
bitfld.long 0x00 17. "  SPIS209 ,SPI Status Bit 209" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High"
bitfld.long 0x00 15. "  SPIS207 ,SPI Status Bit 207" "Low,High"
bitfld.long 0x00 14. "  SPIS206 ,SPI Status Bit 206" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High"
bitfld.long 0x00 12. "  SPIS204 ,SPI Status Bit 204" "Low,High"
bitfld.long 0x00 11. "  SPIS203 ,SPI Status Bit 203" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High"
bitfld.long 0x00 9. "  SPIS201 ,SPI Status Bit 201" "Low,High"
bitfld.long 0x00 8. "  SPIS200 ,SPI Status Bit 200" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High"
bitfld.long 0x00 6. "  SPIS198 ,SPI Status Bit 198" "Low,High"
bitfld.long 0x00 5. "  SPIS197 ,SPI Status Bit 197" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High"
bitfld.long 0x00 3. "  SPIS195 ,SPI Status Bit 195" "Low,High"
bitfld.long 0x00 2. "  SPIS194 ,SPI Status Bit 194" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High"
bitfld.long 0x00 0. "  SPIS192 ,SPI Status Bit 192" "Low,High"
else
hgroup.long 0xC098++0x03
hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
rgroup.long 0xC09C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High"
bitfld.long 0x00 30. "  SPIS254 ,SPI Status Bit 254" "Low,High"
bitfld.long 0x00 29. "  SPIS253 ,SPI Status Bit 253" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High"
bitfld.long 0x00 27. "  SPIS251 ,SPI Status Bit 251" "Low,High"
bitfld.long 0x00 26. "  SPIS250 ,SPI Status Bit 250" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High"
bitfld.long 0x00 24. "  SPIS248 ,SPI Status Bit 248" "Low,High"
bitfld.long 0x00 23. "  SPIS247 ,SPI Status Bit 247" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High"
bitfld.long 0x00 21. "  SPIS245 ,SPI Status Bit 245" "Low,High"
bitfld.long 0x00 20. "  SPIS244 ,SPI Status Bit 244" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High"
bitfld.long 0x00 18. "  SPIS242 ,SPI Status Bit 242" "Low,High"
bitfld.long 0x00 17. "  SPIS241 ,SPI Status Bit 241" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High"
bitfld.long 0x00 15. "  SPIS239 ,SPI Status Bit 239" "Low,High"
bitfld.long 0x00 14. "  SPIS238 ,SPI Status Bit 238" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High"
bitfld.long 0x00 12. "  SPIS236 ,SPI Status Bit 236" "Low,High"
bitfld.long 0x00 11. "  SPIS235 ,SPI Status Bit 235" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High"
bitfld.long 0x00 9. "  SPIS233 ,SPI Status Bit 233" "Low,High"
bitfld.long 0x00 8. "  SPIS232 ,SPI Status Bit 232" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High"
bitfld.long 0x00 6. "  SPIS230 ,SPI Status Bit 230" "Low,High"
bitfld.long 0x00 5. "  SPIS229 ,SPI Status Bit 229" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High"
bitfld.long 0x00 3. "  SPIS227 ,SPI Status Bit 227" "Low,High"
bitfld.long 0x00 2. "  SPIS226 ,SPI Status Bit 226" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High"
bitfld.long 0x00 0. "  SPIS224 ,SPI Status Bit 224" "Low,High"
else
hgroup.long 0xC09C++0x03
hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
rgroup.long 0xC0A0++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High"
bitfld.long 0x00 30. "  SPIS286 ,SPI Status Bit 286" "Low,High"
bitfld.long 0x00 29. "  SPIS285 ,SPI Status Bit 285" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High"
bitfld.long 0x00 27. "  SPIS283 ,SPI Status Bit 283" "Low,High"
bitfld.long 0x00 26. "  SPIS282 ,SPI Status Bit 282" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High"
bitfld.long 0x00 24. "  SPIS280 ,SPI Status Bit 280" "Low,High"
bitfld.long 0x00 23. "  SPIS279 ,SPI Status Bit 279" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High"
bitfld.long 0x00 21. "  SPIS277 ,SPI Status Bit 277" "Low,High"
bitfld.long 0x00 20. "  SPIS276 ,SPI Status Bit 276" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High"
bitfld.long 0x00 18. "  SPIS274 ,SPI Status Bit 274" "Low,High"
bitfld.long 0x00 17. "  SPIS273 ,SPI Status Bit 273" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High"
bitfld.long 0x00 15. "  SPIS271 ,SPI Status Bit 271" "Low,High"
bitfld.long 0x00 14. "  SPIS270 ,SPI Status Bit 270" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High"
bitfld.long 0x00 12. "  SPIS268 ,SPI Status Bit 268" "Low,High"
bitfld.long 0x00 11. "  SPIS267 ,SPI Status Bit 267" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High"
bitfld.long 0x00 9. "  SPIS265 ,SPI Status Bit 265" "Low,High"
bitfld.long 0x00 8. "  SPIS264 ,SPI Status Bit 264" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High"
bitfld.long 0x00 6. "  SPIS262 ,SPI Status Bit 262" "Low,High"
bitfld.long 0x00 5. "  SPIS261 ,SPI Status Bit 261" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High"
bitfld.long 0x00 3. "  SPIS259 ,SPI Status Bit 259" "Low,High"
bitfld.long 0x00 2. "  SPIS258 ,SPI Status Bit 258" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High"
bitfld.long 0x00 0. "  SPIS256 ,SPI Status Bit 256" "Low,High"
else
hgroup.long 0xC0A0++0x03
hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
rgroup.long 0xC0A4++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High"
bitfld.long 0x00 30. "  SPIS318 ,SPI Status Bit 318" "Low,High"
bitfld.long 0x00 29. "  SPIS317 ,SPI Status Bit 317" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High"
bitfld.long 0x00 27. "  SPIS315 ,SPI Status Bit 315" "Low,High"
bitfld.long 0x00 26. "  SPIS314 ,SPI Status Bit 314" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High"
bitfld.long 0x00 24. "  SPIS312 ,SPI Status Bit 312" "Low,High"
bitfld.long 0x00 23. "  SPIS311 ,SPI Status Bit 311" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High"
bitfld.long 0x00 21. "  SPIS309 ,SPI Status Bit 309" "Low,High"
bitfld.long 0x00 20. "  SPIS308 ,SPI Status Bit 308" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High"
bitfld.long 0x00 18. "  SPIS306 ,SPI Status Bit 306" "Low,High"
bitfld.long 0x00 17. "  SPIS305 ,SPI Status Bit 305" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High"
bitfld.long 0x00 15. "  SPIS303 ,SPI Status Bit 303" "Low,High"
bitfld.long 0x00 14. "  SPIS302 ,SPI Status Bit 302" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High"
bitfld.long 0x00 12. "  SPIS300 ,SPI Status Bit 300" "Low,High"
bitfld.long 0x00 11. "  SPIS299 ,SPI Status Bit 299" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High"
bitfld.long 0x00 9. "  SPIS297 ,SPI Status Bit 297" "Low,High"
bitfld.long 0x00 8. "  SPIS296 ,SPI Status Bit 296" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High"
bitfld.long 0x00 6. "  SPIS294 ,SPI Status Bit 294" "Low,High"
bitfld.long 0x00 5. "  SPIS293 ,SPI Status Bit 293" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High"
bitfld.long 0x00 3. "  SPIS291 ,SPI Status Bit 291" "Low,High"
bitfld.long 0x00 2. "  SPIS290 ,SPI Status Bit 290" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High"
bitfld.long 0x00 0. "  SPIS288 ,SPI Status Bit 288" "Low,High"
else
hgroup.long 0xC0A4++0x03
hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
rgroup.long 0xC0A8++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High"
bitfld.long 0x00 30. "  SPIS350 ,SPI Status Bit 350" "Low,High"
bitfld.long 0x00 29. "  SPIS349 ,SPI Status Bit 349" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High"
bitfld.long 0x00 27. "  SPIS347 ,SPI Status Bit 347" "Low,High"
bitfld.long 0x00 26. "  SPIS346 ,SPI Status Bit 346" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High"
bitfld.long 0x00 24. "  SPIS344 ,SPI Status Bit 344" "Low,High"
bitfld.long 0x00 23. "  SPIS343 ,SPI Status Bit 343" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High"
bitfld.long 0x00 21. "  SPIS341 ,SPI Status Bit 341" "Low,High"
bitfld.long 0x00 20. "  SPIS340 ,SPI Status Bit 340" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High"
bitfld.long 0x00 18. "  SPIS338 ,SPI Status Bit 338" "Low,High"
bitfld.long 0x00 17. "  SPIS337 ,SPI Status Bit 337" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High"
bitfld.long 0x00 15. "  SPIS335 ,SPI Status Bit 335" "Low,High"
bitfld.long 0x00 14. "  SPIS334 ,SPI Status Bit 334" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High"
bitfld.long 0x00 12. "  SPIS332 ,SPI Status Bit 332" "Low,High"
bitfld.long 0x00 11. "  SPIS331 ,SPI Status Bit 331" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High"
bitfld.long 0x00 9. "  SPIS329 ,SPI Status Bit 329" "Low,High"
bitfld.long 0x00 8. "  SPIS328 ,SPI Status Bit 328" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High"
bitfld.long 0x00 6. "  SPIS326 ,SPI Status Bit 326" "Low,High"
bitfld.long 0x00 5. "  SPIS325 ,SPI Status Bit 325" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High"
bitfld.long 0x00 3. "  SPIS323 ,SPI Status Bit 323" "Low,High"
bitfld.long 0x00 2. "  SPIS322 ,SPI Status Bit 322" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High"
bitfld.long 0x00 0. "  SPIS320 ,SPI Status Bit 320" "Low,High"
else
hgroup.long 0xC0A8++0x03
hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
rgroup.long 0xC0AC++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High"
bitfld.long 0x00 30. "  SPIS382 ,SPI Status Bit 382" "Low,High"
bitfld.long 0x00 29. "  SPIS381 ,SPI Status Bit 381" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High"
bitfld.long 0x00 27. "  SPIS379 ,SPI Status Bit 379" "Low,High"
bitfld.long 0x00 26. "  SPIS378 ,SPI Status Bit 378" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High"
bitfld.long 0x00 24. "  SPIS376 ,SPI Status Bit 376" "Low,High"
bitfld.long 0x00 23. "  SPIS375 ,SPI Status Bit 375" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High"
bitfld.long 0x00 21. "  SPIS373 ,SPI Status Bit 373" "Low,High"
bitfld.long 0x00 20. "  SPIS372 ,SPI Status Bit 372" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High"
bitfld.long 0x00 18. "  SPIS370 ,SPI Status Bit 370" "Low,High"
bitfld.long 0x00 17. "  SPIS369 ,SPI Status Bit 369" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High"
bitfld.long 0x00 15. "  SPIS367 ,SPI Status Bit 367" "Low,High"
bitfld.long 0x00 14. "  SPIS366 ,SPI Status Bit 366" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High"
bitfld.long 0x00 12. "  SPIS364 ,SPI Status Bit 364" "Low,High"
bitfld.long 0x00 11. "  SPIS363 ,SPI Status Bit 363" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High"
bitfld.long 0x00 9. "  SPIS361 ,SPI Status Bit 361" "Low,High"
bitfld.long 0x00 8. "  SPIS360 ,SPI Status Bit 360" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High"
bitfld.long 0x00 6. "  SPIS358 ,SPI Status Bit 358" "Low,High"
bitfld.long 0x00 5. "  SPIS357 ,SPI Status Bit 357" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High"
bitfld.long 0x00 3. "  SPIS355 ,SPI Status Bit 355" "Low,High"
bitfld.long 0x00 2. "  SPIS354 ,SPI Status Bit 354" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High"
bitfld.long 0x00 0. "  SPIS352 ,SPI Status Bit 352" "Low,High"
else
hgroup.long 0xC0AC++0x03
hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
rgroup.long 0xC0B0++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High"
bitfld.long 0x00 30. "  SPIS414 ,SPI Status Bit 414" "Low,High"
bitfld.long 0x00 29. "  SPIS413 ,SPI Status Bit 413" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High"
bitfld.long 0x00 27. "  SPIS411 ,SPI Status Bit 411" "Low,High"
bitfld.long 0x00 26. "  SPIS410 ,SPI Status Bit 410" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High"
bitfld.long 0x00 24. "  SPIS408 ,SPI Status Bit 408" "Low,High"
bitfld.long 0x00 23. "  SPIS407 ,SPI Status Bit 407" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High"
bitfld.long 0x00 21. "  SPIS405 ,SPI Status Bit 405" "Low,High"
bitfld.long 0x00 20. "  SPIS404 ,SPI Status Bit 404" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High"
bitfld.long 0x00 18. "  SPIS402 ,SPI Status Bit 402" "Low,High"
bitfld.long 0x00 17. "  SPIS401 ,SPI Status Bit 401" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High"
bitfld.long 0x00 15. "  SPIS399 ,SPI Status Bit 399" "Low,High"
bitfld.long 0x00 14. "  SPIS398 ,SPI Status Bit 398" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High"
bitfld.long 0x00 12. "  SPIS396 ,SPI Status Bit 396" "Low,High"
bitfld.long 0x00 11. "  SPIS395 ,SPI Status Bit 395" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High"
bitfld.long 0x00 9. "  SPIS393 ,SPI Status Bit 393" "Low,High"
bitfld.long 0x00 8. "  SPIS392 ,SPI Status Bit 392" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High"
bitfld.long 0x00 6. "  SPIS390 ,SPI Status Bit 390" "Low,High"
bitfld.long 0x00 5. "  SPIS389 ,SPI Status Bit 389" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High"
bitfld.long 0x00 3. "  SPIS387 ,SPI Status Bit 387" "Low,High"
bitfld.long 0x00 2. "  SPIS386 ,SPI Status Bit 386" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High"
bitfld.long 0x00 0. "  SPIS384 ,SPI Status Bit 384" "Low,High"
else
hgroup.long 0xC0B0++0x03
hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
rgroup.long 0xC0B4++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High"
bitfld.long 0x00 30. "  SPIS446 ,SPI Status Bit 446" "Low,High"
bitfld.long 0x00 29. "  SPIS445 ,SPI Status Bit 445" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High"
bitfld.long 0x00 27. "  SPIS443 ,SPI Status Bit 443" "Low,High"
bitfld.long 0x00 26. "  SPIS442 ,SPI Status Bit 442" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High"
bitfld.long 0x00 24. "  SPIS440 ,SPI Status Bit 440" "Low,High"
bitfld.long 0x00 23. "  SPIS439 ,SPI Status Bit 439" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High"
bitfld.long 0x00 21. "  SPIS437 ,SPI Status Bit 437" "Low,High"
bitfld.long 0x00 20. "  SPIS436 ,SPI Status Bit 436" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High"
bitfld.long 0x00 18. "  SPIS434 ,SPI Status Bit 434" "Low,High"
bitfld.long 0x00 17. "  SPIS433 ,SPI Status Bit 433" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High"
bitfld.long 0x00 15. "  SPIS431 ,SPI Status Bit 431" "Low,High"
bitfld.long 0x00 14. "  SPIS430 ,SPI Status Bit 430" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High"
bitfld.long 0x00 12. "  SPIS428 ,SPI Status Bit 428" "Low,High"
bitfld.long 0x00 11. "  SPIS427 ,SPI Status Bit 427" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High"
bitfld.long 0x00 9. "  SPIS425 ,SPI Status Bit 425" "Low,High"
bitfld.long 0x00 8. "  SPIS424 ,SPI Status Bit 424" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High"
bitfld.long 0x00 6. "  SPIS422 ,SPI Status Bit 422" "Low,High"
bitfld.long 0x00 5. "  SPIS421 ,SPI Status Bit 421" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High"
bitfld.long 0x00 3. "  SPIS419 ,SPI Status Bit 419" "Low,High"
bitfld.long 0x00 2. "  SPIS418 ,SPI Status Bit 418" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High"
bitfld.long 0x00 0. "  SPIS416 ,SPI Status Bit 416" "Low,High"
else
hgroup.long 0xC0B4++0x03
hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
rgroup.long 0xC0B8++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High"
bitfld.long 0x00 30. "  SPIS478 ,SPI Status Bit 478" "Low,High"
bitfld.long 0x00 29. "  SPIS477 ,SPI Status Bit 477" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High"
bitfld.long 0x00 27. "  SPIS475 ,SPI Status Bit 475" "Low,High"
bitfld.long 0x00 26. "  SPIS474 ,SPI Status Bit 474" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High"
bitfld.long 0x00 24. "  SPIS472 ,SPI Status Bit 472" "Low,High"
bitfld.long 0x00 23. "  SPIS471 ,SPI Status Bit 471" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High"
bitfld.long 0x00 21. "  SPIS469 ,SPI Status Bit 469" "Low,High"
bitfld.long 0x00 20. "  SPIS468 ,SPI Status Bit 468" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High"
bitfld.long 0x00 18. "  SPIS466 ,SPI Status Bit 466" "Low,High"
bitfld.long 0x00 17. "  SPIS465 ,SPI Status Bit 465" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High"
bitfld.long 0x00 15. "  SPIS463 ,SPI Status Bit 463" "Low,High"
bitfld.long 0x00 14. "  SPIS462 ,SPI Status Bit 462" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High"
bitfld.long 0x00 12. "  SPIS460 ,SPI Status Bit 460" "Low,High"
bitfld.long 0x00 11. "  SPIS459 ,SPI Status Bit 459" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High"
bitfld.long 0x00 9. "  SPIS457 ,SPI Status Bit 457" "Low,High"
bitfld.long 0x00 8. "  SPIS456 ,SPI Status Bit 456" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High"
bitfld.long 0x00 6. "  SPIS454 ,SPI Status Bit 454" "Low,High"
bitfld.long 0x00 5. "  SPIS453 ,SPI Status Bit 453" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High"
bitfld.long 0x00 3. "  SPIS451 ,SPI Status Bit 451" "Low,High"
bitfld.long 0x00 2. "  SPIS450 ,SPI Status Bit 450" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High"
bitfld.long 0x00 0. "  SPIS448 ,SPI Status Bit 448" "Low,High"
else
hgroup.long 0xC0B8++0x03
hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
rgroup.long 0xC0BC++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High"
bitfld.long 0x00 30. "  SPIS510 ,SPI Status Bit 510" "Low,High"
bitfld.long 0x00 29. "  SPIS509 ,SPI Status Bit 509" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High"
bitfld.long 0x00 27. "  SPIS507 ,SPI Status Bit 507" "Low,High"
bitfld.long 0x00 26. "  SPIS506 ,SPI Status Bit 506" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High"
bitfld.long 0x00 24. "  SPIS504 ,SPI Status Bit 504" "Low,High"
bitfld.long 0x00 23. "  SPIS503 ,SPI Status Bit 503" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High"
bitfld.long 0x00 21. "  SPIS501 ,SPI Status Bit 501" "Low,High"
bitfld.long 0x00 20. "  SPIS500 ,SPI Status Bit 500" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High"
bitfld.long 0x00 18. "  SPIS498 ,SPI Status Bit 498" "Low,High"
bitfld.long 0x00 17. "  SPIS497 ,SPI Status Bit 497" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High"
bitfld.long 0x00 15. "  SPIS495 ,SPI Status Bit 495" "Low,High"
bitfld.long 0x00 14. "  SPIS494 ,SPI Status Bit 494" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High"
bitfld.long 0x00 12. "  SPIS492 ,SPI Status Bit 492" "Low,High"
bitfld.long 0x00 11. "  SPIS491 ,SPI Status Bit 491" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High"
bitfld.long 0x00 9. "  SPIS489 ,SPI Status Bit 489" "Low,High"
bitfld.long 0x00 8. "  SPIS488 ,SPI Status Bit 488" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High"
bitfld.long 0x00 6. "  SPIS486 ,SPI Status Bit 486" "Low,High"
bitfld.long 0x00 5. "  SPIS485 ,SPI Status Bit 485" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High"
bitfld.long 0x00 3. "  SPIS483 ,SPI Status Bit 483" "Low,High"
bitfld.long 0x00 2. "  SPIS482 ,SPI Status Bit 482" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High"
bitfld.long 0x00 0. "  SPIS480 ,SPI Status Bit 480" "Low,High"
else
hgroup.long 0xC0BC++0x03
hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
rgroup.long 0xC0C0++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High"
bitfld.long 0x00 30. "  SPIS542 ,SPI Status Bit 542" "Low,High"
bitfld.long 0x00 29. "  SPIS541 ,SPI Status Bit 541" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High"
bitfld.long 0x00 27. "  SPIS539 ,SPI Status Bit 539" "Low,High"
bitfld.long 0x00 26. "  SPIS538 ,SPI Status Bit 538" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High"
bitfld.long 0x00 24. "  SPIS536 ,SPI Status Bit 536" "Low,High"
bitfld.long 0x00 23. "  SPIS535 ,SPI Status Bit 535" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High"
bitfld.long 0x00 21. "  SPIS533 ,SPI Status Bit 533" "Low,High"
bitfld.long 0x00 20. "  SPIS532 ,SPI Status Bit 532" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High"
bitfld.long 0x00 18. "  SPIS530 ,SPI Status Bit 530" "Low,High"
bitfld.long 0x00 17. "  SPIS529 ,SPI Status Bit 529" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High"
bitfld.long 0x00 15. "  SPIS527 ,SPI Status Bit 527" "Low,High"
bitfld.long 0x00 14. "  SPIS526 ,SPI Status Bit 526" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High"
bitfld.long 0x00 12. "  SPIS524 ,SPI Status Bit 524" "Low,High"
bitfld.long 0x00 11. "  SPIS523 ,SPI Status Bit 523" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High"
bitfld.long 0x00 9. "  SPIS521 ,SPI Status Bit 521" "Low,High"
bitfld.long 0x00 8. "  SPIS520 ,SPI Status Bit 520" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High"
bitfld.long 0x00 6. "  SPIS518 ,SPI Status Bit 518" "Low,High"
bitfld.long 0x00 5. "  SPIS517 ,SPI Status Bit 517" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High"
bitfld.long 0x00 3. "  SPIS515 ,SPI Status Bit 515" "Low,High"
bitfld.long 0x00 2. "  SPIS514 ,SPI Status Bit 514" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High"
bitfld.long 0x00 0. "  SPIS512 ,SPI Status Bit 512" "Low,High"
else
hgroup.long 0xC0C0++0x03
hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
rgroup.long 0xC0C4++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High"
bitfld.long 0x00 30. "  SPIS574 ,SPI Status Bit 574" "Low,High"
bitfld.long 0x00 29. "  SPIS573 ,SPI Status Bit 573" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High"
bitfld.long 0x00 27. "  SPIS571 ,SPI Status Bit 571" "Low,High"
bitfld.long 0x00 26. "  SPIS570 ,SPI Status Bit 570" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High"
bitfld.long 0x00 24. "  SPIS568 ,SPI Status Bit 568" "Low,High"
bitfld.long 0x00 23. "  SPIS567 ,SPI Status Bit 567" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High"
bitfld.long 0x00 21. "  SPIS565 ,SPI Status Bit 565" "Low,High"
bitfld.long 0x00 20. "  SPIS564 ,SPI Status Bit 564" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High"
bitfld.long 0x00 18. "  SPIS562 ,SPI Status Bit 562" "Low,High"
bitfld.long 0x00 17. "  SPIS561 ,SPI Status Bit 561" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High"
bitfld.long 0x00 15. "  SPIS559 ,SPI Status Bit 559" "Low,High"
bitfld.long 0x00 14. "  SPIS558 ,SPI Status Bit 558" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High"
bitfld.long 0x00 12. "  SPIS556 ,SPI Status Bit 556" "Low,High"
bitfld.long 0x00 11. "  SPIS555 ,SPI Status Bit 555" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High"
bitfld.long 0x00 9. "  SPIS553 ,SPI Status Bit 553" "Low,High"
bitfld.long 0x00 8. "  SPIS552 ,SPI Status Bit 552" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High"
bitfld.long 0x00 6. "  SPIS550 ,SPI Status Bit 550" "Low,High"
bitfld.long 0x00 5. "  SPIS549 ,SPI Status Bit 549" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High"
bitfld.long 0x00 3. "  SPIS547 ,SPI Status Bit 547" "Low,High"
bitfld.long 0x00 2. "  SPIS546 ,SPI Status Bit 546" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High"
bitfld.long 0x00 0. "  SPIS544 ,SPI Status Bit 544" "Low,High"
else
hgroup.long 0xC0C4++0x03
hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
rgroup.long 0xC0C8++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High"
bitfld.long 0x00 30. "  SPIS606 ,SPI Status Bit 606" "Low,High"
bitfld.long 0x00 29. "  SPIS605 ,SPI Status Bit 605" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High"
bitfld.long 0x00 27. "  SPIS603 ,SPI Status Bit 603" "Low,High"
bitfld.long 0x00 26. "  SPIS602 ,SPI Status Bit 602" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High"
bitfld.long 0x00 24. "  SPIS600 ,SPI Status Bit 600" "Low,High"
bitfld.long 0x00 23. "  SPIS599 ,SPI Status Bit 599" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High"
bitfld.long 0x00 21. "  SPIS597 ,SPI Status Bit 597" "Low,High"
bitfld.long 0x00 20. "  SPIS596 ,SPI Status Bit 596" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High"
bitfld.long 0x00 18. "  SPIS594 ,SPI Status Bit 594" "Low,High"
bitfld.long 0x00 17. "  SPIS593 ,SPI Status Bit 593" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High"
bitfld.long 0x00 15. "  SPIS591 ,SPI Status Bit 591" "Low,High"
bitfld.long 0x00 14. "  SPIS590 ,SPI Status Bit 590" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High"
bitfld.long 0x00 12. "  SPIS588 ,SPI Status Bit 588" "Low,High"
bitfld.long 0x00 11. "  SPIS587 ,SPI Status Bit 587" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High"
bitfld.long 0x00 9. "  SPIS585 ,SPI Status Bit 585" "Low,High"
bitfld.long 0x00 8. "  SPIS584 ,SPI Status Bit 584" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High"
bitfld.long 0x00 6. "  SPIS582 ,SPI Status Bit 582" "Low,High"
bitfld.long 0x00 5. "  SPIS581 ,SPI Status Bit 581" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High"
bitfld.long 0x00 3. "  SPIS579 ,SPI Status Bit 579" "Low,High"
bitfld.long 0x00 2. "  SPIS578 ,SPI Status Bit 578" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High"
bitfld.long 0x00 0. "  SPIS576 ,SPI Status Bit 576" "Low,High"
else
hgroup.long 0xC0C8++0x03
hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
rgroup.long 0xC0CC++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High"
bitfld.long 0x00 30. "  SPIS638 ,SPI Status Bit 638" "Low,High"
bitfld.long 0x00 29. "  SPIS637 ,SPI Status Bit 637" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High"
bitfld.long 0x00 27. "  SPIS635 ,SPI Status Bit 635" "Low,High"
bitfld.long 0x00 26. "  SPIS634 ,SPI Status Bit 634" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High"
bitfld.long 0x00 24. "  SPIS632 ,SPI Status Bit 632" "Low,High"
bitfld.long 0x00 23. "  SPIS631 ,SPI Status Bit 631" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High"
bitfld.long 0x00 21. "  SPIS629 ,SPI Status Bit 629" "Low,High"
bitfld.long 0x00 20. "  SPIS628 ,SPI Status Bit 628" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High"
bitfld.long 0x00 18. "  SPIS626 ,SPI Status Bit 626" "Low,High"
bitfld.long 0x00 17. "  SPIS625 ,SPI Status Bit 625" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High"
bitfld.long 0x00 15. "  SPIS623 ,SPI Status Bit 623" "Low,High"
bitfld.long 0x00 14. "  SPIS622 ,SPI Status Bit 622" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High"
bitfld.long 0x00 12. "  SPIS620 ,SPI Status Bit 620" "Low,High"
bitfld.long 0x00 11. "  SPIS619 ,SPI Status Bit 619" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High"
bitfld.long 0x00 9. "  SPIS617 ,SPI Status Bit 617" "Low,High"
bitfld.long 0x00 8. "  SPIS616 ,SPI Status Bit 616" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High"
bitfld.long 0x00 6. "  SPIS614 ,SPI Status Bit 614" "Low,High"
bitfld.long 0x00 5. "  SPIS613 ,SPI Status Bit 613" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High"
bitfld.long 0x00 3. "  SPIS611 ,SPI Status Bit 611" "Low,High"
bitfld.long 0x00 2. "  SPIS610 ,SPI Status Bit 610" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High"
bitfld.long 0x00 0. "  SPIS608 ,SPI Status Bit 608" "Low,High"
else
hgroup.long 0xC0CC++0x03
hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
rgroup.long 0xC0D0++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High"
bitfld.long 0x00 30. "  SPIS670 ,SPI Status Bit 670" "Low,High"
bitfld.long 0x00 29. "  SPIS669 ,SPI Status Bit 669" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High"
bitfld.long 0x00 27. "  SPIS667 ,SPI Status Bit 667" "Low,High"
bitfld.long 0x00 26. "  SPIS666 ,SPI Status Bit 666" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High"
bitfld.long 0x00 24. "  SPIS664 ,SPI Status Bit 664" "Low,High"
bitfld.long 0x00 23. "  SPIS663 ,SPI Status Bit 663" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High"
bitfld.long 0x00 21. "  SPIS661 ,SPI Status Bit 661" "Low,High"
bitfld.long 0x00 20. "  SPIS660 ,SPI Status Bit 660" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High"
bitfld.long 0x00 18. "  SPIS658 ,SPI Status Bit 658" "Low,High"
bitfld.long 0x00 17. "  SPIS657 ,SPI Status Bit 657" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High"
bitfld.long 0x00 15. "  SPIS655 ,SPI Status Bit 655" "Low,High"
bitfld.long 0x00 14. "  SPIS654 ,SPI Status Bit 654" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High"
bitfld.long 0x00 12. "  SPIS652 ,SPI Status Bit 652" "Low,High"
bitfld.long 0x00 11. "  SPIS651 ,SPI Status Bit 651" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High"
bitfld.long 0x00 9. "  SPIS649 ,SPI Status Bit 649" "Low,High"
bitfld.long 0x00 8. "  SPIS648 ,SPI Status Bit 648" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High"
bitfld.long 0x00 6. "  SPIS646 ,SPI Status Bit 646" "Low,High"
bitfld.long 0x00 5. "  SPIS645 ,SPI Status Bit 645" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High"
bitfld.long 0x00 3. "  SPIS643 ,SPI Status Bit 643" "Low,High"
bitfld.long 0x00 2. "  SPIS642 ,SPI Status Bit 642" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High"
bitfld.long 0x00 0. "  SPIS640 ,SPI Status Bit 640" "Low,High"
else
hgroup.long 0xC0D0++0x03
hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
rgroup.long 0xC0D4++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High"
bitfld.long 0x00 30. "  SPIS702 ,SPI Status Bit 702" "Low,High"
bitfld.long 0x00 29. "  SPIS701 ,SPI Status Bit 701" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High"
bitfld.long 0x00 27. "  SPIS699 ,SPI Status Bit 699" "Low,High"
bitfld.long 0x00 26. "  SPIS698 ,SPI Status Bit 698" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High"
bitfld.long 0x00 24. "  SPIS696 ,SPI Status Bit 696" "Low,High"
bitfld.long 0x00 23. "  SPIS695 ,SPI Status Bit 695" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High"
bitfld.long 0x00 21. "  SPIS693 ,SPI Status Bit 693" "Low,High"
bitfld.long 0x00 20. "  SPIS692 ,SPI Status Bit 692" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High"
bitfld.long 0x00 18. "  SPIS690 ,SPI Status Bit 690" "Low,High"
bitfld.long 0x00 17. "  SPIS689 ,SPI Status Bit 689" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High"
bitfld.long 0x00 15. "  SPIS687 ,SPI Status Bit 687" "Low,High"
bitfld.long 0x00 14. "  SPIS686 ,SPI Status Bit 686" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High"
bitfld.long 0x00 12. "  SPIS684 ,SPI Status Bit 684" "Low,High"
bitfld.long 0x00 11. "  SPIS683 ,SPI Status Bit 683" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High"
bitfld.long 0x00 9. "  SPIS681 ,SPI Status Bit 681" "Low,High"
bitfld.long 0x00 8. "  SPIS680 ,SPI Status Bit 680" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High"
bitfld.long 0x00 6. "  SPIS678 ,SPI Status Bit 678" "Low,High"
bitfld.long 0x00 5. "  SPIS677 ,SPI Status Bit 677" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High"
bitfld.long 0x00 3. "  SPIS675 ,SPI Status Bit 675" "Low,High"
bitfld.long 0x00 2. "  SPIS674 ,SPI Status Bit 674" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High"
bitfld.long 0x00 0. "  SPIS672 ,SPI Status Bit 672" "Low,High"
else
hgroup.long 0xC0D4++0x03
hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
rgroup.long 0xC0D8++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High"
bitfld.long 0x00 30. "  SPIS734 ,SPI Status Bit 734" "Low,High"
bitfld.long 0x00 29. "  SPIS733 ,SPI Status Bit 733" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High"
bitfld.long 0x00 27. "  SPIS731 ,SPI Status Bit 731" "Low,High"
bitfld.long 0x00 26. "  SPIS730 ,SPI Status Bit 730" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High"
bitfld.long 0x00 24. "  SPIS728 ,SPI Status Bit 728" "Low,High"
bitfld.long 0x00 23. "  SPIS727 ,SPI Status Bit 727" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High"
bitfld.long 0x00 21. "  SPIS725 ,SPI Status Bit 725" "Low,High"
bitfld.long 0x00 20. "  SPIS724 ,SPI Status Bit 724" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High"
bitfld.long 0x00 18. "  SPIS722 ,SPI Status Bit 722" "Low,High"
bitfld.long 0x00 17. "  SPIS721 ,SPI Status Bit 721" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High"
bitfld.long 0x00 15. "  SPIS719 ,SPI Status Bit 719" "Low,High"
bitfld.long 0x00 14. "  SPIS718 ,SPI Status Bit 718" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High"
bitfld.long 0x00 12. "  SPIS716 ,SPI Status Bit 716" "Low,High"
bitfld.long 0x00 11. "  SPIS715 ,SPI Status Bit 715" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High"
bitfld.long 0x00 9. "  SPIS713 ,SPI Status Bit 713" "Low,High"
bitfld.long 0x00 8. "  SPIS712 ,SPI Status Bit 712" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High"
bitfld.long 0x00 6. "  SPIS710 ,SPI Status Bit 710" "Low,High"
bitfld.long 0x00 5. "  SPIS709 ,SPI Status Bit 709" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High"
bitfld.long 0x00 3. "  SPIS707 ,SPI Status Bit 707" "Low,High"
bitfld.long 0x00 2. "  SPIS706 ,SPI Status Bit 706" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High"
bitfld.long 0x00 0. "  SPIS704 ,SPI Status Bit 704" "Low,High"
else
hgroup.long 0xC0D8++0x03
hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
rgroup.long 0xC0DC++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High"
bitfld.long 0x00 30. "  SPIS766 ,SPI Status Bit 766" "Low,High"
bitfld.long 0x00 29. "  SPIS765 ,SPI Status Bit 765" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High"
bitfld.long 0x00 27. "  SPIS763 ,SPI Status Bit 763" "Low,High"
bitfld.long 0x00 26. "  SPIS762 ,SPI Status Bit 762" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High"
bitfld.long 0x00 24. "  SPIS760 ,SPI Status Bit 760" "Low,High"
bitfld.long 0x00 23. "  SPIS759 ,SPI Status Bit 759" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High"
bitfld.long 0x00 21. "  SPIS757 ,SPI Status Bit 757" "Low,High"
bitfld.long 0x00 20. "  SPIS756 ,SPI Status Bit 756" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High"
bitfld.long 0x00 18. "  SPIS754 ,SPI Status Bit 754" "Low,High"
bitfld.long 0x00 17. "  SPIS753 ,SPI Status Bit 753" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High"
bitfld.long 0x00 15. "  SPIS751 ,SPI Status Bit 751" "Low,High"
bitfld.long 0x00 14. "  SPIS750 ,SPI Status Bit 750" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High"
bitfld.long 0x00 12. "  SPIS748 ,SPI Status Bit 748" "Low,High"
bitfld.long 0x00 11. "  SPIS747 ,SPI Status Bit 747" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High"
bitfld.long 0x00 9. "  SPIS745 ,SPI Status Bit 745" "Low,High"
bitfld.long 0x00 8. "  SPIS744 ,SPI Status Bit 744" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High"
bitfld.long 0x00 6. "  SPIS742 ,SPI Status Bit 742" "Low,High"
bitfld.long 0x00 5. "  SPIS741 ,SPI Status Bit 741" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High"
bitfld.long 0x00 3. "  SPIS739 ,SPI Status Bit 739" "Low,High"
bitfld.long 0x00 2. "  SPIS738 ,SPI Status Bit 738" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High"
bitfld.long 0x00 0. "  SPIS736 ,SPI Status Bit 736" "Low,High"
else
hgroup.long 0xC0DC++0x03
hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
rgroup.long 0xC0E0++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High"
bitfld.long 0x00 30. "  SPIS798 ,SPI Status Bit 798" "Low,High"
bitfld.long 0x00 29. "  SPIS797 ,SPI Status Bit 797" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High"
bitfld.long 0x00 27. "  SPIS795 ,SPI Status Bit 795" "Low,High"
bitfld.long 0x00 26. "  SPIS794 ,SPI Status Bit 794" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High"
bitfld.long 0x00 24. "  SPIS792 ,SPI Status Bit 792" "Low,High"
bitfld.long 0x00 23. "  SPIS791 ,SPI Status Bit 791" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High"
bitfld.long 0x00 21. "  SPIS789 ,SPI Status Bit 789" "Low,High"
bitfld.long 0x00 20. "  SPIS788 ,SPI Status Bit 788" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High"
bitfld.long 0x00 18. "  SPIS786 ,SPI Status Bit 786" "Low,High"
bitfld.long 0x00 17. "  SPIS785 ,SPI Status Bit 785" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High"
bitfld.long 0x00 15. "  SPIS783 ,SPI Status Bit 783" "Low,High"
bitfld.long 0x00 14. "  SPIS782 ,SPI Status Bit 782" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High"
bitfld.long 0x00 12. "  SPIS780 ,SPI Status Bit 780" "Low,High"
bitfld.long 0x00 11. "  SPIS779 ,SPI Status Bit 779" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High"
bitfld.long 0x00 9. "  SPIS777 ,SPI Status Bit 777" "Low,High"
bitfld.long 0x00 8. "  SPIS776 ,SPI Status Bit 776" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High"
bitfld.long 0x00 6. "  SPIS774 ,SPI Status Bit 774" "Low,High"
bitfld.long 0x00 5. "  SPIS773 ,SPI Status Bit 773" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High"
bitfld.long 0x00 3. "  SPIS771 ,SPI Status Bit 771" "Low,High"
bitfld.long 0x00 2. "  SPIS770 ,SPI Status Bit 770" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High"
bitfld.long 0x00 0. "  SPIS768 ,SPI Status Bit 768" "Low,High"
else
hgroup.long 0xC0E0++0x03
hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
rgroup.long 0xC0E4++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High"
bitfld.long 0x00 30. "  SPIS830 ,SPI Status Bit 830" "Low,High"
bitfld.long 0x00 29. "  SPIS829 ,SPI Status Bit 829" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High"
bitfld.long 0x00 27. "  SPIS827 ,SPI Status Bit 827" "Low,High"
bitfld.long 0x00 26. "  SPIS826 ,SPI Status Bit 826" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High"
bitfld.long 0x00 24. "  SPIS824 ,SPI Status Bit 824" "Low,High"
bitfld.long 0x00 23. "  SPIS823 ,SPI Status Bit 823" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High"
bitfld.long 0x00 21. "  SPIS821 ,SPI Status Bit 821" "Low,High"
bitfld.long 0x00 20. "  SPIS820 ,SPI Status Bit 820" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High"
bitfld.long 0x00 18. "  SPIS818 ,SPI Status Bit 818" "Low,High"
bitfld.long 0x00 17. "  SPIS817 ,SPI Status Bit 817" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High"
bitfld.long 0x00 15. "  SPIS815 ,SPI Status Bit 815" "Low,High"
bitfld.long 0x00 14. "  SPIS814 ,SPI Status Bit 814" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High"
bitfld.long 0x00 12. "  SPIS812 ,SPI Status Bit 812" "Low,High"
bitfld.long 0x00 11. "  SPIS811 ,SPI Status Bit 811" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High"
bitfld.long 0x00 9. "  SPIS809 ,SPI Status Bit 809" "Low,High"
bitfld.long 0x00 8. "  SPIS808 ,SPI Status Bit 808" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High"
bitfld.long 0x00 6. "  SPIS806 ,SPI Status Bit 806" "Low,High"
bitfld.long 0x00 5. "  SPIS805 ,SPI Status Bit 805" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High"
bitfld.long 0x00 3. "  SPIS803 ,SPI Status Bit 803" "Low,High"
bitfld.long 0x00 2. "  SPIS802 ,SPI Status Bit 802" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High"
bitfld.long 0x00 0. "  SPIS800 ,SPI Status Bit 800" "Low,High"
else
hgroup.long 0xC0E4++0x03
hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
rgroup.long 0xC0E8++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High"
bitfld.long 0x00 30. "  SPIS862 ,SPI Status Bit 862" "Low,High"
bitfld.long 0x00 29. "  SPIS861 ,SPI Status Bit 861" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High"
bitfld.long 0x00 27. "  SPIS859 ,SPI Status Bit 859" "Low,High"
bitfld.long 0x00 26. "  SPIS858 ,SPI Status Bit 858" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High"
bitfld.long 0x00 24. "  SPIS856 ,SPI Status Bit 856" "Low,High"
bitfld.long 0x00 23. "  SPIS855 ,SPI Status Bit 855" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High"
bitfld.long 0x00 21. "  SPIS853 ,SPI Status Bit 853" "Low,High"
bitfld.long 0x00 20. "  SPIS852 ,SPI Status Bit 852" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High"
bitfld.long 0x00 18. "  SPIS850 ,SPI Status Bit 850" "Low,High"
bitfld.long 0x00 17. "  SPIS849 ,SPI Status Bit 849" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High"
bitfld.long 0x00 15. "  SPIS847 ,SPI Status Bit 847" "Low,High"
bitfld.long 0x00 14. "  SPIS846 ,SPI Status Bit 846" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High"
bitfld.long 0x00 12. "  SPIS844 ,SPI Status Bit 844" "Low,High"
bitfld.long 0x00 11. "  SPIS843 ,SPI Status Bit 843" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High"
bitfld.long 0x00 9. "  SPIS841 ,SPI Status Bit 841" "Low,High"
bitfld.long 0x00 8. "  SPIS840 ,SPI Status Bit 840" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High"
bitfld.long 0x00 6. "  SPIS838 ,SPI Status Bit 838" "Low,High"
bitfld.long 0x00 5. "  SPIS837 ,SPI Status Bit 837" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High"
bitfld.long 0x00 3. "  SPIS835 ,SPI Status Bit 835" "Low,High"
bitfld.long 0x00 2. "  SPIS834 ,SPI Status Bit 834" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High"
bitfld.long 0x00 0. "  SPIS832 ,SPI Status Bit 832" "Low,High"
else
hgroup.long 0xC0E8++0x03
hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
rgroup.long 0xC0EC++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High"
bitfld.long 0x00 30. "  SPIS894 ,SPI Status Bit 894" "Low,High"
bitfld.long 0x00 29. "  SPIS893 ,SPI Status Bit 893" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High"
bitfld.long 0x00 27. "  SPIS891 ,SPI Status Bit 891" "Low,High"
bitfld.long 0x00 26. "  SPIS890 ,SPI Status Bit 890" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High"
bitfld.long 0x00 24. "  SPIS888 ,SPI Status Bit 888" "Low,High"
bitfld.long 0x00 23. "  SPIS887 ,SPI Status Bit 887" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High"
bitfld.long 0x00 21. "  SPIS885 ,SPI Status Bit 885" "Low,High"
bitfld.long 0x00 20. "  SPIS884 ,SPI Status Bit 884" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High"
bitfld.long 0x00 18. "  SPIS882 ,SPI Status Bit 882" "Low,High"
bitfld.long 0x00 17. "  SPIS881 ,SPI Status Bit 881" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High"
bitfld.long 0x00 15. "  SPIS879 ,SPI Status Bit 879" "Low,High"
bitfld.long 0x00 14. "  SPIS878 ,SPI Status Bit 878" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High"
bitfld.long 0x00 12. "  SPIS876 ,SPI Status Bit 876" "Low,High"
bitfld.long 0x00 11. "  SPIS875 ,SPI Status Bit 875" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High"
bitfld.long 0x00 9. "  SPIS873 ,SPI Status Bit 873" "Low,High"
bitfld.long 0x00 8. "  SPIS872 ,SPI Status Bit 872" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High"
bitfld.long 0x00 6. "  SPIS870 ,SPI Status Bit 870" "Low,High"
bitfld.long 0x00 5. "  SPIS869 ,SPI Status Bit 869" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High"
bitfld.long 0x00 3. "  SPIS867 ,SPI Status Bit 867" "Low,High"
bitfld.long 0x00 2. "  SPIS866 ,SPI Status Bit 866" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High"
bitfld.long 0x00 0. "  SPIS864 ,SPI Status Bit 864" "Low,High"
else
hgroup.long 0xC0EC++0x03
hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
rgroup.long 0xC0F0++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High"
bitfld.long 0x00 30. "  SPIS926 ,SPI Status Bit 926" "Low,High"
bitfld.long 0x00 29. "  SPIS925 ,SPI Status Bit 925" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High"
bitfld.long 0x00 27. "  SPIS923 ,SPI Status Bit 923" "Low,High"
bitfld.long 0x00 26. "  SPIS922 ,SPI Status Bit 922" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High"
bitfld.long 0x00 24. "  SPIS920 ,SPI Status Bit 920" "Low,High"
bitfld.long 0x00 23. "  SPIS919 ,SPI Status Bit 919" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High"
bitfld.long 0x00 21. "  SPIS917 ,SPI Status Bit 917" "Low,High"
bitfld.long 0x00 20. "  SPIS916 ,SPI Status Bit 916" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High"
bitfld.long 0x00 18. "  SPIS914 ,SPI Status Bit 914" "Low,High"
bitfld.long 0x00 17. "  SPIS913 ,SPI Status Bit 913" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High"
bitfld.long 0x00 15. "  SPIS911 ,SPI Status Bit 911" "Low,High"
bitfld.long 0x00 14. "  SPIS910 ,SPI Status Bit 910" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High"
bitfld.long 0x00 12. "  SPIS908 ,SPI Status Bit 908" "Low,High"
bitfld.long 0x00 11. "  SPIS907 ,SPI Status Bit 907" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High"
bitfld.long 0x00 9. "  SPIS905 ,SPI Status Bit 905" "Low,High"
bitfld.long 0x00 8. "  SPIS904 ,SPI Status Bit 904" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High"
bitfld.long 0x00 6. "  SPIS902 ,SPI Status Bit 902" "Low,High"
bitfld.long 0x00 5. "  SPIS901 ,SPI Status Bit 901" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High"
bitfld.long 0x00 3. "  SPIS899 ,SPI Status Bit 899" "Low,High"
bitfld.long 0x00 2. "  SPIS898 ,SPI Status Bit 898" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High"
bitfld.long 0x00 0. "  SPIS896 ,SPI Status Bit 896" "Low,High"
else
hgroup.long 0xC0F0++0x03
hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
rgroup.long 0xC0F4++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High"
bitfld.long 0x00 30. "  SPIS958 ,SPI Status Bit 958" "Low,High"
bitfld.long 0x00 29. "  SPIS957 ,SPI Status Bit 957" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High"
bitfld.long 0x00 27. "  SPIS955 ,SPI Status Bit 955" "Low,High"
bitfld.long 0x00 26. "  SPIS954 ,SPI Status Bit 954" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High"
bitfld.long 0x00 24. "  SPIS952 ,SPI Status Bit 952" "Low,High"
bitfld.long 0x00 23. "  SPIS951 ,SPI Status Bit 951" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High"
bitfld.long 0x00 21. "  SPIS949 ,SPI Status Bit 949" "Low,High"
bitfld.long 0x00 20. "  SPIS948 ,SPI Status Bit 948" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High"
bitfld.long 0x00 18. "  SPIS946 ,SPI Status Bit 946" "Low,High"
bitfld.long 0x00 17. "  SPIS945 ,SPI Status Bit 945" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High"
bitfld.long 0x00 15. "  SPIS943 ,SPI Status Bit 943" "Low,High"
bitfld.long 0x00 14. "  SPIS942 ,SPI Status Bit 942" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High"
bitfld.long 0x00 12. "  SPIS940 ,SPI Status Bit 940" "Low,High"
bitfld.long 0x00 11. "  SPIS939 ,SPI Status Bit 939" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High"
bitfld.long 0x00 9. "  SPIS937 ,SPI Status Bit 937" "Low,High"
bitfld.long 0x00 8. "  SPIS936 ,SPI Status Bit 936" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High"
bitfld.long 0x00 6. "  SPIS934 ,SPI Status Bit 934" "Low,High"
bitfld.long 0x00 5. "  SPIS933 ,SPI Status Bit 933" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High"
bitfld.long 0x00 3. "  SPIS931 ,SPI Status Bit 931" "Low,High"
bitfld.long 0x00 2. "  SPIS930 ,SPI Status Bit 930" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High"
bitfld.long 0x00 0. "  SPIS928 ,SPI Status Bit 928" "Low,High"
else
hgroup.long 0xC0F4++0x03
hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
rgroup.long 0xC0F8++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High"
bitfld.long 0x00 30. "  SPIS990 ,SPI Status Bit 990" "Low,High"
bitfld.long 0x00 29. "  SPIS989 ,SPI Status Bit 989" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High"
bitfld.long 0x00 27. "  SPIS987 ,SPI Status Bit 987" "Low,High"
bitfld.long 0x00 26. "  SPIS986 ,SPI Status Bit 986" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High"
bitfld.long 0x00 24. "  SPIS984 ,SPI Status Bit 984" "Low,High"
bitfld.long 0x00 23. "  SPIS983 ,SPI Status Bit 983" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High"
bitfld.long 0x00 21. "  SPIS981 ,SPI Status Bit 981" "Low,High"
bitfld.long 0x00 20. "  SPIS980 ,SPI Status Bit 980" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High"
bitfld.long 0x00 18. "  SPIS978 ,SPI Status Bit 978" "Low,High"
bitfld.long 0x00 17. "  SPIS977 ,SPI Status Bit 977" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High"
bitfld.long 0x00 15. "  SPIS975 ,SPI Status Bit 975" "Low,High"
bitfld.long 0x00 14. "  SPIS974 ,SPI Status Bit 974" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High"
bitfld.long 0x00 12. "  SPIS972 ,SPI Status Bit 972" "Low,High"
bitfld.long 0x00 11. "  SPIS971 ,SPI Status Bit 971" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High"
bitfld.long 0x00 9. "  SPIS969 ,SPI Status Bit 969" "Low,High"
bitfld.long 0x00 8. "  SPIS968 ,SPI Status Bit 968" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High"
bitfld.long 0x00 6. "  SPIS966 ,SPI Status Bit 966" "Low,High"
bitfld.long 0x00 5. "  SPIS965 ,SPI Status Bit 965" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High"
bitfld.long 0x00 3. "  SPIS963 ,SPI Status Bit 963" "Low,High"
bitfld.long 0x00 2. "  SPIS962 ,SPI Status Bit 962" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High"
bitfld.long 0x00 0. "  SPIS960 ,SPI Status Bit 960" "Low,High"
else
hgroup.long 0xC0F8++0x03
hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
endif
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICD_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICD_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICD_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICD_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
base (COMP.BASE("GICD",-1.)+0x20000)
width 24.
tree "Interrupt Translation Service"
group.long 0x00++0x03
line.long 0x00 "GITS_CTLR,ITS Control Register"
rbitfld.long 0x00 31. "         QUIESCENT              ,Indicates completion of all ITS operations" "Not quiescent,Quiescent"
bitfld.long 0x00 0. "                      ENABLED                ,Controls whether the ITS is enabled" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID                 ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "                            VAR                    ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " REV                    ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                                 IMP                    ,Implementer"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 2. "                                 CCT                    ,Cumulative Collection Tables" "0,1"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.quad 0x00 2. " CCT                    ,Cumulative Collection Tables" "0,1"
else
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.quad 0x80++0x07
line.quad 0x00 "GITS_CBASER,The command queue control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated"
bitfld.quad 0x00 59.--61. "                      INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "    PHYSICAL_ADDRESS       ,Bits [51:12] of the base physical address of the command queue"
textline "                                         "
bitfld.quad 0x00 10.--11. " SHAREABILITY           ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                    SIZE                   ,The number of 4KB pages of physical memory allocated to the command queue minus one"
group.quad 0x88++0x7
line.quad 0x00 "GITS_CWRITER,The command queue write pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               RETRY                  ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted"
group.quad 0x90++0x07
line.quad 0x00 "GITS_CREADR,The command queue read pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               STALLED                ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00)
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
else
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                               SIZE                   ,The number of pages of physical memory allocated to the table minus one"
endif
textline "                                         "
wgroup.long 0xC000++0x03
line.long 0x00 "GITS_TRKCTLR,Tracking Control Register"
bitfld.long 0x00 1. "         LPI_TRACK              ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture"
bitfld.long 0x00 0. "  CACHE_COUNT_RESET      ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset"
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 6. "         PID_OUT_OF_RANGE       ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1"
bitfld.long 0x00 5. "          TARGET_OUT_OF_RANGE    ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1"
textline "                                 "
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 3. "         INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
bitfld.long 0x00 2. "          DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
textline "                                 "
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
else
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC008++0x03
line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
hexmask.long.tbyte 0x00 0.--19. 1. "         LPI_DID                ,The Device ID for the interrupt that was tracked"
else
hgroup.long 0xC008++0x03
hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC00C++0x03
line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_PID                ,The ID after translation for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC00C++0x03
hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC010++0x03
line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_ID                 ,The ID before translation of the interrupt that was tracked"
else
hgroup.long 0xC010++0x03
hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC014++0x03
line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
hexmask.long.byte 0x00 0.--6. 1. "         LPI_TARGET_CORE        ,The target core for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC014++0x03
hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
endif
rgroup.long 0xC018++0x03
line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         ITE_CACHE_HITS         ,Number of hits in the ITE cache"
hexmask.long.word 0x00 0.--15. 1. "       ITE_CACHE_MISSES       ,Number of misses in the ITE cache"
rgroup.long 0xC01C++0x03
line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         LPI_CACHE_HITS         ,Number of hits in the LPI cache"
hexmask.long.word 0x00 0.--15. 1. "       LPI_CACHE_MISSES       ,Number of misses in the LPI cache"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         PART_0                 ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. "         DES_1                  ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         PART_1                 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. "         ARCHREV                ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "   JEDEC                  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
textline "                                 "
bitfld.long 0x00 0.--2. "         DES_1                  ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. "         REVAND                 ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         CMOD                   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. "         SIZE                   ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         DES_2                  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GITS_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GITS_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GITS_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GITS_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
textline "                                 "
base (COMP.BASE("GICD",-1.)+0x20000)+0x10000
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01)
wgroup.long 0x40++0x03
line.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
else
hgroup.long 0x40++0x03
hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
endif
tree.end
width 0x0B
base COMP.BASE("GICR",-1.)
width 17.
tree "Redistributor Interface"
tree "Control Registers"
if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID    ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "           VAR            ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x00 12.--15. " REV       ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                IMP            ,Implementer"
rgroup.quad 0x0008++0x07
line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register"
hexmask.quad.byte 0x00 56.--63. 1. " AFF3      ,Affinity level 3 value for the Redistributor"
hexmask.quad.byte 0x00 48.--55. 1. "                AFF2           ,Affinity level 2 value for the Redistributor"
hexmask.quad.byte 0x00 40.--47. 1. "              AFF1             ,Affinity level 1 value for the Redistributor"
textline "                                  "
hexmask.quad.byte 0x00 32.--39. 1. " AFF0      ,Affinity level 0 value for the Redistributor"
bitfld.quad 0x00 24.--25. "                COMMONLPIAFF   ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1"
hexmask.quad.word 0x00 8.--23. 1. "  PROCESSOR_NUMBER ,A unique identifier for the PE"
textline "                                  "
bitfld.quad 0x00 5. " DPGS      ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported"
bitfld.quad 0x00 4. "     LAST           ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest"
bitfld.quad 0x00 3. "     DIRECTLPI        ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported"
textline "                                  "
bitfld.quad 0x00 0. " PLPIS     ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014))))
group.long 0x0014++0x03
line.long 0x00 "GICR_WAKER,Power Management Control Register"
bitfld.long 0x00 31. "         QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent"
bitfld.long 0x00 2. "     CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent"
bitfld.long 0x00 1. "   PROCESSORASLEEP  ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes"
textline "                                  "
bitfld.long 0x00 0. " SLEEP     ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes"
textline "                                  "
else
hgroup.long 0x0014++0x03
hide.long 0x00 "GICR_WAKER,Power Management Control Register"
endif
group.quad 0x070++0x07
line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register"
bitfld.quad 0x00 56.--58. " OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "  PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table"
textline "                                  "
bitfld.quad 0x00 10.--11. " SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
bitfld.quad 0x00 7.--9. "                  INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                  "
bitfld.quad 0x00 0.--4. " IDBITS           ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address"
group.quad 0x78++0x07
line.quad 0x00 "GICR_PENDBASER,LPI pending table base register"
bitfld.quad 0x00 62. "         PTZ              ,Pending Table Zero" "Not zero,Zero" 
bitfld.quad 0x00 56.--58. "                         OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
textline "                                  "
hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table"
bitfld.quad 0x00 10.--11. "                 SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                  "
bitfld.quad 0x00 7.--9. " INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                 "
tree.end
tree "SGI and PPI Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080))
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9  ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8  ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6  ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5  ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3  ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2  ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0  ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000)
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30 ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29 ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27 ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26 ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24 ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23 ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21 ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20 ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18 ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17 ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15 ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14 ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12 ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11 ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9  ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8  ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6  ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5  ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3  ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2  ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0  ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x10080++0x03
hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
textline "                          "
width 24.
group.long 0x10100++0x03
line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRENB31    ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRENB30    ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRENB29    ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRENB28    ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRENB27    ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRENB26    ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRENB25    ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRENB24    ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRENB23    ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRENB22    ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRENB21    ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRENB20    ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRENB19    ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRENB18    ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRENB17    ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRENB16    ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRENB15    ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRENB14    ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRENB13    ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRENB12    ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRENB11    ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRENB10    ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRENB9     ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRENB8     ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRENB7     ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRENB6     ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRENB5     ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRENB4     ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRENB3     ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRENB2     ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRENB1     ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRENB0     ,Set/Clear Enable Bit 0" "Disabled,Enabled"
group.long 0x10200++0x03
line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
group.long 0x10300++0x03
line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9  ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8  ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRACTIVE7  ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6  ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5  ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRACTIVE4  ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3  ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2  ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRACTIVE1  ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0  ,Set/Clear Active Bit 0" "Not active,Active"
textline "                                 "
width 18.
group.long 0x10400++0x03
line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID2    ,Interrupt ID2    Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID0    ,Interrupt ID0    Priority/Priority Byte Offset 0   "
group.long 0x10404++0x03
line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID6    ,Interrupt ID6    Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID4    ,Interrupt ID4    Priority/Priority Byte Offset 4   "
group.long 0x10408++0x03
line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID10   ,Interrupt ID10   Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID8    ,Interrupt ID8    Priority/Priority Byte Offset 8   "
group.long 0x1040C++0x03
line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID14   ,Interrupt ID14   Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID12   ,Interrupt ID12   Priority/Priority Byte Offset 12  "
group.long 0x10410++0x03
line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID18   ,Interrupt ID18   Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID16   ,Interrupt ID16   Priority/Priority Byte Offset 16  "
group.long 0x10414++0x03
line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID22   ,Interrupt ID22   Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID20   ,Interrupt ID20   Priority/Priority Byte Offset 20  "
group.long 0x10418++0x03
line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID26   ,Interrupt ID26   Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID24   ,Interrupt ID24   Priority/Priority Byte Offset 24  "
group.long 0x1041C++0x03
line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID30   ,Interrupt ID30   Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID28   ,Interrupt ID28   Priority/Priority Byte Offset 28  "
textline "                                 "
rgroup.long 0x10C00++0x03
line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (SGI)" "Level,Edge"
group.long 0x10C04++0x03
line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1    ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                           "
width 18.
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00))
group.long 0x10D00++0x03
line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1"
bitfld.long 0x00 30. "  GMB30 ,Group Modifier Bit 30" "0,1"
bitfld.long 0x00 29. "  GMB29 ,Group Modifier Bit 29" "0,1"
textline "                           "
bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1"
bitfld.long 0x00 27. "  GMB27 ,Group Modifier Bit 27" "0,1"
bitfld.long 0x00 26. "  GMB26 ,Group Modifier Bit 26" "0,1"
textline "                           "
bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1"
bitfld.long 0x00 24. "  GMB24 ,Group Modifier Bit 24" "0,1"
bitfld.long 0x00 23. "  GMB23 ,Group Modifier Bit 23" "0,1"
textline "                           "
bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1"
bitfld.long 0x00 21. "  GMB21 ,Group Modifier Bit 21" "0,1"
bitfld.long 0x00 20. "  GMB20 ,Group Modifier Bit 20" "0,1"
textline "                           "
bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1"
bitfld.long 0x00 18. "  GMB18 ,Group Modifier Bit 18" "0,1"
bitfld.long 0x00 17. "  GMB17 ,Group Modifier Bit 17" "0,1"
textline "                           "
bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1"
bitfld.long 0x00 15. "  GMB15 ,Group Modifier Bit 15" "0,1"
bitfld.long 0x00 14. "  GMB14 ,Group Modifier Bit 14" "0,1"
textline "                           "
bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1"
bitfld.long 0x00 12. "  GMB12 ,Group Modifier Bit 12" "0,1"
bitfld.long 0x00 11. "  GMB11 ,Group Modifier Bit 11" "0,1"
textline "                           "
bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1"
bitfld.long 0x00 9. "  GMB9  ,Group Modifier Bit 9" "0,1"
bitfld.long 0x00 8. "  GMB8  ,Group Modifier Bit 8" "0,1"
textline "                           "
bitfld.long 0x00 7. " GMB7  ,Group Modifier Bit 7" "0,1"
bitfld.long 0x00 6. "  GMB6  ,Group Modifier Bit 6" "0,1"
bitfld.long 0x00 5. "  GMB5  ,Group Modifier Bit 5" "0,1"
textline "                           "
bitfld.long 0x00 4. " GMB4  ,Group Modifier Bit 4" "0,1"
bitfld.long 0x00 3. "  GMB3  ,Group Modifier Bit 3" "0,1"
bitfld.long 0x00 2. "  GMB2  ,Group Modifier Bit 2" "0,1"
textline "                           "
bitfld.long 0x00 1. " GMB1  ,Group Modifier Bit 1" "0,1"
bitfld.long 0x00 0. "  GMB0  ,Group Modifier Bit 0" "0,1"
textline "                           "
else
hgroup.long 0x10D00++0x03
hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00))
group.long 0x10E00++0x03
line.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 28.--29. "  NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 26.--27. "  NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 22.--23. "  NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 20.--21. "  NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 18.--19. " NS_ACCESS9  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 16.--17. "  NS_ACCESS8  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 14.--15. "  NS_ACCESS7  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 12.--13. " NS_ACCESS6  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 10.--11. "  NS_ACCESS5  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 8.--9. "  NS_ACCESS4  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 6.--7. " NS_ACCESS3  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 4.--5. "  NS_ACCESS2  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 2.--3. "  NS_ACCESS1  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 0.--1. " NS_ACCESS0  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..."
textline "                           "
else
hgroup.long 0x10E00++0x03
hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
rgroup.long 0x1C000++0x03
line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register"
bitfld.long 0x00 31. " CPU_AS     ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High"
bitfld.long 0x00 2. "  ENABLEGRP1_S ,EnableGrp1 Secure" "0,1"
bitfld.long 0x00 1. "     ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1"
textline "                           "
bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1"
rgroup.long 0x1C080++0x03
line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register"
bitfld.long 0x00 31. " PPI31S     ,Actual status of the PPI31 input signal" "Low,High"
bitfld.long 0x00 30. "  PPI30S       ,Actual status of the PPI30 input signal" "Low,High"
bitfld.long 0x00 29. "  PPI29S        ,Actual status of the PPI29 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 28. " PPI28S     ,Actual status of the PPI28 input signal" "Low,High"
bitfld.long 0x00 27. "  PPI27S       ,Actual status of the PPI27 input signal" "Low,High"
bitfld.long 0x00 26. "  PPI26S        ,Actual status of the PPI26 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 25. " PPI25S     ,Actual status of the PPI25 input signal" "Low,High"
bitfld.long 0x00 24. "  PPI24S       ,Actual status of the PPI24 input signal" "Low,High"
bitfld.long 0x00 23. "  PPI23S        ,Actual status of the PPI23 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 22. " PPI22S     ,Actual status of the PPI22 input signal" "Low,High"
bitfld.long 0x00 21. "  PPI21S       ,Actual status of the PPI21 input signal" "Low,High"
bitfld.long 0x00 20. "  PPI20S        ,Actual status of the PPI20 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 19. " PPI19S     ,Actual status of the PPI19 input signal" "Low,High"
bitfld.long 0x00 18. "  PPI18S       ,Actual status of the PPI18 input signal" "Low,High"
bitfld.long 0x00 17. "  PPI17S        ,Actual status of the PPI17 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 16. " PPI16S     ,Actual status of the PPI16 input signal" "Low,High"
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICR_CIDR0,Component ID0 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICR_CIDR1,Component ID1 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICR_CIDR2,Component ID2 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICR_CIDR3,Component ID3 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
sif COMP.AVAILABLE("GICC")
base COMP.BASE("GICC",-1.)
width 14.
tree "CPU Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.)))
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 10. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 9. "  EOIMODES      ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 6. "          IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 4. " CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "               FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 6. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODE       ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 7. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 4. "          CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
textline "                       "
bitfld.long 0x00 3. " FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
endif
textline "                       "
group.long 0x04++0x03
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICC_BPR,Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x0C++0x03
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
in
wgroup.long 0x10++0x03
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x20++0x03
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
in
wgroup.long 0x24++0x03
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x2C++0x03
line.long 0x00 "GICC_STATUSR,CPU Interface Status Register"
bitfld.long 0x00 4. " ASV      ,Attempted security violation" "Not detected,Detected"
bitfld.long 0x00 3. "  WROD    ,Write to an RO location" "Not detected,Detected"
bitfld.long 0x00 2. "  RWOD ,Read of a WO location" "Not detected,Detected"
textline "                       "
bitfld.long 0x00 1. " WRD      ,Write to a reserved location" "Not detected,Detected"
bitfld.long 0x00 0. "  RRD     ,Read of a reserved location" "Not detected,Detected"
group.long 0xD0++0x03
line.long 0x00 "GICC_APR0,Active Priorities Register 0"
group.long 0xD4++0x03
line.long 0x00 "GICC_APR1,Active Priorities Register 1"
group.long 0xD8++0x03
line.long 0x00 "GICC_APR2,Active Priorities Register 2"
group.long 0xDC++0x03
line.long 0x00 "GICC_APR3,Active Priorities Register 3"
group.long 0xE0++0x03
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0"
group.long 0xE4++0x03
line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1"
group.long 0xE8++0x03
line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2"
group.long 0xEC++0x03
line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3"
rgroup.long 0xFC++0x03
line.long 0x00 "GICC_IIDR,CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID   ,Product ID"
bitfld.long 0x00 16.--19. "          ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..."
bitfld.long 0x00 12.--15. "         REV  ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "            IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICH")
base COMP.BASE("GICH",-1.)
width 13.
tree "Virtual CPU Control Interface"
group.long 0x00++0x03
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "             VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "      VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "             VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "       NPIE     ,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      LRENPIE  ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "             UIE      ,Underflow Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " EN       ,Virtual CPU interface Enable" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GICH_VTR,Virtual Type Register"
bitfld.long 0x00 29.--31. " PRIBITS  ,Number of priority bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 26.--28. "              PREBITS  ,Number of pre-emption bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 23.--25. "             IDBITS   ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..."
textline "                      "
bitfld.long 0x00 22. " SEIS     ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "  A3V      ,Affinity 3 valid" "Invalid,Valid"
bitfld.long 0x00 0.--4. "       LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x08++0x03
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. " VPMR     ,Virtual priority mask"
bitfld.long 0x00 21.--23. "             VBPR0    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "             VBPR1    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "                    VEOIM    ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
textline "                      "
bitfld.long 0x00 4. " VCBPR    ,Virtual Common Binary Point Register" "ABPR,BPR"
bitfld.long 0x00 3. "           VFIQEN   ,Virtual FIQ enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      VACKCTL  ,Virtual AckCtl" "INTID=1022,INTID=corresponding"
bitfld.long 0x00 1. "  VENG1    ,Virtual interrupt enable for group 1" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " VENG0    ,Virtual interrupt enable for group 0" "Disabled,Enabled"
rgroup.long 0x10++0x03
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
bitfld.long 0x00 7. " VGRP1D   ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 6. "   VGRP1E   ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 5. "  VGRP0D   ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 4. "         VGRP0E   ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
textline "                      "
bitfld.long 0x00 3. " NP       ,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 2. "   LRENP    ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 1. "  U        ,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 0. "         EOI      ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
rgroup.long 0x20++0x03
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
rgroup.long 0x30++0x03
line.long 0x00 "GICH_ELRSR0,Empty List register Status Register"
bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,Status bit for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,Status bit for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,Status bit for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,Status bit for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,Status bit for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,Status bit for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,Status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,Status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,Status bit for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,Status bit for List register 0" "No interrupt,Interrupt"
textline "                      "
group.long 0xF0++0x03
line.long 0x00 "GICH_APR0,Active Priorities Register 0"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF4++0x03
line.long 0x00 "GICH_APR1,Active Priorities Register 1"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF8++0x03
line.long 0x00 "GICH_APR2,Active Priorities Register 2"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xFC++0x03
line.long 0x00 "GICH_APR3,Active Priorities Register 3"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
textline "                       "
group.long 0x100++0x03
line.long 0x00 "GICH_LR0,List Register 0"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x104++0x03
line.long 0x00 "GICH_LR1,List Register 1"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x108++0x03
line.long 0x00 "GICH_LR2,List Register 2"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x10C++0x03
line.long 0x00 "GICH_LR3,List Register 3"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x110++0x03
line.long 0x00 "GICH_LR4,List Register 4"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x114++0x03
line.long 0x00 "GICH_LR5,List Register 5"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x118++0x03
line.long 0x00 "GICH_LR6,List Register 6"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x11C++0x03
line.long 0x00 "GICH_LR7,List Register 7"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x120++0x03
line.long 0x00 "GICH_LR8,List Register 8"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x124++0x03
line.long 0x00 "GICH_LR9,List Register 9"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x128++0x03
line.long 0x00 "GICH_LR10,List Register 10"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x12C++0x03
line.long 0x00 "GICH_LR11,List Register 11"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x130++0x03
line.long 0x00 "GICH_LR12,List Register 12"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x134++0x03
line.long 0x00 "GICH_LR13,List Register 13"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x138++0x03
line.long 0x00 "GICH_LR14,List Register 14"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICV")
base COMP.BASE("GICV",-1.)
width 14.
tree "Virtual CPU Interface"
group.long 0x00++0x03
line.long 0x00 "GICV_CTLR,VM Control Register"
bitfld.long 0x00 9. " EOIMODE    ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 4. "  CBPR       ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "       FIQEN ,FIQ Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding"
textline "                      "
bitfld.long 0x00 1. "  ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
group.long 0x04++0x03
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority mask level for the virtual CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICV_BPR,VM Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x0C++0x03
line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x10++0x03
line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICV_RPR,VM Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x20++0x03
line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x24++0x03
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
textline ""
group.long 0xD0++0x03
line.long 0x00 "GICV_APR0,VM Active Priority Register 0"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD4++0x03
line.long 0x00 "GICV_APR1,VM Active Priority Register 1"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD8++0x03
line.long 0x00 "GICV_APR2,VM Active Priority Register 2"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xDC++0x03
line.long 0x00 "GICV_APR3,VM Active Priority Register 3"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
textline "                      "
rgroup.long 0xFC++0x03
line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID     ,Product ID"
bitfld.long 0x00 16.--19. "    ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "  REV ,Revision number for the CPU interface" ",,,GICv3,?..."
hexmask.long.word 0x00 0.--11. 1. "  IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
tree.end
width 0x0b
endif
width 0x0B
tree.end
tree.end
else
tree.close "Core Registers (Cortex-M7F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 28. " DISFPUISSOPT   ,DISFPUISSOPT" "No,Yes"
bitfld.long 0x00 27. "                   DISCRITAXIRUW  ,Disables critical AXI read-under-write" "No,Yes"
bitfld.long 0x00 26. "                  DISDYNADD      ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 21.--25. " DISISSCH1      ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
bitfld.long 0x00 16.--20. "   DISDI          ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
bitfld.long 0x00 15. "  DISCRITAXIRUR  ,Disables critical AXI read-under-read" "No,Yes"
textline "                     "
bitfld.long 0x00 14. " DISBTACALLOC   ,DISBTACALLOC" "No,Yes"
bitfld.long 0x00 13. "                   DISBTACREAD    ,DISBTACREAD" "No,Yes"
bitfld.long 0x00 12. "                  DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
textline "                     "
bitfld.long 0x00 11. " DISRAMODE      ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
bitfld.long 0x00 10. "                   FPEXCODIS      ,Disables FPU exception outputs" "No,Yes"
bitfld.long 0x00 2. "                  DISFOLD        ,Disables dual-issue functionality" "No,Yes"
textline ""
group.long 0x10++0x03
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "        TICKINT        ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
group.long 0x14++0x07
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x04 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "         TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Indicates implementer"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,Revision 1,?..."
bitfld.long 0x00 16.--19. "      ARCHITECTURE   ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. "              PENDSVSET      ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. "     PENDSTSET      ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline "                     "
rbitfld.long 0x00 23. " ISRPREEMPT     ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. "              ISRPENDING     ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "     VECTPENDING    ,The exception number of the highest priority pending and enabled interrupt"
textline "                     "
rbitfld.long 0x00 11. " RETTOBASE      ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. "               VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT    ,Vector Key"
rbitfld.long 0x08 15. "                  ENDIANNESS     ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 8.--10. "   PRIGROUP       ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
bitfld.long 0x08 0. "       VECTRESET      ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "  SLEEPONEXIT    ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "        DC             ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
bitfld.long 0x10 4. "         DIV_0_TRP      ,Controls the trap on divide by 0" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
bitfld.long 0x10 0. "        NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "              PRI_5          ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "              PRI_9          ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "              PRI_13         ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "        MEMFAULTENA    ,MemManage" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall status" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
bitfld.long 0x20 13. "     MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick status" "Not active,Active"
bitfld.long 0x20 10. "      PENDSVACT      ,PendSV status" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor status" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall status" "Not active,Active"
bitfld.long 0x20 3. "      USGFAULTACT    ,UsageFault status" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault status" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "    MSTKERR        ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "    IACCVIOL       ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "    STKERR         ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "    PRECISERR      ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "        NOCP           ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "        UNDEFINSTR     ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x13
line.long 0x00 "HFSR,HardFault Status Register"
eventfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
eventfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
eventfld.long 0x00 1. "    VECTTBL        ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
eventfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
eventfld.long 0x04 3. "          VCATCH         ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
eventfld.long 0x04 2. "    DWTTRAP        ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
eventfld.long 0x04 1. " BKPT           ,Indicates a debug event generated by  BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
eventfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
line.long 0x08 "MMFAR,MemManage Fault Address Register"
line.long 0x0C "BFAR,BusFault Address Register"
line.long 0x10 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
bitfld.long 0x00 20.--21. "            CP10           ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. "      CP7            ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. "            CP5            ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. "      CP4            ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. "            CP2            ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. "      CP1            ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x0B
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU       ,Level of Unification" "Level 1,level 2,?..."
bitfld.long 0x00 24.--26. "          LOC      ,Level of Coherency" "Level 1,level 2,?..."
bitfld.long 0x00 18.--20. "          CL7           ,Cache type field level 7" "No cache,?..."
textline "                   "
bitfld.long 0x00 15.--17. " CL6       ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. "         CL5      ,Cache type field level 5" "No cache,?..."
bitfld.long 0x00 9.--11. "         CL4           ,Cache type field level 4" "No cache,?..."
textline "                   "
bitfld.long 0x00 6.--8. " CL3       ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. "         CL2      ,Cache type field level 2" "No cache,?..."
bitfld.long 0x00 0.--2. "         CL1           ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
line.long 0x04 "CTR,Cache Type Register"
bitfld.long 0x04 29.--31. " FORMAT    ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
bitfld.long 0x04 24.--27. "            CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x04 20.--23. "                ERG           ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline "                   "
bitfld.long 0x04 16.--19. " DMINLINE  ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "               IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CCSIDR,Cache Size ID Register"
bitfld.long 0x08 31. " WT        ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x08 30. "    WB       ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x08 29. "    RA            ,Indicates support available for read allocation" "Not supported,Supported"
textline "                   "
bitfld.long 0x08 28. " WA        ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x08 13.--27. 1. "    NUMSETS  ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x08 3.--12. 1. "             ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline "                   "
bitfld.long 0x08 0.--2. " LINESIZE  ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL     ,Identifies which cache level to select" "Level 1,?..."
bitfld.long 0x00 0. "          IND      ,Identifies instruction or data cache to use" "Data,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
wgroup.long 0xF58++0x1F
line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
line.long 0x08 "DCISW,Data cache invalidate by set/way"
line.long 0x0C "DCCMVAU,Data cache by address to PoU"
line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
line.long 0x14 "DCCSW,Data cache clean by set/way"
line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
group.long 0xF90++0x13
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
bitfld.long 0x00 3.--6. " SZ        ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
bitfld.long 0x00 2. "  RETEN    ,Retry phase enable" "Disabled,Enabled"
bitfld.long 0x00 1. "         RMW           ,Read-Modify-Write enable" "Disabled,Enabled"
textline "                   "
bitfld.long 0x00 0. " EN        ,TCM enable" "Disabled,Enabled"
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
bitfld.long 0x04 3.--6. " SZ        ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
bitfld.long 0x04 2. "  RETEN    ,Retry phase enable" "Disabled,Enabled"
bitfld.long 0x04 1. "         RMW           ,Read-Modify-Write enable" "Disabled,Enabled"
textline "                   "
bitfld.long 0x04 0. " EN        ,TCM enable" "Disabled,Enabled"
line.long 0x08 "AHBPCR,AHBP control register"
bitfld.long 0x08 1.--3. " SZ        ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
bitfld.long 0x08 0. "    EN       ,AHBP enable" "Disabled,Enabled"
line.long 0x0C "CACR,L1 Cache Control Register"
bitfld.long 0x0C 2. " FORCEWT   ,Enables Force Write-through in the data cache" "Disabled,Enabled"
bitfld.long 0x0C 1. "         ECCDIS   ,Disables ECC in the instruction and data cache" "No,Yes"
bitfld.long 0x0C 0. "              SIWT          ,Enables limited cache coherency usage" "Disabled,Enabled"
line.long 0x10 "AHBSCR,AHB Slave Control Register"
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 2.--10. 1. "               TPRI     ,Threshold execution priority for AHBS traffic demotion"
bitfld.long 0x10 0.--1. "             CTL           ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
group.long 0xFA8++0x03
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
bitfld.long 0x00 8.--9. " AXIMTYPE  ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
bitfld.long 0x00 4. "           EPPB     ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
bitfld.long 0x00 3. "     AXIM          ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
textline "                   "
bitfld.long 0x00 2. " AHBP      ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
bitfld.long 0x00 1. "     DTCM     ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
bitfld.long 0x00 0. "     ITCM          ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
group.long 0xFB0++0x03
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
group.long 0xFB4++0x03
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
group.long 0xFB8++0x03
line.long 0x00 "DEBR0,Data Error bank Register 0"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
group.long 0xFBC++0x03
line.long 0x00 "DEBR1,Data Error bank Register 1"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
tree "CoreSight Identification Registers"
width 6.
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM7F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
newline
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
newline
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
newline
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC     ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. "  ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
newline
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
newline
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
newline
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
newline
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
newline
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
line.long 0x08 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
newline
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
autoindent.on center tree
tree "AIPSTZ (AHB to IP Bridge Trust Zone)"
repeat 5. (list 1. 2. 3. 4. 5.) (list ad:0x301F0000 ad:0x305F0000 ad:0x309F0000 ad:0x32DF0000 ad:0x30DF0000)
tree "AIPSTZ$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MPR,Master Priviledge Registers"
bitfld.long 0x00 28.--31. "MPROT0,Master 0 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
bitfld.long 0x00 24.--27. "MPROT1,Master 1 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
newline
bitfld.long 0x00 20.--23. "MPROT2,Master 2 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
bitfld.long 0x00 16.--19. "MPROT3,Master 3 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
newline
bitfld.long 0x00 8.--11. "MPROT5,Master 5 Priviledge Buffer Read Write Control" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to..,2: Accesses from this master are forced to..,3: Accesses from this master are not forced to..,4: Accesses from this master are forced to..,5: Accesses from this master are not forced to..,6: Accesses from this master are forced to..,7: Accesses from this master are not forced to..,8: Accesses from this master are forced to..,9: Accesses from this master are not forced to..,10: Accesses from this master are forced to..,11: Accesses from this master are not forced to..,12: Accesses from this master are forced to..,13: Accesses from this master are not forced to..,14: Accesses from this master are forced to..,15: Accesses from this master are not forced to.."
group.long 0x40++0x03
line.long 0x00 "OPACR,Off-Platform Peripheral Access Control Registers"
bitfld.long 0x00 28.--31. "OPAC0,Off-platform Peripheral Access Control 0" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 24.--27. "OPAC1,Off-platform Peripheral Access Control 1" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 20.--23. "OPAC2,Off-platform Peripheral Access Control 2" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 16.--19. "OPAC3,Off-platform Peripheral Access Control 3" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 12.--15. "OPAC4,Off-platform Peripheral Access Control 4" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 8.--11. "OPAC5,Off-platform Peripheral Access Control 5" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 4.--7. "OPAC6,Off-platform Peripheral Access Control 6" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 0.--3. "OPAC7,Off-platform Peripheral Access Control 7" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
group.long 0x44++0x03
line.long 0x00 "OPACR1,Off-Platform Peripheral Access Control Registers"
bitfld.long 0x00 28.--31. "OPAC8,Off-platform Peripheral Access Control 8" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 24.--27. "OPAC9,Off-platform Peripheral Access Control 9" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 20.--23. "OPAC10,Off-platform Peripheral Access Control 10" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 16.--19. "OPAC11,Off-platform Peripheral Access Control 11" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 12.--15. "OPAC12,Off-platform Peripheral Access Control 12" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 8.--11. "OPAC13,Off-platform Peripheral Access Control 13" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 4.--7. "OPAC14,Off-platform Peripheral Access Control 14" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 0.--3. "OPAC15,Off-platform Peripheral Access Control 15" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
group.long 0x48++0x03
line.long 0x00 "OPACR2,Off-Platform Peripheral Access Control Registers"
bitfld.long 0x00 28.--31. "OPAC16,Off-platform Peripheral Access Control 16" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 24.--27. "OPAC17,Off-platform Peripheral Access Control 17" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 20.--23. "OPAC18,Off-platform Peripheral Access Control 18" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 16.--19. "OPAC19,Off-platform Peripheral Access Control 19" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 12.--15. "OPAC20,Off-platform Peripheral Access Control 20" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 8.--11. "OPAC21,Off-platform Peripheral Access Control 21" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 4.--7. "OPAC22,Off-platform Peripheral Access Control 22" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 0.--3. "OPAC23,Off-platform Peripheral Access Control 23" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
group.long 0x4C++0x03
line.long 0x00 "OPACR3,Off-Platform Peripheral Access Control Registers"
bitfld.long 0x00 28.--31. "OPAC24,Off-platform Peripheral Access Control 24" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 24.--27. "OPAC25,Off-platform Peripheral Access Control 25" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 20.--23. "OPAC26,Off-platform Peripheral Access Control 26" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 16.--19. "OPAC27,Off-platform Peripheral Access Control 27" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 12.--15. "OPAC28,Off-platform Peripheral Access Control 28" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 8.--11. "OPAC29,Off-platform Peripheral Access Control 29" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
newline
bitfld.long 0x00 4.--7. "OPAC30,Off-platform Peripheral Access Control 30" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 0.--3. "OPAC31,Off-platform Peripheral Access Control 31" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
group.long 0x50++0x03
line.long 0x00 "OPACR4,Off-Platform Peripheral Access Control Registers"
bitfld.long 0x00 28.--31. "OPAC32,Off-platform Peripheral Access Control 32" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
bitfld.long 0x00 24.--27. "OPAC33,Off-platform Peripheral Access Control 33" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not..,2: Accesses from an untrusted master are allowed,3: Accesses from an untrusted master are not..,4: Accesses from an untrusted master are allowed,5: Accesses from an untrusted master are not..,6: Accesses from an untrusted master are allowed,7: Accesses from an untrusted master are not..,8: Accesses from an untrusted master are allowed,9: Accesses from an untrusted master are not..,10: Accesses from an untrusted master are allowed,11: Accesses from an untrusted master are not..,12: Accesses from an untrusted master are allowed,13: Accesses from an untrusted master are not..,14: Accesses from an untrusted master are allowed,15: Accesses from an untrusted master are not.."
tree.end
repeat.end
tree.end
tree "APBH (AHB-to-APBH Bridge with DMA)"
base ad:0x33000000
group.long 0x00++0x03
line.long 0x00 "CTRL0,AHB to APBH Bridge Control and Status Register 0"
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable normal APBH DMA operation" "0,1"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
newline
bitfld.long 0x00 29. "AHB_BURST8_EN,Set this bit to one (default) to enable AHB 8-beat burst" "0,1"
bitfld.long 0x00 28. "APB_BURST_EN,Set this bit to one to enable apb master do a continous transfers when a device request a burst dma" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,These bits must be set to zero for normal operation of each channel"
group.long 0x04++0x03
line.long 0x00 "CTRL0_SET,AHB to APBH Bridge Control and Status Register 0"
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable normal APBH DMA operation" "0,1"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
newline
bitfld.long 0x00 29. "AHB_BURST8_EN,Set this bit to one (default) to enable AHB 8-beat burst" "0,1"
bitfld.long 0x00 28. "APB_BURST_EN,Set this bit to one to enable apb master do a continous transfers when a device request a burst dma" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,These bits must be set to zero for normal operation of each channel"
group.long 0x08++0x03
line.long 0x00 "CTRL0_CLR,AHB to APBH Bridge Control and Status Register 0"
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable normal APBH DMA operation" "0,1"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
newline
bitfld.long 0x00 29. "AHB_BURST8_EN,Set this bit to one (default) to enable AHB 8-beat burst" "0,1"
bitfld.long 0x00 28. "APB_BURST_EN,Set this bit to one to enable apb master do a continous transfers when a device request a burst dma" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,These bits must be set to zero for normal operation of each channel"
group.long 0x0C++0x03
line.long 0x00 "CTRL0_TOG,AHB to APBH Bridge Control and Status Register 0"
bitfld.long 0x00 31. "SFTRST,Set this bit to zero to enable normal APBH DMA operation" "0,1"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
newline
bitfld.long 0x00 29. "AHB_BURST8_EN,Set this bit to one (default) to enable AHB 8-beat burst" "0,1"
bitfld.long 0x00 28. "APB_BURST_EN,Set this bit to one to enable apb master do a continous transfers when a device request a burst dma" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,These bits must be set to zero for normal operation of each channel"
group.long 0x10++0x03
line.long 0x00 "CTRL1,AHB to APBH Bridge Control and Status Register 1"
bitfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 15" "0,1"
bitfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 14" "0,1"
newline
bitfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 13" "0,1"
bitfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 12" "0,1"
newline
bitfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 11" "0,1"
bitfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 10" "0,1"
newline
bitfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 9" "0,1"
bitfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 8" "0,1"
newline
bitfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 7" "0,1"
bitfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 5" "0,1"
bitfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 3" "0,1"
bitfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 1" "0,1"
bitfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 7" "0,1"
bitfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 5" "0,1"
bitfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 3" "0,1"
bitfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 1" "0,1"
bitfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 0" "0,1"
group.long 0x14++0x03
line.long 0x00 "CTRL1_SET,AHB to APBH Bridge Control and Status Register 1"
bitfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 15" "0,1"
bitfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 14" "0,1"
newline
bitfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 13" "0,1"
bitfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 12" "0,1"
newline
bitfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 11" "0,1"
bitfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 10" "0,1"
newline
bitfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 9" "0,1"
bitfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 8" "0,1"
newline
bitfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 7" "0,1"
bitfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 5" "0,1"
bitfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 3" "0,1"
bitfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 1" "0,1"
bitfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 7" "0,1"
bitfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 5" "0,1"
bitfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 3" "0,1"
bitfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 1" "0,1"
bitfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 0" "0,1"
group.long 0x18++0x03
line.long 0x00 "CTRL1_CLR,AHB to APBH Bridge Control and Status Register 1"
bitfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 15" "0,1"
bitfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 14" "0,1"
newline
bitfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 13" "0,1"
bitfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 12" "0,1"
newline
bitfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 11" "0,1"
bitfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 10" "0,1"
newline
bitfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 9" "0,1"
bitfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 8" "0,1"
newline
bitfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 7" "0,1"
bitfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 5" "0,1"
bitfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 3" "0,1"
bitfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 1" "0,1"
bitfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 7" "0,1"
bitfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 5" "0,1"
bitfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 3" "0,1"
bitfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 1" "0,1"
bitfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 0" "0,1"
group.long 0x1C++0x03
line.long 0x00 "CTRL1_TOG,AHB to APBH Bridge Control and Status Register 1"
bitfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 15" "0,1"
bitfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 14" "0,1"
newline
bitfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 13" "0,1"
bitfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 12" "0,1"
newline
bitfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 11" "0,1"
bitfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 10" "0,1"
newline
bitfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 9" "0,1"
bitfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 8" "0,1"
newline
bitfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 7" "0,1"
bitfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 5" "0,1"
bitfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 3" "0,1"
bitfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 1" "0,1"
bitfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,Setting this bit enables the generation of an interrupt request for APBH DMA channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 7" "0,1"
bitfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 5" "0,1"
bitfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 3" "0,1"
bitfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 1" "0,1"
bitfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,Interrupt request status bit for APBH DMA channel 0" "0,1"
group.long 0x20++0x03
line.long 0x00 "CTRL2,AHB to APBH Bridge Control and Status Register 2"
rbitfld.long 0x00 31. "CH15_ERROR_STATUS,Error status bit for APBH DMA Channel 15" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 30. "CH14_ERROR_STATUS,Error status bit for APBH DMA Channel 14" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 29. "CH13_ERROR_STATUS,Error status bit for APBH DMA Channel 13" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 28. "CH12_ERROR_STATUS,Error status bit for APBH DMA Channel 12" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 27. "CH11_ERROR_STATUS,Error status bit for APBH DMA Channel 11" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 26. "CH10_ERROR_STATUS,Error status bit for APBH DMA Channel 10" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 25. "CH9_ERROR_STATUS,Error status bit for APBH DMA Channel 9" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 24. "CH8_ERROR_STATUS,Error status bit for APBH DMA Channel 8" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 23. "CH7_ERROR_STATUS,Error status bit for APBX DMA Channel 7" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 22. "CH6_ERROR_STATUS,Error status bit for APBX DMA Channel 6" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 21. "CH5_ERROR_STATUS,Error status bit for APBX DMA Channel 5" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 20. "CH4_ERROR_STATUS,Error status bit for APBX DMA Channel 4" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 19. "CH3_ERROR_STATUS,Error status bit for APBX DMA Channel 3" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 18. "CH2_ERROR_STATUS,Error status bit for APBX DMA Channel 2" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 17. "CH1_ERROR_STATUS,Error status bit for APBX DMA Channel 1" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 16. "CH0_ERROR_STATUS,Error status bit for APBX DMA Channel 0" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
bitfld.long 0x00 15. "CH15_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 7" "0,1"
bitfld.long 0x00 6. "CH6_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 5" "0,1"
bitfld.long 0x00 4. "CH4_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 3" "0,1"
bitfld.long 0x00 2. "CH2_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 1" "0,1"
bitfld.long 0x00 0. "CH0_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 0" "0,1"
group.long 0x24++0x03
line.long 0x00 "CTRL2_SET,AHB to APBH Bridge Control and Status Register 2"
rbitfld.long 0x00 31. "CH15_ERROR_STATUS,Error status bit for APBH DMA Channel 15" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 30. "CH14_ERROR_STATUS,Error status bit for APBH DMA Channel 14" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 29. "CH13_ERROR_STATUS,Error status bit for APBH DMA Channel 13" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 28. "CH12_ERROR_STATUS,Error status bit for APBH DMA Channel 12" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 27. "CH11_ERROR_STATUS,Error status bit for APBH DMA Channel 11" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 26. "CH10_ERROR_STATUS,Error status bit for APBH DMA Channel 10" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 25. "CH9_ERROR_STATUS,Error status bit for APBH DMA Channel 9" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 24. "CH8_ERROR_STATUS,Error status bit for APBH DMA Channel 8" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 23. "CH7_ERROR_STATUS,Error status bit for APBX DMA Channel 7" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 22. "CH6_ERROR_STATUS,Error status bit for APBX DMA Channel 6" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 21. "CH5_ERROR_STATUS,Error status bit for APBX DMA Channel 5" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 20. "CH4_ERROR_STATUS,Error status bit for APBX DMA Channel 4" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 19. "CH3_ERROR_STATUS,Error status bit for APBX DMA Channel 3" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 18. "CH2_ERROR_STATUS,Error status bit for APBX DMA Channel 2" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 17. "CH1_ERROR_STATUS,Error status bit for APBX DMA Channel 1" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 16. "CH0_ERROR_STATUS,Error status bit for APBX DMA Channel 0" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
bitfld.long 0x00 15. "CH15_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 7" "0,1"
bitfld.long 0x00 6. "CH6_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 5" "0,1"
bitfld.long 0x00 4. "CH4_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 3" "0,1"
bitfld.long 0x00 2. "CH2_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 1" "0,1"
bitfld.long 0x00 0. "CH0_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 0" "0,1"
group.long 0x28++0x03
line.long 0x00 "CTRL2_CLR,AHB to APBH Bridge Control and Status Register 2"
rbitfld.long 0x00 31. "CH15_ERROR_STATUS,Error status bit for APBH DMA Channel 15" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 30. "CH14_ERROR_STATUS,Error status bit for APBH DMA Channel 14" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 29. "CH13_ERROR_STATUS,Error status bit for APBH DMA Channel 13" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 28. "CH12_ERROR_STATUS,Error status bit for APBH DMA Channel 12" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 27. "CH11_ERROR_STATUS,Error status bit for APBH DMA Channel 11" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 26. "CH10_ERROR_STATUS,Error status bit for APBH DMA Channel 10" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 25. "CH9_ERROR_STATUS,Error status bit for APBH DMA Channel 9" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 24. "CH8_ERROR_STATUS,Error status bit for APBH DMA Channel 8" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 23. "CH7_ERROR_STATUS,Error status bit for APBX DMA Channel 7" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 22. "CH6_ERROR_STATUS,Error status bit for APBX DMA Channel 6" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 21. "CH5_ERROR_STATUS,Error status bit for APBX DMA Channel 5" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 20. "CH4_ERROR_STATUS,Error status bit for APBX DMA Channel 4" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 19. "CH3_ERROR_STATUS,Error status bit for APBX DMA Channel 3" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 18. "CH2_ERROR_STATUS,Error status bit for APBX DMA Channel 2" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 17. "CH1_ERROR_STATUS,Error status bit for APBX DMA Channel 1" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 16. "CH0_ERROR_STATUS,Error status bit for APBX DMA Channel 0" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
bitfld.long 0x00 15. "CH15_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 7" "0,1"
bitfld.long 0x00 6. "CH6_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 5" "0,1"
bitfld.long 0x00 4. "CH4_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 3" "0,1"
bitfld.long 0x00 2. "CH2_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 1" "0,1"
bitfld.long 0x00 0. "CH0_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 0" "0,1"
group.long 0x2C++0x03
line.long 0x00 "CTRL2_TOG,AHB to APBH Bridge Control and Status Register 2"
rbitfld.long 0x00 31. "CH15_ERROR_STATUS,Error status bit for APBH DMA Channel 15" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 30. "CH14_ERROR_STATUS,Error status bit for APBH DMA Channel 14" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 29. "CH13_ERROR_STATUS,Error status bit for APBH DMA Channel 13" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 28. "CH12_ERROR_STATUS,Error status bit for APBH DMA Channel 12" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 27. "CH11_ERROR_STATUS,Error status bit for APBH DMA Channel 11" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 26. "CH10_ERROR_STATUS,Error status bit for APBH DMA Channel 10" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 25. "CH9_ERROR_STATUS,Error status bit for APBH DMA Channel 9" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 24. "CH8_ERROR_STATUS,Error status bit for APBH DMA Channel 8" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 23. "CH7_ERROR_STATUS,Error status bit for APBX DMA Channel 7" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 22. "CH6_ERROR_STATUS,Error status bit for APBX DMA Channel 6" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 21. "CH5_ERROR_STATUS,Error status bit for APBX DMA Channel 5" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 20. "CH4_ERROR_STATUS,Error status bit for APBX DMA Channel 4" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 19. "CH3_ERROR_STATUS,Error status bit for APBX DMA Channel 3" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 18. "CH2_ERROR_STATUS,Error status bit for APBX DMA Channel 2" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
rbitfld.long 0x00 17. "CH1_ERROR_STATUS,Error status bit for APBX DMA Channel 1" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
rbitfld.long 0x00 16. "CH0_ERROR_STATUS,Error status bit for APBX DMA Channel 0" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
newline
bitfld.long 0x00 15. "CH15_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 15" "0,1"
bitfld.long 0x00 14. "CH14_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 14" "0,1"
newline
bitfld.long 0x00 13. "CH13_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 13" "0,1"
bitfld.long 0x00 12. "CH12_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 12" "0,1"
newline
bitfld.long 0x00 11. "CH11_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 11" "0,1"
bitfld.long 0x00 10. "CH10_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 10" "0,1"
newline
bitfld.long 0x00 9. "CH9_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 9" "0,1"
bitfld.long 0x00 8. "CH8_ERROR_IRQ,Error interrupt status bit for APBH DMA Channel 8" "0,1"
newline
bitfld.long 0x00 7. "CH7_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 7" "0,1"
bitfld.long 0x00 6. "CH6_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 5" "0,1"
bitfld.long 0x00 4. "CH4_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 3" "0,1"
bitfld.long 0x00 2. "CH2_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 1" "0,1"
bitfld.long 0x00 0. "CH0_ERROR_IRQ,Error interrupt status bit for APBX DMA Channel 0" "0,1"
group.long 0x30++0x03
line.long 0x00 "CHANNEL_CTRL,AHB to APBH Bridge Channel Register"
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state"
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,Setting a bit in this field will freeze the DMA channel associated with it"
group.long 0x34++0x03
line.long 0x00 "CHANNEL_CTRL_SET,AHB to APBH Bridge Channel Register"
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state"
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,Setting a bit in this field will freeze the DMA channel associated with it"
group.long 0x38++0x03
line.long 0x00 "CHANNEL_CTRL_CLR,AHB to APBH Bridge Channel Register"
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state"
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,Setting a bit in this field will freeze the DMA channel associated with it"
group.long 0x3C++0x03
line.long 0x00 "CHANNEL_CTRL_TOG,AHB to APBH Bridge Channel Register"
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state"
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,Setting a bit in this field will freeze the DMA channel associated with it"
rgroup.long 0x40++0x03
line.long 0x00 "DEVSEL,AHB to APBH DMA Device Assignment Register"
group.long 0x50++0x03
line.long 0x00 "DMA_BURST_SIZE,AHB to APBH DMA burst size"
bitfld.long 0x00 16.--17. "CH8,DMA burst size for SSP" "0: BURST0,1: BURST4,2: BURST8,?..."
bitfld.long 0x00 14.--15. "CH7,DMA burst size for GPMI channel 7" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "CH6,DMA burst size for GPMI channel 6" "0,1,2,3"
bitfld.long 0x00 10.--11. "CH5,DMA burst size for GPMI channel 5" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "CH4,DMA burst size for GPMI channel 4" "0,1,2,3"
bitfld.long 0x00 6.--7. "CH3,DMA burst size for GPMI channel 3" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CH2,DMA burst size for GPMI channel 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "CH1,DMA burst size for GPMI channel 1" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "CH0,DMA burst size for GPMI channel 0" "0,1,2,3"
group.long 0x60++0x03
line.long 0x00 "DEBUG,AHB to APBH DMA Debug Register"
bitfld.long 0x00 0. "GPMI_ONE_FIFO,Set to 0ne and the 8 GPMI channels will share the DMA FIFO and when set to zero the 8 GPMI channels will use its own DMA FIFO" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CH0_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x170++0x03
line.long 0x00 "CH1_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x1E0++0x03
line.long 0x00 "CH2_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x250++0x03
line.long 0x00 "CH3_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x2C0++0x03
line.long 0x00 "CH4_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x330++0x03
line.long 0x00 "CH5_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x3A0++0x03
line.long 0x00 "CH6_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x410++0x03
line.long 0x00 "CH7_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x480++0x03
line.long 0x00 "CH8_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x4F0++0x03
line.long 0x00 "CH9_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x560++0x03
line.long 0x00 "CH10_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x5D0++0x03
line.long 0x00 "CH11_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x640++0x03
line.long 0x00 "CH12_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x6B0++0x03
line.long 0x00 "CH13_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x720++0x03
line.long 0x00 "CH14_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
rgroup.long 0x790++0x03
line.long 0x00 "CH15_CURCMDAR,APBH DMA Channel n Current Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to command structure currently being processed for channel n"
group.long 0x110++0x03
line.long 0x00 "CH0_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x180++0x03
line.long 0x00 "CH1_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x1F0++0x03
line.long 0x00 "CH2_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x260++0x03
line.long 0x00 "CH3_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x2D0++0x03
line.long 0x00 "CH4_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x340++0x03
line.long 0x00 "CH5_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x3B0++0x03
line.long 0x00 "CH6_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x420++0x03
line.long 0x00 "CH7_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x490++0x03
line.long 0x00 "CH8_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x500++0x03
line.long 0x00 "CH9_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x570++0x03
line.long 0x00 "CH10_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x5E0++0x03
line.long 0x00 "CH11_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x650++0x03
line.long 0x00 "CH12_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x6C0++0x03
line.long 0x00 "CH13_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x730++0x03
line.long 0x00 "CH14_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
group.long 0x7A0++0x03
line.long 0x00 "CH15_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,Pointer to next command structure for channel n"
rgroup.long 0x120++0x03
line.long 0x00 "CH0_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x190++0x03
line.long 0x00 "CH1_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x200++0x03
line.long 0x00 "CH2_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x270++0x03
line.long 0x00 "CH3_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x2E0++0x03
line.long 0x00 "CH4_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x350++0x03
line.long 0x00 "CH5_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x3C0++0x03
line.long 0x00 "CH6_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x430++0x03
line.long 0x00 "CH7_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x4A0++0x03
line.long 0x00 "CH8_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x510++0x03
line.long 0x00 "CH9_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x580++0x03
line.long 0x00 "CH10_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x5F0++0x03
line.long 0x00 "CH11_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x660++0x03
line.long 0x00 "CH12_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x6D0++0x03
line.long 0x00 "CH13_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x740++0x03
line.long 0x00 "CH14_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x7B0++0x03
line.long 0x00 "CH15_CMD,APBH DMA Channel n Command Register"
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device"
bitfld.long 0x00 12.--15. "CMDWORDS,This field indicates the number of command words to send to the GPMI0 starting with the base PIO address of the GPMI0 control register and incrementing from there" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "HALTONTERMINATE,A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set" "0,1"
bitfld.long 0x00 7. "WAIT4ENDCMD,A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command" "0,1"
newline
bitfld.long 0x00 6. "SEMAPHORE,A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure" "0,1"
bitfld.long 0x00 5. "NANDWAIT4READY,A value of one indicates that the NAND DMA channel will will wait until the NAND device reports ready before executing the command" "0,1"
newline
bitfld.long 0x00 4. "NANDLOCK,A value of one indicates that the NAND DMA channel will remain locked in the arbiter at the expense of other NAND DMA channels" "0,1"
bitfld.long 0x00 3. "IRQONCMPLT,A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command i" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,A value of one indicates that another command is chained onto the end of the current command structure" "0,1"
bitfld.long 0x00 0.--1. "COMMAND,This bitfield indicates the type of current command" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
rgroup.long 0x130++0x03
line.long 0x00 "CH0_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x1A0++0x03
line.long 0x00 "CH1_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x210++0x03
line.long 0x00 "CH2_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x280++0x03
line.long 0x00 "CH3_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x2F0++0x03
line.long 0x00 "CH4_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x360++0x03
line.long 0x00 "CH5_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x3D0++0x03
line.long 0x00 "CH6_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x440++0x03
line.long 0x00 "CH7_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x4B0++0x03
line.long 0x00 "CH8_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x520++0x03
line.long 0x00 "CH9_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x590++0x03
line.long 0x00 "CH10_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x600++0x03
line.long 0x00 "CH11_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x670++0x03
line.long 0x00 "CH12_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x6E0++0x03
line.long 0x00 "CH13_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x750++0x03
line.long 0x00 "CH14_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
rgroup.long 0x7C0++0x03
line.long 0x00 "CH15_BAR,APBH DMA Channel n Buffer Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of system memory buffer to be read or written over the AHB bus"
group.long 0x140++0x03
line.long 0x00 "CH0_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x1B0++0x03
line.long 0x00 "CH1_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x220++0x03
line.long 0x00 "CH2_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x290++0x03
line.long 0x00 "CH3_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x300++0x03
line.long 0x00 "CH4_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x370++0x03
line.long 0x00 "CH5_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x3E0++0x03
line.long 0x00 "CH6_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x450++0x03
line.long 0x00 "CH7_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x4C0++0x03
line.long 0x00 "CH8_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x530++0x03
line.long 0x00 "CH9_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x5A0++0x03
line.long 0x00 "CH10_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x610++0x03
line.long 0x00 "CH11_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x680++0x03
line.long 0x00 "CH12_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x6F0++0x03
line.long 0x00 "CH13_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x760++0x03
line.long 0x00 "CH14_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
group.long 0x7D0++0x03
line.long 0x00 "CH15_SEMA,APBH DMA Channel n Semaphore Register"
hexmask.long.byte 0x00 16.--23. 1. "PHORE,This read-only field shows the current (instantaneous) value of the semaphore counter"
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected"
rgroup.long 0x150++0x03
line.long 0x00 "CH0_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x1C0++0x03
line.long 0x00 "CH1_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x230++0x03
line.long 0x00 "CH2_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x2A0++0x03
line.long 0x00 "CH3_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x310++0x03
line.long 0x00 "CH4_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x380++0x03
line.long 0x00 "CH5_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x3F0++0x03
line.long 0x00 "CH6_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x460++0x03
line.long 0x00 "CH7_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x4D0++0x03
line.long 0x00 "CH8_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x540++0x03
line.long 0x00 "CH9_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x5B0++0x03
line.long 0x00 "CH10_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x620++0x03
line.long 0x00 "CH11_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x690++0x03
line.long 0x00 "CH12_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x700++0x03
line.long 0x00 "CH13_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x770++0x03
line.long 0x00 "CH14_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x7E0++0x03
line.long 0x00 "CH15_DEBUG1,AHB to APBH DMA Channel n Debug Information"
bitfld.long 0x00 31. "REQ,This bit reflects the current state of the DMA Request Signal from the APB device" "0,1"
bitfld.long 0x00 30. "BURST,This bit reflects the current state of the DMA Burst Signal from the APB device" "0,1"
newline
bitfld.long 0x00 29. "KICK,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "0,1"
bitfld.long 0x00 28. "END,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "0,1"
newline
bitfld.long 0x00 26. "READY,This bit is reserved for this DMA Channel and always reads 0" "0,1"
bitfld.long 0x00 24. "NEXTCMDADDRVALID,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "0,1"
newline
bitfld.long 0x00 23. "RD_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "0,1"
bitfld.long 0x00 22. "RD_FIFO_FULL,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "0,1"
newline
bitfld.long 0x00 21. "WR_FIFO_EMPTY,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "0,1"
bitfld.long 0x00 20. "WR_FIFO_FULL,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "0,1"
newline
bitfld.long 0x00 0.--4. "STATEMACHINE,PIO Display of the DMA Channel n state machine state" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
rgroup.long 0x160++0x03
line.long 0x00 "CH0_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x1D0++0x03
line.long 0x00 "CH1_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x240++0x03
line.long 0x00 "CH2_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x2B0++0x03
line.long 0x00 "CH3_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x320++0x03
line.long 0x00 "CH4_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x390++0x03
line.long 0x00 "CH5_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x400++0x03
line.long 0x00 "CH6_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x470++0x03
line.long 0x00 "CH7_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x4E0++0x03
line.long 0x00 "CH8_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x550++0x03
line.long 0x00 "CH9_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x5C0++0x03
line.long 0x00 "CH10_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x630++0x03
line.long 0x00 "CH11_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x6A0++0x03
line.long 0x00 "CH12_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x710++0x03
line.long 0x00 "CH13_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x780++0x03
line.long 0x00 "CH14_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x7F0++0x03
line.long 0x00 "CH15_DEBUG2,AHB to APBH DMA Channel n Debug Information"
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,This value reflects the current number of APB bytes remaining to be transfered in the current transfer"
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer"
rgroup.long 0x800++0x03
line.long 0x00 "VERSION,APBH Bridge Version Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value reflecting the MAJOR field of the RTL version"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value reflecting the MINOR field of the RTL version"
newline
hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the RTL version"
tree.end
tree "ASRC"
base ad:0x30C90000
repeat 4. (increment 0 1) (increment 0 0x4)
wgroup.long ($2+0x00)++0x03
line.long 0x00 "WRFIFO[$1],ASRC Input Write FIFO $1"
hexmask.long 0x00 0.--31. 1. "CTX_WR_DATA,Write Data For CTX Input FIFO"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x10)++0x03
line.long 0x00 "RDFIFO[$1],ASRC Output Read FIFO $1"
hexmask.long 0x00 0.--31. 1. "CTX_RD_DATA,Read Data For CTX Output FIFO"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x20)++0x03
line.long 0x00 "CTX_CTRL[$1],ASRC Context Control $1"
bitfld.long 0x00 31. "RUN_EN,Context Run Enable" "0,1"
bitfld.long 0x00 29. "RUN_STOP,Context Run Stop" "0,1"
newline
bitfld.long 0x00 28. "FWMDE,FIFO Watermark DMA Enable" "0: Input DMA Requests Not Enabled for This Context,1: Input DMA Requests Enabled for This Context"
hexmask.long.byte 0x00 16.--22. 1. "FIFO_WTMK,Context Input FIFO Watermark"
newline
bitfld.long 0x00 11.--15. "SAMPLE_POSITION,Sample Position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "BIT_REV,Sample Bit Reversal" "0: Keep Input Ordering,1: Reverse Bit Ordering"
newline
bitfld.long 0x00 8.--9. "BITS_PER_SAMPLE,Number of Bits Per Audio Sample" "0: 16-bits Per Sample,1: 20-bits Per Sample,2: 24-bits Per Sample,3: 32-bits Per Sample"
bitfld.long 0x00 7. "FLOAT_FMT,Context Input Floating Point Format" "0: Integer Format,1: Single Precision Floating Point Format"
newline
bitfld.long 0x00 6. "SIGN_IN,Input Data Sign" "0: Signed Format,1: Unsigned Format"
bitfld.long 0x00 0.--4. "NUM_CH_EN,Number of Channels In Context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x30)++0x03
line.long 0x00 "CTX_CTRL_EXT[$1],ASRC Context Control Extended 1"
bitfld.long 0x00 25. "PF_COEFF_STAGE_WR,Prefilter Coefficient Write Select" "0,1"
bitfld.long 0x00 24. "PF_COEFF_MEM_RST,Prefilter Coefficient Memory Reset" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PF_EXPANSION_FACTOR,Prefilter IFIR Expansion Factor"
bitfld.long 0x00 9. "PF_ST1_WB_FLOAT,Prefilter Stage1 Writeback Floating Point" "0: The pre-filter stage1 results are stored in..,1: The pre-filter stage1 results are stored in.."
newline
bitfld.long 0x00 8. "PF_TWO_STAGE_EN,Prefilter Two-Stage Enable" "0: The pre-filter will run in single stage mode..,1: The pre-filter will run in two stage mode.."
bitfld.long 0x00 7. "RS_BYPASS_MODE,Resampler Bypass Mode" "0: Run the resampler in normal operation,1: Run the resampler in bypass mode"
newline
bitfld.long 0x00 6. "PF_BYPASS_MODE,Prefilter Bypass Mode" "0: Run the prefilter in normal operation,1: Run the prefilter in bypass mode"
bitfld.long 0x00 5. "RS_STOP_MODE,Resampler Stop Mode" "0: Replicate the final prefilter output for the..,1: Zero-Fill the left-half of the resampler on.."
newline
bitfld.long 0x00 4. "PF_STOP_MODE,Pre-Filter Stop Mode" "0: Replicate the last sample input to the..,1: Zero-Fill the left-half of the pre-filter on.."
bitfld.long 0x00 2.--3. "RS_INIT_MODE,Resampler Initialization Mode" "0: Do not pre-fill any resampler taps,1: Replicate the first prefilter output sample..,2: Fill the right half of the re-sampler with..,3: RS_INIT_MODE_3"
newline
bitfld.long 0x00 0.--1. "PF_INIT_MODE,Prefilter Initialization Mode" "0: Do not pre-fill any prefilter taps,1: Replicate the first sample to fill the right..,2: Zero fill the right half of the prefilter,3: PF_INIT_MODE_3"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x40)++0x03
line.long 0x00 "CTX_CTRL_EXT[$1],ASRC Context Control Extended 2"
hexmask.long.word 0x00 16.--24. 1. "ST2_NUM_TAPS,Prefilter Stage2 Number of Taps"
hexmask.long.word 0x00 0.--8. 1. "ST1_NUM_TAPS,Prefilter Stage1 Number of Taps"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x50)++0x03
line.long 0x00 "CTRL_IN_ACCESS[$1],ASRC Control Input Access $1"
bitfld.long 0x00 16.--21. "ITERATIONS,Number of Sequential Fetches Per Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "GROUP_LENGTH,Number of Channels in a Context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "ACCESS_LENGTH,Number Of Channels Per Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x60)++0x03
line.long 0x00 "PROC_CTRL_SLOT0_R[$1],ASRC Datapath Processor Control Slot0 Register0"
bitfld.long 0x00 24.--28. "SLOT0_MAX_CH,SLOT0 Maximum Global Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "SLOT0_MIN_CH,SLOT0 Minimum Global Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "SLOT0_NUM_CH,SLOT0 Number of Channels" "0: Context SLOT0 owns 1 of 8 channels,1: Context SLOT0 owns 2 of 8 channels,2: Context SLOT0 owns 3 of 8 channels,3: Context SLOT0 owns N of 8 channels,4: Context SLOT0 owns N of 8 channels,5: Context SLOT0 owns N of 8 channels,6: Context SLOT0 owns N of 8 channels,7: Context SLOT0 owns N of 8 channels,?..."
bitfld.long 0x00 1.--2. "SLOT0_CTX_NUM,Context SLOT0 Selection" "0,1,2,3"
newline
bitfld.long 0x00 0. "SLOT0_EN,SLOT0 Enable" "0: Context SLOT0 is disabled,1: Context SLOT0 is enabled"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x70)++0x03
line.long 0x00 "PROC_CTRL_SLOT0_R[$1],ASRC Datapath Processor Control Slot0 Register1"
hexmask.long.word 0x00 0.--12. 1. "SLOT0_ST1_CHANxEXP,SLOT0 Stage1 Channels x Expansion Factor"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "PROC_CTRL_SLOT0_R[$1],ASRC Datapath Processor Control Slot0 Register2"
hexmask.long.word 0x00 16.--28. 1. "SLOT0_ST1_MEM_ALLOC,SLOT0 Stage1 Memory Allocation"
hexmask.long.word 0x00 0.--12. 1. "SLOT0_ST1_ST_ADDR,SLOT0 Stage1 Start Address"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x90)++0x03
line.long 0x00 "PROC_CTRL_SLOT0_R[$1],ASRC Datapath Processor Control Slot0 Register3"
hexmask.long.word 0x00 16.--28. 1. "SLOT0_ST2_MEM_ALLOC,SLOT0 Stage2 Memory Allocation"
hexmask.long.word 0x00 0.--12. 1. "SLOT0_ST2_ST_ADDR,SLOT0 Stage2 Start Address"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xA0)++0x03
line.long 0x00 "PROC_CTRL_SLOT1_R[$1],ASRC Datapath Processor Control Slot1 Register0"
bitfld.long 0x00 24.--28. "SLOT1_MAX_CH,Slot1 Maximum Global Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "SLOT1_MIN_CH,Slot1 Minimum Global Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "SLOT1_NUM_CH,SLOT1 Number of Channels" "0: Context SLOT1 owns 1 of 8 channels,1: Context SLOT1 owns 2 of 8 channels,2: Context SLOT1 owns 3 of 8 channels,3: Context SLOT1 owns N of 8 channels,4: Context SLOT1 owns N of 8 channels,5: Context SLOT1 owns N of 8 channels,6: Context SLOT1 owns N of 8 channels,7: Context SLOT1 owns N of 8 channels,?..."
bitfld.long 0x00 1.--2. "SLOT1_CTX_NUM,Context SLOT1 Selection" "0,1,2,3"
newline
bitfld.long 0x00 0. "SLOT1_EN,SLOT1 Enable" "0: Context SLOT1 is disabled,1: Context SLOT1 is enabled"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xB0)++0x03
line.long 0x00 "PROC_CTRL_SLOT1_R[$1],ASRC Datapath Processor Control SLOT1 Register1"
hexmask.long.word 0x00 0.--12. 1. "SLOT1_ST1_CHANxEXP,SLOT1 Stage1 Channels x Expansion Factor"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xC0)++0x03
line.long 0x00 "PROC_CTRL_SLOT1_R[$1],ASRC Datapath Processor Control SLOT1 Register2"
hexmask.long.word 0x00 16.--28. 1. "SLOT1_ST1_MEM_ALLOC,SLOT1 Stage1 Memory Allocation"
hexmask.long.word 0x00 0.--12. 1. "SLOT1_ST1_ST_ADDR,SLOT1 Stage1 Start Address"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xD0)++0x03
line.long 0x00 "PROC_CTRL_SLOT1_R[$1],ASRC Datapath Processor Control SLOT1 Register3"
hexmask.long.word 0x00 16.--28. 1. "SLOT1_ST2_MEM_ALLOC,SLOT1 Stage2 Memory Allocation"
hexmask.long.word 0x00 0.--12. 1. "SLOT1_ST2_ST_ADDR,SLOT1 Stage2 Start Address"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xE0)++0x03
line.long 0x00 "CTX_OUT_CTRL[$1],ASRC Context Output Control $1"
bitfld.long 0x00 28. "FWMDE,Output FIFO Watermark DMA Enable" "0: Output DMA Requests Not Enabled for This..,1: Output DMA Requests Enabled for This Context"
hexmask.long.byte 0x00 16.--22. 1. "FIFO_WTMK,Context Output FIFO Watermark"
newline
bitfld.long 0x00 11.--15. "SAMPLE_POSITION,Sample Position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "BIT_REV,Sample Bit-Reversal" "0: No change,1: Bit-reverse sample data"
newline
bitfld.long 0x00 8.--9. "BITS_PER_SAMPLE,Number of Bits Per Audio Sample" "0: 16-bits Per Sample,1: 20-bits Per Sample,2: 24-bits Per Sample,3: 32-bits Per Sample"
bitfld.long 0x00 7. "FLOAT_FMT,Context Output Floating Point Format" "0: Integer Format,1: Single Precision Floating Point Format"
newline
bitfld.long 0x00 6. "SIGN_OUT,Output Data Sign" "0: Signed Format,1: Convert to Unsigned"
bitfld.long 0x00 2. "IEC_V_DATA,IEC60958 Validity Flag" "0,1"
newline
bitfld.long 0x00 1. "IEC_EN,IEC60958 Bit-Field Insertion Enable" "0: No Data Insertion Enabled,1: IEC60958 Bit-Field Insertion Enabled"
bitfld.long 0x00 0. "DITHER_EN,Output Dither Enable" "0,1"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0xF0)++0x03
line.long 0x00 "CTRL_OUT_ACCESS[$1],ASRC Control Output Access $1"
bitfld.long 0x00 16.--21. "ITERATIONS,Number of Sequential Fetches Per Channel Group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "GROUP_LENGTH,Number of Channels in a Context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "ACCESS_LENGTH,Number Of Channels Per Destination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x100)++0x03
line.long 0x00 "SAMPLE_FIFO_STATUS[$1],ASRC Sample FIFO Status $1"
bitfld.long 0x00 23. "INFIFO_WTMK,Input FIFO Watermark Flag" "0,1"
hexmask.long.byte 0x00 16.--22. 1. "NUM_SAMPLE_GROUPS_IN,Number Of Sample Groups Stored in Input FIFO"
newline
bitfld.long 0x00 7. "OUTFIFO_WTMK,Output FIFO Watermark Flag" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "NUM_SAMPLE_GROUPS_OUT,Number Of Sample Groups Stored in the output FIFO"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x130)++0x03
line.long 0x00 "RS_UPDATE_CTRL[$1],ASRC Resampling Ratio Update Control $1"
hexmask.long 0x00 0.--31. 1. "RS_RATIO_MOD,Resampling Ratio Modifier"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x140)++0x03
line.long 0x00 "RS_UPDATE_RATE[$1],ASRC Resampling Ratio Update Rate $1"
hexmask.long 0x00 0.--30. 1. "RS_RATIO_RAMP_RATE,Resampling Ratio Ramp Rate"
repeat.end
group.long 0x150++0x03
line.long 0x00 "RS_CT_LOW,ASRC Resampling Center Tap Coefficient Low"
hexmask.long 0x00 0.--31. 1. "RS_CT_LOW,Resampling Center Tap Coefficient LSBs"
group.long 0x154++0x03
line.long 0x00 "RS_CT_HIGH,ASRC Resampling Center Tap Coefficient High"
hexmask.long 0x00 0.--31. 1. "RS_CT_HIGH,Resampling Center Tap Coefficient MSBs"
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x160)++0x03
line.long 0x00 "PRE_COEFF_FIFO[$1],ASRC Prefilter Coefficient FIFO $1"
hexmask.long 0x00 0.--31. 1. "COEFF_DATA,Coefficient Value For Prefilter"
repeat.end
wgroup.long 0x170++0x03
line.long 0x00 "CTX_RS_COEFF_MEM,ASRC Context Resampling Coefficient Memory"
hexmask.long 0x00 0.--31. 1. "RS_COEFF_WDATA,Resampling Coefficient Write Data"
group.long 0x174++0x03
line.long 0x00 "CTX_RS_COEFF_CTRL,ASRC Context Resampling Coefficient Control"
hexmask.long.word 0x00 16.--26. 1. "RS_COEFF_ADDR,Resampling Coefficient Address"
bitfld.long 0x00 1.--2. "NUM_RES_TAPS,Number of Resampling Coefficient Taps" "0: 32-Tap Resampling Filter,1: 64-Tap Resampling Filter,2: 128-Tap Resampling Filter,3: NUM_RES_TAPS_3"
newline
bitfld.long 0x00 0. "RS_COEFF_PTR_RST,Resampling Coefficient Write Pointer Reset" "0,1"
group.long 0x178++0x03
line.long 0x00 "IRQ_CTRL,ASRC Interrupt Control"
bitfld.long 0x00 8.--11. "RUN_STOP_DONE_MASK,ASRC RUN STOP DONE MASK" "0: The RUN_STOP_DONE interrupt is enabled for..,1: The RUN_STOP_DONE interrupt is disabled for..,2: The RUN_STOP_DONE interrupt is disabled for..,3: The RUN_STOP_DONE interrupt is enabled for..,4: The RUN_STOP_DONE interrupt is enabled for..,5: The RUN_STOP_DONE interrupt is enabled for..,6: The RUN_STOP_DONE interrupt is enabled for..,7: The RUN_STOP_DONE interrupt is enabled for..,8: The RUN_STOP_DONE interrupt is enabled for..,9: The RUN_STOP_DONE interrupt is enabled for..,?,?,?,?,?,15: The RUN_STOP_DONE interrupt is disabled for.."
bitfld.long 0x00 4.--7. "OUTFIFO_EMPTY_RD_MASK,ASRC Output FIFO Empty Read Mask" "0: The OUTFIFO_EMPTY_RD interrupt is enabled for..,1: The OUTFIFO_EMPTY_RD interrupt is disabled..,2: The OUTFIFO_EMPTY_RD interrupt is disabled..,3: The OUTFIFO_EMPTY_RD interrupt is enabled for..,4: The OUTFIFO_EMPTY_RD interrupt is enabled for..,5: The OUTFIFO_EMPTY_RD interrupt is enabled for..,6: The OUTFIFO_EMPTY_RD interrupt is enabled for..,7: The OUTFIFO_EMPTY_RD interrupt is enabled for..,8: The OUTFIFO_EMPTY_RD interrupt is enabled for..,9: The OUTFIFO_EMPTY_RD interrupt is enabled for..,?,?,?,?,?,15: The OUTFIFO_EMPTY_RD interrupt is disabled.."
newline
bitfld.long 0x00 0.--3. "INFIFO_OVF_MASK,ASRC Input FIFO Overflow Mask" "0: The INFIFO_OVF interrupt is enabled for..,1: The INFIFO_OVF interrupt is disabled for..,2: The INFIFO_OVF interrupt is disabled for..,3: The INFIFO_OVF interrupt is enabled for any..,4: The INFIFO_OVF interrupt is enabled for any..,5: The INFIFO_OVF interrupt is enabled for any..,6: The INFIFO_OVF interrupt is enabled for any..,7: The INFIFO_OVF interrupt is enabled for any..,8: The INFIFO_OVF interrupt is enabled for any..,9: The INFIFO_OVF interrupt is enabled for any..,?,?,?,?,?,15: The INFIFO_OVF interrupt is disabled for.."
group.long 0x17C++0x03
line.long 0x00 "IRQ_FLAGS,ASRC Interrupt Status Flags"
eventfld.long 0x00 8.--11. "RUN_STOP_DONE,ASRC RUN STOP DONE FLAG" "0: No RUN_STOP operations have been completed,1: The RUN_STOP operation for Context 0 has..,2: The RUN_STOP operation for Context 1 has..,3: The RUN_STOP operation has completed for any..,4: The RUN_STOP operation has completed for any..,5: The RUN_STOP operation has completed for any..,6: The RUN_STOP operation has completed for any..,7: The RUN_STOP operation has completed for any..,8: The RUN_STOP operation has completed for any..,9: The RUN_STOP operation has completed for any..,?,?,?,?,?,15: The RUN_STOP operation has completed for.."
eventfld.long 0x00 4.--7. "OUTFIFO_EMPTY_RD,ASRC Output FIFO Empty Read Flag" "0: No reads have been requested from an empty..,1: A read has been requested from ASRC_RDFIFO0..,2: A read has been requested from ASRC_RDFIFO1..,3: A read has been requested from ASRC_RDFIFOn..,4: A read has been requested from ASRC_RDFIFOn..,5: A read has been requested from ASRC_RDFIFOn..,6: A read has been requested from ASRC_RDFIFOn..,7: A read has been requested from ASRC_RDFIFOn..,8: A read has been requested from ASRC_RDFIFOn..,9: A read has been requested from ASRC_RDFIFOn..,?,?,?,?,?,15: A read has been requested from ASRC_RDFIFO0.."
newline
eventfld.long 0x00 0.--3. "INFIFO_OVF,ASRC Input FIFO Overflow Flag" "0: No INFIFO_OVF errors have been recorded,1: The ASRC_WRFIFO0 has overflown,2: The ASRC_WRFIFO1 has overflown,3: The ASRC_WRFIFOn has overflown,4: The ASRC_WRFIFOn has overflown,5: The ASRC_WRFIFOn has overflown,6: The ASRC_WRFIFOn has overflown,7: The ASRC_WRFIFOn has overflown,8: The ASRC_WRFIFOn has overflown,9: The ASRC_WRFIFOn has overflown,?,?,?,?,?,15: ASRC_WRFIFO0 ASRC_WRFIFO1 ASRC_WRFIFO2 and.."
repeat 24. (increment 0 1) (increment 0 0x04)
group.long ($2+0x180)++0x03
line.long 0x00 "CHANNEL_STATUS_[$1],ASRC Channel Status 0"
hexmask.long 0x00 0.--31. 1. "CHN_STAT,Channel Status Data"
repeat.end
repeat 4. (increment 0 1)(increment  0 0x08)
tree "RS_RATIO_LOW[$1]"
group.long ($2+0x110)++0x03
line.long 0x00 "RS_RATIO_LOW,ASRC Resampling Ratio Low"
hexmask.long 0x00 0.--31. 1. "RS_RATIO_LOW,Resampling Ratio Low"
group.long ($2+0x114)++0x03
line.long 0x00 "RS_RATIO_HIGH,ASRC Resampling Ratio High"
rbitfld.long 0x00 31. "RS_RATIO_VLD,Resampling Ratio Valid" "0,1"
hexmask.long.word 0x00 0.--11. 1. "RS_RATIO_HIGH,Resampling Ratio High"
tree.end
repeat.end
tree.end
tree "AUDIOMIX"
base ad:0x30E20000
group.long 0x00++0x03
line.long 0x00 "CLKEN0,IP Clock Enable Control Register 0"
bitfld.long 0x00 31. "EARC,EARC clock enable" "0,1"
bitfld.long 0x00 30. "AudioDSP_DEBUG,AudioDSP DEBUG clock enable" "0,1"
newline
bitfld.long 0x00 29. "AudioDSP,AudioDSP core clock enable" "0,1"
bitfld.long 0x00 28. "SPBA2,SPBA2 clock enable" "0,1"
newline
bitfld.long 0x00 27. "SDMA3,SDMA3 clock enable" "0,1"
bitfld.long 0x00 26. "SDMA2,SDMA2 clock enable" "0,1"
newline
bitfld.long 0x00 25. "PDM,PDM clock enable" "0,1"
bitfld.long 0x00 24. "ASRC,ASRC clock enable" "0,1"
newline
bitfld.long 0x00 23. "SAI7_MCLK3,SAI7 mclk3 clock enable" "0,1"
bitfld.long 0x00 22. "SAI7_MCLK2,SAI7 mclk2 clock enable" "0,1"
newline
bitfld.long 0x00 21. "SAI7_MCLK1,SAI7 mclk1 clock enable" "0,1"
bitfld.long 0x00 20. "SAI7,SAI7 clock enable" "0: SAI7 sai clock disable,1: SAI7 sai clock enable"
newline
bitfld.long 0x00 19. "SAI6_MCLK3,SAI6 mclk3 clock enable" "0,1"
bitfld.long 0x00 18. "SAI6_MCLK2,SAI6 mclk2 clock enable" "0,1"
newline
bitfld.long 0x00 17. "SAI6_MCLK1,SAI6 mclk1 clock enable" "0,1"
bitfld.long 0x00 16. "SAI6,SAI6 clock enable" "0: SAI6 IPG clock disable,1: SAI6 IPG clock enable"
newline
bitfld.long 0x00 15. "SAI5_MCLK3,SAI5 mclk3 clock enable" "0,1"
bitfld.long 0x00 14. "SAI5_MCLK2,SAI5 mclk2 clock enable" "0,1"
newline
bitfld.long 0x00 13. "SAI5_MCLK1,SAI5 mclk1 clock enable" "0,1"
bitfld.long 0x00 12. "SAI5,SAI5 clock enable" "0: SAI5 sai clock disable,1: SAI5 sai clock enable"
newline
bitfld.long 0x00 11. "SAI3_MCLK3,SAI3 mclk3 clock enable" "0,1"
bitfld.long 0x00 10. "SAI3_MCLK2,SAI3 mclk2 clock enable" "0,1"
newline
bitfld.long 0x00 9. "SAI3_MCLK1,SAI3 mclk1 clock enable" "0,1"
bitfld.long 0x00 8. "SAI3,SAI3 clock enable" "0: SAI3 sai clock disable,1: SAI3 sai clock enable"
newline
bitfld.long 0x00 7. "SAI2_MCLK3,SAI2 mclk3 clock enable" "0,1"
bitfld.long 0x00 6. "SAI2_MCLK2,SAI2 mclk2 clock enable" "0,1"
newline
bitfld.long 0x00 5. "SAI2_MCLK1,SAI2 mclk1 clock enable" "0,1"
bitfld.long 0x00 4. "SAI2,SAI2 clock enable" "0: SAI2 sai clock disable,1: SAI2 sai clock enable"
newline
bitfld.long 0x00 3. "SAI1_MCLK3,SAI1 mclk3 clock enable" "0,1"
bitfld.long 0x00 2. "SAI1_MCLK2,SAI1 mclk2 clock enable" "0,1"
newline
bitfld.long 0x00 1. "SAI1_MCLK1,SAI1 mclk1 clock enable" "0,1"
bitfld.long 0x00 0. "SAI1,SAI1 clock enable" "0: SAI1 sai clock disable,1: SAI1 sai clock enable"
group.long 0x04++0x03
line.long 0x00 "CLKEN1,IP Clock Enable Control Register 1"
bitfld.long 0x00 6. "EARC_PHY,EARC PHY audio ss clock enable" "0,1"
bitfld.long 0x00 5. "MU3,MU3 clock enable" "0,1"
newline
bitfld.long 0x00 4. "MU2,MU2 clock enable" "0,1"
bitfld.long 0x00 3. "PLL,PLL clock enable" "0,1"
newline
bitfld.long 0x00 2. "EDMA,EDMA clock enable" "0,1"
bitfld.long 0x00 1. "AUD2HTX,AUDIO LINK MASTER clock enable" "0,1"
newline
bitfld.long 0x00 0. "OCRAM_A,OCRAM_A clock enable" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "AudioDSP_REG0,AudioDSP EXPSTATE Register"
hexmask.long 0x00 0.--31. 1. "EXPSTATE,TIE_EXPSTATE output port of the AudioDSP"
group.long 0x104++0x03
line.long 0x00 "AudioDSP_REG1,AudioDSP IMPWIRE Register"
hexmask.long 0x00 0.--31. 1. "IMPWIRE,TIE_IMPWIRE input port of the AudioDSP"
group.long 0x108++0x03
line.long 0x00 "AudioDSP_REG2,AudioDSP XOCDMODE Register"
bitfld.long 0x00 14. "a53WaitMode,CA53 in Wait Mode for MU2" "0: not in wait mode,1: a53WaitMode_1"
bitfld.long 0x00 13. "a53DsmMode,CA53 in DSM Mode for MU2" "0: not in DSM mode,1: a53DsmMode_1"
newline
bitfld.long 0x00 12. "m7WaitMode,M7 in Wait Mode for MU3" "0: not in wait mode,1: m7WaitMode_1"
bitfld.long 0x00 11. "m7DsmMode,M7 in DSM Mode for MU3" "0: not in DSM mode,1: m7DsmMode_1"
newline
bitfld.long 0x00 10. "WaitMode,AudioDSP in Wait Mode for MU" "0: not in wait mode,1: in wait mode"
bitfld.long 0x00 9. "DsmMode,AudioDSP in DSM Mode for MU" "0: not in DSM mode,1: in DSM mode"
newline
bitfld.long 0x00 8. "AddrMode,AudioDSP Addr Mode(Alias) Register" "0,1"
bitfld.long 0x00 6. "StatVectorSel,Selects between one of two stationary vector bases" "0: StatVectorSel_0,1: StatVectorSel_1"
newline
bitfld.long 0x00 5. "RunStall,AudioDSP RunStall control bit" "?,1: stalls the processor"
bitfld.long 0x00 4. "OCDHALTONRESET,AudioDSP enters OCDHaltMode if this signal is samped asserted on reset" "0,1"
newline
rbitfld.long 0x00 1. "PWAITMODE,Indicates that the AudioDSP is in sleep mode" "0,1"
rbitfld.long 0x00 0. "XOCDMODE,Indicates that the AudioDSP is in OCD halt mode" "0,1"
group.long 0x10C++0x03
line.long 0x00 "AudioDSP_REG3,AudioDSP PID Register"
hexmask.long.word 0x00 0.--15. 1. "PID,AudioDSP PID Register"
group.long 0x200++0x03
line.long 0x00 "EARC,EARC Control Register"
bitfld.long 0x00 1. "PHY_RESETB,Earc PHY Software Reset" "0: provide a software reset for EARC PHY,1: return from reset"
bitfld.long 0x00 0. "RESETB,Earc Software Reset" "0: provide a software reset for EARC controller,1: return from reset"
group.long 0x300++0x03
line.long 0x00 "SAI1_MCLK_SEL,SAI1 MCLK SELECT Register"
bitfld.long 0x00 1.--4. "MCLK2_SEL,MCLK2 Select Register" "0: SAI1_CLK_ROOT is selected,1: SAI2_CLK_ROOT is selected,2: SAI3_CLK_ROOT is selected,?,4: SAI5_CLK_ROOT is selected,5: SAI6_CLK_ROOT is selected,6: SAI7_CLK_ROOT is selected,7: SAI1.MCLK is selected,8: SAI2.MCLK is selected,9: SAI3.MCLK is selected,?,11: SAI5.MCLK is selected,12: SAI6.MCLK is selected,13: SAI7.MCLK is selected,14: SPDIF.ETXCLK is selected,?..."
bitfld.long 0x00 0. "MCLK1_SEL,MCLK1 Select Register" "0: SAI1_CLK_ROOT is selected,1: SAI1.MCLK is selected"
group.long 0x304++0x03
line.long 0x00 "SAI2_MCLK_SEL,SAI2 MCLK SELECT Register"
bitfld.long 0x00 1.--4. "MCLK2_SEL,MCLK2 Select Register" "0: SAI1_CLK_ROOT is selected,1: SAI2_CLK_ROOT is selected,2: SAI3_CLK_ROOT is selected,?,4: SAI5_CLK_ROOT is selected,5: SAI6_CLK_ROOT is selected,6: SAI7_CLK_ROOT is selected,7: SAI1.MCLK is selected,8: SAI2.MCLK is selected,9: SAI3.MCLK is selected,?,11: SAI5.MCLK is selected,12: SAI6.MCLK is selected,13: SAI7.MCLK is selected,14: SPDIF.ETXCLK is selected,?..."
bitfld.long 0x00 0. "MCLK1_SEL,MCLK1 Select Register" "0: SAI2_CLK_ROOT is selected,1: SAI2.MCLK is selected"
group.long 0x308++0x03
line.long 0x00 "SAI3_MCLK_SEL,SAI3 MCLK SELECT Register"
bitfld.long 0x00 1.--4. "MCLK2_SEL,MCLK2 Select Register" "0: SAI1_CLK_ROOT is selected,1: SAI2_CLK_ROOT is selected,2: SAI3_CLK_ROOT is selected,?,4: SAI5_CLK_ROOT is selected,5: SAI6_CLK_ROOT is selected,6: SAI7_CLK_ROOT is selected,7: SAI1.MCLK is selected,8: SAI2.MCLK is selected,9: SAI3.MCLK is selected,?,11: SAI5.MCLK is selected,12: SAI6.MCLK is selected,13: SAI7.MCLK is selected,14: SPDIF.ETXCLK is selected,?..."
bitfld.long 0x00 0. "MCLK1_SEL,MCLK1 Select Register" "0: SAI3_CLK_ROOT is selected,1: SAI3.MCLK is selected"
group.long 0x30C++0x03
line.long 0x00 "SAI5_MCLK_SEL,SAI5 MCLK SELECT Register"
bitfld.long 0x00 1.--4. "MCLK2_SEL,MCLK2 Select Register" "0: SAI1_CLK_ROOT is selected,1: SAI2_CLK_ROOT is selected,2: SAI3_CLK_ROOT is selected,?,4: SAI5_CLK_ROOT is selected,5: SAI6_CLK_ROOT is selected,6: SAI7_CLK_ROOT is selected,7: SAI1.MCLK is selected,8: SAI2.MCLK is selected,9: SAI3.MCLK is selected,?,11: SAI5.MCLK is selected,12: SAI6.MCLK is selected,13: SAI7.MCLK is selected,14: SPDIF.ETXCLK is selected,?..."
bitfld.long 0x00 0. "MCLK1_SEL,MCLK1 Select Register" "0: SAI5_CLK_ROOT is selected,1: SAI5.MCLK is selected"
group.long 0x310++0x03
line.long 0x00 "SAI6_MCLK_SEL,SAI6 MCLK SELECT Register"
bitfld.long 0x00 1.--4. "MCLK2_SEL,MCLK2 Select Register" "0: SAI1_CLK_ROOT is selected,1: SAI2_CLK_ROOT is selected,2: SAI3_CLK_ROOT is selected,?,4: SAI5_CLK_ROOT is selected,5: SAI6_CLK_ROOT is selected,6: SAI7_CLK_ROOT is selected,7: SAI1.MCLK is selected,8: SAI2.MCLK is selected,9: SAI3.MCLK is selected,?,11: SAI5.MCLK is selected,12: SAI6.MCLK is selected,13: SAI7.MCLK is selected,14: SPDIF.ETXCLK is selected,?..."
bitfld.long 0x00 0. "MCLK1_SEL,MCLK1 Select Register" "0: SAI6_CLK_ROOT is selected,1: SAI6.MCLK is selected"
group.long 0x314++0x03
line.long 0x00 "SAI7_MCLK_SEL,SAI7 MCLK SELECT Register"
bitfld.long 0x00 1.--4. "MCLK2_SEL,MCLK2 Select Register" "0: SAI1_CLK_ROOT is selected,1: SAI2_CLK_ROOT is selected,2: SAI3_CLK_ROOT is selected,?,4: SAI5_CLK_ROOT is selected,5: SAI6_CLK_ROOT is selected,6: SAI7_CLK_ROOT is selected,7: SAI1.MCLK is selected,8: SAI2.MCLK is selected,9: SAI3.MCLK is selected,?,11: SAI5.MCLK is selected,12: SAI6.MCLK is selected,13: SAI7.MCLK is selected,14: SPDIF.ETXCLK is selected,?..."
bitfld.long 0x00 0. "MCLK1_SEL,MCLK1 Select Register" "0: SAI7_CLK_ROOT is selected,1: SAI7.MCLK is selected"
group.long 0x318++0x03
line.long 0x00 "PDM_CLK,PDM Root Clock Select Register"
bitfld.long 0x00 0.--1. "select,PDM Root Clock Select Bits" "0: ccm pdm clock is selected,1: sai_pll div2 is selected,2: SAI1_MCLK is selected,?..."
group.long 0x400++0x03
line.long 0x00 "SAI_PLL_GNRL_CTL,SAI PLL General control Register"
rbitfld.long 0x00 31. "lock,pll lock" "0,1"
bitfld.long 0x00 16. "blk_bypass,blk bypass" "0,1"
newline
bitfld.long 0x00 13. "cke,pll cke" "0,1"
bitfld.long 0x00 12. "cke_override,pll cke override" "0,1"
newline
bitfld.long 0x00 9. "resetb,pll resetb" "0,1"
bitfld.long 0x00 8. "resetb_override,resetb override" "0,1"
newline
bitfld.long 0x00 4. "bypass,pll bypass" "0,1"
bitfld.long 0x00 2.--3. "pad_clk_sel,pad clock select" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "ref_clk_sel,reference clock select" "0,1,2,3"
group.long 0x404++0x03
line.long 0x00 "SAI_PLL_FDIV_CTL0,SAI PLL Frequency Divider control Register"
hexmask.long.word 0x00 12.--21. 1. "main_div,main divider value"
bitfld.long 0x00 4.--9. "pre_div,pre divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "post_div,post divider value" "0,1,2,3,4,5,6,7"
group.long 0x408++0x03
line.long 0x00 "SAI_PLL_FDIV_CTL1,SAI PLL DSM value Register"
hexmask.long.word 0x00 0.--15. 1. "dsm,pll DSM(K) value"
group.long 0x40C++0x03
line.long 0x00 "SAI_PLL_SSCG_CTL,SAI PLL SSCG control Register"
bitfld.long 0x00 31. "sscg_en,SSCG Enable Bit" "0,1"
hexmask.long.byte 0x00 12.--19. 1. "mfreq_ctl,pll modulation frequency control"
newline
bitfld.long 0x00 4.--9. "mrat_ctl,pll modulation rate control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "sel_pf,pll modulation method control" "0,1,2,3"
group.long 0x410++0x03
line.long 0x00 "SAI_PLL_MNIT_CTL,SAI PLL SSCG control Register"
bitfld.long 0x00 20. "afc_sel,PLL AFC SEL" "0,1"
bitfld.long 0x00 19. "pbias_ctrl,PLL PBIAS CTRL" "0,1"
newline
bitfld.long 0x00 18. "pbias_ctrl_en,PLL PBIAS CTRL EN" "0,1"
bitfld.long 0x00 17. "afcinit_sel,PLL AFC INIT SEL" "0,1"
newline
bitfld.long 0x00 15. "fsel,PLL FEED SEL control" "0,1"
bitfld.long 0x00 14. "feed_en,PLL FEED Enable control" "0,1"
newline
bitfld.long 0x00 4.--8. "extafc,AFC Enable control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3. "afc_enb,AFC Enable control" "0,1"
newline
bitfld.long 0x00 0.--2. "icp,Charge-pump current control" "0,1,2,3,4,5,6,7"
group.long 0x500++0x03
line.long 0x00 "AUDIO_EXT_ADDR,AUDIOMIX Extra Addr Bits Register"
bitfld.long 0x00 4.--5. "edma,EDMA extra Addr Bits" "0,1,2,3"
bitfld.long 0x00 2.--3. "sdma3,SDMA3 Extra Addr Bits" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "sdma2,SDMA2 Extra Addr Bits" "0,1,2,3"
group.long 0x504++0x03
line.long 0x00 "IPG_LP_CTRL,IPG Low Power Control Register"
rbitfld.long 0x00 19. "sai7_ipg_stop_ack,SAI1 IPG_STOP_ACK Bit" "0,1"
rbitfld.long 0x00 18. "sai6_ipg_stop_ack,SAI6 IPG_STOP_ACK Bit" "0,1"
newline
rbitfld.long 0x00 17. "sai5_ipg_stop_ack,SAI5 IPG_STOP_ACK Bit" "0,1"
rbitfld.long 0x00 16. "sai3_ipg_stop_ack,SAI3 IPG_STOP_ACK Bit" "0,1"
newline
rbitfld.long 0x00 15. "sai2_ipg_stop_ack,SAI2 IPG_STOP_ACK Bit" "0,1"
rbitfld.long 0x00 14. "sai1_ipg_stop_ack,SAI1 IPG_STOP_ACK Bit" "0,1"
newline
rbitfld.long 0x00 13. "pdm_ipg_stop_ack,PDM IPG_STOP_ACK Bit" "0,1"
rbitfld.long 0x00 12. "sdma3_ipg_stop_ack,SDMA3 IPG_STOP_ACK Bit" "0,1"
newline
rbitfld.long 0x00 11. "sdma2_ipg_stop_ack,SDMA2 IPG_STOP_ACK Bit" "0,1"
rbitfld.long 0x00 10. "edma_ipg_stop_ack,EDMA IPG_STOP_ACK Bit" "0,1"
newline
bitfld.long 0x00 9. "sai7_ipg_stop,SAI1 IPG_STOP Bit" "0,1"
bitfld.long 0x00 8. "sai6_ipg_stop,SAI6 IPG_STOP Bit" "0,1"
newline
bitfld.long 0x00 7. "sai5_ipg_stop,SAI5 IPG_STOP Bit" "0,1"
bitfld.long 0x00 6. "sai3_ipg_stop,SAI3 IPG_STOP Bit" "0,1"
newline
bitfld.long 0x00 5. "sai2_ipg_stop,SAI2 IPG_STOP Bit" "0,1"
bitfld.long 0x00 4. "sai1_ipg_stop,SAI1 IPG_STOP Bit" "0,1"
newline
bitfld.long 0x00 3. "pdm_ipg_stop,PDM IPG_STOP Bit" "0,1"
bitfld.long 0x00 2. "sdma3_ipg_stop,SDMA3 IPG_STOP Bit" "0,1"
newline
bitfld.long 0x00 1. "sdma2_ipg_stop,SDMA2 IPG_STOP Bit" "0,1"
bitfld.long 0x00 0. "edma_ipg_stop,EDMA IPG_STOP Bit" "0,1"
group.long 0x508++0x03
line.long 0x00 "AUDIO_AXI_LIMIT,AUDIOMIX AXI LIMIT CTRL Register"
hexmask.long.word 0x00 4.--19. 1. "BEAT_LIMIT,Beat Limit"
bitfld.long 0x00 0. "enable,AXI Limit enable" "0,1"
tree.end
tree "AUDIOPACKETIZER (AudioPacketizer)"
base ad:0x32FDB200
group.byte 0x00++0x00
line.byte 0x00 "aud_n1,Audio Clock Regenerator N Value Register 1 For N expected values refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "AudN,HDMI Audio Clock Regenerator N value"
group.byte 0x01++0x00
line.byte 0x00 "aud_n2,Audio Clock Regenerator N Value Register 2 For N expected values refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "AudN,HDMI Audio Clock Regenerator N value"
group.byte 0x02++0x00
line.byte 0x00 "aud_n3,Audio Clock Regenerator N Value Register 3 For N expected values refer to the HDMI 1"
bitfld.byte 0x00 7. "ncts_atomic_write,When set the new N and CTS values are only used when aud_n1 register is written" "0,1"
bitfld.byte 0x00 0.--3. "AudN,HDMI Audio Clock Regenerator N value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x03++0x00
line.byte 0x00 "aud_cts1,Audio Clock Regenerator CTS Value Register 1 For CTS expected values refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "AudCTS,HDMI Audio Clock Regenerator CTS calculated value"
group.byte 0x04++0x00
line.byte 0x00 "aud_cts2,Audio Clock Regenerator CTS Register 2 For CTS expected values refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "AudCTS,HDMI Audio Clock Regenerator CTS calculated value"
group.byte 0x05++0x00
line.byte 0x00 "aud_cts3,Audio Clock Regenerator CTS value Register 3"
bitfld.byte 0x00 5.--7. "spare,Reserved as spare bit with no associated functionality" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 4. "CTS_manual,If the CTS_manual bit equals 0b this registers contains audCTS[19:0] generated by the Cycle time counter according to the specified timing" "0,1"
newline
bitfld.byte 0x00 0.--3. "AudCTS,HDMI Audio Clock Regenerator CTS calculated value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x06++0x00
line.byte 0x00 "aud_inputclkfs,Audio Input Clock FS Factor Register"
group.byte 0x07++0x00
line.byte 0x00 "aud_cts_dither,Audio CTS Dither Register"
bitfld.byte 0x00 4.--7. "dividend,Dither dividend (4'd1 if no CTS Dither) This field should be configured with the value of dividend from the HDMI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "divisor,Dither divisor (4'd1 if no CTS Dither) This field should be configured with the value of divisor from the HDMI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "AUDIOSAMPLEGP (AudioSampleGP)"
base ad:0x32FDB500
group.byte 0x00++0x00
line.byte 0x00 "gp_conf0,Audio GPA Software FIFO Reset Control Register 0"
bitfld.byte 0x00 0. "sw_audio_fifo_rst,Audio FIFOs software reset - Writing" "0: no action taken - Writing,1: Resets all audio FIFOs Reading from this"
group.byte 0x01++0x00
line.byte 0x00 "gp_conf1,Audio GPA Channel Enable Configuration Register 1"
hexmask.byte 0x00 0.--7. 1. "ch_in_en,Each bit controls the enabling of the respective audio channel"
group.byte 0x02++0x00
line.byte 0x00 "gp_conf2,Audio GPA HBR Enable Register 2"
bitfld.byte 0x00 1. "insert_pcuv,When set (1'b1) this bit enables the insertion of the PCUV (Parity Channel Status User bit and Validity) bits on the incoming audio stream (support limited to Linear PCM audio)" "0,1"
bitfld.byte 0x00 0. "HBR,HBR packets enable" "0,1"
group.byte 0x06++0x00
line.byte 0x00 "gp_mask,Audio GPA FIFO Full and Empty Mask Interrupt Register"
bitfld.byte 0x00 4. "fifo_overrun_mask,FIFO overrun mask" "0,1"
bitfld.byte 0x00 1. "fifo_empty_mask,FIFO empty flag mask" "0,1"
newline
bitfld.byte 0x00 0. "fifo_full_mask,FIFO full flag mask" "0,1"
tree.end
tree "BCH (62BIT Correcting ECC Accelerator)"
base ad:0x33004000
group.long 0x00++0x03
line.long 0x00 "CTRL,Hardware BCH ECC Accelerator Control Register"
bitfld.long 0x00 31. "SFTRST,Set this bit to 0 to enable normal BCH operation" "0: Allow BCH to operate normally,1: Hold BCH in reset"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to 0 for normal operation" "0: Allow BCH to operate normally,1: Do not clock BCH gates in order to minimize.."
newline
hexmask.long.byte 0x00 23.--29. 1. "RSVD5,This field is reserved"
bitfld.long 0x00 22. "DEBUGSYNDROME,(For debug purposes only)" "0,1"
newline
rbitfld.long 0x00 20.--21. "RSVD4,This field is reserved" "0,1,2,3"
bitfld.long 0x00 18.--19. "M2M_LAYOUT,Selects the flash page format for memory-to-memory operations" "0,1,2,3"
newline
bitfld.long 0x00 17. "M2M_ENCODE,Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations" "0,1"
bitfld.long 0x00 16. "M2M_ENABLE,NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION" "0,1"
newline
rbitfld.long 0x00 11.--15. "RSVD3,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "DEBUG_STALL_IRQ_EN," "0,1"
newline
rbitfld.long 0x00 9. "RSVD2,This field is reserved" "0,1"
bitfld.long 0x00 8. "COMPLETE_IRQ_EN," "0,1"
newline
rbitfld.long 0x00 4.--7. "RSVD1,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "BM_ERROR_IRQ,AHB Bus interface Error Interrupt Status" "0,1"
newline
bitfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG STALL Interrupt Status" "0,1"
rbitfld.long 0x00 1. "RSVD0,This field is reserved" "0,1"
newline
bitfld.long 0x00 0. "COMPLETE_IRQ,This bit indicates the state of the external interrupt line" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTRL_SET,Hardware BCH ECC Accelerator Control Register"
bitfld.long 0x00 31. "SFTRST,Set this bit to 0 to enable normal BCH operation" "0: Allow BCH to operate normally,1: Hold BCH in reset"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to 0 for normal operation" "0: Allow BCH to operate normally,1: Do not clock BCH gates in order to minimize.."
newline
hexmask.long.byte 0x00 23.--29. 1. "RSVD5,This field is reserved"
bitfld.long 0x00 22. "DEBUGSYNDROME,(For debug purposes only)" "0,1"
newline
rbitfld.long 0x00 20.--21. "RSVD4,This field is reserved" "0,1,2,3"
bitfld.long 0x00 18.--19. "M2M_LAYOUT,Selects the flash page format for memory-to-memory operations" "0,1,2,3"
newline
bitfld.long 0x00 17. "M2M_ENCODE,Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations" "0,1"
bitfld.long 0x00 16. "M2M_ENABLE,NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION" "0,1"
newline
rbitfld.long 0x00 11.--15. "RSVD3,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "DEBUG_STALL_IRQ_EN," "0,1"
newline
rbitfld.long 0x00 9. "RSVD2,This field is reserved" "0,1"
bitfld.long 0x00 8. "COMPLETE_IRQ_EN," "0,1"
newline
rbitfld.long 0x00 4.--7. "RSVD1,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "BM_ERROR_IRQ,AHB Bus interface Error Interrupt Status" "0,1"
newline
bitfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG STALL Interrupt Status" "0,1"
rbitfld.long 0x00 1. "RSVD0,This field is reserved" "0,1"
newline
bitfld.long 0x00 0. "COMPLETE_IRQ,This bit indicates the state of the external interrupt line" "0,1"
group.long 0x08++0x03
line.long 0x00 "CTRL_CLR,Hardware BCH ECC Accelerator Control Register"
bitfld.long 0x00 31. "SFTRST,Set this bit to 0 to enable normal BCH operation" "0: Allow BCH to operate normally,1: Hold BCH in reset"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to 0 for normal operation" "0: Allow BCH to operate normally,1: Do not clock BCH gates in order to minimize.."
newline
hexmask.long.byte 0x00 23.--29. 1. "RSVD5,This field is reserved"
bitfld.long 0x00 22. "DEBUGSYNDROME,(For debug purposes only)" "0,1"
newline
rbitfld.long 0x00 20.--21. "RSVD4,This field is reserved" "0,1,2,3"
bitfld.long 0x00 18.--19. "M2M_LAYOUT,Selects the flash page format for memory-to-memory operations" "0,1,2,3"
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bitfld.long 0x00 17. "M2M_ENCODE,Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations" "0,1"
bitfld.long 0x00 16. "M2M_ENABLE,NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION" "0,1"
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rbitfld.long 0x00 11.--15. "RSVD3,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "DEBUG_STALL_IRQ_EN," "0,1"
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rbitfld.long 0x00 9. "RSVD2,This field is reserved" "0,1"
bitfld.long 0x00 8. "COMPLETE_IRQ_EN," "0,1"
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rbitfld.long 0x00 4.--7. "RSVD1,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "BM_ERROR_IRQ,AHB Bus interface Error Interrupt Status" "0,1"
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bitfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG STALL Interrupt Status" "0,1"
rbitfld.long 0x00 1. "RSVD0,This field is reserved" "0,1"
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bitfld.long 0x00 0. "COMPLETE_IRQ,This bit indicates the state of the external interrupt line" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CTRL_TOG,Hardware BCH ECC Accelerator Control Register"
bitfld.long 0x00 31. "SFTRST,Set this bit to 0 to enable normal BCH operation" "0: Allow BCH to operate normally,1: Hold BCH in reset"
bitfld.long 0x00 30. "CLKGATE,This bit must be set to 0 for normal operation" "0: Allow BCH to operate normally,1: Do not clock BCH gates in order to minimize.."
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hexmask.long.byte 0x00 23.--29. 1. "RSVD5,This field is reserved"
bitfld.long 0x00 22. "DEBUGSYNDROME,(For debug purposes only)" "0,1"
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rbitfld.long 0x00 20.--21. "RSVD4,This field is reserved" "0,1,2,3"
bitfld.long 0x00 18.--19. "M2M_LAYOUT,Selects the flash page format for memory-to-memory operations" "0,1,2,3"
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bitfld.long 0x00 17. "M2M_ENCODE,Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations" "0,1"
bitfld.long 0x00 16. "M2M_ENABLE,NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION" "0,1"
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rbitfld.long 0x00 11.--15. "RSVD3,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "DEBUG_STALL_IRQ_EN," "0,1"
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rbitfld.long 0x00 9. "RSVD2,This field is reserved" "0,1"
bitfld.long 0x00 8. "COMPLETE_IRQ_EN," "0,1"
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rbitfld.long 0x00 4.--7. "RSVD1,This field is reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "BM_ERROR_IRQ,AHB Bus interface Error Interrupt Status" "0,1"
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bitfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG STALL Interrupt Status" "0,1"
rbitfld.long 0x00 1. "RSVD0,This field is reserved" "0,1"
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bitfld.long 0x00 0. "COMPLETE_IRQ,This bit indicates the state of the external interrupt line" "0,1"
rgroup.long 0x10++0x03
line.long 0x00 "STATUS0,Hardware ECC Accelerator Status Register 0"
hexmask.long.word 0x00 20.--31. 1. "HANDLE,Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction"
bitfld.long 0x00 16.--19. "COMPLETED_CE,This is the chip enable number corresponding to the NAND device from which this data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 8.--15. 1. "STATUS_BLK0,Count of symbols in error during processing of first block of flash (metadata block)"
bitfld.long 0x00 5.--7. "RSVD1,This field is reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ALLONES," "0,1"
bitfld.long 0x00 3. "CORRECTED," "0,1"
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bitfld.long 0x00 2. "UNCORRECTABLE," "0,1"
bitfld.long 0x00 0.--1. "RSVD0,This field is reserved" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "MODE,Hardware ECC Accelerator Mode Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RSVD,This field is reserved"
hexmask.long.byte 0x00 0.--7. 1. "ERASE_THRESHOLD,This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased"
group.long 0x30++0x03
line.long 0x00 "ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register"
hexmask.long 0x00 0.--31. 1. "ADDR,Address pointer to encode buffer"
group.long 0x40++0x03
line.long 0x00 "DATAPTR,Hardware BCH ECC Loopback Data Buffer Register"
hexmask.long 0x00 0.--31. 1. "ADDR,Address pointer to data buffer"
group.long 0x50++0x03
line.long 0x00 "METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register"
hexmask.long 0x00 0.--31. 1. "ADDR,Address pointer to metadata buffer"
group.long 0x70++0x03
line.long 0x00 "LAYOUTSELECT,Hardware ECC Accelerator Layout Select Register"
bitfld.long 0x00 30.--31. "CS15_SELECT,Selects which layout is used for chip select 15" "0,1,2,3"
bitfld.long 0x00 28.--29. "CS14_SELECT,Selects which layout is used for chip select 14" "0,1,2,3"
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bitfld.long 0x00 26.--27. "CS13_SELECT,Selects which layout is used for chip select 13" "0,1,2,3"
bitfld.long 0x00 24.--25. "CS12_SELECT,Selects which layout is used for chip select 12" "0,1,2,3"
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bitfld.long 0x00 22.--23. "CS11_SELECT,Selects which layout is used for chip select 11" "0,1,2,3"
bitfld.long 0x00 20.--21. "CS10_SELECT,Selects which layout is used for chip select 10" "0,1,2,3"
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bitfld.long 0x00 18.--19. "CS9_SELECT,Selects which layout is used for chip select 9" "0,1,2,3"
bitfld.long 0x00 16.--17. "CS8_SELECT,Selects which layout is used for chip select 8" "0,1,2,3"
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bitfld.long 0x00 14.--15. "CS7_SELECT,Selects which layout is used for chip select 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "CS6_SELECT,Selects which layout is used for chip select 6" "0,1,2,3"
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bitfld.long 0x00 10.--11. "CS5_SELECT,Selects which layout is used for chip select 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "CS4_SELECT,Selects which layout is used for chip select 4" "0,1,2,3"
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bitfld.long 0x00 6.--7. "CS3_SELECT,Selects which layout is used for chip select 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "CS2_SELECT,Selects which layout is used for chip select 2" "0,1,2,3"
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bitfld.long 0x00 2.--3. "CS1_SELECT,Selects which layout is used for chip select 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "CS0_SELECT,Selects which layout is used for chip select 0" "0,1,2,3"
group.long 0x80++0x03
line.long 0x00 "FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register"
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,Number of subsequent blocks on the flash page (excluding the data0 block)"
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,Indicates the size of the metadata (in bytes) to be stored on a flash page"
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bitfld.long 0x00 11.--15. "ECC0,Indicates the ECC level for the first block on the flash page" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page"
group.long 0x90++0x03
line.long 0x00 "FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register"
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,Indicates the total size of the flash page (in bytes)"
bitfld.long 0x00 11.--15. "ECCN,Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
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bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page"
group.long 0xA0++0x03
line.long 0x00 "FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register"
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,Number of subsequent blocks on the flash page (excluding the data0 block)"
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,Indicates the size of the metadata (in bytes) to be stored on a flash page"
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bitfld.long 0x00 11.--15. "ECC0,Indicates the ECC level for the first block on the flash page" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page"
group.long 0xB0++0x03
line.long 0x00 "FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register"
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,Indicates the total size of the flash page (in bytes)"
bitfld.long 0x00 11.--15. "ECCN,Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
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bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page"
group.long 0xC0++0x03
line.long 0x00 "FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register"
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,Number of subsequent blocks on the flash page (excluding the data0 block)"
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,Indicates the size of the metadata (in bytes) to be stored on a flash page"
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bitfld.long 0x00 11.--15. "ECC0,Indicates the ECC level for the first block on the flash page" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page"
group.long 0xD0++0x03
line.long 0x00 "FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register"
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,Indicates the total size of the flash page (in bytes)"
bitfld.long 0x00 11.--15. "ECCN,Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
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bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page"
group.long 0xE0++0x03
line.long 0x00 "FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register"
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,Number of subsequent blocks on the flash page (excluding the data0 block)"
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,Indicates the size of the metadata (in bytes) to be stored on a flash page"
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bitfld.long 0x00 11.--15. "ECC0,Indicates the ECC level for the first block on the flash page" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page"
group.long 0xF0++0x03
line.long 0x00 "FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register"
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,Indicates the total size of the flash page (in bytes)"
bitfld.long 0x00 11.--15. "ECCN,Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n)" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
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bitfld.long 0x00 10. "GF13_0_GF14_1,Select GF13 or GF14: 0-GF13 1-GF14" "0,1"
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page"
group.long 0x100++0x03
line.long 0x00 "DEBUG0,Hardware BCH ECC Debug Register0"
hexmask.long.byte 0x00 25.--31. 1. "RSVD1,This field is reserved"
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled"
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bitfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine" "0,1"
bitfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input payload flag" "?,1: Payload is set for 512 bytes data block"
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bitfld.long 0x00 13. "KES_DEBUG_MODE4K,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)" "?,1: Mode is set for 4K NAND pages"
bitfld.long 0x00 12. "KES_DEBUG_KICK,Toggling causes KES engine FSM to start as if kick by the Bus Master" "0,1"
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bitfld.long 0x00 11. "KES_STANDALONE,Set to one cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine" "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
bitfld.long 0x00 10. "KES_DEBUG_STEP,Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block" "0,1"
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bitfld.long 0x00 9. "KES_DEBUG_STALL,Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete" "0: KES FSM proceeds to next block supplied by..,1: KES FSM waits after current equations are.."
bitfld.long 0x00 8. "BM_KES_TEST_BYPASS," "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
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rbitfld.long 0x00 6.--7. "RSVD0,This field is reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "DEBUG_REG_SELECT,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x104++0x03
line.long 0x00 "DEBUG0_SET,Hardware BCH ECC Debug Register0"
hexmask.long.byte 0x00 25.--31. 1. "RSVD1,This field is reserved"
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled"
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bitfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine" "0,1"
bitfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input payload flag" "?,1: Payload is set for 512 bytes data block"
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bitfld.long 0x00 13. "KES_DEBUG_MODE4K,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)" "?,1: Mode is set for 4K NAND pages"
bitfld.long 0x00 12. "KES_DEBUG_KICK,Toggling causes KES engine FSM to start as if kick by the Bus Master" "0,1"
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bitfld.long 0x00 11. "KES_STANDALONE,Set to one cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine" "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
bitfld.long 0x00 10. "KES_DEBUG_STEP,Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block" "0,1"
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bitfld.long 0x00 9. "KES_DEBUG_STALL,Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete" "0: KES FSM proceeds to next block supplied by..,1: KES FSM waits after current equations are.."
bitfld.long 0x00 8. "BM_KES_TEST_BYPASS," "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
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rbitfld.long 0x00 6.--7. "RSVD0,This field is reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "DEBUG_REG_SELECT,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x108++0x03
line.long 0x00 "DEBUG0_CLR,Hardware BCH ECC Debug Register0"
hexmask.long.byte 0x00 25.--31. 1. "RSVD1,This field is reserved"
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled"
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bitfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine" "0,1"
bitfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input payload flag" "?,1: Payload is set for 512 bytes data block"
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bitfld.long 0x00 13. "KES_DEBUG_MODE4K,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)" "?,1: Mode is set for 4K NAND pages"
bitfld.long 0x00 12. "KES_DEBUG_KICK,Toggling causes KES engine FSM to start as if kick by the Bus Master" "0,1"
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bitfld.long 0x00 11. "KES_STANDALONE,Set to one cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine" "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
bitfld.long 0x00 10. "KES_DEBUG_STEP,Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block" "0,1"
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bitfld.long 0x00 9. "KES_DEBUG_STALL,Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete" "0: KES FSM proceeds to next block supplied by..,1: KES FSM waits after current equations are.."
bitfld.long 0x00 8. "BM_KES_TEST_BYPASS," "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
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rbitfld.long 0x00 6.--7. "RSVD0,This field is reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "DEBUG_REG_SELECT,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10C++0x03
line.long 0x00 "DEBUG0_TOG,Hardware BCH ECC Debug Register0"
hexmask.long.byte 0x00 25.--31. 1. "RSVD1,This field is reserved"
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled"
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bitfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine" "0,1"
bitfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input payload flag" "?,1: Payload is set for 512 bytes data block"
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bitfld.long 0x00 13. "KES_DEBUG_MODE4K,When running the stand alone debug mode on the error calculator the state of this bit is presented to the KES engine as the input mode (4K or 2K pages)" "?,1: Mode is set for 4K NAND pages"
bitfld.long 0x00 12. "KES_DEBUG_KICK,Toggling causes KES engine FSM to start as if kick by the Bus Master" "0,1"
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bitfld.long 0x00 11. "KES_STANDALONE,Set to one cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine" "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
bitfld.long 0x00 10. "KES_DEBUG_STEP,Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block" "0,1"
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bitfld.long 0x00 9. "KES_DEBUG_STALL,Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete" "0: KES FSM proceeds to next block supplied by..,1: KES FSM waits after current equations are.."
bitfld.long 0x00 8. "BM_KES_TEST_BYPASS," "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
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rbitfld.long 0x00 6.--7. "RSVD0,This field is reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "DEBUG_REG_SELECT,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x110++0x03
line.long 0x00 "DBGKESREAD,KES Debug Read Register"
hexmask.long 0x00 0.--31. 1. "VALUES,This register returns the ROM BIST CRC value after a BIST test"
rgroup.long 0x120++0x03
line.long 0x00 "DBGCSFEREAD,Chien Search Debug Read Register"
hexmask.long 0x00 0.--31. 1. "VALUES,Reserved"
rgroup.long 0x130++0x03
line.long 0x00 "DBGSYNDGENREAD,Syndrome Generator Debug Read Register"
hexmask.long 0x00 0.--31. 1. "VALUES,Reserved"
rgroup.long 0x140++0x03
line.long 0x00 "DBGAHBMREAD,Bus Master and ECC Controller Debug Read Register"
hexmask.long 0x00 0.--31. 1. "VALUES,Reserved"
rgroup.long 0x150++0x03
line.long 0x00 "BLOCKNAME,Block Name Register"
hexmask.long 0x00 0.--31. 1. "NAME,The name is in the ASCII characters BCH (0x20 H C B)"
rgroup.long 0x160++0x03
line.long 0x00 "VERSION,BCH Version Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value indicates the MAJOR field of the RTL version"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value indicates the MINOR field of the RTL version"
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hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the RTL version"
group.long 0x170++0x03
line.long 0x00 "DEBUG1,Hardware BCH ECC Debug Register 1"
bitfld.long 0x00 31. "DEBUG1_PREERASECHK,Blank page enables pre-erase check" "0: Turn off pre-erase check,1: Turn on pre-erase check"
hexmask.long.tbyte 0x00 9.--30. 1. "RSVD,This field is reserved"
newline
hexmask.long.word 0x00 0.--8. 1. "ERASED_ZERO_COUNT,The zero counts on one page"
tree.end
tree "CAN"
repeat 2. (list 1. 2.) (list ad:0x308C0000 ad:0x308D0000)
tree "FLEXCAN$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MCR,Module Configuration register"
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable the FlexCAN module,1: Disable the FlexCAN module"
bitfld.long 0x00 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode"
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bitfld.long 0x00 29. "RFEN,Rx FIFO Enable" "0: Rx FIFO not enabled,1: Rx FIFO enabled"
bitfld.long 0x00 28. "HALT,Halt FlexCAN" "0: No Freeze mode request,1: Enters Freeze mode if the FRZ bit is asserted"
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rbitfld.long 0x00 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN module is either in Normal mode..,1: FlexCAN module is either in Disable mode Doze.."
bitfld.long 0x00 26. "WAKMSK,Wake Up Interrupt Mask" "0: Wake Up interrupt is disabled,1: Wake Up interrupt is enabled"
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bitfld.long 0x00 25. "SOFTRST,Soft Reset" "0: SOFTRST_no_reset_request,1: Resets the registers affected by soft reset"
rbitfld.long 0x00 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running,1: FlexCAN in Freeze mode prescaler stopped"
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bitfld.long 0x00 23. "SUPV,Supervisor Mode" "0: FlexCAN is in User mode,1: FlexCAN is in Supervisor mode"
bitfld.long 0x00 22. "SLFWAK,Self Wake Up" "0: FlexCAN Self Wake Up feature is disabled,1: FlexCAN Self Wake Up feature is enabled"
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bitfld.long 0x00 21. "WRNEN,Warning Interrupt Enable" "0: TWRNINT and RWRNINT bits are zero independent..,1: TWRNINT and RWRNINT bits are set when the.."
rbitfld.long 0x00 20. "LPMACK,Low-Power Mode Acknowledge" "0: FlexCAN is not in a low-power mode,1: FlexCAN is in a low-power mode"
newline
bitfld.long 0x00 19. "WAKSRC,Wake Up Source" "0: FlexCAN uses the unfiltered Rx input to..,1: FlexCAN uses the filtered Rx input to detect.."
bitfld.long 0x00 18. "DOZE,Doze Mode Enable" "0: FlexCAN is not enabled to enter low-power..,1: FlexCAN is enabled to enter low-power mode.."
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bitfld.long 0x00 17. "SRXDIS,Self Reception Disable" "0: Self-reception enabled,1: Self-reception disabled"
bitfld.long 0x00 16. "IRMQ,Individual Rx Masking And Queue Enable" "0: Individual Rx masking and queue feature are..,1: Individual Rx masking and queue feature are.."
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bitfld.long 0x00 15. "DMA,DMA Enable" "0: DMA feature for RX FIFO disabled,1: DMA feature for RX FIFO enabled"
bitfld.long 0x00 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled,1: Local Priority enabled"
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bitfld.long 0x00 12. "AEN,Abort Enable" "0: Abort disabled,1: Abort enabled"
bitfld.long 0x00 11. "FDEN,CAN FD operation enable" "0: CAN FD is disabled,1: CAN FD is enabled"
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bitfld.long 0x00 8.--9. "IDAM,ID Acceptance Mode" "0: Format A,1: Format B,2: Format C,3: Format D"
hexmask.long.byte 0x00 0.--6. 1. "MAXMB,Number Of The Last Message Buffer"
group.long 0x04++0x03
line.long 0x00 "CTRL1,Control 1 register"
hexmask.long.byte 0x00 24.--31. 1. "PRESDIV,Prescaler Division Factor"
bitfld.long 0x00 22.--23. "RJW,Resync Jump Width" "0,1,2,3"
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bitfld.long 0x00 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled,1: Bus Off interrupt enabled"
bitfld.long 0x00 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled,1: Error interrupt enabled"
newline
bitfld.long 0x00 13. "CLKSRC,CAN Engine Clock Source" "0: The CAN engine clock source is the oscillator..,1: The CAN engine clock source is the peripheral.."
bitfld.long 0x00 12. "LPB,Loop Back Mode" "0: Loop Back disabled,1: Loop Back enabled"
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bitfld.long 0x00 11. "TWRNMSK,Tx Warning Interrupt Mask" "0: Tx Warning interrupt disabled,1: Tx Warning interrupt enabled"
bitfld.long 0x00 10. "RWRNMSK,Rx Warning Interrupt Mask" "0: Rx Warning interrupt disabled,1: Rx Warning interrupt enabled"
newline
bitfld.long 0x00 7. "SMP,CAN Bit Sampling" "0: Just one sample is used to determine the bit..,1: Three samples are used to determine the value.."
bitfld.long 0x00 6. "BOFFREC,Bus Off Recovery" "0: Automatic recovering from Bus Off state enabled,1: Automatic recovering from Bus Off state.."
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bitfld.long 0x00 5. "TSYN,Timer Sync" "0: Timer sync feature disabled,1: Timer sync feature enabled"
bitfld.long 0x00 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted..,1: Lowest number buffer is transmitted first"
newline
bitfld.long 0x00 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated,1: FlexCAN module operates in Listen-Only mode"
bitfld.long 0x00 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "TIMER,Free Running Timer"
hexmask.long.word 0x00 0.--15. 1. "TIMER,Timer Value"
group.long 0x10++0x03
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask register"
hexmask.long 0x00 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits"
group.long 0x14++0x03
line.long 0x00 "RX14MASK,Rx 14 Mask register"
hexmask.long 0x00 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits"
group.long 0x18++0x03
line.long 0x00 "RX15MASK,Rx 15 Mask register"
hexmask.long 0x00 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits"
group.long 0x1C++0x03
line.long 0x00 "ECR,Error Counter"
hexmask.long.byte 0x00 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits"
hexmask.long.byte 0x00 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits"
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hexmask.long.byte 0x00 8.--15. 1. "RXERRCNT,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TXERRCNT,Transmit Error Counter"
group.long 0x20++0x03
line.long 0x00 "ESR1,Error and Status 1 register"
rbitfld.long 0x00 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as recessive is.."
rbitfld.long 0x00 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as dominant is received.."
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rbitfld.long 0x00 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A CRC error occurred since last read of this.."
rbitfld.long 0x00 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A form error occurred since last read of this.."
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rbitfld.long 0x00 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A stuffing error occurred since last read of.."
eventfld.long 0x00 21. "ERROVR,Error Overrun" "0: Overrun has not occurred,1: Overrun has occurred"
newline
eventfld.long 0x00 20. "ERRINT_FAST,Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set" "0: errors_data_phase_no,1: Indicates setting of any error bit detected.."
eventfld.long 0x00 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence,1: FlexCAN module has completed Bus Off process"
newline
rbitfld.long 0x00 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus,1: FlexCAN is synchronized to the CAN bus"
eventfld.long 0x00 17. "TWRNINT,Tx Warning Interrupt Flag" "0: No such occurrence,1: The Tx error counter transitioned from less.."
newline
eventfld.long 0x00 16. "RWRNINT,Rx Warning Interrupt Flag" "0: No such occurrence,1: The Rx error counter transitioned from less.."
rbitfld.long 0x00 15. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: At least one bit sent as recessive is.."
newline
rbitfld.long 0x00 14. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: At least one bit sent as dominant is received.."
rbitfld.long 0x00 13. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An ACK error occurred since last read of this.."
newline
rbitfld.long 0x00 12. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error occurred since last read of this.."
rbitfld.long 0x00 11. "FRMERR,Form Error" "0: No such occurrence,1: A Form Error occurred since last read of this.."
newline
rbitfld.long 0x00 10. "STFERR,Stuffing Error" "0: No such occurrence,1: A stuffing error occurred since last read of.."
rbitfld.long 0x00 9. "TXWRN,TX Error Warning" "0: No such occurrence,1: TXERRCNT is greater than or equal to 96"
newline
rbitfld.long 0x00 8. "RXWRN,Rx Error Warning" "0: No such occurrence,1: RXERRCNT is greater than or equal to 96"
rbitfld.long 0x00 7. "IDLE,IDLE" "0: No such occurrence,1: CAN bus is now IDLE"
newline
rbitfld.long 0x00 6. "TX,FlexCAN In Transmission" "0: FlexCAN is not transmitting a message,1: FlexCAN is transmitting a message"
rbitfld.long 0x00 4.--5. "FLTCONF,Fault Confinement State" "0: error_active,1: error_passive,2: bus_off,3: bus_off"
newline
rbitfld.long 0x00 3. "RX,FlexCAN In Reception" "0: FlexCAN is not receiving a message,1: FlexCAN is receiving a message"
eventfld.long 0x00 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence,1: FlexCAN module entered Bus Off state"
newline
eventfld.long 0x00 1. "ERRINT,Error Interrupt" "0: No such occurrence,1: Indicates setting of any error bit in the.."
eventfld.long 0x00 0. "WAKINT,Wake-Up Interrupt" "0: No such occurrence,1: Indicates a recessive to dominant transition.."
group.long 0x24++0x03
line.long 0x00 "IMASK2,Interrupt Masks 2 register"
hexmask.long 0x00 0.--31. 1. "BUF63TO32M,Buffer MBi Mask"
group.long 0x28++0x03
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
hexmask.long 0x00 0.--31. 1. "BUF31TO0M,Buffer MBi Mask"
group.long 0x2C++0x03
line.long 0x00 "IFLAG2,Interrupt Flags 2 register"
hexmask.long 0x00 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt"
group.long 0x30++0x03
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
hexmask.long.tbyte 0x00 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt"
eventfld.long 0x00 7. "BUF7I,Buffer MB7 Interrupt Or Rx FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.."
newline
eventfld.long 0x00 6. "BUF6I,Buffer MB6 Interrupt Or Rx FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.."
eventfld.long 0x00 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Rx FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.."
newline
eventfld.long 0x00 1.--4. "BUF4TO1I,Buffer MBi Interrupt Or Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
eventfld.long 0x00 0. "BUF0I,Buffer MB0 Interrupt Or Clear FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.."
group.long 0x34++0x03
line.long 0x00 "CTRL2,Control 2 register"
bitfld.long 0x00 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames" "0: ERRINT_FAST error interrupt disabled,1: ERRINT_FAST error interrupt enabled"
bitfld.long 0x00 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus off done interrupt disabled,1: Bus off done interrupt enabled"
newline
bitfld.long 0x00 29. "ECRWRE,Error-correction Configuration Register Write Enable" "0: Disable update,1: Enable update"
bitfld.long 0x00 28. "WRMFRZ,Write-Access To Memory In Freeze Mode" "0: Maintain the write access restrictions,1: Enable unrestricted write access to FlexCAN.."
newline
bitfld.long 0x00 24.--27. "RFFN,Number Of Rx FIFO Filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19.--23. "TASD,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Rx FIFO or Enhanced Rx..,1: Matching starts from mailboxes and continues.."
bitfld.long 0x00 17. "RRS,Remote Request Storing" "0: remote_response_frame_not_generated,1: remote_response_frame_generated"
newline
bitfld.long 0x00 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "0: Rx mailbox filter's IDE bit is always..,1: Enables the comparison of both Rx mailbox.."
bitfld.long 0x00 15. "TIMER_SRC,Timer Source" "0: The free running timer is clocked by the CAN..,1: The free running timer is clocked by an.."
newline
bitfld.long 0x00 14. "PREXCEN,Protocol Exception Enable" "0: Protocol exception is disabled,1: Protocol exception is enabled"
bitfld.long 0x00 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD.."
newline
bitfld.long 0x00 11. "EDFLTDIS,Edge Filter Disable" "0: Edge filter is enabled,1: Edge filter is disabled"
rgroup.long 0x38++0x03
line.long 0x00 "ESR2,Error and Status 2 register"
hexmask.long.byte 0x00 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox"
bitfld.long 0x00 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid,1: Contents of IMB and LPTM are valid"
newline
bitfld.long 0x00 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is..,1: If ESR2[VPS] is asserted there is at least.."
rgroup.long 0x44++0x03
line.long 0x00 "CRCR,CRC register"
hexmask.long.byte 0x00 16.--22. 1. "MBCRC,CRC Mailbox"
hexmask.long.word 0x00 0.--14. 1. "TXCRC,Transmitted CRC value"
group.long 0x48++0x03
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
hexmask.long 0x00 0.--31. 1. "FGM,Rx FIFO Global Mask Bits"
rgroup.long 0x4C++0x03
line.long 0x00 "RXFIR,Rx FIFO Information register"
hexmask.long.word 0x00 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator"
group.long 0x50++0x03
line.long 0x00 "CBT,CAN Bit Timing register"
bitfld.long 0x00 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled,1: Extended bit time definitions enabled"
hexmask.long.word 0x00 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor"
newline
bitfld.long 0x00 16.--20. "ERJW,Extended Resync Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--15. "EPROPSEG,Extended Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 5.--9. "EPSEG1,Extended Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "EPSEG2,Extended Phase Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80++0x03
line.long 0x00 "MB0_CS,Message Buffer 0 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x84++0x03
line.long 0x00 "MB0_ID,Message Buffer 0 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x88++0x03
line.long 0x00 "MB0_WORD0,Message Buffer 0 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x8C++0x03
line.long 0x00 "MB0_WORD1,Message Buffer 0 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x90++0x03
line.long 0x00 "MB1_CS,Message Buffer 1 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x94++0x03
line.long 0x00 "MB1_ID,Message Buffer 1 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x98++0x03
line.long 0x00 "MB1_WORD0,Message Buffer 1 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x9C++0x03
line.long 0x00 "MB1_WORD1,Message Buffer 1 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0xA0++0x03
line.long 0x00 "MB2_CS,Message Buffer 2 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0xA4++0x03
line.long 0x00 "MB2_ID,Message Buffer 2 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0xA8++0x03
line.long 0x00 "MB2_WORD0,Message Buffer 2 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0xAC++0x03
line.long 0x00 "MB2_WORD1,Message Buffer 2 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0xB0++0x03
line.long 0x00 "MB3_CS,Message Buffer 3 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0xB4++0x03
line.long 0x00 "MB3_ID,Message Buffer 3 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0xB8++0x03
line.long 0x00 "MB3_WORD0,Message Buffer 3 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0xBC++0x03
line.long 0x00 "MB3_WORD1,Message Buffer 3 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0xC0++0x03
line.long 0x00 "MB4_CS,Message Buffer 4 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0xC4++0x03
line.long 0x00 "MB4_ID,Message Buffer 4 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0xC8++0x03
line.long 0x00 "MB4_WORD0,Message Buffer 4 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0xCC++0x03
line.long 0x00 "MB4_WORD1,Message Buffer 4 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0xD0++0x03
line.long 0x00 "MB5_CS,Message Buffer 5 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0xD4++0x03
line.long 0x00 "MB5_ID,Message Buffer 5 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0xD8++0x03
line.long 0x00 "MB5_WORD0,Message Buffer 5 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0xDC++0x03
line.long 0x00 "MB5_WORD1,Message Buffer 5 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0xE0++0x03
line.long 0x00 "MB6_CS,Message Buffer 6 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0xE4++0x03
line.long 0x00 "MB6_ID,Message Buffer 6 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0xE8++0x03
line.long 0x00 "MB6_WORD0,Message Buffer 6 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0xEC++0x03
line.long 0x00 "MB6_WORD1,Message Buffer 6 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0xF0++0x03
line.long 0x00 "MB7_CS,Message Buffer 7 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0xF4++0x03
line.long 0x00 "MB7_ID,Message Buffer 7 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0xF8++0x03
line.long 0x00 "MB7_WORD0,Message Buffer 7 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0xFC++0x03
line.long 0x00 "MB7_WORD1,Message Buffer 7 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x100++0x03
line.long 0x00 "MB8_CS,Message Buffer 8 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x104++0x03
line.long 0x00 "MB8_ID,Message Buffer 8 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x108++0x03
line.long 0x00 "MB8_WORD0,Message Buffer 8 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x10C++0x03
line.long 0x00 "MB8_WORD1,Message Buffer 8 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x110++0x03
line.long 0x00 "MB9_CS,Message Buffer 9 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x114++0x03
line.long 0x00 "MB9_ID,Message Buffer 9 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x118++0x03
line.long 0x00 "MB9_WORD0,Message Buffer 9 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x11C++0x03
line.long 0x00 "MB9_WORD1,Message Buffer 9 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x120++0x03
line.long 0x00 "MB10_CS,Message Buffer 10 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x124++0x03
line.long 0x00 "MB10_ID,Message Buffer 10 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x128++0x03
line.long 0x00 "MB10_WORD0,Message Buffer 10 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x12C++0x03
line.long 0x00 "MB10_WORD1,Message Buffer 10 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x130++0x03
line.long 0x00 "MB11_CS,Message Buffer 11 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x134++0x03
line.long 0x00 "MB11_ID,Message Buffer 11 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x138++0x03
line.long 0x00 "MB11_WORD0,Message Buffer 11 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x13C++0x03
line.long 0x00 "MB11_WORD1,Message Buffer 11 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x140++0x03
line.long 0x00 "MB12_CS,Message Buffer 12 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x144++0x03
line.long 0x00 "MB12_ID,Message Buffer 12 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x148++0x03
line.long 0x00 "MB12_WORD0,Message Buffer 12 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x14C++0x03
line.long 0x00 "MB12_WORD1,Message Buffer 12 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x150++0x03
line.long 0x00 "MB13_CS,Message Buffer 13 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x154++0x03
line.long 0x00 "MB13_ID,Message Buffer 13 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x158++0x03
line.long 0x00 "MB13_WORD0,Message Buffer 13 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x15C++0x03
line.long 0x00 "MB13_WORD1,Message Buffer 13 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x160++0x03
line.long 0x00 "MB14_CS,Message Buffer 14 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x164++0x03
line.long 0x00 "MB14_ID,Message Buffer 14 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x168++0x03
line.long 0x00 "MB14_WORD0,Message Buffer 14 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x16C++0x03
line.long 0x00 "MB14_WORD1,Message Buffer 14 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x170++0x03
line.long 0x00 "MB15_CS,Message Buffer 15 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x174++0x03
line.long 0x00 "MB15_ID,Message Buffer 15 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x178++0x03
line.long 0x00 "MB15_WORD0,Message Buffer 15 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x17C++0x03
line.long 0x00 "MB15_WORD1,Message Buffer 15 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x180++0x03
line.long 0x00 "MB16_CS,Message Buffer 16 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x184++0x03
line.long 0x00 "MB16_ID,Message Buffer 16 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x188++0x03
line.long 0x00 "MB16_WORD0,Message Buffer 16 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x18C++0x03
line.long 0x00 "MB16_WORD1,Message Buffer 16 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x190++0x03
line.long 0x00 "MB17_CS,Message Buffer 17 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x194++0x03
line.long 0x00 "MB17_ID,Message Buffer 17 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x198++0x03
line.long 0x00 "MB17_WORD0,Message Buffer 17 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x19C++0x03
line.long 0x00 "MB17_WORD1,Message Buffer 17 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x1A0++0x03
line.long 0x00 "MB18_CS,Message Buffer 18 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x1A4++0x03
line.long 0x00 "MB18_ID,Message Buffer 18 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x1A8++0x03
line.long 0x00 "MB18_WORD0,Message Buffer 18 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x1AC++0x03
line.long 0x00 "MB18_WORD1,Message Buffer 18 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x1B0++0x03
line.long 0x00 "MB19_CS,Message Buffer 19 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x1B4++0x03
line.long 0x00 "MB19_ID,Message Buffer 19 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x1B8++0x03
line.long 0x00 "MB19_WORD0,Message Buffer 19 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x1BC++0x03
line.long 0x00 "MB19_WORD1,Message Buffer 19 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x1C0++0x03
line.long 0x00 "MB20_CS,Message Buffer 20 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x1C4++0x03
line.long 0x00 "MB20_ID,Message Buffer 20 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x1C8++0x03
line.long 0x00 "MB20_WORD0,Message Buffer 20 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x1CC++0x03
line.long 0x00 "MB20_WORD1,Message Buffer 20 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x1D0++0x03
line.long 0x00 "MB21_CS,Message Buffer 21 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x1D4++0x03
line.long 0x00 "MB21_ID,Message Buffer 21 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x1D8++0x03
line.long 0x00 "MB21_WORD0,Message Buffer 21 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x1DC++0x03
line.long 0x00 "MB21_WORD1,Message Buffer 21 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x1E0++0x03
line.long 0x00 "MB22_CS,Message Buffer 22 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x1E4++0x03
line.long 0x00 "MB22_ID,Message Buffer 22 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x1E8++0x03
line.long 0x00 "MB22_WORD0,Message Buffer 22 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x1EC++0x03
line.long 0x00 "MB22_WORD1,Message Buffer 22 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x1F0++0x03
line.long 0x00 "MB23_CS,Message Buffer 23 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x1F4++0x03
line.long 0x00 "MB23_ID,Message Buffer 23 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x1F8++0x03
line.long 0x00 "MB23_WORD0,Message Buffer 23 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x1FC++0x03
line.long 0x00 "MB23_WORD1,Message Buffer 23 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x200++0x03
line.long 0x00 "MB24_CS,Message Buffer 24 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x204++0x03
line.long 0x00 "MB24_ID,Message Buffer 24 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x208++0x03
line.long 0x00 "MB24_WORD0,Message Buffer 24 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x20C++0x03
line.long 0x00 "MB24_WORD1,Message Buffer 24 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x210++0x03
line.long 0x00 "MB25_CS,Message Buffer 25 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x214++0x03
line.long 0x00 "MB25_ID,Message Buffer 25 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x218++0x03
line.long 0x00 "MB25_WORD0,Message Buffer 25 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x21C++0x03
line.long 0x00 "MB25_WORD1,Message Buffer 25 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x220++0x03
line.long 0x00 "MB26_CS,Message Buffer 26 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x224++0x03
line.long 0x00 "MB26_ID,Message Buffer 26 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x228++0x03
line.long 0x00 "MB26_WORD0,Message Buffer 26 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x22C++0x03
line.long 0x00 "MB26_WORD1,Message Buffer 26 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x230++0x03
line.long 0x00 "MB27_CS,Message Buffer 27 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x234++0x03
line.long 0x00 "MB27_ID,Message Buffer 27 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x238++0x03
line.long 0x00 "MB27_WORD0,Message Buffer 27 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x23C++0x03
line.long 0x00 "MB27_WORD1,Message Buffer 27 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x240++0x03
line.long 0x00 "MB28_CS,Message Buffer 28 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x244++0x03
line.long 0x00 "MB28_ID,Message Buffer 28 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x248++0x03
line.long 0x00 "MB28_WORD0,Message Buffer 28 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x24C++0x03
line.long 0x00 "MB28_WORD1,Message Buffer 28 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x250++0x03
line.long 0x00 "MB29_CS,Message Buffer 29 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x254++0x03
line.long 0x00 "MB29_ID,Message Buffer 29 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x258++0x03
line.long 0x00 "MB29_WORD0,Message Buffer 29 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x25C++0x03
line.long 0x00 "MB29_WORD1,Message Buffer 29 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x260++0x03
line.long 0x00 "MB30_CS,Message Buffer 30 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x264++0x03
line.long 0x00 "MB30_ID,Message Buffer 30 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x268++0x03
line.long 0x00 "MB30_WORD0,Message Buffer 30 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x26C++0x03
line.long 0x00 "MB30_WORD1,Message Buffer 30 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x270++0x03
line.long 0x00 "MB31_CS,Message Buffer 31 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x274++0x03
line.long 0x00 "MB31_ID,Message Buffer 31 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x278++0x03
line.long 0x00 "MB31_WORD0,Message Buffer 31 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x27C++0x03
line.long 0x00 "MB31_WORD1,Message Buffer 31 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x280++0x03
line.long 0x00 "MB32_CS,Message Buffer 32 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x284++0x03
line.long 0x00 "MB32_ID,Message Buffer 32 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x288++0x03
line.long 0x00 "MB32_WORD0,Message Buffer 32 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x28C++0x03
line.long 0x00 "MB32_WORD1,Message Buffer 32 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x290++0x03
line.long 0x00 "MB33_CS,Message Buffer 33 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x294++0x03
line.long 0x00 "MB33_ID,Message Buffer 33 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x298++0x03
line.long 0x00 "MB33_WORD0,Message Buffer 33 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x29C++0x03
line.long 0x00 "MB33_WORD1,Message Buffer 33 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x2A0++0x03
line.long 0x00 "MB34_CS,Message Buffer 34 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x2A4++0x03
line.long 0x00 "MB34_ID,Message Buffer 34 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x2A8++0x03
line.long 0x00 "MB34_WORD0,Message Buffer 34 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x2AC++0x03
line.long 0x00 "MB34_WORD1,Message Buffer 34 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x2B0++0x03
line.long 0x00 "MB35_CS,Message Buffer 35 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x2B4++0x03
line.long 0x00 "MB35_ID,Message Buffer 35 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x2B8++0x03
line.long 0x00 "MB35_WORD0,Message Buffer 35 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x2BC++0x03
line.long 0x00 "MB35_WORD1,Message Buffer 35 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x2C0++0x03
line.long 0x00 "MB36_CS,Message Buffer 36 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x2C4++0x03
line.long 0x00 "MB36_ID,Message Buffer 36 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x2C8++0x03
line.long 0x00 "MB36_WORD0,Message Buffer 36 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x2CC++0x03
line.long 0x00 "MB36_WORD1,Message Buffer 36 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x2D0++0x03
line.long 0x00 "MB37_CS,Message Buffer 37 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x2D4++0x03
line.long 0x00 "MB37_ID,Message Buffer 37 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x2D8++0x03
line.long 0x00 "MB37_WORD0,Message Buffer 37 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x2DC++0x03
line.long 0x00 "MB37_WORD1,Message Buffer 37 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x2E0++0x03
line.long 0x00 "MB38_CS,Message Buffer 38 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x2E4++0x03
line.long 0x00 "MB38_ID,Message Buffer 38 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x2E8++0x03
line.long 0x00 "MB38_WORD0,Message Buffer 38 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x2EC++0x03
line.long 0x00 "MB38_WORD1,Message Buffer 38 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x2F0++0x03
line.long 0x00 "MB39_CS,Message Buffer 39 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x2F4++0x03
line.long 0x00 "MB39_ID,Message Buffer 39 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x2F8++0x03
line.long 0x00 "MB39_WORD0,Message Buffer 39 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x2FC++0x03
line.long 0x00 "MB39_WORD1,Message Buffer 39 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x300++0x03
line.long 0x00 "MB40_CS,Message Buffer 40 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x304++0x03
line.long 0x00 "MB40_ID,Message Buffer 40 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x308++0x03
line.long 0x00 "MB40_WORD0,Message Buffer 40 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x30C++0x03
line.long 0x00 "MB40_WORD1,Message Buffer 40 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x310++0x03
line.long 0x00 "MB41_CS,Message Buffer 41 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x314++0x03
line.long 0x00 "MB41_ID,Message Buffer 41 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x318++0x03
line.long 0x00 "MB41_WORD0,Message Buffer 41 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x31C++0x03
line.long 0x00 "MB41_WORD1,Message Buffer 41 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x320++0x03
line.long 0x00 "MB42_CS,Message Buffer 42 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x324++0x03
line.long 0x00 "MB42_ID,Message Buffer 42 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x328++0x03
line.long 0x00 "MB42_WORD0,Message Buffer 42 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x32C++0x03
line.long 0x00 "MB42_WORD1,Message Buffer 42 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x330++0x03
line.long 0x00 "MB43_CS,Message Buffer 43 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x334++0x03
line.long 0x00 "MB43_ID,Message Buffer 43 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x338++0x03
line.long 0x00 "MB43_WORD0,Message Buffer 43 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x33C++0x03
line.long 0x00 "MB43_WORD1,Message Buffer 43 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x340++0x03
line.long 0x00 "MB44_CS,Message Buffer 44 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x344++0x03
line.long 0x00 "MB44_ID,Message Buffer 44 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x348++0x03
line.long 0x00 "MB44_WORD0,Message Buffer 44 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x34C++0x03
line.long 0x00 "MB44_WORD1,Message Buffer 44 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x350++0x03
line.long 0x00 "MB45_CS,Message Buffer 45 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x354++0x03
line.long 0x00 "MB45_ID,Message Buffer 45 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x358++0x03
line.long 0x00 "MB45_WORD0,Message Buffer 45 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x35C++0x03
line.long 0x00 "MB45_WORD1,Message Buffer 45 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x360++0x03
line.long 0x00 "MB46_CS,Message Buffer 46 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x364++0x03
line.long 0x00 "MB46_ID,Message Buffer 46 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x368++0x03
line.long 0x00 "MB46_WORD0,Message Buffer 46 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x36C++0x03
line.long 0x00 "MB46_WORD1,Message Buffer 46 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x370++0x03
line.long 0x00 "MB47_CS,Message Buffer 47 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x374++0x03
line.long 0x00 "MB47_ID,Message Buffer 47 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x378++0x03
line.long 0x00 "MB47_WORD0,Message Buffer 47 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x37C++0x03
line.long 0x00 "MB47_WORD1,Message Buffer 47 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x380++0x03
line.long 0x00 "MB48_CS,Message Buffer 48 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x384++0x03
line.long 0x00 "MB48_ID,Message Buffer 48 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x388++0x03
line.long 0x00 "MB48_WORD0,Message Buffer 48 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x38C++0x03
line.long 0x00 "MB48_WORD1,Message Buffer 48 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x390++0x03
line.long 0x00 "MB49_CS,Message Buffer 49 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x394++0x03
line.long 0x00 "MB49_ID,Message Buffer 49 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x398++0x03
line.long 0x00 "MB49_WORD0,Message Buffer 49 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x39C++0x03
line.long 0x00 "MB49_WORD1,Message Buffer 49 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x3A0++0x03
line.long 0x00 "MB50_CS,Message Buffer 50 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x3A4++0x03
line.long 0x00 "MB50_ID,Message Buffer 50 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x3A8++0x03
line.long 0x00 "MB50_WORD0,Message Buffer 50 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x3AC++0x03
line.long 0x00 "MB50_WORD1,Message Buffer 50 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x3B0++0x03
line.long 0x00 "MB51_CS,Message Buffer 51 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x3B4++0x03
line.long 0x00 "MB51_ID,Message Buffer 51 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x3B8++0x03
line.long 0x00 "MB51_WORD0,Message Buffer 51 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x3BC++0x03
line.long 0x00 "MB51_WORD1,Message Buffer 51 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x3C0++0x03
line.long 0x00 "MB52_CS,Message Buffer 52 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x3C4++0x03
line.long 0x00 "MB52_ID,Message Buffer 52 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x3C8++0x03
line.long 0x00 "MB52_WORD0,Message Buffer 52 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x3CC++0x03
line.long 0x00 "MB52_WORD1,Message Buffer 52 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x3D0++0x03
line.long 0x00 "MB53_CS,Message Buffer 53 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x3D4++0x03
line.long 0x00 "MB53_ID,Message Buffer 53 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x3D8++0x03
line.long 0x00 "MB53_WORD0,Message Buffer 53 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x3DC++0x03
line.long 0x00 "MB53_WORD1,Message Buffer 53 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x3E0++0x03
line.long 0x00 "MB54_CS,Message Buffer 54 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x3E4++0x03
line.long 0x00 "MB54_ID,Message Buffer 54 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x3E8++0x03
line.long 0x00 "MB54_WORD0,Message Buffer 54 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x3EC++0x03
line.long 0x00 "MB54_WORD1,Message Buffer 54 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x3F0++0x03
line.long 0x00 "MB55_CS,Message Buffer 55 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x3F4++0x03
line.long 0x00 "MB55_ID,Message Buffer 55 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x3F8++0x03
line.long 0x00 "MB55_WORD0,Message Buffer 55 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x3FC++0x03
line.long 0x00 "MB55_WORD1,Message Buffer 55 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x400++0x03
line.long 0x00 "MB56_CS,Message Buffer 56 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x404++0x03
line.long 0x00 "MB56_ID,Message Buffer 56 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x408++0x03
line.long 0x00 "MB56_WORD0,Message Buffer 56 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x40C++0x03
line.long 0x00 "MB56_WORD1,Message Buffer 56 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x410++0x03
line.long 0x00 "MB57_CS,Message Buffer 57 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x414++0x03
line.long 0x00 "MB57_ID,Message Buffer 57 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x418++0x03
line.long 0x00 "MB57_WORD0,Message Buffer 57 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x41C++0x03
line.long 0x00 "MB57_WORD1,Message Buffer 57 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x420++0x03
line.long 0x00 "MB58_CS,Message Buffer 58 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x424++0x03
line.long 0x00 "MB58_ID,Message Buffer 58 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x428++0x03
line.long 0x00 "MB58_WORD0,Message Buffer 58 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x42C++0x03
line.long 0x00 "MB58_WORD1,Message Buffer 58 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x430++0x03
line.long 0x00 "MB59_CS,Message Buffer 59 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x434++0x03
line.long 0x00 "MB59_ID,Message Buffer 59 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x438++0x03
line.long 0x00 "MB59_WORD0,Message Buffer 59 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x43C++0x03
line.long 0x00 "MB59_WORD1,Message Buffer 59 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x440++0x03
line.long 0x00 "MB60_CS,Message Buffer 60 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x444++0x03
line.long 0x00 "MB60_ID,Message Buffer 60 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x448++0x03
line.long 0x00 "MB60_WORD0,Message Buffer 60 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x44C++0x03
line.long 0x00 "MB60_WORD1,Message Buffer 60 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
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hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x450++0x03
line.long 0x00 "MB61_CS,Message Buffer 61 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
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bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
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bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x454++0x03
line.long 0x00 "MB61_ID,Message Buffer 61 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x458++0x03
line.long 0x00 "MB61_WORD0,Message Buffer 61 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
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hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x45C++0x03
line.long 0x00 "MB61_WORD1,Message Buffer 61 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
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hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x460++0x03
line.long 0x00 "MB62_CS,Message Buffer 62 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
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bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x464++0x03
line.long 0x00 "MB62_ID,Message Buffer 62 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x468++0x03
line.long 0x00 "MB62_WORD0,Message Buffer 62 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
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hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x46C++0x03
line.long 0x00 "MB62_WORD1,Message Buffer 62 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
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hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
group.long 0x470++0x03
line.long 0x00 "MB63_CS,Message Buffer 63 CS Register"
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
newline
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
newline
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
group.long 0x474++0x03
line.long 0x00 "MB63_ID,Message Buffer 63 ID Register"
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
group.long 0x478++0x03
line.long 0x00 "MB63_WORD0,Message Buffer 63 WORD0 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
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hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
group.long 0x47C++0x03
line.long 0x00 "MB63_WORD1,Message Buffer 63 WORD1 Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
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hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x880)++0x03
line.long 0x00 "RXIMR[$1],Rx Individual Mask registers $1"
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
repeat.end
group.long 0xAE0++0x03
line.long 0x00 "MECR,Memory Error Control register"
bitfld.long 0x00 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Write is enabled,1: Write is disabled"
bitfld.long 0x00 19. "HANCEI_MSK,Host Access With Non-Correctable Errors Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled"
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bitfld.long 0x00 18. "FANCEI_MSK,FlexCAN Access With Non-Correctable Errors Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled"
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bitfld.long 0x00 15. "HAERRIE,Host Access Error Injection Enable" "0: Injection is disabled,1: Injection is enabled"
bitfld.long 0x00 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Injection is disabled,1: Injection is enabled"
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bitfld.long 0x00 13. "EXTERRIE,Extended Error Injection Enable" "0: Error injection is applied only to the 32-bit..,1: Error injection is applied to the 64-bit word"
bitfld.long 0x00 9. "RERRDIS,Error Report Disable" "0: Enable updates of the error report registers,1: Disable updates of the error report registers"
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bitfld.long 0x00 8. "ECCDIS,Error Correction Disable" "0: Enable memory error correction,1: Disable memory error correction"
bitfld.long 0x00 7. "NCEFAFRZ,Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode" "0: Keep normal operation,1: Put FlexCAN in Freeze mode (see section.."
group.long 0xAE4++0x03
line.long 0x00 "ERRIAR,Error Injection Address register"
hexmask.long.word 0x00 2.--13. 1. "INJADDR_H,Error Injection Address High"
rbitfld.long 0x00 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3"
group.long 0xAE8++0x03
line.long 0x00 "ERRIDPR,Error Injection Data Pattern register"
hexmask.long 0x00 0.--31. 1. "DFLIP,Data flip pattern"
group.long 0xAEC++0x03
line.long 0x00 "ERRIPPR,Error Injection Parity Pattern register"
bitfld.long 0x00 24.--28. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PFLIP2,Parity Flip Pattern For Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PFLIP1,Parity Flip Pattern For Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "PFLIP0,Parity Flip Pattern For Byte 0 (Least Significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xAF0++0x03
line.long 0x00 "RERRAR,Error Report Address register"
bitfld.long 0x00 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error"
bitfld.long 0x00 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--13. 1. "ERRADDR,Address Where Error Detected"
rgroup.long 0xAF4++0x03
line.long 0x00 "RERRDR,Error Report Data register"
hexmask.long 0x00 0.--31. 1. "RDATA,Raw data word read from memory with error"
rgroup.long 0xAF8++0x03
line.long 0x00 "RERRSYNR,Error Report Syndrome register"
bitfld.long 0x00 31. "BE3,Byte Enabled For Byte 3 (most significant)" "0: The byte was not,1: The byte was"
bitfld.long 0x00 24.--28. "SYND3,Error Syndrome For Byte 3 (most significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 23. "BE2,Byte Enabled For Byte 2" "0: The byte was not,1: The byte was"
bitfld.long 0x00 16.--20. "SYND2,Error Syndrome For Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "BE1,Byte Enabled For Byte 1" "0: The byte was not,1: The byte was"
bitfld.long 0x00 8.--12. "SYND1,Error Syndrome for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7. "BE0,Byte Enabled For Byte 0 (least significant)" "0: The byte was not,1: The byte was"
bitfld.long 0x00 0.--4. "SYND0,Error Syndrome For Byte 0 (least significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAFC++0x03
line.long 0x00 "ERRSR,Error Status register"
eventfld.long 0x00 19. "HANCEIF,Host Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.."
eventfld.long 0x00 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.."
newline
eventfld.long 0x00 16. "CEIF,Correctable Error Interrupt Flag" "0: No correctable errors were detected so far,1: A correctable error was detected"
eventfld.long 0x00 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in host..,1: Overrun on non-correctable errors in host.."
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eventfld.long 0x00 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in..,1: Overrun on non-correctable errors in FlexCAN.."
eventfld.long 0x00 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No overrun on correctable errors,1: Overrun on correctable errors"
group.long 0xC00++0x03
line.long 0x00 "FDCTRL,CAN FD Control register"
bitfld.long 0x00 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate,1: Transmit a frame with bit rate switching if.."
bitfld.long 0x00 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: Selects 8 bytes per message buffer,1: Selects 16 bytes per message buffer,2: Selects 32 bytes per message buffer,3: Selects 64 bytes per message buffer"
newline
bitfld.long 0x00 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per message buffer,1: Selects 16 bytes per message buffer,2: Selects 32 bytes per message buffer,3: Selects 64 bytes per message buffer"
bitfld.long 0x00 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
newline
eventfld.long 0x00 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
bitfld.long 0x00 8.--12. "TDCOFF,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 0.--5. "TDCVAL,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC04++0x03
line.long 0x00 "FDCBT,CAN FD Bit Timing register"
hexmask.long.word 0x00 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor"
bitfld.long 0x00 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--14. "FPROPSEG,Fast Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7"
rgroup.long 0xC08++0x03
line.long 0x00 "FDCRC,CAN FD CRC register"
hexmask.long.byte 0x00 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC"
hexmask.long.tbyte 0x00 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value"
tree.end
repeat.end
tree.end
tree "CCM (Clock Controller Module)"
base ad:0x30380000
group.long 0x00++0x03
line.long 0x00 "GPR0,General Purpose Register"
hexmask.long 0x00 0.--31. 1. "GP0,Timeout cycle count of ipg_clk when perform read and write"
group.long 0x04++0x03
line.long 0x00 "GPR0_SET,General Purpose Register"
hexmask.long 0x00 0.--31. 1. "GP0,Timeout cycle count of ipg_clk when perform read and write"
group.long 0x08++0x03
line.long 0x00 "GPR0_CLR,General Purpose Register"
hexmask.long 0x00 0.--31. 1. "GP0,Timeout cycle count of ipg_clk when perform read and write"
group.long 0x0C++0x03
line.long 0x00 "GPR0_TOG,General Purpose Register"
hexmask.long 0x00 0.--31. 1. "GP0,Timeout cycle count of ipg_clk when perform read and write"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x800)++0x03
line.long 0x00 "PLL_CTRL$1,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x900)++0x03
line.long 0x00 "PLL_CTRL$1,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 7. (strings "32" "33" "34" "35" "36" "37" "38" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 )
group.long ($2+0xA00)++0x03
line.long 0x00 "PLL_CTRL$1,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
group.long 0x804++0x03
line.long 0x00 "PLL_CTRL0_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x814++0x03
line.long 0x00 "PLL_CTRL1_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x824++0x03
line.long 0x00 "PLL_CTRL2_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x834++0x03
line.long 0x00 "PLL_CTRL3_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x844++0x03
line.long 0x00 "PLL_CTRL4_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x854++0x03
line.long 0x00 "PLL_CTRL5_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x864++0x03
line.long 0x00 "PLL_CTRL6_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x874++0x03
line.long 0x00 "PLL_CTRL7_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x884++0x03
line.long 0x00 "PLL_CTRL8_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x894++0x03
line.long 0x00 "PLL_CTRL9_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8A4++0x03
line.long 0x00 "PLL_CTRL10_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8B4++0x03
line.long 0x00 "PLL_CTRL11_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8C4++0x03
line.long 0x00 "PLL_CTRL12_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8D4++0x03
line.long 0x00 "PLL_CTRL13_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8E4++0x03
line.long 0x00 "PLL_CTRL14_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8F4++0x03
line.long 0x00 "PLL_CTRL15_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x904++0x03
line.long 0x00 "PLL_CTRL16_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x914++0x03
line.long 0x00 "PLL_CTRL17_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x924++0x03
line.long 0x00 "PLL_CTRL18_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x934++0x03
line.long 0x00 "PLL_CTRL19_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x944++0x03
line.long 0x00 "PLL_CTRL20_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x954++0x03
line.long 0x00 "PLL_CTRL21_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x964++0x03
line.long 0x00 "PLL_CTRL22_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x974++0x03
line.long 0x00 "PLL_CTRL23_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x984++0x03
line.long 0x00 "PLL_CTRL24_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x994++0x03
line.long 0x00 "PLL_CTRL25_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9A4++0x03
line.long 0x00 "PLL_CTRL26_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9B4++0x03
line.long 0x00 "PLL_CTRL27_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9C4++0x03
line.long 0x00 "PLL_CTRL28_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9D4++0x03
line.long 0x00 "PLL_CTRL29_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9E4++0x03
line.long 0x00 "PLL_CTRL30_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9F4++0x03
line.long 0x00 "PLL_CTRL31_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA04++0x03
line.long 0x00 "PLL_CTRL32_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA14++0x03
line.long 0x00 "PLL_CTRL33_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA24++0x03
line.long 0x00 "PLL_CTRL34_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA34++0x03
line.long 0x00 "PLL_CTRL35_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA44++0x03
line.long 0x00 "PLL_CTRL36_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA54++0x03
line.long 0x00 "PLL_CTRL37_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA64++0x03
line.long 0x00 "PLL_CTRL38_SET,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x808++0x03
line.long 0x00 "PLL_CTRL0_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x818++0x03
line.long 0x00 "PLL_CTRL1_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x828++0x03
line.long 0x00 "PLL_CTRL2_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x838++0x03
line.long 0x00 "PLL_CTRL3_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x848++0x03
line.long 0x00 "PLL_CTRL4_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x858++0x03
line.long 0x00 "PLL_CTRL5_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x868++0x03
line.long 0x00 "PLL_CTRL6_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x878++0x03
line.long 0x00 "PLL_CTRL7_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x888++0x03
line.long 0x00 "PLL_CTRL8_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x898++0x03
line.long 0x00 "PLL_CTRL9_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8A8++0x03
line.long 0x00 "PLL_CTRL10_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8B8++0x03
line.long 0x00 "PLL_CTRL11_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8C8++0x03
line.long 0x00 "PLL_CTRL12_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8D8++0x03
line.long 0x00 "PLL_CTRL13_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8E8++0x03
line.long 0x00 "PLL_CTRL14_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8F8++0x03
line.long 0x00 "PLL_CTRL15_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x908++0x03
line.long 0x00 "PLL_CTRL16_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x918++0x03
line.long 0x00 "PLL_CTRL17_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x928++0x03
line.long 0x00 "PLL_CTRL18_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x938++0x03
line.long 0x00 "PLL_CTRL19_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x948++0x03
line.long 0x00 "PLL_CTRL20_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x958++0x03
line.long 0x00 "PLL_CTRL21_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x968++0x03
line.long 0x00 "PLL_CTRL22_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x978++0x03
line.long 0x00 "PLL_CTRL23_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x988++0x03
line.long 0x00 "PLL_CTRL24_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x998++0x03
line.long 0x00 "PLL_CTRL25_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9A8++0x03
line.long 0x00 "PLL_CTRL26_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9B8++0x03
line.long 0x00 "PLL_CTRL27_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9C8++0x03
line.long 0x00 "PLL_CTRL28_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9D8++0x03
line.long 0x00 "PLL_CTRL29_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9E8++0x03
line.long 0x00 "PLL_CTRL30_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9F8++0x03
line.long 0x00 "PLL_CTRL31_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA08++0x03
line.long 0x00 "PLL_CTRL32_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA18++0x03
line.long 0x00 "PLL_CTRL33_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA28++0x03
line.long 0x00 "PLL_CTRL34_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA38++0x03
line.long 0x00 "PLL_CTRL35_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA48++0x03
line.long 0x00 "PLL_CTRL36_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA58++0x03
line.long 0x00 "PLL_CTRL37_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA68++0x03
line.long 0x00 "PLL_CTRL38_CLR,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x80C++0x03
line.long 0x00 "PLL_CTRL0_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x81C++0x03
line.long 0x00 "PLL_CTRL1_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x82C++0x03
line.long 0x00 "PLL_CTRL2_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x83C++0x03
line.long 0x00 "PLL_CTRL3_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x84C++0x03
line.long 0x00 "PLL_CTRL4_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x85C++0x03
line.long 0x00 "PLL_CTRL5_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x86C++0x03
line.long 0x00 "PLL_CTRL6_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x87C++0x03
line.long 0x00 "PLL_CTRL7_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x88C++0x03
line.long 0x00 "PLL_CTRL8_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x89C++0x03
line.long 0x00 "PLL_CTRL9_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8AC++0x03
line.long 0x00 "PLL_CTRL10_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8BC++0x03
line.long 0x00 "PLL_CTRL11_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8CC++0x03
line.long 0x00 "PLL_CTRL12_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8DC++0x03
line.long 0x00 "PLL_CTRL13_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8EC++0x03
line.long 0x00 "PLL_CTRL14_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8FC++0x03
line.long 0x00 "PLL_CTRL15_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x90C++0x03
line.long 0x00 "PLL_CTRL16_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x91C++0x03
line.long 0x00 "PLL_CTRL17_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x92C++0x03
line.long 0x00 "PLL_CTRL18_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x93C++0x03
line.long 0x00 "PLL_CTRL19_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x94C++0x03
line.long 0x00 "PLL_CTRL20_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x95C++0x03
line.long 0x00 "PLL_CTRL21_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x96C++0x03
line.long 0x00 "PLL_CTRL22_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x97C++0x03
line.long 0x00 "PLL_CTRL23_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x98C++0x03
line.long 0x00 "PLL_CTRL24_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x99C++0x03
line.long 0x00 "PLL_CTRL25_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9AC++0x03
line.long 0x00 "PLL_CTRL26_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9BC++0x03
line.long 0x00 "PLL_CTRL27_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9CC++0x03
line.long 0x00 "PLL_CTRL28_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9DC++0x03
line.long 0x00 "PLL_CTRL29_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9EC++0x03
line.long 0x00 "PLL_CTRL30_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x9FC++0x03
line.long 0x00 "PLL_CTRL31_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA0C++0x03
line.long 0x00 "PLL_CTRL32_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA1C++0x03
line.long 0x00 "PLL_CTRL33_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA2C++0x03
line.long 0x00 "PLL_CTRL34_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA3C++0x03
line.long 0x00 "PLL_CTRL35_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA4C++0x03
line.long 0x00 "PLL_CTRL36_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA5C++0x03
line.long 0x00 "PLL_CTRL37_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0xA6C++0x03
line.long 0x00 "PLL_CTRL38_TOG,CCM PLL Control Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4000)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4100)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4200)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4300)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4400)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4500)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4600)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4700)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "128" "129" "130" "131" "132" "133" "134" "135" "136" "137" "138" "139" "140" "141" "142" "143" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4800)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "144" "145" "146" "147" "148" "149" "150" "151" "152" "153" "154" "155" "156" "157" "158" "159" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4900)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "160" "161" "162" "163" "164" "165" "166" "167" "168" "169" "170" "171" "172" "173" "174" "175" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4A00)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
repeat 16. (strings "176" "177" "178" "179" "180" "181" "182" "183" "184" "185" "186" "187" "188" "189" "190" "191" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x4B00)++0x03
line.long 0x00 "CCGR$1,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
repeat.end
group.long 0x4004++0x03
line.long 0x00 "CCGR0_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4014++0x03
line.long 0x00 "CCGR1_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4024++0x03
line.long 0x00 "CCGR2_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4034++0x03
line.long 0x00 "CCGR3_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4044++0x03
line.long 0x00 "CCGR4_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4054++0x03
line.long 0x00 "CCGR5_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4064++0x03
line.long 0x00 "CCGR6_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4074++0x03
line.long 0x00 "CCGR7_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4084++0x03
line.long 0x00 "CCGR8_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4094++0x03
line.long 0x00 "CCGR9_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40A4++0x03
line.long 0x00 "CCGR10_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40B4++0x03
line.long 0x00 "CCGR11_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40C4++0x03
line.long 0x00 "CCGR12_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40D4++0x03
line.long 0x00 "CCGR13_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40E4++0x03
line.long 0x00 "CCGR14_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40F4++0x03
line.long 0x00 "CCGR15_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4104++0x03
line.long 0x00 "CCGR16_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4114++0x03
line.long 0x00 "CCGR17_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4124++0x03
line.long 0x00 "CCGR18_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4134++0x03
line.long 0x00 "CCGR19_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4144++0x03
line.long 0x00 "CCGR20_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4154++0x03
line.long 0x00 "CCGR21_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4164++0x03
line.long 0x00 "CCGR22_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4174++0x03
line.long 0x00 "CCGR23_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4184++0x03
line.long 0x00 "CCGR24_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4194++0x03
line.long 0x00 "CCGR25_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41A4++0x03
line.long 0x00 "CCGR26_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41B4++0x03
line.long 0x00 "CCGR27_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41C4++0x03
line.long 0x00 "CCGR28_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41D4++0x03
line.long 0x00 "CCGR29_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41E4++0x03
line.long 0x00 "CCGR30_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41F4++0x03
line.long 0x00 "CCGR31_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4204++0x03
line.long 0x00 "CCGR32_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4214++0x03
line.long 0x00 "CCGR33_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4224++0x03
line.long 0x00 "CCGR34_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4234++0x03
line.long 0x00 "CCGR35_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4244++0x03
line.long 0x00 "CCGR36_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4254++0x03
line.long 0x00 "CCGR37_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4264++0x03
line.long 0x00 "CCGR38_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4274++0x03
line.long 0x00 "CCGR39_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4284++0x03
line.long 0x00 "CCGR40_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4294++0x03
line.long 0x00 "CCGR41_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42A4++0x03
line.long 0x00 "CCGR42_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42B4++0x03
line.long 0x00 "CCGR43_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42C4++0x03
line.long 0x00 "CCGR44_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42D4++0x03
line.long 0x00 "CCGR45_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42E4++0x03
line.long 0x00 "CCGR46_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42F4++0x03
line.long 0x00 "CCGR47_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4304++0x03
line.long 0x00 "CCGR48_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4314++0x03
line.long 0x00 "CCGR49_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4324++0x03
line.long 0x00 "CCGR50_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4334++0x03
line.long 0x00 "CCGR51_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4344++0x03
line.long 0x00 "CCGR52_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4354++0x03
line.long 0x00 "CCGR53_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4364++0x03
line.long 0x00 "CCGR54_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4374++0x03
line.long 0x00 "CCGR55_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4384++0x03
line.long 0x00 "CCGR56_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4394++0x03
line.long 0x00 "CCGR57_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43A4++0x03
line.long 0x00 "CCGR58_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43B4++0x03
line.long 0x00 "CCGR59_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43C4++0x03
line.long 0x00 "CCGR60_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43D4++0x03
line.long 0x00 "CCGR61_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43E4++0x03
line.long 0x00 "CCGR62_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43F4++0x03
line.long 0x00 "CCGR63_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4404++0x03
line.long 0x00 "CCGR64_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4414++0x03
line.long 0x00 "CCGR65_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4424++0x03
line.long 0x00 "CCGR66_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4434++0x03
line.long 0x00 "CCGR67_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4444++0x03
line.long 0x00 "CCGR68_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4454++0x03
line.long 0x00 "CCGR69_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4464++0x03
line.long 0x00 "CCGR70_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4474++0x03
line.long 0x00 "CCGR71_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4484++0x03
line.long 0x00 "CCGR72_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4494++0x03
line.long 0x00 "CCGR73_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44A4++0x03
line.long 0x00 "CCGR74_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44B4++0x03
line.long 0x00 "CCGR75_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44C4++0x03
line.long 0x00 "CCGR76_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44D4++0x03
line.long 0x00 "CCGR77_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44E4++0x03
line.long 0x00 "CCGR78_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44F4++0x03
line.long 0x00 "CCGR79_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4504++0x03
line.long 0x00 "CCGR80_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4514++0x03
line.long 0x00 "CCGR81_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4524++0x03
line.long 0x00 "CCGR82_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4534++0x03
line.long 0x00 "CCGR83_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4544++0x03
line.long 0x00 "CCGR84_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4554++0x03
line.long 0x00 "CCGR85_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4564++0x03
line.long 0x00 "CCGR86_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4574++0x03
line.long 0x00 "CCGR87_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4584++0x03
line.long 0x00 "CCGR88_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4594++0x03
line.long 0x00 "CCGR89_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45A4++0x03
line.long 0x00 "CCGR90_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45B4++0x03
line.long 0x00 "CCGR91_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45C4++0x03
line.long 0x00 "CCGR92_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45D4++0x03
line.long 0x00 "CCGR93_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45E4++0x03
line.long 0x00 "CCGR94_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45F4++0x03
line.long 0x00 "CCGR95_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4604++0x03
line.long 0x00 "CCGR96_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4614++0x03
line.long 0x00 "CCGR97_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4624++0x03
line.long 0x00 "CCGR98_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4634++0x03
line.long 0x00 "CCGR99_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4644++0x03
line.long 0x00 "CCGR100_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4654++0x03
line.long 0x00 "CCGR101_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4664++0x03
line.long 0x00 "CCGR102_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4674++0x03
line.long 0x00 "CCGR103_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4684++0x03
line.long 0x00 "CCGR104_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4694++0x03
line.long 0x00 "CCGR105_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46A4++0x03
line.long 0x00 "CCGR106_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46B4++0x03
line.long 0x00 "CCGR107_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46C4++0x03
line.long 0x00 "CCGR108_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46D4++0x03
line.long 0x00 "CCGR109_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46E4++0x03
line.long 0x00 "CCGR110_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46F4++0x03
line.long 0x00 "CCGR111_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4704++0x03
line.long 0x00 "CCGR112_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4714++0x03
line.long 0x00 "CCGR113_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4724++0x03
line.long 0x00 "CCGR114_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4734++0x03
line.long 0x00 "CCGR115_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4744++0x03
line.long 0x00 "CCGR116_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4754++0x03
line.long 0x00 "CCGR117_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4764++0x03
line.long 0x00 "CCGR118_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4774++0x03
line.long 0x00 "CCGR119_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4784++0x03
line.long 0x00 "CCGR120_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4794++0x03
line.long 0x00 "CCGR121_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47A4++0x03
line.long 0x00 "CCGR122_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47B4++0x03
line.long 0x00 "CCGR123_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47C4++0x03
line.long 0x00 "CCGR124_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47D4++0x03
line.long 0x00 "CCGR125_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47E4++0x03
line.long 0x00 "CCGR126_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47F4++0x03
line.long 0x00 "CCGR127_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4804++0x03
line.long 0x00 "CCGR128_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4814++0x03
line.long 0x00 "CCGR129_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4824++0x03
line.long 0x00 "CCGR130_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4834++0x03
line.long 0x00 "CCGR131_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4844++0x03
line.long 0x00 "CCGR132_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4854++0x03
line.long 0x00 "CCGR133_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4864++0x03
line.long 0x00 "CCGR134_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4874++0x03
line.long 0x00 "CCGR135_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4884++0x03
line.long 0x00 "CCGR136_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4894++0x03
line.long 0x00 "CCGR137_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48A4++0x03
line.long 0x00 "CCGR138_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48B4++0x03
line.long 0x00 "CCGR139_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48C4++0x03
line.long 0x00 "CCGR140_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48D4++0x03
line.long 0x00 "CCGR141_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48E4++0x03
line.long 0x00 "CCGR142_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48F4++0x03
line.long 0x00 "CCGR143_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4904++0x03
line.long 0x00 "CCGR144_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4914++0x03
line.long 0x00 "CCGR145_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4924++0x03
line.long 0x00 "CCGR146_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4934++0x03
line.long 0x00 "CCGR147_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4944++0x03
line.long 0x00 "CCGR148_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4954++0x03
line.long 0x00 "CCGR149_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4964++0x03
line.long 0x00 "CCGR150_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4974++0x03
line.long 0x00 "CCGR151_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4984++0x03
line.long 0x00 "CCGR152_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4994++0x03
line.long 0x00 "CCGR153_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49A4++0x03
line.long 0x00 "CCGR154_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49B4++0x03
line.long 0x00 "CCGR155_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49C4++0x03
line.long 0x00 "CCGR156_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49D4++0x03
line.long 0x00 "CCGR157_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49E4++0x03
line.long 0x00 "CCGR158_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49F4++0x03
line.long 0x00 "CCGR159_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A04++0x03
line.long 0x00 "CCGR160_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A14++0x03
line.long 0x00 "CCGR161_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A24++0x03
line.long 0x00 "CCGR162_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A34++0x03
line.long 0x00 "CCGR163_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A44++0x03
line.long 0x00 "CCGR164_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A54++0x03
line.long 0x00 "CCGR165_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A64++0x03
line.long 0x00 "CCGR166_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A74++0x03
line.long 0x00 "CCGR167_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A84++0x03
line.long 0x00 "CCGR168_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A94++0x03
line.long 0x00 "CCGR169_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AA4++0x03
line.long 0x00 "CCGR170_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AB4++0x03
line.long 0x00 "CCGR171_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AC4++0x03
line.long 0x00 "CCGR172_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AD4++0x03
line.long 0x00 "CCGR173_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AE4++0x03
line.long 0x00 "CCGR174_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AF4++0x03
line.long 0x00 "CCGR175_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B04++0x03
line.long 0x00 "CCGR176_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B14++0x03
line.long 0x00 "CCGR177_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B24++0x03
line.long 0x00 "CCGR178_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B34++0x03
line.long 0x00 "CCGR179_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B44++0x03
line.long 0x00 "CCGR180_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B54++0x03
line.long 0x00 "CCGR181_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B64++0x03
line.long 0x00 "CCGR182_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B74++0x03
line.long 0x00 "CCGR183_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B84++0x03
line.long 0x00 "CCGR184_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B94++0x03
line.long 0x00 "CCGR185_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BA4++0x03
line.long 0x00 "CCGR186_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BB4++0x03
line.long 0x00 "CCGR187_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BC4++0x03
line.long 0x00 "CCGR188_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BD4++0x03
line.long 0x00 "CCGR189_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BE4++0x03
line.long 0x00 "CCGR190_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BF4++0x03
line.long 0x00 "CCGR191_SET,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4008++0x03
line.long 0x00 "CCGR0_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4018++0x03
line.long 0x00 "CCGR1_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4028++0x03
line.long 0x00 "CCGR2_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4038++0x03
line.long 0x00 "CCGR3_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4048++0x03
line.long 0x00 "CCGR4_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4058++0x03
line.long 0x00 "CCGR5_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4068++0x03
line.long 0x00 "CCGR6_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4078++0x03
line.long 0x00 "CCGR7_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4088++0x03
line.long 0x00 "CCGR8_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4098++0x03
line.long 0x00 "CCGR9_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40A8++0x03
line.long 0x00 "CCGR10_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40B8++0x03
line.long 0x00 "CCGR11_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40C8++0x03
line.long 0x00 "CCGR12_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40D8++0x03
line.long 0x00 "CCGR13_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40E8++0x03
line.long 0x00 "CCGR14_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40F8++0x03
line.long 0x00 "CCGR15_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4108++0x03
line.long 0x00 "CCGR16_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4118++0x03
line.long 0x00 "CCGR17_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4128++0x03
line.long 0x00 "CCGR18_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4138++0x03
line.long 0x00 "CCGR19_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4148++0x03
line.long 0x00 "CCGR20_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4158++0x03
line.long 0x00 "CCGR21_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4168++0x03
line.long 0x00 "CCGR22_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4178++0x03
line.long 0x00 "CCGR23_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4188++0x03
line.long 0x00 "CCGR24_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4198++0x03
line.long 0x00 "CCGR25_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41A8++0x03
line.long 0x00 "CCGR26_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41B8++0x03
line.long 0x00 "CCGR27_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41C8++0x03
line.long 0x00 "CCGR28_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41D8++0x03
line.long 0x00 "CCGR29_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41E8++0x03
line.long 0x00 "CCGR30_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41F8++0x03
line.long 0x00 "CCGR31_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4208++0x03
line.long 0x00 "CCGR32_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4218++0x03
line.long 0x00 "CCGR33_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4228++0x03
line.long 0x00 "CCGR34_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4238++0x03
line.long 0x00 "CCGR35_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4248++0x03
line.long 0x00 "CCGR36_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4258++0x03
line.long 0x00 "CCGR37_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4268++0x03
line.long 0x00 "CCGR38_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4278++0x03
line.long 0x00 "CCGR39_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4288++0x03
line.long 0x00 "CCGR40_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4298++0x03
line.long 0x00 "CCGR41_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42A8++0x03
line.long 0x00 "CCGR42_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42B8++0x03
line.long 0x00 "CCGR43_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42C8++0x03
line.long 0x00 "CCGR44_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42D8++0x03
line.long 0x00 "CCGR45_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42E8++0x03
line.long 0x00 "CCGR46_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42F8++0x03
line.long 0x00 "CCGR47_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4308++0x03
line.long 0x00 "CCGR48_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4318++0x03
line.long 0x00 "CCGR49_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4328++0x03
line.long 0x00 "CCGR50_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4338++0x03
line.long 0x00 "CCGR51_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4348++0x03
line.long 0x00 "CCGR52_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4358++0x03
line.long 0x00 "CCGR53_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4368++0x03
line.long 0x00 "CCGR54_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4378++0x03
line.long 0x00 "CCGR55_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4388++0x03
line.long 0x00 "CCGR56_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4398++0x03
line.long 0x00 "CCGR57_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43A8++0x03
line.long 0x00 "CCGR58_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43B8++0x03
line.long 0x00 "CCGR59_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43C8++0x03
line.long 0x00 "CCGR60_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43D8++0x03
line.long 0x00 "CCGR61_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43E8++0x03
line.long 0x00 "CCGR62_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43F8++0x03
line.long 0x00 "CCGR63_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4408++0x03
line.long 0x00 "CCGR64_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4418++0x03
line.long 0x00 "CCGR65_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4428++0x03
line.long 0x00 "CCGR66_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4438++0x03
line.long 0x00 "CCGR67_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4448++0x03
line.long 0x00 "CCGR68_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4458++0x03
line.long 0x00 "CCGR69_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4468++0x03
line.long 0x00 "CCGR70_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4478++0x03
line.long 0x00 "CCGR71_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4488++0x03
line.long 0x00 "CCGR72_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4498++0x03
line.long 0x00 "CCGR73_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44A8++0x03
line.long 0x00 "CCGR74_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44B8++0x03
line.long 0x00 "CCGR75_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44C8++0x03
line.long 0x00 "CCGR76_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44D8++0x03
line.long 0x00 "CCGR77_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44E8++0x03
line.long 0x00 "CCGR78_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44F8++0x03
line.long 0x00 "CCGR79_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4508++0x03
line.long 0x00 "CCGR80_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4518++0x03
line.long 0x00 "CCGR81_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4528++0x03
line.long 0x00 "CCGR82_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4538++0x03
line.long 0x00 "CCGR83_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4548++0x03
line.long 0x00 "CCGR84_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4558++0x03
line.long 0x00 "CCGR85_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4568++0x03
line.long 0x00 "CCGR86_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4578++0x03
line.long 0x00 "CCGR87_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4588++0x03
line.long 0x00 "CCGR88_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4598++0x03
line.long 0x00 "CCGR89_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45A8++0x03
line.long 0x00 "CCGR90_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45B8++0x03
line.long 0x00 "CCGR91_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45C8++0x03
line.long 0x00 "CCGR92_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45D8++0x03
line.long 0x00 "CCGR93_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45E8++0x03
line.long 0x00 "CCGR94_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45F8++0x03
line.long 0x00 "CCGR95_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4608++0x03
line.long 0x00 "CCGR96_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4618++0x03
line.long 0x00 "CCGR97_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4628++0x03
line.long 0x00 "CCGR98_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4638++0x03
line.long 0x00 "CCGR99_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4648++0x03
line.long 0x00 "CCGR100_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4658++0x03
line.long 0x00 "CCGR101_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4668++0x03
line.long 0x00 "CCGR102_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4678++0x03
line.long 0x00 "CCGR103_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4688++0x03
line.long 0x00 "CCGR104_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4698++0x03
line.long 0x00 "CCGR105_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46A8++0x03
line.long 0x00 "CCGR106_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46B8++0x03
line.long 0x00 "CCGR107_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46C8++0x03
line.long 0x00 "CCGR108_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46D8++0x03
line.long 0x00 "CCGR109_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46E8++0x03
line.long 0x00 "CCGR110_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46F8++0x03
line.long 0x00 "CCGR111_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4708++0x03
line.long 0x00 "CCGR112_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4718++0x03
line.long 0x00 "CCGR113_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4728++0x03
line.long 0x00 "CCGR114_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4738++0x03
line.long 0x00 "CCGR115_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4748++0x03
line.long 0x00 "CCGR116_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4758++0x03
line.long 0x00 "CCGR117_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4768++0x03
line.long 0x00 "CCGR118_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4778++0x03
line.long 0x00 "CCGR119_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4788++0x03
line.long 0x00 "CCGR120_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4798++0x03
line.long 0x00 "CCGR121_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47A8++0x03
line.long 0x00 "CCGR122_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47B8++0x03
line.long 0x00 "CCGR123_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47C8++0x03
line.long 0x00 "CCGR124_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47D8++0x03
line.long 0x00 "CCGR125_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47E8++0x03
line.long 0x00 "CCGR126_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47F8++0x03
line.long 0x00 "CCGR127_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4808++0x03
line.long 0x00 "CCGR128_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4818++0x03
line.long 0x00 "CCGR129_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4828++0x03
line.long 0x00 "CCGR130_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4838++0x03
line.long 0x00 "CCGR131_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4848++0x03
line.long 0x00 "CCGR132_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4858++0x03
line.long 0x00 "CCGR133_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4868++0x03
line.long 0x00 "CCGR134_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4878++0x03
line.long 0x00 "CCGR135_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4888++0x03
line.long 0x00 "CCGR136_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4898++0x03
line.long 0x00 "CCGR137_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48A8++0x03
line.long 0x00 "CCGR138_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48B8++0x03
line.long 0x00 "CCGR139_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48C8++0x03
line.long 0x00 "CCGR140_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48D8++0x03
line.long 0x00 "CCGR141_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48E8++0x03
line.long 0x00 "CCGR142_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48F8++0x03
line.long 0x00 "CCGR143_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4908++0x03
line.long 0x00 "CCGR144_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4918++0x03
line.long 0x00 "CCGR145_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4928++0x03
line.long 0x00 "CCGR146_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4938++0x03
line.long 0x00 "CCGR147_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4948++0x03
line.long 0x00 "CCGR148_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4958++0x03
line.long 0x00 "CCGR149_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4968++0x03
line.long 0x00 "CCGR150_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4978++0x03
line.long 0x00 "CCGR151_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4988++0x03
line.long 0x00 "CCGR152_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4998++0x03
line.long 0x00 "CCGR153_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49A8++0x03
line.long 0x00 "CCGR154_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49B8++0x03
line.long 0x00 "CCGR155_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49C8++0x03
line.long 0x00 "CCGR156_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49D8++0x03
line.long 0x00 "CCGR157_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49E8++0x03
line.long 0x00 "CCGR158_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49F8++0x03
line.long 0x00 "CCGR159_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A08++0x03
line.long 0x00 "CCGR160_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A18++0x03
line.long 0x00 "CCGR161_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A28++0x03
line.long 0x00 "CCGR162_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A38++0x03
line.long 0x00 "CCGR163_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A48++0x03
line.long 0x00 "CCGR164_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A58++0x03
line.long 0x00 "CCGR165_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A68++0x03
line.long 0x00 "CCGR166_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A78++0x03
line.long 0x00 "CCGR167_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A88++0x03
line.long 0x00 "CCGR168_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A98++0x03
line.long 0x00 "CCGR169_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AA8++0x03
line.long 0x00 "CCGR170_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AB8++0x03
line.long 0x00 "CCGR171_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AC8++0x03
line.long 0x00 "CCGR172_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AD8++0x03
line.long 0x00 "CCGR173_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AE8++0x03
line.long 0x00 "CCGR174_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AF8++0x03
line.long 0x00 "CCGR175_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B08++0x03
line.long 0x00 "CCGR176_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B18++0x03
line.long 0x00 "CCGR177_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B28++0x03
line.long 0x00 "CCGR178_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B38++0x03
line.long 0x00 "CCGR179_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B48++0x03
line.long 0x00 "CCGR180_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B58++0x03
line.long 0x00 "CCGR181_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B68++0x03
line.long 0x00 "CCGR182_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B78++0x03
line.long 0x00 "CCGR183_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B88++0x03
line.long 0x00 "CCGR184_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B98++0x03
line.long 0x00 "CCGR185_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BA8++0x03
line.long 0x00 "CCGR186_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BB8++0x03
line.long 0x00 "CCGR187_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BC8++0x03
line.long 0x00 "CCGR188_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BD8++0x03
line.long 0x00 "CCGR189_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BE8++0x03
line.long 0x00 "CCGR190_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BF8++0x03
line.long 0x00 "CCGR191_CLR,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x400C++0x03
line.long 0x00 "CCGR0_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x401C++0x03
line.long 0x00 "CCGR1_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x402C++0x03
line.long 0x00 "CCGR2_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x403C++0x03
line.long 0x00 "CCGR3_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x404C++0x03
line.long 0x00 "CCGR4_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x405C++0x03
line.long 0x00 "CCGR5_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x406C++0x03
line.long 0x00 "CCGR6_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x407C++0x03
line.long 0x00 "CCGR7_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x408C++0x03
line.long 0x00 "CCGR8_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x409C++0x03
line.long 0x00 "CCGR9_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40AC++0x03
line.long 0x00 "CCGR10_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40BC++0x03
line.long 0x00 "CCGR11_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40CC++0x03
line.long 0x00 "CCGR12_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40DC++0x03
line.long 0x00 "CCGR13_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40EC++0x03
line.long 0x00 "CCGR14_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x40FC++0x03
line.long 0x00 "CCGR15_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x410C++0x03
line.long 0x00 "CCGR16_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x411C++0x03
line.long 0x00 "CCGR17_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x412C++0x03
line.long 0x00 "CCGR18_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x413C++0x03
line.long 0x00 "CCGR19_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x414C++0x03
line.long 0x00 "CCGR20_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x415C++0x03
line.long 0x00 "CCGR21_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x416C++0x03
line.long 0x00 "CCGR22_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x417C++0x03
line.long 0x00 "CCGR23_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x418C++0x03
line.long 0x00 "CCGR24_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x419C++0x03
line.long 0x00 "CCGR25_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41AC++0x03
line.long 0x00 "CCGR26_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41BC++0x03
line.long 0x00 "CCGR27_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41CC++0x03
line.long 0x00 "CCGR28_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41DC++0x03
line.long 0x00 "CCGR29_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41EC++0x03
line.long 0x00 "CCGR30_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x41FC++0x03
line.long 0x00 "CCGR31_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x420C++0x03
line.long 0x00 "CCGR32_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x421C++0x03
line.long 0x00 "CCGR33_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x422C++0x03
line.long 0x00 "CCGR34_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x423C++0x03
line.long 0x00 "CCGR35_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x424C++0x03
line.long 0x00 "CCGR36_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x425C++0x03
line.long 0x00 "CCGR37_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x426C++0x03
line.long 0x00 "CCGR38_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x427C++0x03
line.long 0x00 "CCGR39_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x428C++0x03
line.long 0x00 "CCGR40_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x429C++0x03
line.long 0x00 "CCGR41_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42AC++0x03
line.long 0x00 "CCGR42_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42BC++0x03
line.long 0x00 "CCGR43_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42CC++0x03
line.long 0x00 "CCGR44_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42DC++0x03
line.long 0x00 "CCGR45_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42EC++0x03
line.long 0x00 "CCGR46_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x42FC++0x03
line.long 0x00 "CCGR47_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x430C++0x03
line.long 0x00 "CCGR48_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x431C++0x03
line.long 0x00 "CCGR49_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x432C++0x03
line.long 0x00 "CCGR50_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x433C++0x03
line.long 0x00 "CCGR51_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x434C++0x03
line.long 0x00 "CCGR52_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x435C++0x03
line.long 0x00 "CCGR53_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x436C++0x03
line.long 0x00 "CCGR54_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x437C++0x03
line.long 0x00 "CCGR55_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x438C++0x03
line.long 0x00 "CCGR56_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x439C++0x03
line.long 0x00 "CCGR57_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43AC++0x03
line.long 0x00 "CCGR58_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43BC++0x03
line.long 0x00 "CCGR59_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43CC++0x03
line.long 0x00 "CCGR60_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43DC++0x03
line.long 0x00 "CCGR61_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43EC++0x03
line.long 0x00 "CCGR62_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x43FC++0x03
line.long 0x00 "CCGR63_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x440C++0x03
line.long 0x00 "CCGR64_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x441C++0x03
line.long 0x00 "CCGR65_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x442C++0x03
line.long 0x00 "CCGR66_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x443C++0x03
line.long 0x00 "CCGR67_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x444C++0x03
line.long 0x00 "CCGR68_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x445C++0x03
line.long 0x00 "CCGR69_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x446C++0x03
line.long 0x00 "CCGR70_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x447C++0x03
line.long 0x00 "CCGR71_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x448C++0x03
line.long 0x00 "CCGR72_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x449C++0x03
line.long 0x00 "CCGR73_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44AC++0x03
line.long 0x00 "CCGR74_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44BC++0x03
line.long 0x00 "CCGR75_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44CC++0x03
line.long 0x00 "CCGR76_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44DC++0x03
line.long 0x00 "CCGR77_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44EC++0x03
line.long 0x00 "CCGR78_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x44FC++0x03
line.long 0x00 "CCGR79_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x450C++0x03
line.long 0x00 "CCGR80_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x451C++0x03
line.long 0x00 "CCGR81_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x452C++0x03
line.long 0x00 "CCGR82_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x453C++0x03
line.long 0x00 "CCGR83_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x454C++0x03
line.long 0x00 "CCGR84_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x455C++0x03
line.long 0x00 "CCGR85_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x456C++0x03
line.long 0x00 "CCGR86_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x457C++0x03
line.long 0x00 "CCGR87_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x458C++0x03
line.long 0x00 "CCGR88_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x459C++0x03
line.long 0x00 "CCGR89_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45AC++0x03
line.long 0x00 "CCGR90_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45BC++0x03
line.long 0x00 "CCGR91_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45CC++0x03
line.long 0x00 "CCGR92_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45DC++0x03
line.long 0x00 "CCGR93_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45EC++0x03
line.long 0x00 "CCGR94_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x45FC++0x03
line.long 0x00 "CCGR95_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x460C++0x03
line.long 0x00 "CCGR96_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x461C++0x03
line.long 0x00 "CCGR97_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x462C++0x03
line.long 0x00 "CCGR98_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x463C++0x03
line.long 0x00 "CCGR99_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x464C++0x03
line.long 0x00 "CCGR100_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x465C++0x03
line.long 0x00 "CCGR101_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x466C++0x03
line.long 0x00 "CCGR102_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x467C++0x03
line.long 0x00 "CCGR103_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x468C++0x03
line.long 0x00 "CCGR104_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x469C++0x03
line.long 0x00 "CCGR105_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46AC++0x03
line.long 0x00 "CCGR106_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46BC++0x03
line.long 0x00 "CCGR107_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46CC++0x03
line.long 0x00 "CCGR108_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46DC++0x03
line.long 0x00 "CCGR109_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46EC++0x03
line.long 0x00 "CCGR110_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x46FC++0x03
line.long 0x00 "CCGR111_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x470C++0x03
line.long 0x00 "CCGR112_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x471C++0x03
line.long 0x00 "CCGR113_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x472C++0x03
line.long 0x00 "CCGR114_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x473C++0x03
line.long 0x00 "CCGR115_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x474C++0x03
line.long 0x00 "CCGR116_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x475C++0x03
line.long 0x00 "CCGR117_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x476C++0x03
line.long 0x00 "CCGR118_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x477C++0x03
line.long 0x00 "CCGR119_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x478C++0x03
line.long 0x00 "CCGR120_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x479C++0x03
line.long 0x00 "CCGR121_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47AC++0x03
line.long 0x00 "CCGR122_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47BC++0x03
line.long 0x00 "CCGR123_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47CC++0x03
line.long 0x00 "CCGR124_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47DC++0x03
line.long 0x00 "CCGR125_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47EC++0x03
line.long 0x00 "CCGR126_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x47FC++0x03
line.long 0x00 "CCGR127_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x480C++0x03
line.long 0x00 "CCGR128_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x481C++0x03
line.long 0x00 "CCGR129_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x482C++0x03
line.long 0x00 "CCGR130_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x483C++0x03
line.long 0x00 "CCGR131_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x484C++0x03
line.long 0x00 "CCGR132_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x485C++0x03
line.long 0x00 "CCGR133_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x486C++0x03
line.long 0x00 "CCGR134_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x487C++0x03
line.long 0x00 "CCGR135_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x488C++0x03
line.long 0x00 "CCGR136_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x489C++0x03
line.long 0x00 "CCGR137_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48AC++0x03
line.long 0x00 "CCGR138_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48BC++0x03
line.long 0x00 "CCGR139_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48CC++0x03
line.long 0x00 "CCGR140_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48DC++0x03
line.long 0x00 "CCGR141_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48EC++0x03
line.long 0x00 "CCGR142_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x48FC++0x03
line.long 0x00 "CCGR143_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x490C++0x03
line.long 0x00 "CCGR144_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x491C++0x03
line.long 0x00 "CCGR145_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x492C++0x03
line.long 0x00 "CCGR146_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x493C++0x03
line.long 0x00 "CCGR147_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x494C++0x03
line.long 0x00 "CCGR148_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x495C++0x03
line.long 0x00 "CCGR149_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x496C++0x03
line.long 0x00 "CCGR150_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x497C++0x03
line.long 0x00 "CCGR151_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x498C++0x03
line.long 0x00 "CCGR152_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x499C++0x03
line.long 0x00 "CCGR153_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49AC++0x03
line.long 0x00 "CCGR154_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49BC++0x03
line.long 0x00 "CCGR155_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49CC++0x03
line.long 0x00 "CCGR156_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49DC++0x03
line.long 0x00 "CCGR157_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49EC++0x03
line.long 0x00 "CCGR158_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x49FC++0x03
line.long 0x00 "CCGR159_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A0C++0x03
line.long 0x00 "CCGR160_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A1C++0x03
line.long 0x00 "CCGR161_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A2C++0x03
line.long 0x00 "CCGR162_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A3C++0x03
line.long 0x00 "CCGR163_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A4C++0x03
line.long 0x00 "CCGR164_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A5C++0x03
line.long 0x00 "CCGR165_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A6C++0x03
line.long 0x00 "CCGR166_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A7C++0x03
line.long 0x00 "CCGR167_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A8C++0x03
line.long 0x00 "CCGR168_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4A9C++0x03
line.long 0x00 "CCGR169_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AAC++0x03
line.long 0x00 "CCGR170_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4ABC++0x03
line.long 0x00 "CCGR171_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4ACC++0x03
line.long 0x00 "CCGR172_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4ADC++0x03
line.long 0x00 "CCGR173_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AEC++0x03
line.long 0x00 "CCGR174_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4AFC++0x03
line.long 0x00 "CCGR175_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B0C++0x03
line.long 0x00 "CCGR176_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B1C++0x03
line.long 0x00 "CCGR177_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B2C++0x03
line.long 0x00 "CCGR178_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B3C++0x03
line.long 0x00 "CCGR179_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B4C++0x03
line.long 0x00 "CCGR180_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B5C++0x03
line.long 0x00 "CCGR181_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B6C++0x03
line.long 0x00 "CCGR182_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B7C++0x03
line.long 0x00 "CCGR183_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B8C++0x03
line.long 0x00 "CCGR184_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4B9C++0x03
line.long 0x00 "CCGR185_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BAC++0x03
line.long 0x00 "CCGR186_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BBC++0x03
line.long 0x00 "CCGR187_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
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bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BCC++0x03
line.long 0x00 "CCGR188_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BDC++0x03
line.long 0x00 "CCGR189_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BEC++0x03
line.long 0x00 "CCGR190_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x4BFC++0x03
line.long 0x00 "CCGR191_TOG,CCM Clock Gating Register"
bitfld.long 0x00 12.--13. "SETTING3,Clock gate control setting for domain 3" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 8.--9. "SETTING2,Clock gate control setting for domain 2" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
newline
bitfld.long 0x00 4.--5. "SETTING1,Clock gate control setting for domain 1" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
bitfld.long 0x00 0.--1. "SETTING0,Clock gate control setting for domain 0" "0: Domain clocks not needed,1: Domain clocks needed when in RUN,2: Domain clocks needed when in RUN and WAIT,3: Domain clocks needed all the time"
group.long 0x8000++0x03
line.long 0x00 "TARGET_ROOT0,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8004++0x03
line.long 0x00 "TARGET_ROOT0_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8008++0x03
line.long 0x00 "TARGET_ROOT0_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x800C++0x03
line.long 0x00 "TARGET_ROOT0_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8010++0x03
line.long 0x00 "MISC0,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8014++0x03
line.long 0x00 "MISC_ROOT0_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8018++0x03
line.long 0x00 "MISC_ROOT0_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x801C++0x03
line.long 0x00 "MISC_ROOT0_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8020++0x03
line.long 0x00 "POST0,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8024++0x03
line.long 0x00 "POST_ROOT0_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8028++0x03
line.long 0x00 "POST_ROOT0_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x802C++0x03
line.long 0x00 "POST_ROOT0_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8030++0x03
line.long 0x00 "PRE0,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8034++0x03
line.long 0x00 "PRE_ROOT0_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8038++0x03
line.long 0x00 "PRE_ROOT0_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x803C++0x03
line.long 0x00 "PRE_ROOT0_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8070++0x03
line.long 0x00 "ACCESS_CTRL0,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8074++0x03
line.long 0x00 "ACCESS_CTRL_ROOT0_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8078++0x03
line.long 0x00 "ACCESS_CTRL_ROOT0_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x807C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT0_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8080++0x03
line.long 0x00 "TARGET_ROOT1,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8084++0x03
line.long 0x00 "TARGET_ROOT1_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8088++0x03
line.long 0x00 "TARGET_ROOT1_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x808C++0x03
line.long 0x00 "TARGET_ROOT1_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8090++0x03
line.long 0x00 "MISC1,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8094++0x03
line.long 0x00 "MISC_ROOT1_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8098++0x03
line.long 0x00 "MISC_ROOT1_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x809C++0x03
line.long 0x00 "MISC_ROOT1_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x80A0++0x03
line.long 0x00 "POST1,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x80A4++0x03
line.long 0x00 "POST_ROOT1_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x80A8++0x03
line.long 0x00 "POST_ROOT1_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x80AC++0x03
line.long 0x00 "POST_ROOT1_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x80B0++0x03
line.long 0x00 "PRE1,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x80B4++0x03
line.long 0x00 "PRE_ROOT1_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x80B8++0x03
line.long 0x00 "PRE_ROOT1_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x80BC++0x03
line.long 0x00 "PRE_ROOT1_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x80F0++0x03
line.long 0x00 "ACCESS_CTRL1,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT1_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT1_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT1_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8100++0x03
line.long 0x00 "TARGET_ROOT2,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8104++0x03
line.long 0x00 "TARGET_ROOT2_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8108++0x03
line.long 0x00 "TARGET_ROOT2_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x810C++0x03
line.long 0x00 "TARGET_ROOT2_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8110++0x03
line.long 0x00 "MISC2,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8114++0x03
line.long 0x00 "MISC_ROOT2_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8118++0x03
line.long 0x00 "MISC_ROOT2_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x811C++0x03
line.long 0x00 "MISC_ROOT2_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8120++0x03
line.long 0x00 "POST2,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8124++0x03
line.long 0x00 "POST_ROOT2_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8128++0x03
line.long 0x00 "POST_ROOT2_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x812C++0x03
line.long 0x00 "POST_ROOT2_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8130++0x03
line.long 0x00 "PRE2,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8134++0x03
line.long 0x00 "PRE_ROOT2_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8138++0x03
line.long 0x00 "PRE_ROOT2_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x813C++0x03
line.long 0x00 "PRE_ROOT2_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8170++0x03
line.long 0x00 "ACCESS_CTRL2,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8174++0x03
line.long 0x00 "ACCESS_CTRL_ROOT2_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8178++0x03
line.long 0x00 "ACCESS_CTRL_ROOT2_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x817C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT2_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8180++0x03
line.long 0x00 "TARGET_ROOT3,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8184++0x03
line.long 0x00 "TARGET_ROOT3_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8188++0x03
line.long 0x00 "TARGET_ROOT3_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x818C++0x03
line.long 0x00 "TARGET_ROOT3_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8190++0x03
line.long 0x00 "MISC3,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8194++0x03
line.long 0x00 "MISC_ROOT3_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8198++0x03
line.long 0x00 "MISC_ROOT3_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x819C++0x03
line.long 0x00 "MISC_ROOT3_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x81A0++0x03
line.long 0x00 "POST3,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x81A4++0x03
line.long 0x00 "POST_ROOT3_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x81A8++0x03
line.long 0x00 "POST_ROOT3_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x81AC++0x03
line.long 0x00 "POST_ROOT3_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x81B0++0x03
line.long 0x00 "PRE3,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x81B4++0x03
line.long 0x00 "PRE_ROOT3_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x81B8++0x03
line.long 0x00 "PRE_ROOT3_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x81BC++0x03
line.long 0x00 "PRE_ROOT3_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x81F0++0x03
line.long 0x00 "ACCESS_CTRL3,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x81F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT3_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x81F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT3_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x81FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT3_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8200++0x03
line.long 0x00 "TARGET_ROOT4,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8204++0x03
line.long 0x00 "TARGET_ROOT4_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8208++0x03
line.long 0x00 "TARGET_ROOT4_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x820C++0x03
line.long 0x00 "TARGET_ROOT4_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8210++0x03
line.long 0x00 "MISC4,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8214++0x03
line.long 0x00 "MISC_ROOT4_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8218++0x03
line.long 0x00 "MISC_ROOT4_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x821C++0x03
line.long 0x00 "MISC_ROOT4_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8220++0x03
line.long 0x00 "POST4,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8224++0x03
line.long 0x00 "POST_ROOT4_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8228++0x03
line.long 0x00 "POST_ROOT4_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x822C++0x03
line.long 0x00 "POST_ROOT4_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8230++0x03
line.long 0x00 "PRE4,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8234++0x03
line.long 0x00 "PRE_ROOT4_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8238++0x03
line.long 0x00 "PRE_ROOT4_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x823C++0x03
line.long 0x00 "PRE_ROOT4_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8270++0x03
line.long 0x00 "ACCESS_CTRL4,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8274++0x03
line.long 0x00 "ACCESS_CTRL_ROOT4_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8278++0x03
line.long 0x00 "ACCESS_CTRL_ROOT4_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x827C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT4_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8280++0x03
line.long 0x00 "TARGET_ROOT5,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8284++0x03
line.long 0x00 "TARGET_ROOT5_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8288++0x03
line.long 0x00 "TARGET_ROOT5_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x828C++0x03
line.long 0x00 "TARGET_ROOT5_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8290++0x03
line.long 0x00 "MISC5,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8294++0x03
line.long 0x00 "MISC_ROOT5_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8298++0x03
line.long 0x00 "MISC_ROOT5_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x829C++0x03
line.long 0x00 "MISC_ROOT5_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x82A0++0x03
line.long 0x00 "POST5,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x82A4++0x03
line.long 0x00 "POST_ROOT5_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x82A8++0x03
line.long 0x00 "POST_ROOT5_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x82AC++0x03
line.long 0x00 "POST_ROOT5_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x82B0++0x03
line.long 0x00 "PRE5,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x82B4++0x03
line.long 0x00 "PRE_ROOT5_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x82B8++0x03
line.long 0x00 "PRE_ROOT5_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x82BC++0x03
line.long 0x00 "PRE_ROOT5_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x82F0++0x03
line.long 0x00 "ACCESS_CTRL5,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x82F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT5_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x82F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT5_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x82FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT5_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8300++0x03
line.long 0x00 "TARGET_ROOT6,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8304++0x03
line.long 0x00 "TARGET_ROOT6_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8308++0x03
line.long 0x00 "TARGET_ROOT6_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x830C++0x03
line.long 0x00 "TARGET_ROOT6_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8310++0x03
line.long 0x00 "MISC6,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8314++0x03
line.long 0x00 "MISC_ROOT6_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8318++0x03
line.long 0x00 "MISC_ROOT6_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x831C++0x03
line.long 0x00 "MISC_ROOT6_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8320++0x03
line.long 0x00 "POST6,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8324++0x03
line.long 0x00 "POST_ROOT6_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8328++0x03
line.long 0x00 "POST_ROOT6_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x832C++0x03
line.long 0x00 "POST_ROOT6_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8330++0x03
line.long 0x00 "PRE6,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8334++0x03
line.long 0x00 "PRE_ROOT6_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8338++0x03
line.long 0x00 "PRE_ROOT6_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x833C++0x03
line.long 0x00 "PRE_ROOT6_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8370++0x03
line.long 0x00 "ACCESS_CTRL6,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8374++0x03
line.long 0x00 "ACCESS_CTRL_ROOT6_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8378++0x03
line.long 0x00 "ACCESS_CTRL_ROOT6_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x837C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT6_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8380++0x03
line.long 0x00 "TARGET_ROOT7,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8384++0x03
line.long 0x00 "TARGET_ROOT7_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8388++0x03
line.long 0x00 "TARGET_ROOT7_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x838C++0x03
line.long 0x00 "TARGET_ROOT7_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8390++0x03
line.long 0x00 "MISC7,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8394++0x03
line.long 0x00 "MISC_ROOT7_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8398++0x03
line.long 0x00 "MISC_ROOT7_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x839C++0x03
line.long 0x00 "MISC_ROOT7_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x83A0++0x03
line.long 0x00 "POST7,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x83A4++0x03
line.long 0x00 "POST_ROOT7_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x83A8++0x03
line.long 0x00 "POST_ROOT7_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x83AC++0x03
line.long 0x00 "POST_ROOT7_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x83B0++0x03
line.long 0x00 "PRE7,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x83B4++0x03
line.long 0x00 "PRE_ROOT7_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x83B8++0x03
line.long 0x00 "PRE_ROOT7_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x83BC++0x03
line.long 0x00 "PRE_ROOT7_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x83F0++0x03
line.long 0x00 "ACCESS_CTRL7,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x83F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT7_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x83F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT7_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x83FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT7_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8400++0x03
line.long 0x00 "TARGET_ROOT8,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8404++0x03
line.long 0x00 "TARGET_ROOT8_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8408++0x03
line.long 0x00 "TARGET_ROOT8_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x840C++0x03
line.long 0x00 "TARGET_ROOT8_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources Please see Clock Root Selects for clock root offsets and muxing information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8410++0x03
line.long 0x00 "MISC8,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8414++0x03
line.long 0x00 "MISC_ROOT8_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8418++0x03
line.long 0x00 "MISC_ROOT8_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x841C++0x03
line.long 0x00 "MISC_ROOT8_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8420++0x03
line.long 0x00 "POST8,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8424++0x03
line.long 0x00 "POST_ROOT8_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8428++0x03
line.long 0x00 "POST_ROOT8_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x842C++0x03
line.long 0x00 "POST_ROOT8_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of post clock branches This field is not applicable to Peripheral (IP) Clock Slice see Peripheral clock slicePeripheral clock slice" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8430++0x03
line.long 0x00 "PRE8,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8434++0x03
line.long 0x00 "PRE_ROOT8_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8438++0x03
line.long 0x00 "PRE_ROOT8_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x843C++0x03
line.long 0x00 "PRE_ROOT8_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8470++0x03
line.long 0x00 "ACCESS_CTRL8,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8474++0x03
line.long 0x00 "ACCESS_CTRL_ROOT8_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8478++0x03
line.long 0x00 "ACCESS_CTRL_ROOT8_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x847C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT8_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8800++0x03
line.long 0x00 "TARGET_ROOT16,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8804++0x03
line.long 0x00 "TARGET_ROOT16_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8808++0x03
line.long 0x00 "TARGET_ROOT16_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x880C++0x03
line.long 0x00 "TARGET_ROOT16_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8810++0x03
line.long 0x00 "MISC16,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8814++0x03
line.long 0x00 "MISC_ROOT16_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8818++0x03
line.long 0x00 "MISC_ROOT16_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x881C++0x03
line.long 0x00 "MISC_ROOT16_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8820++0x03
line.long 0x00 "POST16,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8824++0x03
line.long 0x00 "POST_ROOT16_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8828++0x03
line.long 0x00 "POST_ROOT16_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x882C++0x03
line.long 0x00 "POST_ROOT16_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8830++0x03
line.long 0x00 "PRE16,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8834++0x03
line.long 0x00 "PRE_ROOT16_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8838++0x03
line.long 0x00 "PRE_ROOT16_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x883C++0x03
line.long 0x00 "PRE_ROOT16_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8870++0x03
line.long 0x00 "ACCESS_CTRL16,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8874++0x03
line.long 0x00 "ACCESS_CTRL_ROOT16_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8878++0x03
line.long 0x00 "ACCESS_CTRL_ROOT16_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x887C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT16_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8880++0x03
line.long 0x00 "TARGET_ROOT17,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8884++0x03
line.long 0x00 "TARGET_ROOT17_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8888++0x03
line.long 0x00 "TARGET_ROOT17_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x888C++0x03
line.long 0x00 "TARGET_ROOT17_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8890++0x03
line.long 0x00 "MISC17,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8894++0x03
line.long 0x00 "MISC_ROOT17_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8898++0x03
line.long 0x00 "MISC_ROOT17_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x889C++0x03
line.long 0x00 "MISC_ROOT17_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x88A0++0x03
line.long 0x00 "POST17,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x88A4++0x03
line.long 0x00 "POST_ROOT17_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x88A8++0x03
line.long 0x00 "POST_ROOT17_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x88AC++0x03
line.long 0x00 "POST_ROOT17_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x88B0++0x03
line.long 0x00 "PRE17,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x88B4++0x03
line.long 0x00 "PRE_ROOT17_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x88B8++0x03
line.long 0x00 "PRE_ROOT17_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x88BC++0x03
line.long 0x00 "PRE_ROOT17_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x88F0++0x03
line.long 0x00 "ACCESS_CTRL17,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x88F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT17_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x88F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT17_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x88FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT17_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8900++0x03
line.long 0x00 "TARGET_ROOT18,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8904++0x03
line.long 0x00 "TARGET_ROOT18_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8908++0x03
line.long 0x00 "TARGET_ROOT18_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x890C++0x03
line.long 0x00 "TARGET_ROOT18_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8910++0x03
line.long 0x00 "MISC18,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8914++0x03
line.long 0x00 "MISC_ROOT18_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8918++0x03
line.long 0x00 "MISC_ROOT18_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x891C++0x03
line.long 0x00 "MISC_ROOT18_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8920++0x03
line.long 0x00 "POST18,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8924++0x03
line.long 0x00 "POST_ROOT18_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8928++0x03
line.long 0x00 "POST_ROOT18_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x892C++0x03
line.long 0x00 "POST_ROOT18_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8930++0x03
line.long 0x00 "PRE18,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8934++0x03
line.long 0x00 "PRE_ROOT18_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8938++0x03
line.long 0x00 "PRE_ROOT18_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x893C++0x03
line.long 0x00 "PRE_ROOT18_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8970++0x03
line.long 0x00 "ACCESS_CTRL18,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8974++0x03
line.long 0x00 "ACCESS_CTRL_ROOT18_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8978++0x03
line.long 0x00 "ACCESS_CTRL_ROOT18_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x897C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT18_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8980++0x03
line.long 0x00 "TARGET_ROOT19,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8984++0x03
line.long 0x00 "TARGET_ROOT19_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8988++0x03
line.long 0x00 "TARGET_ROOT19_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x898C++0x03
line.long 0x00 "TARGET_ROOT19_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8990++0x03
line.long 0x00 "MISC19,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8994++0x03
line.long 0x00 "MISC_ROOT19_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8998++0x03
line.long 0x00 "MISC_ROOT19_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x899C++0x03
line.long 0x00 "MISC_ROOT19_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x89A0++0x03
line.long 0x00 "POST19,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x89A4++0x03
line.long 0x00 "POST_ROOT19_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x89A8++0x03
line.long 0x00 "POST_ROOT19_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x89AC++0x03
line.long 0x00 "POST_ROOT19_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x89B0++0x03
line.long 0x00 "PRE19,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x89B4++0x03
line.long 0x00 "PRE_ROOT19_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x89B8++0x03
line.long 0x00 "PRE_ROOT19_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x89BC++0x03
line.long 0x00 "PRE_ROOT19_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x89F0++0x03
line.long 0x00 "ACCESS_CTRL19,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x89F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT19_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x89F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT19_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x89FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT19_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8A00++0x03
line.long 0x00 "TARGET_ROOT20,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A04++0x03
line.long 0x00 "TARGET_ROOT20_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A08++0x03
line.long 0x00 "TARGET_ROOT20_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A0C++0x03
line.long 0x00 "TARGET_ROOT20_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A10++0x03
line.long 0x00 "MISC20,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8A14++0x03
line.long 0x00 "MISC_ROOT20_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8A18++0x03
line.long 0x00 "MISC_ROOT20_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8A1C++0x03
line.long 0x00 "MISC_ROOT20_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8A20++0x03
line.long 0x00 "POST20,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A24++0x03
line.long 0x00 "POST_ROOT20_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A28++0x03
line.long 0x00 "POST_ROOT20_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A2C++0x03
line.long 0x00 "POST_ROOT20_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A30++0x03
line.long 0x00 "PRE20,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8A34++0x03
line.long 0x00 "PRE_ROOT20_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8A38++0x03
line.long 0x00 "PRE_ROOT20_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8A3C++0x03
line.long 0x00 "PRE_ROOT20_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8A70++0x03
line.long 0x00 "ACCESS_CTRL20,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8A74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT20_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8A78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT20_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8A7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT20_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8A80++0x03
line.long 0x00 "TARGET_ROOT21,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A84++0x03
line.long 0x00 "TARGET_ROOT21_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A88++0x03
line.long 0x00 "TARGET_ROOT21_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A8C++0x03
line.long 0x00 "TARGET_ROOT21_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8A90++0x03
line.long 0x00 "MISC21,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8A94++0x03
line.long 0x00 "MISC_ROOT21_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8A98++0x03
line.long 0x00 "MISC_ROOT21_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8A9C++0x03
line.long 0x00 "MISC_ROOT21_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8AA0++0x03
line.long 0x00 "POST21,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8AA4++0x03
line.long 0x00 "POST_ROOT21_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8AA8++0x03
line.long 0x00 "POST_ROOT21_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8AAC++0x03
line.long 0x00 "POST_ROOT21_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8AB0++0x03
line.long 0x00 "PRE21,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8AB4++0x03
line.long 0x00 "PRE_ROOT21_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8AB8++0x03
line.long 0x00 "PRE_ROOT21_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8ABC++0x03
line.long 0x00 "PRE_ROOT21_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8AF0++0x03
line.long 0x00 "ACCESS_CTRL21,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8AF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT21_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8AF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT21_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8AFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT21_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8B00++0x03
line.long 0x00 "TARGET_ROOT22,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B04++0x03
line.long 0x00 "TARGET_ROOT22_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B08++0x03
line.long 0x00 "TARGET_ROOT22_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B0C++0x03
line.long 0x00 "TARGET_ROOT22_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B10++0x03
line.long 0x00 "MISC22,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8B14++0x03
line.long 0x00 "MISC_ROOT22_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8B18++0x03
line.long 0x00 "MISC_ROOT22_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8B1C++0x03
line.long 0x00 "MISC_ROOT22_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8B20++0x03
line.long 0x00 "POST22,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B24++0x03
line.long 0x00 "POST_ROOT22_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B28++0x03
line.long 0x00 "POST_ROOT22_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B2C++0x03
line.long 0x00 "POST_ROOT22_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B30++0x03
line.long 0x00 "PRE22,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8B34++0x03
line.long 0x00 "PRE_ROOT22_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8B38++0x03
line.long 0x00 "PRE_ROOT22_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8B3C++0x03
line.long 0x00 "PRE_ROOT22_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8B70++0x03
line.long 0x00 "ACCESS_CTRL22,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8B74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT22_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8B78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT22_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8B7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT22_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8B80++0x03
line.long 0x00 "TARGET_ROOT23,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B84++0x03
line.long 0x00 "TARGET_ROOT23_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B88++0x03
line.long 0x00 "TARGET_ROOT23_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B8C++0x03
line.long 0x00 "TARGET_ROOT23_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8B90++0x03
line.long 0x00 "MISC23,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8B94++0x03
line.long 0x00 "MISC_ROOT23_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8B98++0x03
line.long 0x00 "MISC_ROOT23_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8B9C++0x03
line.long 0x00 "MISC_ROOT23_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8BA0++0x03
line.long 0x00 "POST23,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8BA4++0x03
line.long 0x00 "POST_ROOT23_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8BA8++0x03
line.long 0x00 "POST_ROOT23_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8BAC++0x03
line.long 0x00 "POST_ROOT23_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8BB0++0x03
line.long 0x00 "PRE23,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8BB4++0x03
line.long 0x00 "PRE_ROOT23_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8BB8++0x03
line.long 0x00 "PRE_ROOT23_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8BBC++0x03
line.long 0x00 "PRE_ROOT23_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8BF0++0x03
line.long 0x00 "ACCESS_CTRL23,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8BF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT23_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8BF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT23_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8BFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT23_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C00++0x03
line.long 0x00 "TARGET_ROOT24,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C04++0x03
line.long 0x00 "TARGET_ROOT24_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C08++0x03
line.long 0x00 "TARGET_ROOT24_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C0C++0x03
line.long 0x00 "TARGET_ROOT24_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C10++0x03
line.long 0x00 "MISC24,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8C14++0x03
line.long 0x00 "MISC_ROOT24_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8C18++0x03
line.long 0x00 "MISC_ROOT24_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8C1C++0x03
line.long 0x00 "MISC_ROOT24_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8C20++0x03
line.long 0x00 "POST24,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C24++0x03
line.long 0x00 "POST_ROOT24_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C28++0x03
line.long 0x00 "POST_ROOT24_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C2C++0x03
line.long 0x00 "POST_ROOT24_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C30++0x03
line.long 0x00 "PRE24,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8C34++0x03
line.long 0x00 "PRE_ROOT24_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8C38++0x03
line.long 0x00 "PRE_ROOT24_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8C3C++0x03
line.long 0x00 "PRE_ROOT24_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8C70++0x03
line.long 0x00 "ACCESS_CTRL24,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT24_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT24_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT24_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C80++0x03
line.long 0x00 "TARGET_ROOT25,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C84++0x03
line.long 0x00 "TARGET_ROOT25_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C88++0x03
line.long 0x00 "TARGET_ROOT25_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C8C++0x03
line.long 0x00 "TARGET_ROOT25_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8C90++0x03
line.long 0x00 "MISC25,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8C94++0x03
line.long 0x00 "MISC_ROOT25_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8C98++0x03
line.long 0x00 "MISC_ROOT25_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8C9C++0x03
line.long 0x00 "MISC_ROOT25_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8CA0++0x03
line.long 0x00 "POST25,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8CA4++0x03
line.long 0x00 "POST_ROOT25_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8CA8++0x03
line.long 0x00 "POST_ROOT25_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8CAC++0x03
line.long 0x00 "POST_ROOT25_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8CB0++0x03
line.long 0x00 "PRE25,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8CB4++0x03
line.long 0x00 "PRE_ROOT25_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8CB8++0x03
line.long 0x00 "PRE_ROOT25_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8CBC++0x03
line.long 0x00 "PRE_ROOT25_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8CF0++0x03
line.long 0x00 "ACCESS_CTRL25,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8CF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT25_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8CF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT25_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8CFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT25_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8D00++0x03
line.long 0x00 "TARGET_ROOT26,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D04++0x03
line.long 0x00 "TARGET_ROOT26_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D08++0x03
line.long 0x00 "TARGET_ROOT26_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D0C++0x03
line.long 0x00 "TARGET_ROOT26_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D10++0x03
line.long 0x00 "MISC26,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8D14++0x03
line.long 0x00 "MISC_ROOT26_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8D18++0x03
line.long 0x00 "MISC_ROOT26_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8D1C++0x03
line.long 0x00 "MISC_ROOT26_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8D20++0x03
line.long 0x00 "POST26,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D24++0x03
line.long 0x00 "POST_ROOT26_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D28++0x03
line.long 0x00 "POST_ROOT26_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D2C++0x03
line.long 0x00 "POST_ROOT26_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D30++0x03
line.long 0x00 "PRE26,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8D34++0x03
line.long 0x00 "PRE_ROOT26_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8D38++0x03
line.long 0x00 "PRE_ROOT26_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8D3C++0x03
line.long 0x00 "PRE_ROOT26_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8D70++0x03
line.long 0x00 "ACCESS_CTRL26,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8D74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT26_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8D78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT26_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8D7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT26_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8D80++0x03
line.long 0x00 "TARGET_ROOT27,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D84++0x03
line.long 0x00 "TARGET_ROOT27_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D88++0x03
line.long 0x00 "TARGET_ROOT27_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D8C++0x03
line.long 0x00 "TARGET_ROOT27_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8D90++0x03
line.long 0x00 "MISC27,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8D94++0x03
line.long 0x00 "MISC_ROOT27_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8D98++0x03
line.long 0x00 "MISC_ROOT27_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8D9C++0x03
line.long 0x00 "MISC_ROOT27_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8DA0++0x03
line.long 0x00 "POST27,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8DA4++0x03
line.long 0x00 "POST_ROOT27_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8DA8++0x03
line.long 0x00 "POST_ROOT27_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8DAC++0x03
line.long 0x00 "POST_ROOT27_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8DB0++0x03
line.long 0x00 "PRE27,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8DB4++0x03
line.long 0x00 "PRE_ROOT27_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8DB8++0x03
line.long 0x00 "PRE_ROOT27_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8DBC++0x03
line.long 0x00 "PRE_ROOT27_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8DF0++0x03
line.long 0x00 "ACCESS_CTRL27,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8DF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT27_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8DF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT27_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8DFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT27_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8E00++0x03
line.long 0x00 "TARGET_ROOT28,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E04++0x03
line.long 0x00 "TARGET_ROOT28_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E08++0x03
line.long 0x00 "TARGET_ROOT28_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E0C++0x03
line.long 0x00 "TARGET_ROOT28_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E10++0x03
line.long 0x00 "MISC28,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8E14++0x03
line.long 0x00 "MISC_ROOT28_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8E18++0x03
line.long 0x00 "MISC_ROOT28_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8E1C++0x03
line.long 0x00 "MISC_ROOT28_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8E20++0x03
line.long 0x00 "POST28,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E24++0x03
line.long 0x00 "POST_ROOT28_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E28++0x03
line.long 0x00 "POST_ROOT28_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E2C++0x03
line.long 0x00 "POST_ROOT28_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E30++0x03
line.long 0x00 "PRE28,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8E34++0x03
line.long 0x00 "PRE_ROOT28_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8E38++0x03
line.long 0x00 "PRE_ROOT28_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8E3C++0x03
line.long 0x00 "PRE_ROOT28_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8E70++0x03
line.long 0x00 "ACCESS_CTRL28,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8E74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT28_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8E78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT28_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8E7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT28_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8E80++0x03
line.long 0x00 "TARGET_ROOT29,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E84++0x03
line.long 0x00 "TARGET_ROOT29_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E88++0x03
line.long 0x00 "TARGET_ROOT29_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E8C++0x03
line.long 0x00 "TARGET_ROOT29_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8E90++0x03
line.long 0x00 "MISC29,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8E94++0x03
line.long 0x00 "MISC_ROOT29_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8E98++0x03
line.long 0x00 "MISC_ROOT29_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8E9C++0x03
line.long 0x00 "MISC_ROOT29_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x8EA0++0x03
line.long 0x00 "POST29,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8EA4++0x03
line.long 0x00 "POST_ROOT29_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8EA8++0x03
line.long 0x00 "POST_ROOT29_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8EAC++0x03
line.long 0x00 "POST_ROOT29_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x8EB0++0x03
line.long 0x00 "PRE29,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8EB4++0x03
line.long 0x00 "PRE_ROOT29_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8EB8++0x03
line.long 0x00 "PRE_ROOT29_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8EBC++0x03
line.long 0x00 "PRE_ROOT29_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x8EF0++0x03
line.long 0x00 "ACCESS_CTRL29,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8EF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT29_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8EF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT29_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8EFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT29_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9000++0x03
line.long 0x00 "TARGET_ROOT32,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9004++0x03
line.long 0x00 "TARGET_ROOT32_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9008++0x03
line.long 0x00 "TARGET_ROOT32_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x900C++0x03
line.long 0x00 "TARGET_ROOT32_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9010++0x03
line.long 0x00 "MISC32,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9014++0x03
line.long 0x00 "MISC_ROOT32_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9018++0x03
line.long 0x00 "MISC_ROOT32_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x901C++0x03
line.long 0x00 "MISC_ROOT32_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9020++0x03
line.long 0x00 "POST32,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9024++0x03
line.long 0x00 "POST_ROOT32_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9028++0x03
line.long 0x00 "POST_ROOT32_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x902C++0x03
line.long 0x00 "POST_ROOT32_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9030++0x03
line.long 0x00 "PRE32,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9034++0x03
line.long 0x00 "PRE_ROOT32_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9038++0x03
line.long 0x00 "PRE_ROOT32_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x903C++0x03
line.long 0x00 "PRE_ROOT32_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9070++0x03
line.long 0x00 "ACCESS_CTRL32,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9074++0x03
line.long 0x00 "ACCESS_CTRL_ROOT32_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9078++0x03
line.long 0x00 "ACCESS_CTRL_ROOT32_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x907C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT32_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9080++0x03
line.long 0x00 "TARGET_ROOT33,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9084++0x03
line.long 0x00 "TARGET_ROOT33_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9088++0x03
line.long 0x00 "TARGET_ROOT33_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x908C++0x03
line.long 0x00 "TARGET_ROOT33_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9090++0x03
line.long 0x00 "MISC33,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9094++0x03
line.long 0x00 "MISC_ROOT33_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9098++0x03
line.long 0x00 "MISC_ROOT33_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x909C++0x03
line.long 0x00 "MISC_ROOT33_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x90A0++0x03
line.long 0x00 "POST33,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x90A4++0x03
line.long 0x00 "POST_ROOT33_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x90A8++0x03
line.long 0x00 "POST_ROOT33_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x90AC++0x03
line.long 0x00 "POST_ROOT33_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x90B0++0x03
line.long 0x00 "PRE33,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x90B4++0x03
line.long 0x00 "PRE_ROOT33_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x90B8++0x03
line.long 0x00 "PRE_ROOT33_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x90BC++0x03
line.long 0x00 "PRE_ROOT33_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x90F0++0x03
line.long 0x00 "ACCESS_CTRL33,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT33_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT33_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT33_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9100++0x03
line.long 0x00 "TARGET_ROOT34,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9104++0x03
line.long 0x00 "TARGET_ROOT34_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9108++0x03
line.long 0x00 "TARGET_ROOT34_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x910C++0x03
line.long 0x00 "TARGET_ROOT34_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9110++0x03
line.long 0x00 "MISC34,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9114++0x03
line.long 0x00 "MISC_ROOT34_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9118++0x03
line.long 0x00 "MISC_ROOT34_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x911C++0x03
line.long 0x00 "MISC_ROOT34_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9120++0x03
line.long 0x00 "POST34,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9124++0x03
line.long 0x00 "POST_ROOT34_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9128++0x03
line.long 0x00 "POST_ROOT34_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x912C++0x03
line.long 0x00 "POST_ROOT34_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9130++0x03
line.long 0x00 "PRE34,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9134++0x03
line.long 0x00 "PRE_ROOT34_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9138++0x03
line.long 0x00 "PRE_ROOT34_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x913C++0x03
line.long 0x00 "PRE_ROOT34_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9170++0x03
line.long 0x00 "ACCESS_CTRL34,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9174++0x03
line.long 0x00 "ACCESS_CTRL_ROOT34_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9178++0x03
line.long 0x00 "ACCESS_CTRL_ROOT34_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x917C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT34_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9180++0x03
line.long 0x00 "TARGET_ROOT35,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9184++0x03
line.long 0x00 "TARGET_ROOT35_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9188++0x03
line.long 0x00 "TARGET_ROOT35_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x918C++0x03
line.long 0x00 "TARGET_ROOT35_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9190++0x03
line.long 0x00 "MISC35,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9194++0x03
line.long 0x00 "MISC_ROOT35_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9198++0x03
line.long 0x00 "MISC_ROOT35_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x919C++0x03
line.long 0x00 "MISC_ROOT35_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x91A0++0x03
line.long 0x00 "POST35,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x91A4++0x03
line.long 0x00 "POST_ROOT35_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x91A8++0x03
line.long 0x00 "POST_ROOT35_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x91AC++0x03
line.long 0x00 "POST_ROOT35_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x91B0++0x03
line.long 0x00 "PRE35,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x91B4++0x03
line.long 0x00 "PRE_ROOT35_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x91B8++0x03
line.long 0x00 "PRE_ROOT35_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x91BC++0x03
line.long 0x00 "PRE_ROOT35_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x91F0++0x03
line.long 0x00 "ACCESS_CTRL35,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x91F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT35_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x91F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT35_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x91FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT35_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9200++0x03
line.long 0x00 "TARGET_ROOT36,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9204++0x03
line.long 0x00 "TARGET_ROOT36_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9208++0x03
line.long 0x00 "TARGET_ROOT36_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x920C++0x03
line.long 0x00 "TARGET_ROOT36_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9210++0x03
line.long 0x00 "MISC36,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9214++0x03
line.long 0x00 "MISC_ROOT36_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9218++0x03
line.long 0x00 "MISC_ROOT36_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x921C++0x03
line.long 0x00 "MISC_ROOT36_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9220++0x03
line.long 0x00 "POST36,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9224++0x03
line.long 0x00 "POST_ROOT36_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9228++0x03
line.long 0x00 "POST_ROOT36_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x922C++0x03
line.long 0x00 "POST_ROOT36_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9230++0x03
line.long 0x00 "PRE36,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9234++0x03
line.long 0x00 "PRE_ROOT36_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9238++0x03
line.long 0x00 "PRE_ROOT36_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x923C++0x03
line.long 0x00 "PRE_ROOT36_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9270++0x03
line.long 0x00 "ACCESS_CTRL36,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9274++0x03
line.long 0x00 "ACCESS_CTRL_ROOT36_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9278++0x03
line.long 0x00 "ACCESS_CTRL_ROOT36_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x927C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT36_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9280++0x03
line.long 0x00 "TARGET_ROOT37,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9284++0x03
line.long 0x00 "TARGET_ROOT37_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9288++0x03
line.long 0x00 "TARGET_ROOT37_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x928C++0x03
line.long 0x00 "TARGET_ROOT37_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9290++0x03
line.long 0x00 "MISC37,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9294++0x03
line.long 0x00 "MISC_ROOT37_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9298++0x03
line.long 0x00 "MISC_ROOT37_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x929C++0x03
line.long 0x00 "MISC_ROOT37_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x92A0++0x03
line.long 0x00 "POST37,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x92A4++0x03
line.long 0x00 "POST_ROOT37_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x92A8++0x03
line.long 0x00 "POST_ROOT37_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x92AC++0x03
line.long 0x00 "POST_ROOT37_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x92B0++0x03
line.long 0x00 "PRE37,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x92B4++0x03
line.long 0x00 "PRE_ROOT37_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x92B8++0x03
line.long 0x00 "PRE_ROOT37_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x92BC++0x03
line.long 0x00 "PRE_ROOT37_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x92F0++0x03
line.long 0x00 "ACCESS_CTRL37,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x92F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT37_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x92F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT37_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x92FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT37_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9300++0x03
line.long 0x00 "TARGET_ROOT38,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9304++0x03
line.long 0x00 "TARGET_ROOT38_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9308++0x03
line.long 0x00 "TARGET_ROOT38_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x930C++0x03
line.long 0x00 "TARGET_ROOT38_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9310++0x03
line.long 0x00 "MISC38,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9314++0x03
line.long 0x00 "MISC_ROOT38_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9318++0x03
line.long 0x00 "MISC_ROOT38_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x931C++0x03
line.long 0x00 "MISC_ROOT38_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9320++0x03
line.long 0x00 "POST38,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9324++0x03
line.long 0x00 "POST_ROOT38_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9328++0x03
line.long 0x00 "POST_ROOT38_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x932C++0x03
line.long 0x00 "POST_ROOT38_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9330++0x03
line.long 0x00 "PRE38,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9334++0x03
line.long 0x00 "PRE_ROOT38_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9338++0x03
line.long 0x00 "PRE_ROOT38_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x933C++0x03
line.long 0x00 "PRE_ROOT38_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9370++0x03
line.long 0x00 "ACCESS_CTRL38,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9374++0x03
line.long 0x00 "ACCESS_CTRL_ROOT38_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9378++0x03
line.long 0x00 "ACCESS_CTRL_ROOT38_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x937C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT38_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9380++0x03
line.long 0x00 "TARGET_ROOT39,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9384++0x03
line.long 0x00 "TARGET_ROOT39_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9388++0x03
line.long 0x00 "TARGET_ROOT39_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x938C++0x03
line.long 0x00 "TARGET_ROOT39_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9390++0x03
line.long 0x00 "MISC39,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9394++0x03
line.long 0x00 "MISC_ROOT39_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9398++0x03
line.long 0x00 "MISC_ROOT39_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x939C++0x03
line.long 0x00 "MISC_ROOT39_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x93A0++0x03
line.long 0x00 "POST39,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x93A4++0x03
line.long 0x00 "POST_ROOT39_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x93A8++0x03
line.long 0x00 "POST_ROOT39_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x93AC++0x03
line.long 0x00 "POST_ROOT39_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x93B0++0x03
line.long 0x00 "PRE39,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x93B4++0x03
line.long 0x00 "PRE_ROOT39_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x93B8++0x03
line.long 0x00 "PRE_ROOT39_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x93BC++0x03
line.long 0x00 "PRE_ROOT39_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x93F0++0x03
line.long 0x00 "ACCESS_CTRL39,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x93F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT39_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x93F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT39_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x93FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT39_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9800++0x03
line.long 0x00 "TARGET_ROOT48,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9804++0x03
line.long 0x00 "TARGET_ROOT48_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9808++0x03
line.long 0x00 "TARGET_ROOT48_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x980C++0x03
line.long 0x00 "TARGET_ROOT48_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9810++0x03
line.long 0x00 "MISC48,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9814++0x03
line.long 0x00 "MISC_ROOT48_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9818++0x03
line.long 0x00 "MISC_ROOT48_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x981C++0x03
line.long 0x00 "MISC_ROOT48_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9820++0x03
line.long 0x00 "POST48,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9824++0x03
line.long 0x00 "POST_ROOT48_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9828++0x03
line.long 0x00 "POST_ROOT48_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x982C++0x03
line.long 0x00 "POST_ROOT48_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9830++0x03
line.long 0x00 "PRE48,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9834++0x03
line.long 0x00 "PRE_ROOT48_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9838++0x03
line.long 0x00 "PRE_ROOT48_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x983C++0x03
line.long 0x00 "PRE_ROOT48_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x9870++0x03
line.long 0x00 "ACCESS_CTRL48,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9874++0x03
line.long 0x00 "ACCESS_CTRL_ROOT48_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9878++0x03
line.long 0x00 "ACCESS_CTRL_ROOT48_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x987C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT48_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9880++0x03
line.long 0x00 "TARGET_ROOT49,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9884++0x03
line.long 0x00 "TARGET_ROOT49_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9888++0x03
line.long 0x00 "TARGET_ROOT49_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x988C++0x03
line.long 0x00 "TARGET_ROOT49_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x9890++0x03
line.long 0x00 "MISC49,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9894++0x03
line.long 0x00 "MISC_ROOT49_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x9898++0x03
line.long 0x00 "MISC_ROOT49_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x989C++0x03
line.long 0x00 "MISC_ROOT49_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0x98A0++0x03
line.long 0x00 "POST49,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x98A4++0x03
line.long 0x00 "POST_ROOT49_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x98A8++0x03
line.long 0x00 "POST_ROOT49_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x98AC++0x03
line.long 0x00 "POST_ROOT49_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0x98B0++0x03
line.long 0x00 "PRE49,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x98B4++0x03
line.long 0x00 "PRE_ROOT49_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x98B8++0x03
line.long 0x00 "PRE_ROOT49_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x98BC++0x03
line.long 0x00 "PRE_ROOT49_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0x98F0++0x03
line.long 0x00 "ACCESS_CTRL49,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x98F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT49_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x98F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT49_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x98FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT49_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA000++0x03
line.long 0x00 "TARGET_ROOT64,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA004++0x03
line.long 0x00 "TARGET_ROOT64_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA008++0x03
line.long 0x00 "TARGET_ROOT64_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA00C++0x03
line.long 0x00 "TARGET_ROOT64_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA010++0x03
line.long 0x00 "MISC64,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA014++0x03
line.long 0x00 "MISC_ROOT64_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA018++0x03
line.long 0x00 "MISC_ROOT64_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA01C++0x03
line.long 0x00 "MISC_ROOT64_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA020++0x03
line.long 0x00 "POST64,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA024++0x03
line.long 0x00 "POST_ROOT64_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA028++0x03
line.long 0x00 "POST_ROOT64_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA02C++0x03
line.long 0x00 "POST_ROOT64_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA030++0x03
line.long 0x00 "PRE64,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA034++0x03
line.long 0x00 "PRE_ROOT64_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA038++0x03
line.long 0x00 "PRE_ROOT64_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA03C++0x03
line.long 0x00 "PRE_ROOT64_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA070++0x03
line.long 0x00 "ACCESS_CTRL64,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA074++0x03
line.long 0x00 "ACCESS_CTRL_ROOT64_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA078++0x03
line.long 0x00 "ACCESS_CTRL_ROOT64_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA07C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT64_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA080++0x03
line.long 0x00 "TARGET_ROOT65,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA084++0x03
line.long 0x00 "TARGET_ROOT65_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA088++0x03
line.long 0x00 "TARGET_ROOT65_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA08C++0x03
line.long 0x00 "TARGET_ROOT65_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA090++0x03
line.long 0x00 "MISC65,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA094++0x03
line.long 0x00 "MISC_ROOT65_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA098++0x03
line.long 0x00 "MISC_ROOT65_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA09C++0x03
line.long 0x00 "MISC_ROOT65_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA0A0++0x03
line.long 0x00 "POST65,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA0A4++0x03
line.long 0x00 "POST_ROOT65_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA0A8++0x03
line.long 0x00 "POST_ROOT65_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA0AC++0x03
line.long 0x00 "POST_ROOT65_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA0B0++0x03
line.long 0x00 "PRE65,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA0B4++0x03
line.long 0x00 "PRE_ROOT65_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA0B8++0x03
line.long 0x00 "PRE_ROOT65_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA0BC++0x03
line.long 0x00 "PRE_ROOT65_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA0F0++0x03
line.long 0x00 "ACCESS_CTRL65,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT65_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT65_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT65_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA100++0x03
line.long 0x00 "TARGET_ROOT66,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA104++0x03
line.long 0x00 "TARGET_ROOT66_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA108++0x03
line.long 0x00 "TARGET_ROOT66_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA10C++0x03
line.long 0x00 "TARGET_ROOT66_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA110++0x03
line.long 0x00 "MISC66,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA114++0x03
line.long 0x00 "MISC_ROOT66_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA118++0x03
line.long 0x00 "MISC_ROOT66_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA11C++0x03
line.long 0x00 "MISC_ROOT66_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA120++0x03
line.long 0x00 "POST66,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA124++0x03
line.long 0x00 "POST_ROOT66_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA128++0x03
line.long 0x00 "POST_ROOT66_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA12C++0x03
line.long 0x00 "POST_ROOT66_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA130++0x03
line.long 0x00 "PRE66,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA134++0x03
line.long 0x00 "PRE_ROOT66_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA138++0x03
line.long 0x00 "PRE_ROOT66_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA13C++0x03
line.long 0x00 "PRE_ROOT66_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA170++0x03
line.long 0x00 "ACCESS_CTRL66,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA174++0x03
line.long 0x00 "ACCESS_CTRL_ROOT66_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA178++0x03
line.long 0x00 "ACCESS_CTRL_ROOT66_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA17C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT66_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA180++0x03
line.long 0x00 "TARGET_ROOT67,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA184++0x03
line.long 0x00 "TARGET_ROOT67_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA188++0x03
line.long 0x00 "TARGET_ROOT67_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA18C++0x03
line.long 0x00 "TARGET_ROOT67_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA190++0x03
line.long 0x00 "MISC67,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA194++0x03
line.long 0x00 "MISC_ROOT67_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA198++0x03
line.long 0x00 "MISC_ROOT67_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA19C++0x03
line.long 0x00 "MISC_ROOT67_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA1A0++0x03
line.long 0x00 "POST67,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA1A4++0x03
line.long 0x00 "POST_ROOT67_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA1A8++0x03
line.long 0x00 "POST_ROOT67_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA1AC++0x03
line.long 0x00 "POST_ROOT67_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA1B0++0x03
line.long 0x00 "PRE67,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA1B4++0x03
line.long 0x00 "PRE_ROOT67_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA1B8++0x03
line.long 0x00 "PRE_ROOT67_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA1BC++0x03
line.long 0x00 "PRE_ROOT67_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA1F0++0x03
line.long 0x00 "ACCESS_CTRL67,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA1F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT67_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA1F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT67_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA1FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT67_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA200++0x03
line.long 0x00 "TARGET_ROOT68,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA204++0x03
line.long 0x00 "TARGET_ROOT68_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA208++0x03
line.long 0x00 "TARGET_ROOT68_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA20C++0x03
line.long 0x00 "TARGET_ROOT68_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA210++0x03
line.long 0x00 "MISC68,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA214++0x03
line.long 0x00 "MISC_ROOT68_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA218++0x03
line.long 0x00 "MISC_ROOT68_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA21C++0x03
line.long 0x00 "MISC_ROOT68_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA220++0x03
line.long 0x00 "POST68,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA224++0x03
line.long 0x00 "POST_ROOT68_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA228++0x03
line.long 0x00 "POST_ROOT68_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA22C++0x03
line.long 0x00 "POST_ROOT68_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA230++0x03
line.long 0x00 "PRE68,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA234++0x03
line.long 0x00 "PRE_ROOT68_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA238++0x03
line.long 0x00 "PRE_ROOT68_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA23C++0x03
line.long 0x00 "PRE_ROOT68_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA270++0x03
line.long 0x00 "ACCESS_CTRL68,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA274++0x03
line.long 0x00 "ACCESS_CTRL_ROOT68_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA278++0x03
line.long 0x00 "ACCESS_CTRL_ROOT68_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA27C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT68_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA280++0x03
line.long 0x00 "TARGET_ROOT69,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA284++0x03
line.long 0x00 "TARGET_ROOT69_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA288++0x03
line.long 0x00 "TARGET_ROOT69_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA28C++0x03
line.long 0x00 "TARGET_ROOT69_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA290++0x03
line.long 0x00 "MISC69,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA294++0x03
line.long 0x00 "MISC_ROOT69_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA298++0x03
line.long 0x00 "MISC_ROOT69_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA29C++0x03
line.long 0x00 "MISC_ROOT69_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA2A0++0x03
line.long 0x00 "POST69,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA2A4++0x03
line.long 0x00 "POST_ROOT69_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA2A8++0x03
line.long 0x00 "POST_ROOT69_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA2AC++0x03
line.long 0x00 "POST_ROOT69_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA2B0++0x03
line.long 0x00 "PRE69,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA2B4++0x03
line.long 0x00 "PRE_ROOT69_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA2B8++0x03
line.long 0x00 "PRE_ROOT69_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA2BC++0x03
line.long 0x00 "PRE_ROOT69_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA2F0++0x03
line.long 0x00 "ACCESS_CTRL69,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA2F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT69_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA2F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT69_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA2FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT69_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA300++0x03
line.long 0x00 "TARGET_ROOT70,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA304++0x03
line.long 0x00 "TARGET_ROOT70_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA308++0x03
line.long 0x00 "TARGET_ROOT70_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA30C++0x03
line.long 0x00 "TARGET_ROOT70_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA310++0x03
line.long 0x00 "MISC70,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA314++0x03
line.long 0x00 "MISC_ROOT70_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA318++0x03
line.long 0x00 "MISC_ROOT70_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA31C++0x03
line.long 0x00 "MISC_ROOT70_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA320++0x03
line.long 0x00 "POST70,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA324++0x03
line.long 0x00 "POST_ROOT70_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA328++0x03
line.long 0x00 "POST_ROOT70_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA32C++0x03
line.long 0x00 "POST_ROOT70_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA330++0x03
line.long 0x00 "PRE70,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA334++0x03
line.long 0x00 "PRE_ROOT70_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA338++0x03
line.long 0x00 "PRE_ROOT70_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA33C++0x03
line.long 0x00 "PRE_ROOT70_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA370++0x03
line.long 0x00 "ACCESS_CTRL70,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA374++0x03
line.long 0x00 "ACCESS_CTRL_ROOT70_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA378++0x03
line.long 0x00 "ACCESS_CTRL_ROOT70_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA37C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT70_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA380++0x03
line.long 0x00 "TARGET_ROOT71,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA384++0x03
line.long 0x00 "TARGET_ROOT71_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA388++0x03
line.long 0x00 "TARGET_ROOT71_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA38C++0x03
line.long 0x00 "TARGET_ROOT71_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA390++0x03
line.long 0x00 "MISC71,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA394++0x03
line.long 0x00 "MISC_ROOT71_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA398++0x03
line.long 0x00 "MISC_ROOT71_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA39C++0x03
line.long 0x00 "MISC_ROOT71_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA3A0++0x03
line.long 0x00 "POST71,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA3A4++0x03
line.long 0x00 "POST_ROOT71_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA3A8++0x03
line.long 0x00 "POST_ROOT71_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA3AC++0x03
line.long 0x00 "POST_ROOT71_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA3B0++0x03
line.long 0x00 "PRE71,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA3B4++0x03
line.long 0x00 "PRE_ROOT71_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA3B8++0x03
line.long 0x00 "PRE_ROOT71_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA3BC++0x03
line.long 0x00 "PRE_ROOT71_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA3F0++0x03
line.long 0x00 "ACCESS_CTRL71,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA3F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT71_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA3F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT71_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA3FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT71_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA400++0x03
line.long 0x00 "TARGET_ROOT72,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA404++0x03
line.long 0x00 "TARGET_ROOT72_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA408++0x03
line.long 0x00 "TARGET_ROOT72_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA40C++0x03
line.long 0x00 "TARGET_ROOT72_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA410++0x03
line.long 0x00 "MISC72,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA414++0x03
line.long 0x00 "MISC_ROOT72_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA418++0x03
line.long 0x00 "MISC_ROOT72_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA41C++0x03
line.long 0x00 "MISC_ROOT72_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA420++0x03
line.long 0x00 "POST72,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA424++0x03
line.long 0x00 "POST_ROOT72_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA428++0x03
line.long 0x00 "POST_ROOT72_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA42C++0x03
line.long 0x00 "POST_ROOT72_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA430++0x03
line.long 0x00 "PRE72,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA434++0x03
line.long 0x00 "PRE_ROOT72_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA438++0x03
line.long 0x00 "PRE_ROOT72_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA43C++0x03
line.long 0x00 "PRE_ROOT72_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA470++0x03
line.long 0x00 "ACCESS_CTRL72,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA474++0x03
line.long 0x00 "ACCESS_CTRL_ROOT72_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA478++0x03
line.long 0x00 "ACCESS_CTRL_ROOT72_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA47C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT72_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA480++0x03
line.long 0x00 "TARGET_ROOT73,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA484++0x03
line.long 0x00 "TARGET_ROOT73_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA488++0x03
line.long 0x00 "TARGET_ROOT73_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA48C++0x03
line.long 0x00 "TARGET_ROOT73_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA490++0x03
line.long 0x00 "MISC73,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA494++0x03
line.long 0x00 "MISC_ROOT73_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA498++0x03
line.long 0x00 "MISC_ROOT73_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA49C++0x03
line.long 0x00 "MISC_ROOT73_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA4A0++0x03
line.long 0x00 "POST73,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA4A4++0x03
line.long 0x00 "POST_ROOT73_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA4A8++0x03
line.long 0x00 "POST_ROOT73_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA4AC++0x03
line.long 0x00 "POST_ROOT73_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA4B0++0x03
line.long 0x00 "PRE73,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA4B4++0x03
line.long 0x00 "PRE_ROOT73_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA4B8++0x03
line.long 0x00 "PRE_ROOT73_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA4BC++0x03
line.long 0x00 "PRE_ROOT73_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA4F0++0x03
line.long 0x00 "ACCESS_CTRL73,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA4F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT73_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA4F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT73_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA4FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT73_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA500++0x03
line.long 0x00 "TARGET_ROOT74,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA504++0x03
line.long 0x00 "TARGET_ROOT74_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA508++0x03
line.long 0x00 "TARGET_ROOT74_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA50C++0x03
line.long 0x00 "TARGET_ROOT74_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA510++0x03
line.long 0x00 "MISC74,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA514++0x03
line.long 0x00 "MISC_ROOT74_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA518++0x03
line.long 0x00 "MISC_ROOT74_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA51C++0x03
line.long 0x00 "MISC_ROOT74_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA520++0x03
line.long 0x00 "POST74,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA524++0x03
line.long 0x00 "POST_ROOT74_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA528++0x03
line.long 0x00 "POST_ROOT74_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA52C++0x03
line.long 0x00 "POST_ROOT74_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA530++0x03
line.long 0x00 "PRE74,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA534++0x03
line.long 0x00 "PRE_ROOT74_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA538++0x03
line.long 0x00 "PRE_ROOT74_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA53C++0x03
line.long 0x00 "PRE_ROOT74_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA570++0x03
line.long 0x00 "ACCESS_CTRL74,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA574++0x03
line.long 0x00 "ACCESS_CTRL_ROOT74_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA578++0x03
line.long 0x00 "ACCESS_CTRL_ROOT74_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA57C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT74_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA580++0x03
line.long 0x00 "TARGET_ROOT75,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA584++0x03
line.long 0x00 "TARGET_ROOT75_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA588++0x03
line.long 0x00 "TARGET_ROOT75_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA58C++0x03
line.long 0x00 "TARGET_ROOT75_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA590++0x03
line.long 0x00 "MISC75,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA594++0x03
line.long 0x00 "MISC_ROOT75_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA598++0x03
line.long 0x00 "MISC_ROOT75_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA59C++0x03
line.long 0x00 "MISC_ROOT75_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA5A0++0x03
line.long 0x00 "POST75,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA5A4++0x03
line.long 0x00 "POST_ROOT75_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA5A8++0x03
line.long 0x00 "POST_ROOT75_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA5AC++0x03
line.long 0x00 "POST_ROOT75_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA5B0++0x03
line.long 0x00 "PRE75,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA5B4++0x03
line.long 0x00 "PRE_ROOT75_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA5B8++0x03
line.long 0x00 "PRE_ROOT75_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA5BC++0x03
line.long 0x00 "PRE_ROOT75_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA5F0++0x03
line.long 0x00 "ACCESS_CTRL75,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA5F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT75_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA5F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT75_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA5FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT75_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA600++0x03
line.long 0x00 "TARGET_ROOT76,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA604++0x03
line.long 0x00 "TARGET_ROOT76_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA608++0x03
line.long 0x00 "TARGET_ROOT76_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA60C++0x03
line.long 0x00 "TARGET_ROOT76_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA610++0x03
line.long 0x00 "MISC76,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA614++0x03
line.long 0x00 "MISC_ROOT76_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA618++0x03
line.long 0x00 "MISC_ROOT76_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA61C++0x03
line.long 0x00 "MISC_ROOT76_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA620++0x03
line.long 0x00 "POST76,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA624++0x03
line.long 0x00 "POST_ROOT76_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA628++0x03
line.long 0x00 "POST_ROOT76_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA62C++0x03
line.long 0x00 "POST_ROOT76_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA630++0x03
line.long 0x00 "PRE76,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA634++0x03
line.long 0x00 "PRE_ROOT76_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA638++0x03
line.long 0x00 "PRE_ROOT76_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA63C++0x03
line.long 0x00 "PRE_ROOT76_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA670++0x03
line.long 0x00 "ACCESS_CTRL76,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA674++0x03
line.long 0x00 "ACCESS_CTRL_ROOT76_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA678++0x03
line.long 0x00 "ACCESS_CTRL_ROOT76_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA67C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT76_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA680++0x03
line.long 0x00 "TARGET_ROOT77,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA684++0x03
line.long 0x00 "TARGET_ROOT77_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA688++0x03
line.long 0x00 "TARGET_ROOT77_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA68C++0x03
line.long 0x00 "TARGET_ROOT77_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA690++0x03
line.long 0x00 "MISC77,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA694++0x03
line.long 0x00 "MISC_ROOT77_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA698++0x03
line.long 0x00 "MISC_ROOT77_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA69C++0x03
line.long 0x00 "MISC_ROOT77_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA6A0++0x03
line.long 0x00 "POST77,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA6A4++0x03
line.long 0x00 "POST_ROOT77_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA6A8++0x03
line.long 0x00 "POST_ROOT77_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA6AC++0x03
line.long 0x00 "POST_ROOT77_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA6B0++0x03
line.long 0x00 "PRE77,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA6B4++0x03
line.long 0x00 "PRE_ROOT77_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA6B8++0x03
line.long 0x00 "PRE_ROOT77_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA6BC++0x03
line.long 0x00 "PRE_ROOT77_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA6F0++0x03
line.long 0x00 "ACCESS_CTRL77,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA6F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT77_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA6F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT77_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA6FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT77_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA700++0x03
line.long 0x00 "TARGET_ROOT78,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA704++0x03
line.long 0x00 "TARGET_ROOT78_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA708++0x03
line.long 0x00 "TARGET_ROOT78_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA70C++0x03
line.long 0x00 "TARGET_ROOT78_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA710++0x03
line.long 0x00 "MISC78,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA714++0x03
line.long 0x00 "MISC_ROOT78_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA718++0x03
line.long 0x00 "MISC_ROOT78_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA71C++0x03
line.long 0x00 "MISC_ROOT78_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA720++0x03
line.long 0x00 "POST78,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA724++0x03
line.long 0x00 "POST_ROOT78_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA728++0x03
line.long 0x00 "POST_ROOT78_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA72C++0x03
line.long 0x00 "POST_ROOT78_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA730++0x03
line.long 0x00 "PRE78,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA734++0x03
line.long 0x00 "PRE_ROOT78_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA738++0x03
line.long 0x00 "PRE_ROOT78_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA73C++0x03
line.long 0x00 "PRE_ROOT78_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA770++0x03
line.long 0x00 "ACCESS_CTRL78,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA774++0x03
line.long 0x00 "ACCESS_CTRL_ROOT78_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA778++0x03
line.long 0x00 "ACCESS_CTRL_ROOT78_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA77C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT78_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA780++0x03
line.long 0x00 "TARGET_ROOT79,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA784++0x03
line.long 0x00 "TARGET_ROOT79_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA788++0x03
line.long 0x00 "TARGET_ROOT79_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA78C++0x03
line.long 0x00 "TARGET_ROOT79_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA790++0x03
line.long 0x00 "MISC79,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA794++0x03
line.long 0x00 "MISC_ROOT79_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA798++0x03
line.long 0x00 "MISC_ROOT79_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA79C++0x03
line.long 0x00 "MISC_ROOT79_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA7A0++0x03
line.long 0x00 "POST79,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA7A4++0x03
line.long 0x00 "POST_ROOT79_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA7A8++0x03
line.long 0x00 "POST_ROOT79_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA7AC++0x03
line.long 0x00 "POST_ROOT79_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA7B0++0x03
line.long 0x00 "PRE79,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA7B4++0x03
line.long 0x00 "PRE_ROOT79_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA7B8++0x03
line.long 0x00 "PRE_ROOT79_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA7BC++0x03
line.long 0x00 "PRE_ROOT79_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA7F0++0x03
line.long 0x00 "ACCESS_CTRL79,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA7F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT79_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA7F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT79_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA7FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT79_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA800++0x03
line.long 0x00 "TARGET_ROOT80,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA804++0x03
line.long 0x00 "TARGET_ROOT80_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA808++0x03
line.long 0x00 "TARGET_ROOT80_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA80C++0x03
line.long 0x00 "TARGET_ROOT80_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA810++0x03
line.long 0x00 "MISC80,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA814++0x03
line.long 0x00 "MISC_ROOT80_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA818++0x03
line.long 0x00 "MISC_ROOT80_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA81C++0x03
line.long 0x00 "MISC_ROOT80_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA820++0x03
line.long 0x00 "POST80,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA824++0x03
line.long 0x00 "POST_ROOT80_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA828++0x03
line.long 0x00 "POST_ROOT80_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA82C++0x03
line.long 0x00 "POST_ROOT80_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA830++0x03
line.long 0x00 "PRE80,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA834++0x03
line.long 0x00 "PRE_ROOT80_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA838++0x03
line.long 0x00 "PRE_ROOT80_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA83C++0x03
line.long 0x00 "PRE_ROOT80_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA870++0x03
line.long 0x00 "ACCESS_CTRL80,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA874++0x03
line.long 0x00 "ACCESS_CTRL_ROOT80_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA878++0x03
line.long 0x00 "ACCESS_CTRL_ROOT80_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA87C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT80_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA880++0x03
line.long 0x00 "TARGET_ROOT81,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA884++0x03
line.long 0x00 "TARGET_ROOT81_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA888++0x03
line.long 0x00 "TARGET_ROOT81_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA88C++0x03
line.long 0x00 "TARGET_ROOT81_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA890++0x03
line.long 0x00 "MISC81,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA894++0x03
line.long 0x00 "MISC_ROOT81_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA898++0x03
line.long 0x00 "MISC_ROOT81_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA89C++0x03
line.long 0x00 "MISC_ROOT81_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA8A0++0x03
line.long 0x00 "POST81,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA8A4++0x03
line.long 0x00 "POST_ROOT81_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA8A8++0x03
line.long 0x00 "POST_ROOT81_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA8AC++0x03
line.long 0x00 "POST_ROOT81_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA8B0++0x03
line.long 0x00 "PRE81,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA8B4++0x03
line.long 0x00 "PRE_ROOT81_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA8B8++0x03
line.long 0x00 "PRE_ROOT81_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA8BC++0x03
line.long 0x00 "PRE_ROOT81_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA8F0++0x03
line.long 0x00 "ACCESS_CTRL81,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA8F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT81_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA8F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT81_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA8FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT81_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA900++0x03
line.long 0x00 "TARGET_ROOT82,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA904++0x03
line.long 0x00 "TARGET_ROOT82_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA908++0x03
line.long 0x00 "TARGET_ROOT82_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA90C++0x03
line.long 0x00 "TARGET_ROOT82_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA910++0x03
line.long 0x00 "MISC82,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA914++0x03
line.long 0x00 "MISC_ROOT82_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA918++0x03
line.long 0x00 "MISC_ROOT82_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA91C++0x03
line.long 0x00 "MISC_ROOT82_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA920++0x03
line.long 0x00 "POST82,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA924++0x03
line.long 0x00 "POST_ROOT82_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA928++0x03
line.long 0x00 "POST_ROOT82_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA92C++0x03
line.long 0x00 "POST_ROOT82_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA930++0x03
line.long 0x00 "PRE82,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA934++0x03
line.long 0x00 "PRE_ROOT82_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA938++0x03
line.long 0x00 "PRE_ROOT82_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA93C++0x03
line.long 0x00 "PRE_ROOT82_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA970++0x03
line.long 0x00 "ACCESS_CTRL82,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA974++0x03
line.long 0x00 "ACCESS_CTRL_ROOT82_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA978++0x03
line.long 0x00 "ACCESS_CTRL_ROOT82_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA97C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT82_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA980++0x03
line.long 0x00 "TARGET_ROOT83,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA984++0x03
line.long 0x00 "TARGET_ROOT83_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA988++0x03
line.long 0x00 "TARGET_ROOT83_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA98C++0x03
line.long 0x00 "TARGET_ROOT83_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA990++0x03
line.long 0x00 "MISC83,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA994++0x03
line.long 0x00 "MISC_ROOT83_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA998++0x03
line.long 0x00 "MISC_ROOT83_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA99C++0x03
line.long 0x00 "MISC_ROOT83_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xA9A0++0x03
line.long 0x00 "POST83,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA9A4++0x03
line.long 0x00 "POST_ROOT83_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA9A8++0x03
line.long 0x00 "POST_ROOT83_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA9AC++0x03
line.long 0x00 "POST_ROOT83_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xA9B0++0x03
line.long 0x00 "PRE83,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA9B4++0x03
line.long 0x00 "PRE_ROOT83_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA9B8++0x03
line.long 0x00 "PRE_ROOT83_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA9BC++0x03
line.long 0x00 "PRE_ROOT83_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xA9F0++0x03
line.long 0x00 "ACCESS_CTRL83,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA9F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT83_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA9F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT83_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA9FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT83_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA00++0x03
line.long 0x00 "TARGET_ROOT84,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA04++0x03
line.long 0x00 "TARGET_ROOT84_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA08++0x03
line.long 0x00 "TARGET_ROOT84_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA0C++0x03
line.long 0x00 "TARGET_ROOT84_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA10++0x03
line.long 0x00 "MISC84,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAA14++0x03
line.long 0x00 "MISC_ROOT84_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAA18++0x03
line.long 0x00 "MISC_ROOT84_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAA1C++0x03
line.long 0x00 "MISC_ROOT84_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAA20++0x03
line.long 0x00 "POST84,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA24++0x03
line.long 0x00 "POST_ROOT84_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA28++0x03
line.long 0x00 "POST_ROOT84_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA2C++0x03
line.long 0x00 "POST_ROOT84_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA30++0x03
line.long 0x00 "PRE84,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAA34++0x03
line.long 0x00 "PRE_ROOT84_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAA38++0x03
line.long 0x00 "PRE_ROOT84_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAA3C++0x03
line.long 0x00 "PRE_ROOT84_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAA70++0x03
line.long 0x00 "ACCESS_CTRL84,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT84_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT84_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT84_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA80++0x03
line.long 0x00 "TARGET_ROOT85,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA84++0x03
line.long 0x00 "TARGET_ROOT85_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA88++0x03
line.long 0x00 "TARGET_ROOT85_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA8C++0x03
line.long 0x00 "TARGET_ROOT85_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAA90++0x03
line.long 0x00 "MISC85,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAA94++0x03
line.long 0x00 "MISC_ROOT85_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAA98++0x03
line.long 0x00 "MISC_ROOT85_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAA9C++0x03
line.long 0x00 "MISC_ROOT85_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAAA0++0x03
line.long 0x00 "POST85,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAAA4++0x03
line.long 0x00 "POST_ROOT85_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAAA8++0x03
line.long 0x00 "POST_ROOT85_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAAAC++0x03
line.long 0x00 "POST_ROOT85_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAAB0++0x03
line.long 0x00 "PRE85,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAAB4++0x03
line.long 0x00 "PRE_ROOT85_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAAB8++0x03
line.long 0x00 "PRE_ROOT85_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAABC++0x03
line.long 0x00 "PRE_ROOT85_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAAF0++0x03
line.long 0x00 "ACCESS_CTRL85,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAAF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT85_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAAF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT85_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAAFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT85_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAB00++0x03
line.long 0x00 "TARGET_ROOT86,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB04++0x03
line.long 0x00 "TARGET_ROOT86_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB08++0x03
line.long 0x00 "TARGET_ROOT86_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB0C++0x03
line.long 0x00 "TARGET_ROOT86_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB10++0x03
line.long 0x00 "MISC86,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAB14++0x03
line.long 0x00 "MISC_ROOT86_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAB18++0x03
line.long 0x00 "MISC_ROOT86_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAB1C++0x03
line.long 0x00 "MISC_ROOT86_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAB20++0x03
line.long 0x00 "POST86,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB24++0x03
line.long 0x00 "POST_ROOT86_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB28++0x03
line.long 0x00 "POST_ROOT86_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB2C++0x03
line.long 0x00 "POST_ROOT86_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB30++0x03
line.long 0x00 "PRE86,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAB34++0x03
line.long 0x00 "PRE_ROOT86_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAB38++0x03
line.long 0x00 "PRE_ROOT86_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAB3C++0x03
line.long 0x00 "PRE_ROOT86_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAB70++0x03
line.long 0x00 "ACCESS_CTRL86,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAB74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT86_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAB78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT86_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAB7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT86_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAB80++0x03
line.long 0x00 "TARGET_ROOT87,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB84++0x03
line.long 0x00 "TARGET_ROOT87_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB88++0x03
line.long 0x00 "TARGET_ROOT87_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB8C++0x03
line.long 0x00 "TARGET_ROOT87_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAB90++0x03
line.long 0x00 "MISC87,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAB94++0x03
line.long 0x00 "MISC_ROOT87_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAB98++0x03
line.long 0x00 "MISC_ROOT87_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAB9C++0x03
line.long 0x00 "MISC_ROOT87_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xABA0++0x03
line.long 0x00 "POST87,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xABA4++0x03
line.long 0x00 "POST_ROOT87_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xABA8++0x03
line.long 0x00 "POST_ROOT87_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xABAC++0x03
line.long 0x00 "POST_ROOT87_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xABB0++0x03
line.long 0x00 "PRE87,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xABB4++0x03
line.long 0x00 "PRE_ROOT87_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xABB8++0x03
line.long 0x00 "PRE_ROOT87_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xABBC++0x03
line.long 0x00 "PRE_ROOT87_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xABF0++0x03
line.long 0x00 "ACCESS_CTRL87,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xABF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT87_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xABF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT87_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xABFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT87_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC00++0x03
line.long 0x00 "TARGET_ROOT88,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC04++0x03
line.long 0x00 "TARGET_ROOT88_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC08++0x03
line.long 0x00 "TARGET_ROOT88_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC0C++0x03
line.long 0x00 "TARGET_ROOT88_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC10++0x03
line.long 0x00 "MISC88,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAC14++0x03
line.long 0x00 "MISC_ROOT88_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAC18++0x03
line.long 0x00 "MISC_ROOT88_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAC1C++0x03
line.long 0x00 "MISC_ROOT88_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAC20++0x03
line.long 0x00 "POST88,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC24++0x03
line.long 0x00 "POST_ROOT88_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC28++0x03
line.long 0x00 "POST_ROOT88_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC2C++0x03
line.long 0x00 "POST_ROOT88_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC30++0x03
line.long 0x00 "PRE88,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAC34++0x03
line.long 0x00 "PRE_ROOT88_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAC38++0x03
line.long 0x00 "PRE_ROOT88_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAC3C++0x03
line.long 0x00 "PRE_ROOT88_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAC70++0x03
line.long 0x00 "ACCESS_CTRL88,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT88_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT88_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT88_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC80++0x03
line.long 0x00 "TARGET_ROOT89,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC84++0x03
line.long 0x00 "TARGET_ROOT89_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC88++0x03
line.long 0x00 "TARGET_ROOT89_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC8C++0x03
line.long 0x00 "TARGET_ROOT89_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAC90++0x03
line.long 0x00 "MISC89,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAC94++0x03
line.long 0x00 "MISC_ROOT89_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAC98++0x03
line.long 0x00 "MISC_ROOT89_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAC9C++0x03
line.long 0x00 "MISC_ROOT89_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xACA0++0x03
line.long 0x00 "POST89,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xACA4++0x03
line.long 0x00 "POST_ROOT89_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xACA8++0x03
line.long 0x00 "POST_ROOT89_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xACAC++0x03
line.long 0x00 "POST_ROOT89_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xACB0++0x03
line.long 0x00 "PRE89,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xACB4++0x03
line.long 0x00 "PRE_ROOT89_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xACB8++0x03
line.long 0x00 "PRE_ROOT89_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xACBC++0x03
line.long 0x00 "PRE_ROOT89_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xACF0++0x03
line.long 0x00 "ACCESS_CTRL89,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xACF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT89_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xACF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT89_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xACFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT89_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAD00++0x03
line.long 0x00 "TARGET_ROOT90,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD04++0x03
line.long 0x00 "TARGET_ROOT90_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD08++0x03
line.long 0x00 "TARGET_ROOT90_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD0C++0x03
line.long 0x00 "TARGET_ROOT90_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD10++0x03
line.long 0x00 "MISC90,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAD14++0x03
line.long 0x00 "MISC_ROOT90_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAD18++0x03
line.long 0x00 "MISC_ROOT90_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAD1C++0x03
line.long 0x00 "MISC_ROOT90_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAD20++0x03
line.long 0x00 "POST90,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD24++0x03
line.long 0x00 "POST_ROOT90_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD28++0x03
line.long 0x00 "POST_ROOT90_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD2C++0x03
line.long 0x00 "POST_ROOT90_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD30++0x03
line.long 0x00 "PRE90,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAD34++0x03
line.long 0x00 "PRE_ROOT90_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAD38++0x03
line.long 0x00 "PRE_ROOT90_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAD3C++0x03
line.long 0x00 "PRE_ROOT90_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAD70++0x03
line.long 0x00 "ACCESS_CTRL90,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAD74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT90_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAD78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT90_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAD7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT90_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAD80++0x03
line.long 0x00 "TARGET_ROOT91,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD84++0x03
line.long 0x00 "TARGET_ROOT91_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD88++0x03
line.long 0x00 "TARGET_ROOT91_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD8C++0x03
line.long 0x00 "TARGET_ROOT91_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAD90++0x03
line.long 0x00 "MISC91,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAD94++0x03
line.long 0x00 "MISC_ROOT91_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAD98++0x03
line.long 0x00 "MISC_ROOT91_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAD9C++0x03
line.long 0x00 "MISC_ROOT91_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xADA0++0x03
line.long 0x00 "POST91,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xADA4++0x03
line.long 0x00 "POST_ROOT91_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xADA8++0x03
line.long 0x00 "POST_ROOT91_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xADAC++0x03
line.long 0x00 "POST_ROOT91_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xADB0++0x03
line.long 0x00 "PRE91,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xADB4++0x03
line.long 0x00 "PRE_ROOT91_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xADB8++0x03
line.long 0x00 "PRE_ROOT91_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xADBC++0x03
line.long 0x00 "PRE_ROOT91_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xADF0++0x03
line.long 0x00 "ACCESS_CTRL91,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xADF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT91_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xADF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT91_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xADFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT91_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAE00++0x03
line.long 0x00 "TARGET_ROOT92,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE04++0x03
line.long 0x00 "TARGET_ROOT92_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE08++0x03
line.long 0x00 "TARGET_ROOT92_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE0C++0x03
line.long 0x00 "TARGET_ROOT92_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE10++0x03
line.long 0x00 "MISC92,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAE14++0x03
line.long 0x00 "MISC_ROOT92_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAE18++0x03
line.long 0x00 "MISC_ROOT92_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAE1C++0x03
line.long 0x00 "MISC_ROOT92_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAE20++0x03
line.long 0x00 "POST92,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE24++0x03
line.long 0x00 "POST_ROOT92_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE28++0x03
line.long 0x00 "POST_ROOT92_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE2C++0x03
line.long 0x00 "POST_ROOT92_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE30++0x03
line.long 0x00 "PRE92,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAE34++0x03
line.long 0x00 "PRE_ROOT92_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAE38++0x03
line.long 0x00 "PRE_ROOT92_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAE3C++0x03
line.long 0x00 "PRE_ROOT92_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAE70++0x03
line.long 0x00 "ACCESS_CTRL92,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAE74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT92_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAE78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT92_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAE7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT92_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAE80++0x03
line.long 0x00 "TARGET_ROOT93,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE84++0x03
line.long 0x00 "TARGET_ROOT93_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE88++0x03
line.long 0x00 "TARGET_ROOT93_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE8C++0x03
line.long 0x00 "TARGET_ROOT93_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAE90++0x03
line.long 0x00 "MISC93,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAE94++0x03
line.long 0x00 "MISC_ROOT93_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAE98++0x03
line.long 0x00 "MISC_ROOT93_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAE9C++0x03
line.long 0x00 "MISC_ROOT93_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAEA0++0x03
line.long 0x00 "POST93,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAEA4++0x03
line.long 0x00 "POST_ROOT93_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAEA8++0x03
line.long 0x00 "POST_ROOT93_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAEAC++0x03
line.long 0x00 "POST_ROOT93_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAEB0++0x03
line.long 0x00 "PRE93,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAEB4++0x03
line.long 0x00 "PRE_ROOT93_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAEB8++0x03
line.long 0x00 "PRE_ROOT93_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAEBC++0x03
line.long 0x00 "PRE_ROOT93_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAEF0++0x03
line.long 0x00 "ACCESS_CTRL93,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAEF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT93_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAEF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT93_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAEFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT93_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAF00++0x03
line.long 0x00 "TARGET_ROOT94,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF04++0x03
line.long 0x00 "TARGET_ROOT94_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF08++0x03
line.long 0x00 "TARGET_ROOT94_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF0C++0x03
line.long 0x00 "TARGET_ROOT94_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF10++0x03
line.long 0x00 "MISC94,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAF14++0x03
line.long 0x00 "MISC_ROOT94_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAF18++0x03
line.long 0x00 "MISC_ROOT94_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAF1C++0x03
line.long 0x00 "MISC_ROOT94_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAF20++0x03
line.long 0x00 "POST94,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF24++0x03
line.long 0x00 "POST_ROOT94_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF28++0x03
line.long 0x00 "POST_ROOT94_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF2C++0x03
line.long 0x00 "POST_ROOT94_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF30++0x03
line.long 0x00 "PRE94,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAF34++0x03
line.long 0x00 "PRE_ROOT94_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAF38++0x03
line.long 0x00 "PRE_ROOT94_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAF3C++0x03
line.long 0x00 "PRE_ROOT94_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAF70++0x03
line.long 0x00 "ACCESS_CTRL94,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAF74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT94_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAF78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT94_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAF7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT94_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAF80++0x03
line.long 0x00 "TARGET_ROOT95,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF84++0x03
line.long 0x00 "TARGET_ROOT95_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF88++0x03
line.long 0x00 "TARGET_ROOT95_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF8C++0x03
line.long 0x00 "TARGET_ROOT95_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAF90++0x03
line.long 0x00 "MISC95,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAF94++0x03
line.long 0x00 "MISC_ROOT95_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAF98++0x03
line.long 0x00 "MISC_ROOT95_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAF9C++0x03
line.long 0x00 "MISC_ROOT95_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xAFA0++0x03
line.long 0x00 "POST95,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAFA4++0x03
line.long 0x00 "POST_ROOT95_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAFA8++0x03
line.long 0x00 "POST_ROOT95_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAFAC++0x03
line.long 0x00 "POST_ROOT95_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xAFB0++0x03
line.long 0x00 "PRE95,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAFB4++0x03
line.long 0x00 "PRE_ROOT95_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAFB8++0x03
line.long 0x00 "PRE_ROOT95_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAFBC++0x03
line.long 0x00 "PRE_ROOT95_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xAFF0++0x03
line.long 0x00 "ACCESS_CTRL95,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAFF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT95_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAFF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT95_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAFFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT95_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB000++0x03
line.long 0x00 "TARGET_ROOT96,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB004++0x03
line.long 0x00 "TARGET_ROOT96_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB008++0x03
line.long 0x00 "TARGET_ROOT96_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB00C++0x03
line.long 0x00 "TARGET_ROOT96_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB010++0x03
line.long 0x00 "MISC96,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB014++0x03
line.long 0x00 "MISC_ROOT96_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB018++0x03
line.long 0x00 "MISC_ROOT96_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB01C++0x03
line.long 0x00 "MISC_ROOT96_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB020++0x03
line.long 0x00 "POST96,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB024++0x03
line.long 0x00 "POST_ROOT96_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB028++0x03
line.long 0x00 "POST_ROOT96_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB02C++0x03
line.long 0x00 "POST_ROOT96_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB030++0x03
line.long 0x00 "PRE96,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB034++0x03
line.long 0x00 "PRE_ROOT96_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB038++0x03
line.long 0x00 "PRE_ROOT96_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB03C++0x03
line.long 0x00 "PRE_ROOT96_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB070++0x03
line.long 0x00 "ACCESS_CTRL96,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB074++0x03
line.long 0x00 "ACCESS_CTRL_ROOT96_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB078++0x03
line.long 0x00 "ACCESS_CTRL_ROOT96_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB07C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT96_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB080++0x03
line.long 0x00 "TARGET_ROOT97,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB084++0x03
line.long 0x00 "TARGET_ROOT97_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB088++0x03
line.long 0x00 "TARGET_ROOT97_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB08C++0x03
line.long 0x00 "TARGET_ROOT97_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB090++0x03
line.long 0x00 "MISC97,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB094++0x03
line.long 0x00 "MISC_ROOT97_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB098++0x03
line.long 0x00 "MISC_ROOT97_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB09C++0x03
line.long 0x00 "MISC_ROOT97_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB0A0++0x03
line.long 0x00 "POST97,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB0A4++0x03
line.long 0x00 "POST_ROOT97_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB0A8++0x03
line.long 0x00 "POST_ROOT97_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB0AC++0x03
line.long 0x00 "POST_ROOT97_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB0B0++0x03
line.long 0x00 "PRE97,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB0B4++0x03
line.long 0x00 "PRE_ROOT97_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB0B8++0x03
line.long 0x00 "PRE_ROOT97_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB0BC++0x03
line.long 0x00 "PRE_ROOT97_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB0F0++0x03
line.long 0x00 "ACCESS_CTRL97,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT97_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT97_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT97_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB100++0x03
line.long 0x00 "TARGET_ROOT98,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB104++0x03
line.long 0x00 "TARGET_ROOT98_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB108++0x03
line.long 0x00 "TARGET_ROOT98_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB10C++0x03
line.long 0x00 "TARGET_ROOT98_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB110++0x03
line.long 0x00 "MISC98,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB114++0x03
line.long 0x00 "MISC_ROOT98_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB118++0x03
line.long 0x00 "MISC_ROOT98_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB11C++0x03
line.long 0x00 "MISC_ROOT98_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB120++0x03
line.long 0x00 "POST98,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB124++0x03
line.long 0x00 "POST_ROOT98_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB128++0x03
line.long 0x00 "POST_ROOT98_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB12C++0x03
line.long 0x00 "POST_ROOT98_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB130++0x03
line.long 0x00 "PRE98,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB134++0x03
line.long 0x00 "PRE_ROOT98_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB138++0x03
line.long 0x00 "PRE_ROOT98_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB13C++0x03
line.long 0x00 "PRE_ROOT98_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB170++0x03
line.long 0x00 "ACCESS_CTRL98,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB174++0x03
line.long 0x00 "ACCESS_CTRL_ROOT98_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB178++0x03
line.long 0x00 "ACCESS_CTRL_ROOT98_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB17C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT98_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB180++0x03
line.long 0x00 "TARGET_ROOT99,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB184++0x03
line.long 0x00 "TARGET_ROOT99_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB188++0x03
line.long 0x00 "TARGET_ROOT99_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB18C++0x03
line.long 0x00 "TARGET_ROOT99_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB190++0x03
line.long 0x00 "MISC99,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB194++0x03
line.long 0x00 "MISC_ROOT99_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB198++0x03
line.long 0x00 "MISC_ROOT99_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB19C++0x03
line.long 0x00 "MISC_ROOT99_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB1A0++0x03
line.long 0x00 "POST99,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB1A4++0x03
line.long 0x00 "POST_ROOT99_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB1A8++0x03
line.long 0x00 "POST_ROOT99_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB1AC++0x03
line.long 0x00 "POST_ROOT99_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB1B0++0x03
line.long 0x00 "PRE99,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB1B4++0x03
line.long 0x00 "PRE_ROOT99_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB1B8++0x03
line.long 0x00 "PRE_ROOT99_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB1BC++0x03
line.long 0x00 "PRE_ROOT99_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB1F0++0x03
line.long 0x00 "ACCESS_CTRL99,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB1F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT99_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB1F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT99_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB1FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT99_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB200++0x03
line.long 0x00 "TARGET_ROOT100,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB204++0x03
line.long 0x00 "TARGET_ROOT100_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB208++0x03
line.long 0x00 "TARGET_ROOT100_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB20C++0x03
line.long 0x00 "TARGET_ROOT100_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB210++0x03
line.long 0x00 "MISC100,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB214++0x03
line.long 0x00 "MISC_ROOT100_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB218++0x03
line.long 0x00 "MISC_ROOT100_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB21C++0x03
line.long 0x00 "MISC_ROOT100_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB220++0x03
line.long 0x00 "POST100,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB224++0x03
line.long 0x00 "POST_ROOT100_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB228++0x03
line.long 0x00 "POST_ROOT100_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB22C++0x03
line.long 0x00 "POST_ROOT100_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB230++0x03
line.long 0x00 "PRE100,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB234++0x03
line.long 0x00 "PRE_ROOT100_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB238++0x03
line.long 0x00 "PRE_ROOT100_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB23C++0x03
line.long 0x00 "PRE_ROOT100_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB270++0x03
line.long 0x00 "ACCESS_CTRL100,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB274++0x03
line.long 0x00 "ACCESS_CTRL_ROOT100_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB278++0x03
line.long 0x00 "ACCESS_CTRL_ROOT100_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB27C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT100_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB280++0x03
line.long 0x00 "TARGET_ROOT101,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB284++0x03
line.long 0x00 "TARGET_ROOT101_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB288++0x03
line.long 0x00 "TARGET_ROOT101_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB28C++0x03
line.long 0x00 "TARGET_ROOT101_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB290++0x03
line.long 0x00 "MISC101,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB294++0x03
line.long 0x00 "MISC_ROOT101_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB298++0x03
line.long 0x00 "MISC_ROOT101_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB29C++0x03
line.long 0x00 "MISC_ROOT101_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB2A0++0x03
line.long 0x00 "POST101,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB2A4++0x03
line.long 0x00 "POST_ROOT101_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB2A8++0x03
line.long 0x00 "POST_ROOT101_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB2AC++0x03
line.long 0x00 "POST_ROOT101_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB2B0++0x03
line.long 0x00 "PRE101,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB2B4++0x03
line.long 0x00 "PRE_ROOT101_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB2B8++0x03
line.long 0x00 "PRE_ROOT101_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB2BC++0x03
line.long 0x00 "PRE_ROOT101_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB2F0++0x03
line.long 0x00 "ACCESS_CTRL101,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB2F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT101_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB2F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT101_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB2FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT101_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB300++0x03
line.long 0x00 "TARGET_ROOT102,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB304++0x03
line.long 0x00 "TARGET_ROOT102_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB308++0x03
line.long 0x00 "TARGET_ROOT102_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB30C++0x03
line.long 0x00 "TARGET_ROOT102_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB310++0x03
line.long 0x00 "MISC102,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB314++0x03
line.long 0x00 "MISC_ROOT102_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB318++0x03
line.long 0x00 "MISC_ROOT102_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB31C++0x03
line.long 0x00 "MISC_ROOT102_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB320++0x03
line.long 0x00 "POST102,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB324++0x03
line.long 0x00 "POST_ROOT102_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB328++0x03
line.long 0x00 "POST_ROOT102_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB32C++0x03
line.long 0x00 "POST_ROOT102_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB330++0x03
line.long 0x00 "PRE102,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB334++0x03
line.long 0x00 "PRE_ROOT102_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB338++0x03
line.long 0x00 "PRE_ROOT102_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB33C++0x03
line.long 0x00 "PRE_ROOT102_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB370++0x03
line.long 0x00 "ACCESS_CTRL102,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB374++0x03
line.long 0x00 "ACCESS_CTRL_ROOT102_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB378++0x03
line.long 0x00 "ACCESS_CTRL_ROOT102_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB37C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT102_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB380++0x03
line.long 0x00 "TARGET_ROOT103,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB384++0x03
line.long 0x00 "TARGET_ROOT103_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB388++0x03
line.long 0x00 "TARGET_ROOT103_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB38C++0x03
line.long 0x00 "TARGET_ROOT103_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB390++0x03
line.long 0x00 "MISC103,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB394++0x03
line.long 0x00 "MISC_ROOT103_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB398++0x03
line.long 0x00 "MISC_ROOT103_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB39C++0x03
line.long 0x00 "MISC_ROOT103_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB3A0++0x03
line.long 0x00 "POST103,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB3A4++0x03
line.long 0x00 "POST_ROOT103_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB3A8++0x03
line.long 0x00 "POST_ROOT103_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB3AC++0x03
line.long 0x00 "POST_ROOT103_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB3B0++0x03
line.long 0x00 "PRE103,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB3B4++0x03
line.long 0x00 "PRE_ROOT103_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB3B8++0x03
line.long 0x00 "PRE_ROOT103_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB3BC++0x03
line.long 0x00 "PRE_ROOT103_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB3F0++0x03
line.long 0x00 "ACCESS_CTRL103,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB3F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT103_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB3F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT103_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB3FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT103_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB400++0x03
line.long 0x00 "TARGET_ROOT104,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB404++0x03
line.long 0x00 "TARGET_ROOT104_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB408++0x03
line.long 0x00 "TARGET_ROOT104_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB40C++0x03
line.long 0x00 "TARGET_ROOT104_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB410++0x03
line.long 0x00 "MISC104,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB414++0x03
line.long 0x00 "MISC_ROOT104_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB418++0x03
line.long 0x00 "MISC_ROOT104_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB41C++0x03
line.long 0x00 "MISC_ROOT104_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB420++0x03
line.long 0x00 "POST104,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB424++0x03
line.long 0x00 "POST_ROOT104_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB428++0x03
line.long 0x00 "POST_ROOT104_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB42C++0x03
line.long 0x00 "POST_ROOT104_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB430++0x03
line.long 0x00 "PRE104,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB434++0x03
line.long 0x00 "PRE_ROOT104_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB438++0x03
line.long 0x00 "PRE_ROOT104_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB43C++0x03
line.long 0x00 "PRE_ROOT104_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB470++0x03
line.long 0x00 "ACCESS_CTRL104,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB474++0x03
line.long 0x00 "ACCESS_CTRL_ROOT104_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB478++0x03
line.long 0x00 "ACCESS_CTRL_ROOT104_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB47C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT104_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB480++0x03
line.long 0x00 "TARGET_ROOT105,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB484++0x03
line.long 0x00 "TARGET_ROOT105_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB488++0x03
line.long 0x00 "TARGET_ROOT105_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB48C++0x03
line.long 0x00 "TARGET_ROOT105_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB490++0x03
line.long 0x00 "MISC105,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB494++0x03
line.long 0x00 "MISC_ROOT105_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB498++0x03
line.long 0x00 "MISC_ROOT105_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB49C++0x03
line.long 0x00 "MISC_ROOT105_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB4A0++0x03
line.long 0x00 "POST105,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB4A4++0x03
line.long 0x00 "POST_ROOT105_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB4A8++0x03
line.long 0x00 "POST_ROOT105_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB4AC++0x03
line.long 0x00 "POST_ROOT105_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB4B0++0x03
line.long 0x00 "PRE105,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB4B4++0x03
line.long 0x00 "PRE_ROOT105_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB4B8++0x03
line.long 0x00 "PRE_ROOT105_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB4BC++0x03
line.long 0x00 "PRE_ROOT105_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB4F0++0x03
line.long 0x00 "ACCESS_CTRL105,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB4F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT105_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB4F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT105_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB4FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT105_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB500++0x03
line.long 0x00 "TARGET_ROOT106,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB504++0x03
line.long 0x00 "TARGET_ROOT106_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB508++0x03
line.long 0x00 "TARGET_ROOT106_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB50C++0x03
line.long 0x00 "TARGET_ROOT106_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB510++0x03
line.long 0x00 "MISC106,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB514++0x03
line.long 0x00 "MISC_ROOT106_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB518++0x03
line.long 0x00 "MISC_ROOT106_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB51C++0x03
line.long 0x00 "MISC_ROOT106_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB520++0x03
line.long 0x00 "POST106,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB524++0x03
line.long 0x00 "POST_ROOT106_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB528++0x03
line.long 0x00 "POST_ROOT106_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB52C++0x03
line.long 0x00 "POST_ROOT106_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB530++0x03
line.long 0x00 "PRE106,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB534++0x03
line.long 0x00 "PRE_ROOT106_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB538++0x03
line.long 0x00 "PRE_ROOT106_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB53C++0x03
line.long 0x00 "PRE_ROOT106_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB570++0x03
line.long 0x00 "ACCESS_CTRL106,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB574++0x03
line.long 0x00 "ACCESS_CTRL_ROOT106_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB578++0x03
line.long 0x00 "ACCESS_CTRL_ROOT106_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB57C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT106_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB580++0x03
line.long 0x00 "TARGET_ROOT107,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB584++0x03
line.long 0x00 "TARGET_ROOT107_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB588++0x03
line.long 0x00 "TARGET_ROOT107_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB58C++0x03
line.long 0x00 "TARGET_ROOT107_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB590++0x03
line.long 0x00 "MISC107,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB594++0x03
line.long 0x00 "MISC_ROOT107_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB598++0x03
line.long 0x00 "MISC_ROOT107_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB59C++0x03
line.long 0x00 "MISC_ROOT107_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB5A0++0x03
line.long 0x00 "POST107,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB5A4++0x03
line.long 0x00 "POST_ROOT107_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB5A8++0x03
line.long 0x00 "POST_ROOT107_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB5AC++0x03
line.long 0x00 "POST_ROOT107_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB5B0++0x03
line.long 0x00 "PRE107,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB5B4++0x03
line.long 0x00 "PRE_ROOT107_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB5B8++0x03
line.long 0x00 "PRE_ROOT107_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB5BC++0x03
line.long 0x00 "PRE_ROOT107_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB5F0++0x03
line.long 0x00 "ACCESS_CTRL107,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB5F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT107_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB5F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT107_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB5FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT107_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB600++0x03
line.long 0x00 "TARGET_ROOT108,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB604++0x03
line.long 0x00 "TARGET_ROOT108_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB608++0x03
line.long 0x00 "TARGET_ROOT108_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB60C++0x03
line.long 0x00 "TARGET_ROOT108_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB610++0x03
line.long 0x00 "MISC108,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB614++0x03
line.long 0x00 "MISC_ROOT108_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB618++0x03
line.long 0x00 "MISC_ROOT108_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB61C++0x03
line.long 0x00 "MISC_ROOT108_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB620++0x03
line.long 0x00 "POST108,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB624++0x03
line.long 0x00 "POST_ROOT108_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB628++0x03
line.long 0x00 "POST_ROOT108_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB62C++0x03
line.long 0x00 "POST_ROOT108_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB630++0x03
line.long 0x00 "PRE108,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB634++0x03
line.long 0x00 "PRE_ROOT108_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB638++0x03
line.long 0x00 "PRE_ROOT108_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB63C++0x03
line.long 0x00 "PRE_ROOT108_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB670++0x03
line.long 0x00 "ACCESS_CTRL108,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB674++0x03
line.long 0x00 "ACCESS_CTRL_ROOT108_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB678++0x03
line.long 0x00 "ACCESS_CTRL_ROOT108_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB67C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT108_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB680++0x03
line.long 0x00 "TARGET_ROOT109,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB684++0x03
line.long 0x00 "TARGET_ROOT109_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB688++0x03
line.long 0x00 "TARGET_ROOT109_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB68C++0x03
line.long 0x00 "TARGET_ROOT109_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB690++0x03
line.long 0x00 "MISC109,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB694++0x03
line.long 0x00 "MISC_ROOT109_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB698++0x03
line.long 0x00 "MISC_ROOT109_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB69C++0x03
line.long 0x00 "MISC_ROOT109_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB6A0++0x03
line.long 0x00 "POST109,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB6A4++0x03
line.long 0x00 "POST_ROOT109_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB6A8++0x03
line.long 0x00 "POST_ROOT109_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB6AC++0x03
line.long 0x00 "POST_ROOT109_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB6B0++0x03
line.long 0x00 "PRE109,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB6B4++0x03
line.long 0x00 "PRE_ROOT109_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB6B8++0x03
line.long 0x00 "PRE_ROOT109_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB6BC++0x03
line.long 0x00 "PRE_ROOT109_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB6F0++0x03
line.long 0x00 "ACCESS_CTRL109,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB6F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT109_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB6F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT109_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB6FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT109_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB700++0x03
line.long 0x00 "TARGET_ROOT110,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB704++0x03
line.long 0x00 "TARGET_ROOT110_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB708++0x03
line.long 0x00 "TARGET_ROOT110_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB70C++0x03
line.long 0x00 "TARGET_ROOT110_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB710++0x03
line.long 0x00 "MISC110,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB714++0x03
line.long 0x00 "MISC_ROOT110_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB718++0x03
line.long 0x00 "MISC_ROOT110_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB71C++0x03
line.long 0x00 "MISC_ROOT110_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB720++0x03
line.long 0x00 "POST110,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB724++0x03
line.long 0x00 "POST_ROOT110_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB728++0x03
line.long 0x00 "POST_ROOT110_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB72C++0x03
line.long 0x00 "POST_ROOT110_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB730++0x03
line.long 0x00 "PRE110,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB734++0x03
line.long 0x00 "PRE_ROOT110_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB738++0x03
line.long 0x00 "PRE_ROOT110_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB73C++0x03
line.long 0x00 "PRE_ROOT110_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB770++0x03
line.long 0x00 "ACCESS_CTRL110,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB774++0x03
line.long 0x00 "ACCESS_CTRL_ROOT110_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB778++0x03
line.long 0x00 "ACCESS_CTRL_ROOT110_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB77C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT110_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB780++0x03
line.long 0x00 "TARGET_ROOT111,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB784++0x03
line.long 0x00 "TARGET_ROOT111_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB788++0x03
line.long 0x00 "TARGET_ROOT111_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB78C++0x03
line.long 0x00 "TARGET_ROOT111_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB790++0x03
line.long 0x00 "MISC111,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB794++0x03
line.long 0x00 "MISC_ROOT111_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB798++0x03
line.long 0x00 "MISC_ROOT111_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB79C++0x03
line.long 0x00 "MISC_ROOT111_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB7A0++0x03
line.long 0x00 "POST111,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB7A4++0x03
line.long 0x00 "POST_ROOT111_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB7A8++0x03
line.long 0x00 "POST_ROOT111_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB7AC++0x03
line.long 0x00 "POST_ROOT111_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB7B0++0x03
line.long 0x00 "PRE111,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB7B4++0x03
line.long 0x00 "PRE_ROOT111_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB7B8++0x03
line.long 0x00 "PRE_ROOT111_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB7BC++0x03
line.long 0x00 "PRE_ROOT111_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB7F0++0x03
line.long 0x00 "ACCESS_CTRL111,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB7F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT111_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB7F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT111_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB7FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT111_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB800++0x03
line.long 0x00 "TARGET_ROOT112,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB804++0x03
line.long 0x00 "TARGET_ROOT112_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB808++0x03
line.long 0x00 "TARGET_ROOT112_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB80C++0x03
line.long 0x00 "TARGET_ROOT112_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB810++0x03
line.long 0x00 "MISC112,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB814++0x03
line.long 0x00 "MISC_ROOT112_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB818++0x03
line.long 0x00 "MISC_ROOT112_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB81C++0x03
line.long 0x00 "MISC_ROOT112_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB820++0x03
line.long 0x00 "POST112,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB824++0x03
line.long 0x00 "POST_ROOT112_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB828++0x03
line.long 0x00 "POST_ROOT112_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB82C++0x03
line.long 0x00 "POST_ROOT112_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB830++0x03
line.long 0x00 "PRE112,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB834++0x03
line.long 0x00 "PRE_ROOT112_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB838++0x03
line.long 0x00 "PRE_ROOT112_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB83C++0x03
line.long 0x00 "PRE_ROOT112_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB870++0x03
line.long 0x00 "ACCESS_CTRL112,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB874++0x03
line.long 0x00 "ACCESS_CTRL_ROOT112_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB878++0x03
line.long 0x00 "ACCESS_CTRL_ROOT112_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB87C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT112_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB880++0x03
line.long 0x00 "TARGET_ROOT113,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB884++0x03
line.long 0x00 "TARGET_ROOT113_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB888++0x03
line.long 0x00 "TARGET_ROOT113_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB88C++0x03
line.long 0x00 "TARGET_ROOT113_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB890++0x03
line.long 0x00 "MISC113,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB894++0x03
line.long 0x00 "MISC_ROOT113_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB898++0x03
line.long 0x00 "MISC_ROOT113_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB89C++0x03
line.long 0x00 "MISC_ROOT113_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB8A0++0x03
line.long 0x00 "POST113,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB8A4++0x03
line.long 0x00 "POST_ROOT113_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB8A8++0x03
line.long 0x00 "POST_ROOT113_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB8AC++0x03
line.long 0x00 "POST_ROOT113_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB8B0++0x03
line.long 0x00 "PRE113,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB8B4++0x03
line.long 0x00 "PRE_ROOT113_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB8B8++0x03
line.long 0x00 "PRE_ROOT113_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB8BC++0x03
line.long 0x00 "PRE_ROOT113_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB8F0++0x03
line.long 0x00 "ACCESS_CTRL113,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB8F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT113_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB8F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT113_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB8FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT113_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB900++0x03
line.long 0x00 "TARGET_ROOT114,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB904++0x03
line.long 0x00 "TARGET_ROOT114_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB908++0x03
line.long 0x00 "TARGET_ROOT114_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB90C++0x03
line.long 0x00 "TARGET_ROOT114_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB910++0x03
line.long 0x00 "MISC114,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB914++0x03
line.long 0x00 "MISC_ROOT114_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB918++0x03
line.long 0x00 "MISC_ROOT114_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB91C++0x03
line.long 0x00 "MISC_ROOT114_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB920++0x03
line.long 0x00 "POST114,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB924++0x03
line.long 0x00 "POST_ROOT114_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB928++0x03
line.long 0x00 "POST_ROOT114_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB92C++0x03
line.long 0x00 "POST_ROOT114_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB930++0x03
line.long 0x00 "PRE114,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB934++0x03
line.long 0x00 "PRE_ROOT114_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB938++0x03
line.long 0x00 "PRE_ROOT114_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB93C++0x03
line.long 0x00 "PRE_ROOT114_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB970++0x03
line.long 0x00 "ACCESS_CTRL114,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB974++0x03
line.long 0x00 "ACCESS_CTRL_ROOT114_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB978++0x03
line.long 0x00 "ACCESS_CTRL_ROOT114_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB97C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT114_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB980++0x03
line.long 0x00 "TARGET_ROOT115,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB984++0x03
line.long 0x00 "TARGET_ROOT115_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB988++0x03
line.long 0x00 "TARGET_ROOT115_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB98C++0x03
line.long 0x00 "TARGET_ROOT115_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB990++0x03
line.long 0x00 "MISC115,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB994++0x03
line.long 0x00 "MISC_ROOT115_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB998++0x03
line.long 0x00 "MISC_ROOT115_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB99C++0x03
line.long 0x00 "MISC_ROOT115_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xB9A0++0x03
line.long 0x00 "POST115,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB9A4++0x03
line.long 0x00 "POST_ROOT115_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB9A8++0x03
line.long 0x00 "POST_ROOT115_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB9AC++0x03
line.long 0x00 "POST_ROOT115_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xB9B0++0x03
line.long 0x00 "PRE115,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB9B4++0x03
line.long 0x00 "PRE_ROOT115_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB9B8++0x03
line.long 0x00 "PRE_ROOT115_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB9BC++0x03
line.long 0x00 "PRE_ROOT115_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xB9F0++0x03
line.long 0x00 "ACCESS_CTRL115,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB9F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT115_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB9F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT115_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB9FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT115_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBA00++0x03
line.long 0x00 "TARGET_ROOT116,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA04++0x03
line.long 0x00 "TARGET_ROOT116_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA08++0x03
line.long 0x00 "TARGET_ROOT116_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA0C++0x03
line.long 0x00 "TARGET_ROOT116_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA10++0x03
line.long 0x00 "MISC116,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBA14++0x03
line.long 0x00 "MISC_ROOT116_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBA18++0x03
line.long 0x00 "MISC_ROOT116_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBA1C++0x03
line.long 0x00 "MISC_ROOT116_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBA20++0x03
line.long 0x00 "POST116,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA24++0x03
line.long 0x00 "POST_ROOT116_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA28++0x03
line.long 0x00 "POST_ROOT116_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA2C++0x03
line.long 0x00 "POST_ROOT116_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA30++0x03
line.long 0x00 "PRE116,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBA34++0x03
line.long 0x00 "PRE_ROOT116_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBA38++0x03
line.long 0x00 "PRE_ROOT116_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBA3C++0x03
line.long 0x00 "PRE_ROOT116_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBA70++0x03
line.long 0x00 "ACCESS_CTRL116,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBA74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT116_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBA78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT116_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBA7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT116_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBA80++0x03
line.long 0x00 "TARGET_ROOT117,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA84++0x03
line.long 0x00 "TARGET_ROOT117_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA88++0x03
line.long 0x00 "TARGET_ROOT117_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA8C++0x03
line.long 0x00 "TARGET_ROOT117_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBA90++0x03
line.long 0x00 "MISC117,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBA94++0x03
line.long 0x00 "MISC_ROOT117_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBA98++0x03
line.long 0x00 "MISC_ROOT117_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBA9C++0x03
line.long 0x00 "MISC_ROOT117_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBAA0++0x03
line.long 0x00 "POST117,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBAA4++0x03
line.long 0x00 "POST_ROOT117_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBAA8++0x03
line.long 0x00 "POST_ROOT117_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBAAC++0x03
line.long 0x00 "POST_ROOT117_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBAB0++0x03
line.long 0x00 "PRE117,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBAB4++0x03
line.long 0x00 "PRE_ROOT117_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBAB8++0x03
line.long 0x00 "PRE_ROOT117_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBABC++0x03
line.long 0x00 "PRE_ROOT117_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBAF0++0x03
line.long 0x00 "ACCESS_CTRL117,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBAF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT117_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBAF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT117_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBAFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT117_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBB00++0x03
line.long 0x00 "TARGET_ROOT118,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB04++0x03
line.long 0x00 "TARGET_ROOT118_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB08++0x03
line.long 0x00 "TARGET_ROOT118_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB0C++0x03
line.long 0x00 "TARGET_ROOT118_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB10++0x03
line.long 0x00 "MISC118,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBB14++0x03
line.long 0x00 "MISC_ROOT118_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBB18++0x03
line.long 0x00 "MISC_ROOT118_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBB1C++0x03
line.long 0x00 "MISC_ROOT118_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBB20++0x03
line.long 0x00 "POST118,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB24++0x03
line.long 0x00 "POST_ROOT118_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB28++0x03
line.long 0x00 "POST_ROOT118_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB2C++0x03
line.long 0x00 "POST_ROOT118_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB30++0x03
line.long 0x00 "PRE118,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBB34++0x03
line.long 0x00 "PRE_ROOT118_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBB38++0x03
line.long 0x00 "PRE_ROOT118_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBB3C++0x03
line.long 0x00 "PRE_ROOT118_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBB70++0x03
line.long 0x00 "ACCESS_CTRL118,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBB74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT118_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBB78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT118_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBB7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT118_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBB80++0x03
line.long 0x00 "TARGET_ROOT119,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB84++0x03
line.long 0x00 "TARGET_ROOT119_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB88++0x03
line.long 0x00 "TARGET_ROOT119_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB8C++0x03
line.long 0x00 "TARGET_ROOT119_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBB90++0x03
line.long 0x00 "MISC119,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBB94++0x03
line.long 0x00 "MISC_ROOT119_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBB98++0x03
line.long 0x00 "MISC_ROOT119_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBB9C++0x03
line.long 0x00 "MISC_ROOT119_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBBA0++0x03
line.long 0x00 "POST119,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBBA4++0x03
line.long 0x00 "POST_ROOT119_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBBA8++0x03
line.long 0x00 "POST_ROOT119_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBBAC++0x03
line.long 0x00 "POST_ROOT119_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBBB0++0x03
line.long 0x00 "PRE119,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBBB4++0x03
line.long 0x00 "PRE_ROOT119_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBBB8++0x03
line.long 0x00 "PRE_ROOT119_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBBBC++0x03
line.long 0x00 "PRE_ROOT119_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBBF0++0x03
line.long 0x00 "ACCESS_CTRL119,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBBF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT119_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBBF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT119_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBBFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT119_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBC00++0x03
line.long 0x00 "TARGET_ROOT120,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC04++0x03
line.long 0x00 "TARGET_ROOT120_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC08++0x03
line.long 0x00 "TARGET_ROOT120_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC0C++0x03
line.long 0x00 "TARGET_ROOT120_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC10++0x03
line.long 0x00 "MISC120,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBC14++0x03
line.long 0x00 "MISC_ROOT120_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBC18++0x03
line.long 0x00 "MISC_ROOT120_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBC1C++0x03
line.long 0x00 "MISC_ROOT120_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBC20++0x03
line.long 0x00 "POST120,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC24++0x03
line.long 0x00 "POST_ROOT120_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC28++0x03
line.long 0x00 "POST_ROOT120_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC2C++0x03
line.long 0x00 "POST_ROOT120_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC30++0x03
line.long 0x00 "PRE120,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBC34++0x03
line.long 0x00 "PRE_ROOT120_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBC38++0x03
line.long 0x00 "PRE_ROOT120_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBC3C++0x03
line.long 0x00 "PRE_ROOT120_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBC70++0x03
line.long 0x00 "ACCESS_CTRL120,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBC74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT120_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBC78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT120_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBC7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT120_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBC80++0x03
line.long 0x00 "TARGET_ROOT121,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC84++0x03
line.long 0x00 "TARGET_ROOT121_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC88++0x03
line.long 0x00 "TARGET_ROOT121_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC8C++0x03
line.long 0x00 "TARGET_ROOT121_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBC90++0x03
line.long 0x00 "MISC121,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBC94++0x03
line.long 0x00 "MISC_ROOT121_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBC98++0x03
line.long 0x00 "MISC_ROOT121_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBC9C++0x03
line.long 0x00 "MISC_ROOT121_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBCA0++0x03
line.long 0x00 "POST121,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBCA4++0x03
line.long 0x00 "POST_ROOT121_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBCA8++0x03
line.long 0x00 "POST_ROOT121_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBCAC++0x03
line.long 0x00 "POST_ROOT121_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBCB0++0x03
line.long 0x00 "PRE121,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBCB4++0x03
line.long 0x00 "PRE_ROOT121_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBCB8++0x03
line.long 0x00 "PRE_ROOT121_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBCBC++0x03
line.long 0x00 "PRE_ROOT121_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBCF0++0x03
line.long 0x00 "ACCESS_CTRL121,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBCF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT121_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBCF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT121_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBCFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT121_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBD00++0x03
line.long 0x00 "TARGET_ROOT122,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD04++0x03
line.long 0x00 "TARGET_ROOT122_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD08++0x03
line.long 0x00 "TARGET_ROOT122_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD0C++0x03
line.long 0x00 "TARGET_ROOT122_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD10++0x03
line.long 0x00 "MISC122,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBD14++0x03
line.long 0x00 "MISC_ROOT122_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBD18++0x03
line.long 0x00 "MISC_ROOT122_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBD1C++0x03
line.long 0x00 "MISC_ROOT122_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBD20++0x03
line.long 0x00 "POST122,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD24++0x03
line.long 0x00 "POST_ROOT122_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD28++0x03
line.long 0x00 "POST_ROOT122_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD2C++0x03
line.long 0x00 "POST_ROOT122_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD30++0x03
line.long 0x00 "PRE122,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBD34++0x03
line.long 0x00 "PRE_ROOT122_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBD38++0x03
line.long 0x00 "PRE_ROOT122_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBD3C++0x03
line.long 0x00 "PRE_ROOT122_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBD70++0x03
line.long 0x00 "ACCESS_CTRL122,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBD74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT122_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBD78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT122_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBD7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT122_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBD80++0x03
line.long 0x00 "TARGET_ROOT123,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD84++0x03
line.long 0x00 "TARGET_ROOT123_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD88++0x03
line.long 0x00 "TARGET_ROOT123_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD8C++0x03
line.long 0x00 "TARGET_ROOT123_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBD90++0x03
line.long 0x00 "MISC123,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBD94++0x03
line.long 0x00 "MISC_ROOT123_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBD98++0x03
line.long 0x00 "MISC_ROOT123_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBD9C++0x03
line.long 0x00 "MISC_ROOT123_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBDA0++0x03
line.long 0x00 "POST123,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBDA4++0x03
line.long 0x00 "POST_ROOT123_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBDA8++0x03
line.long 0x00 "POST_ROOT123_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBDAC++0x03
line.long 0x00 "POST_ROOT123_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBDB0++0x03
line.long 0x00 "PRE123,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBDB4++0x03
line.long 0x00 "PRE_ROOT123_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBDB8++0x03
line.long 0x00 "PRE_ROOT123_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBDBC++0x03
line.long 0x00 "PRE_ROOT123_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBDF0++0x03
line.long 0x00 "ACCESS_CTRL123,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBDF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT123_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBDF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT123_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBDFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT123_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBE00++0x03
line.long 0x00 "TARGET_ROOT124,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE04++0x03
line.long 0x00 "TARGET_ROOT124_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE08++0x03
line.long 0x00 "TARGET_ROOT124_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE0C++0x03
line.long 0x00 "TARGET_ROOT124_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE10++0x03
line.long 0x00 "MISC124,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBE14++0x03
line.long 0x00 "MISC_ROOT124_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBE18++0x03
line.long 0x00 "MISC_ROOT124_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBE1C++0x03
line.long 0x00 "MISC_ROOT124_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBE20++0x03
line.long 0x00 "POST124,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE24++0x03
line.long 0x00 "POST_ROOT124_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE28++0x03
line.long 0x00 "POST_ROOT124_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE2C++0x03
line.long 0x00 "POST_ROOT124_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE30++0x03
line.long 0x00 "PRE124,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBE34++0x03
line.long 0x00 "PRE_ROOT124_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBE38++0x03
line.long 0x00 "PRE_ROOT124_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBE3C++0x03
line.long 0x00 "PRE_ROOT124_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBE70++0x03
line.long 0x00 "ACCESS_CTRL124,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBE74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT124_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBE78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT124_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBE7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT124_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBE80++0x03
line.long 0x00 "TARGET_ROOT125,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE84++0x03
line.long 0x00 "TARGET_ROOT125_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE88++0x03
line.long 0x00 "TARGET_ROOT125_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE8C++0x03
line.long 0x00 "TARGET_ROOT125_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBE90++0x03
line.long 0x00 "MISC125,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBE94++0x03
line.long 0x00 "MISC_ROOT125_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBE98++0x03
line.long 0x00 "MISC_ROOT125_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBE9C++0x03
line.long 0x00 "MISC_ROOT125_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBEA0++0x03
line.long 0x00 "POST125,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBEA4++0x03
line.long 0x00 "POST_ROOT125_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBEA8++0x03
line.long 0x00 "POST_ROOT125_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBEAC++0x03
line.long 0x00 "POST_ROOT125_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBEB0++0x03
line.long 0x00 "PRE125,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBEB4++0x03
line.long 0x00 "PRE_ROOT125_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBEB8++0x03
line.long 0x00 "PRE_ROOT125_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBEBC++0x03
line.long 0x00 "PRE_ROOT125_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBEF0++0x03
line.long 0x00 "ACCESS_CTRL125,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBEF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT125_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBEF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT125_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBEFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT125_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBF00++0x03
line.long 0x00 "TARGET_ROOT126,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF04++0x03
line.long 0x00 "TARGET_ROOT126_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF08++0x03
line.long 0x00 "TARGET_ROOT126_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF0C++0x03
line.long 0x00 "TARGET_ROOT126_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF10++0x03
line.long 0x00 "MISC126,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBF14++0x03
line.long 0x00 "MISC_ROOT126_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBF18++0x03
line.long 0x00 "MISC_ROOT126_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBF1C++0x03
line.long 0x00 "MISC_ROOT126_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBF20++0x03
line.long 0x00 "POST126,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF24++0x03
line.long 0x00 "POST_ROOT126_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF28++0x03
line.long 0x00 "POST_ROOT126_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF2C++0x03
line.long 0x00 "POST_ROOT126_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF30++0x03
line.long 0x00 "PRE126,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBF34++0x03
line.long 0x00 "PRE_ROOT126_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBF38++0x03
line.long 0x00 "PRE_ROOT126_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBF3C++0x03
line.long 0x00 "PRE_ROOT126_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBF70++0x03
line.long 0x00 "ACCESS_CTRL126,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBF74++0x03
line.long 0x00 "ACCESS_CTRL_ROOT126_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBF78++0x03
line.long 0x00 "ACCESS_CTRL_ROOT126_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBF7C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT126_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBF80++0x03
line.long 0x00 "TARGET_ROOT127,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF84++0x03
line.long 0x00 "TARGET_ROOT127_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF88++0x03
line.long 0x00 "TARGET_ROOT127_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF8C++0x03
line.long 0x00 "TARGET_ROOT127_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBF90++0x03
line.long 0x00 "MISC127,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBF94++0x03
line.long 0x00 "MISC_ROOT127_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBF98++0x03
line.long 0x00 "MISC_ROOT127_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBF9C++0x03
line.long 0x00 "MISC_ROOT127_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xBFA0++0x03
line.long 0x00 "POST127,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBFA4++0x03
line.long 0x00 "POST_ROOT127_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBFA8++0x03
line.long 0x00 "POST_ROOT127_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBFAC++0x03
line.long 0x00 "POST_ROOT127_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xBFB0++0x03
line.long 0x00 "PRE127,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBFB4++0x03
line.long 0x00 "PRE_ROOT127_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBFB8++0x03
line.long 0x00 "PRE_ROOT127_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBFBC++0x03
line.long 0x00 "PRE_ROOT127_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xBFF0++0x03
line.long 0x00 "ACCESS_CTRL127,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBFF4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT127_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBFF8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT127_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBFFC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT127_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC000++0x03
line.long 0x00 "TARGET_ROOT128,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC004++0x03
line.long 0x00 "TARGET_ROOT128_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC008++0x03
line.long 0x00 "TARGET_ROOT128_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC00C++0x03
line.long 0x00 "TARGET_ROOT128_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC010++0x03
line.long 0x00 "MISC128,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC014++0x03
line.long 0x00 "MISC_ROOT128_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC018++0x03
line.long 0x00 "MISC_ROOT128_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC01C++0x03
line.long 0x00 "MISC_ROOT128_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC020++0x03
line.long 0x00 "POST128,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC024++0x03
line.long 0x00 "POST_ROOT128_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC028++0x03
line.long 0x00 "POST_ROOT128_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC02C++0x03
line.long 0x00 "POST_ROOT128_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC030++0x03
line.long 0x00 "PRE128,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC034++0x03
line.long 0x00 "PRE_ROOT128_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC038++0x03
line.long 0x00 "PRE_ROOT128_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC03C++0x03
line.long 0x00 "PRE_ROOT128_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC070++0x03
line.long 0x00 "ACCESS_CTRL128,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC074++0x03
line.long 0x00 "ACCESS_CTRL_ROOT128_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC078++0x03
line.long 0x00 "ACCESS_CTRL_ROOT128_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC07C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT128_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC080++0x03
line.long 0x00 "TARGET_ROOT129,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC084++0x03
line.long 0x00 "TARGET_ROOT129_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC088++0x03
line.long 0x00 "TARGET_ROOT129_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC08C++0x03
line.long 0x00 "TARGET_ROOT129_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC090++0x03
line.long 0x00 "MISC129,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC094++0x03
line.long 0x00 "MISC_ROOT129_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC098++0x03
line.long 0x00 "MISC_ROOT129_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC09C++0x03
line.long 0x00 "MISC_ROOT129_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC0A0++0x03
line.long 0x00 "POST129,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC0A4++0x03
line.long 0x00 "POST_ROOT129_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC0A8++0x03
line.long 0x00 "POST_ROOT129_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC0AC++0x03
line.long 0x00 "POST_ROOT129_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC0B0++0x03
line.long 0x00 "PRE129,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC0B4++0x03
line.long 0x00 "PRE_ROOT129_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC0B8++0x03
line.long 0x00 "PRE_ROOT129_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC0BC++0x03
line.long 0x00 "PRE_ROOT129_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC0F0++0x03
line.long 0x00 "ACCESS_CTRL129,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT129_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT129_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT129_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC100++0x03
line.long 0x00 "TARGET_ROOT130,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC104++0x03
line.long 0x00 "TARGET_ROOT130_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC108++0x03
line.long 0x00 "TARGET_ROOT130_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC10C++0x03
line.long 0x00 "TARGET_ROOT130_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC110++0x03
line.long 0x00 "MISC130,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC114++0x03
line.long 0x00 "MISC_ROOT130_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC118++0x03
line.long 0x00 "MISC_ROOT130_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC11C++0x03
line.long 0x00 "MISC_ROOT130_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC120++0x03
line.long 0x00 "POST130,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC124++0x03
line.long 0x00 "POST_ROOT130_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC128++0x03
line.long 0x00 "POST_ROOT130_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC12C++0x03
line.long 0x00 "POST_ROOT130_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC130++0x03
line.long 0x00 "PRE130,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC134++0x03
line.long 0x00 "PRE_ROOT130_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC138++0x03
line.long 0x00 "PRE_ROOT130_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC13C++0x03
line.long 0x00 "PRE_ROOT130_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC170++0x03
line.long 0x00 "ACCESS_CTRL130,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC174++0x03
line.long 0x00 "ACCESS_CTRL_ROOT130_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC178++0x03
line.long 0x00 "ACCESS_CTRL_ROOT130_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC17C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT130_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC180++0x03
line.long 0x00 "TARGET_ROOT131,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC184++0x03
line.long 0x00 "TARGET_ROOT131_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC188++0x03
line.long 0x00 "TARGET_ROOT131_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC18C++0x03
line.long 0x00 "TARGET_ROOT131_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC190++0x03
line.long 0x00 "MISC131,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC194++0x03
line.long 0x00 "MISC_ROOT131_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC198++0x03
line.long 0x00 "MISC_ROOT131_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC19C++0x03
line.long 0x00 "MISC_ROOT131_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC1A0++0x03
line.long 0x00 "POST131,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC1A4++0x03
line.long 0x00 "POST_ROOT131_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC1A8++0x03
line.long 0x00 "POST_ROOT131_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC1AC++0x03
line.long 0x00 "POST_ROOT131_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC1B0++0x03
line.long 0x00 "PRE131,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC1B4++0x03
line.long 0x00 "PRE_ROOT131_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC1B8++0x03
line.long 0x00 "PRE_ROOT131_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC1BC++0x03
line.long 0x00 "PRE_ROOT131_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC1F0++0x03
line.long 0x00 "ACCESS_CTRL131,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC1F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT131_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC1F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT131_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC1FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT131_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC200++0x03
line.long 0x00 "TARGET_ROOT132,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC204++0x03
line.long 0x00 "TARGET_ROOT132_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC208++0x03
line.long 0x00 "TARGET_ROOT132_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC20C++0x03
line.long 0x00 "TARGET_ROOT132_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC210++0x03
line.long 0x00 "MISC132,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC214++0x03
line.long 0x00 "MISC_ROOT132_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC218++0x03
line.long 0x00 "MISC_ROOT132_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC21C++0x03
line.long 0x00 "MISC_ROOT132_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC220++0x03
line.long 0x00 "POST132,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC224++0x03
line.long 0x00 "POST_ROOT132_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC228++0x03
line.long 0x00 "POST_ROOT132_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC22C++0x03
line.long 0x00 "POST_ROOT132_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC230++0x03
line.long 0x00 "PRE132,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC234++0x03
line.long 0x00 "PRE_ROOT132_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC238++0x03
line.long 0x00 "PRE_ROOT132_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC23C++0x03
line.long 0x00 "PRE_ROOT132_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC270++0x03
line.long 0x00 "ACCESS_CTRL132,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC274++0x03
line.long 0x00 "ACCESS_CTRL_ROOT132_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC278++0x03
line.long 0x00 "ACCESS_CTRL_ROOT132_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC27C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT132_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC280++0x03
line.long 0x00 "TARGET_ROOT133,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC284++0x03
line.long 0x00 "TARGET_ROOT133_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC288++0x03
line.long 0x00 "TARGET_ROOT133_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC28C++0x03
line.long 0x00 "TARGET_ROOT133_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC290++0x03
line.long 0x00 "MISC133,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC294++0x03
line.long 0x00 "MISC_ROOT133_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC298++0x03
line.long 0x00 "MISC_ROOT133_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC29C++0x03
line.long 0x00 "MISC_ROOT133_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC2A0++0x03
line.long 0x00 "POST133,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC2A4++0x03
line.long 0x00 "POST_ROOT133_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC2A8++0x03
line.long 0x00 "POST_ROOT133_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC2AC++0x03
line.long 0x00 "POST_ROOT133_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
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rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC2B0++0x03
line.long 0x00 "PRE133,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC2B4++0x03
line.long 0x00 "PRE_ROOT133_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC2B8++0x03
line.long 0x00 "PRE_ROOT133_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC2BC++0x03
line.long 0x00 "PRE_ROOT133_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC2F0++0x03
line.long 0x00 "ACCESS_CTRL133,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC2F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT133_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC2F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT133_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC2FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT133_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC300++0x03
line.long 0x00 "TARGET_ROOT134,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC304++0x03
line.long 0x00 "TARGET_ROOT134_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC308++0x03
line.long 0x00 "TARGET_ROOT134_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC30C++0x03
line.long 0x00 "TARGET_ROOT134_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC310++0x03
line.long 0x00 "MISC134,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC314++0x03
line.long 0x00 "MISC_ROOT134_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC318++0x03
line.long 0x00 "MISC_ROOT134_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC31C++0x03
line.long 0x00 "MISC_ROOT134_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC320++0x03
line.long 0x00 "POST134,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC324++0x03
line.long 0x00 "POST_ROOT134_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC328++0x03
line.long 0x00 "POST_ROOT134_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC32C++0x03
line.long 0x00 "POST_ROOT134_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC330++0x03
line.long 0x00 "PRE134,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC334++0x03
line.long 0x00 "PRE_ROOT134_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC338++0x03
line.long 0x00 "PRE_ROOT134_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC33C++0x03
line.long 0x00 "PRE_ROOT134_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC370++0x03
line.long 0x00 "ACCESS_CTRL134,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC374++0x03
line.long 0x00 "ACCESS_CTRL_ROOT134_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC378++0x03
line.long 0x00 "ACCESS_CTRL_ROOT134_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC37C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT134_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC380++0x03
line.long 0x00 "TARGET_ROOT135,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC384++0x03
line.long 0x00 "TARGET_ROOT135_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC388++0x03
line.long 0x00 "TARGET_ROOT135_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC38C++0x03
line.long 0x00 "TARGET_ROOT135_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC390++0x03
line.long 0x00 "MISC135,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC394++0x03
line.long 0x00 "MISC_ROOT135_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC398++0x03
line.long 0x00 "MISC_ROOT135_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC39C++0x03
line.long 0x00 "MISC_ROOT135_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC3A0++0x03
line.long 0x00 "POST135,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC3A4++0x03
line.long 0x00 "POST_ROOT135_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC3A8++0x03
line.long 0x00 "POST_ROOT135_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC3AC++0x03
line.long 0x00 "POST_ROOT135_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC3B0++0x03
line.long 0x00 "PRE135,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC3B4++0x03
line.long 0x00 "PRE_ROOT135_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC3B8++0x03
line.long 0x00 "PRE_ROOT135_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC3BC++0x03
line.long 0x00 "PRE_ROOT135_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC3F0++0x03
line.long 0x00 "ACCESS_CTRL135,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC3F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT135_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC3F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT135_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC3FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT135_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC400++0x03
line.long 0x00 "TARGET_ROOT136,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC404++0x03
line.long 0x00 "TARGET_ROOT136_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC408++0x03
line.long 0x00 "TARGET_ROOT136_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC40C++0x03
line.long 0x00 "TARGET_ROOT136_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC410++0x03
line.long 0x00 "MISC136,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC414++0x03
line.long 0x00 "MISC_ROOT136_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC418++0x03
line.long 0x00 "MISC_ROOT136_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC41C++0x03
line.long 0x00 "MISC_ROOT136_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC420++0x03
line.long 0x00 "POST136,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC424++0x03
line.long 0x00 "POST_ROOT136_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC428++0x03
line.long 0x00 "POST_ROOT136_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC42C++0x03
line.long 0x00 "POST_ROOT136_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC430++0x03
line.long 0x00 "PRE136,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC434++0x03
line.long 0x00 "PRE_ROOT136_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC438++0x03
line.long 0x00 "PRE_ROOT136_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC43C++0x03
line.long 0x00 "PRE_ROOT136_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC470++0x03
line.long 0x00 "ACCESS_CTRL136,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC474++0x03
line.long 0x00 "ACCESS_CTRL_ROOT136_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC478++0x03
line.long 0x00 "ACCESS_CTRL_ROOT136_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC47C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT136_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC480++0x03
line.long 0x00 "TARGET_ROOT137,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC484++0x03
line.long 0x00 "TARGET_ROOT137_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC488++0x03
line.long 0x00 "TARGET_ROOT137_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC48C++0x03
line.long 0x00 "TARGET_ROOT137_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC490++0x03
line.long 0x00 "MISC137,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC494++0x03
line.long 0x00 "MISC_ROOT137_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC498++0x03
line.long 0x00 "MISC_ROOT137_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC49C++0x03
line.long 0x00 "MISC_ROOT137_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC4A0++0x03
line.long 0x00 "POST137,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC4A4++0x03
line.long 0x00 "POST_ROOT137_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC4A8++0x03
line.long 0x00 "POST_ROOT137_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC4AC++0x03
line.long 0x00 "POST_ROOT137_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC4B0++0x03
line.long 0x00 "PRE137,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC4B4++0x03
line.long 0x00 "PRE_ROOT137_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC4B8++0x03
line.long 0x00 "PRE_ROOT137_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC4BC++0x03
line.long 0x00 "PRE_ROOT137_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC4F0++0x03
line.long 0x00 "ACCESS_CTRL137,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC4F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT137_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC4F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT137_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC4FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT137_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC500++0x03
line.long 0x00 "TARGET_ROOT138,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC504++0x03
line.long 0x00 "TARGET_ROOT138_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC508++0x03
line.long 0x00 "TARGET_ROOT138_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC50C++0x03
line.long 0x00 "TARGET_ROOT138_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC510++0x03
line.long 0x00 "MISC138,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC514++0x03
line.long 0x00 "MISC_ROOT138_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC518++0x03
line.long 0x00 "MISC_ROOT138_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC51C++0x03
line.long 0x00 "MISC_ROOT138_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC520++0x03
line.long 0x00 "POST138,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC524++0x03
line.long 0x00 "POST_ROOT138_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC528++0x03
line.long 0x00 "POST_ROOT138_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC52C++0x03
line.long 0x00 "POST_ROOT138_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC530++0x03
line.long 0x00 "PRE138,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC534++0x03
line.long 0x00 "PRE_ROOT138_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC538++0x03
line.long 0x00 "PRE_ROOT138_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC53C++0x03
line.long 0x00 "PRE_ROOT138_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC570++0x03
line.long 0x00 "ACCESS_CTRL138,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC574++0x03
line.long 0x00 "ACCESS_CTRL_ROOT138_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC578++0x03
line.long 0x00 "ACCESS_CTRL_ROOT138_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC57C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT138_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC580++0x03
line.long 0x00 "TARGET_ROOT139,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC584++0x03
line.long 0x00 "TARGET_ROOT139_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC588++0x03
line.long 0x00 "TARGET_ROOT139_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC58C++0x03
line.long 0x00 "TARGET_ROOT139_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC590++0x03
line.long 0x00 "MISC139,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC594++0x03
line.long 0x00 "MISC_ROOT139_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC598++0x03
line.long 0x00 "MISC_ROOT139_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC59C++0x03
line.long 0x00 "MISC_ROOT139_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC5A0++0x03
line.long 0x00 "POST139,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC5A4++0x03
line.long 0x00 "POST_ROOT139_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC5A8++0x03
line.long 0x00 "POST_ROOT139_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC5AC++0x03
line.long 0x00 "POST_ROOT139_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC5B0++0x03
line.long 0x00 "PRE139,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
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bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC5B4++0x03
line.long 0x00 "PRE_ROOT139_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
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bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC5B8++0x03
line.long 0x00 "PRE_ROOT139_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC5BC++0x03
line.long 0x00 "PRE_ROOT139_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC5F0++0x03
line.long 0x00 "ACCESS_CTRL139,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC5F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT139_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC5F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT139_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC5FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT139_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC600++0x03
line.long 0x00 "TARGET_ROOT140,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC604++0x03
line.long 0x00 "TARGET_ROOT140_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC608++0x03
line.long 0x00 "TARGET_ROOT140_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC60C++0x03
line.long 0x00 "TARGET_ROOT140_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC610++0x03
line.long 0x00 "MISC140,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC614++0x03
line.long 0x00 "MISC_ROOT140_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC618++0x03
line.long 0x00 "MISC_ROOT140_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC61C++0x03
line.long 0x00 "MISC_ROOT140_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC620++0x03
line.long 0x00 "POST140,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC624++0x03
line.long 0x00 "POST_ROOT140_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC628++0x03
line.long 0x00 "POST_ROOT140_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC62C++0x03
line.long 0x00 "POST_ROOT140_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC630++0x03
line.long 0x00 "PRE140,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC634++0x03
line.long 0x00 "PRE_ROOT140_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC638++0x03
line.long 0x00 "PRE_ROOT140_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC63C++0x03
line.long 0x00 "PRE_ROOT140_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC670++0x03
line.long 0x00 "ACCESS_CTRL140,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC674++0x03
line.long 0x00 "ACCESS_CTRL_ROOT140_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC678++0x03
line.long 0x00 "ACCESS_CTRL_ROOT140_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC67C++0x03
line.long 0x00 "ACCESS_CTRL_ROOT140_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC680++0x03
line.long 0x00 "TARGET_ROOT141,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC684++0x03
line.long 0x00 "TARGET_ROOT141_SET,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC688++0x03
line.long 0x00 "TARGET_ROOT141_CLR,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divider divide the number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC68C++0x03
line.long 0x00 "TARGET_ROOT141_TOG,Target Register"
bitfld.long 0x00 28. "ENABLE,Enable this clock" "0: clock root is OFF,1: clock root is ON"
bitfld.long 0x00 24.--26. "MUX,Selection of clock sources This field is 1 bit long for DRAM and CORE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRE_PODF,Pre divide divide number Divider value is n+1 This field does not apply for CORE DRAM DRAM_PHYM" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC690++0x03
line.long 0x00 "MISC141,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
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bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC694++0x03
line.long 0x00 "MISC_ROOT141_SET,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC698++0x03
line.long 0x00 "MISC_ROOT141_CLR,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC69C++0x03
line.long 0x00 "MISC_ROOT141_TOG,Miscellaneous Register"
bitfld.long 0x00 8. "VIOLATE,This sticky bit reflects access violation in normal interface of this clock" "0,1"
bitfld.long 0x00 4. "TIMEOUT,This sticky bit reflects time out happened during accessing this clock" "0,1"
newline
bitfld.long 0x00 0. "AUTHEN_FAIL,This sticky bit reflects access restricted by access control of this clock" "0,1"
group.long 0xC6A0++0x03
line.long 0x00 "POST141,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC6A4++0x03
line.long 0x00 "POST_ROOT141_SET,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC6A8++0x03
line.long 0x00 "POST_ROOT141_CLR,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide the number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC6AC++0x03
line.long 0x00 "POST_ROOT141_TOG,Post Divider Register"
rbitfld.long 0x00 31. "BUSY2,Clock switching multiplexer is applying new setting" "0,1"
bitfld.long 0x00 28. "SELECT,Selection of pre clock branches This field is not applied in IP" "0: select branch A,1: select branch B"
newline
rbitfld.long 0x00 7. "BUSY1,Post divider is applying new set value" "0,1"
bitfld.long 0x00 0.--5. "POST_PODF,Post divider divide number Divider value is n + 1 For CORE this field is 3 bit long" "0: POST_PODF_0,1: POST_PODF_1,2: POST_PODF_2,3: POST_PODF_3,4: POST_PODF_4,5: POST_PODF_5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: POST_PODF_63"
group.long 0xC6B0++0x03
line.long 0x00 "PRE141,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
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bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC6B4++0x03
line.long 0x00 "PRE_ROOT141_SET,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applying field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC6B8++0x03
line.long 0x00 "PRE_ROOT141_CLR,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch A is applied This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC6BC++0x03
line.long 0x00 "PRE_ROOT141_TOG,Pre Divider Register"
rbitfld.long 0x00 31. "BUSY4,EN_A field is applied to field This field applies to DRAM and DRAM_PHYM" "0,1"
bitfld.long 0x00 28. "EN_A,Branch A clock gate control This field applies to DRAM and DRAM_PHYM" "0: Clock shutdown,1: clock ON"
newline
bitfld.long 0x00 24.--26. "MUX_A,Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "BUSY3,Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 16.--18. "PRE_PODF_A,Pre divider divide number for branch A Divider value is n + 1" "0: PRE_PODF_A_0,1: PRE_PODF_A_1,2: PRE_PODF_A_2,3: PRE_PODF_A_3,4: PRE_PODF_A_4,5: PRE_PODF_A_5,6: PRE_PODF_A_6,7: PRE_PODF_A_7"
rbitfld.long 0x00 15. "BUSY1,EN_B is applied to field This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
newline
bitfld.long 0x00 12. "EN_B,Branch B clock gate control This field does not apply for CORE IP DRAM DRAM_PHYM" "0: Clock shutdown,1: Clock ON"
bitfld.long 0x00 8.--10. "MUX_B,Selection control of multiplexer of branch B This field does not apply for CORE IP DRAM DRAM_PHYM" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "BUSY0,Pre divider value for branch a is applied field does not apply for CORE IP DRAM DRAM_PHYM" "0,1"
bitfld.long 0x00 0.--2. "PRE_PODF_B,Pre divider divide number for branch B Divider value is n + 1" "0: PRE_PODF_B_0,1: PRE_PODF_B_1,2: PRE_PODF_B_2,3: PRE_PODF_B_3,4: PRE_PODF_B_4,5: PRE_PODF_B_5,6: PRE_PODF_B_6,7: PRE_PODF_B_7"
group.long 0xC6F0++0x03
line.long 0x00 "ACCESS_CTRL141,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
newline
bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC6F4++0x03
line.long 0x00 "ACCESS_CTRL_ROOT141_SET,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
newline
bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
newline
bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC6F8++0x03
line.long 0x00 "ACCESS_CTRL_ROOT141_CLR,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC6FC++0x03
line.long 0x00 "ACCESS_CTRL_ROOT141_TOG,Access Control Register"
bitfld.long 0x00 31. "LOCK,Lock this clock root to use access control This bit can be set to 1 by software and can be cleared only by system reset" "0: Access control inactive,1: Access control active"
bitfld.long 0x00 28. "SEMA_EN,Enable internal semaphore This field cannot be changed when lock bit is 1" "0: SEMA_EN_0,1: SEMA_EN_1"
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bitfld.long 0x00 27. "DOMAIN3_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 26. "DOMAIN2_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 25. "DOMAIN1_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
bitfld.long 0x00 24. "DOMAIN0_WHITELIST,White list of domains that can change setting of this clock root" "0: Domain cannot change the setting,1: Domain can change the setting"
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bitfld.long 0x00 20. "MUTEX,Semaphore to control access" "0: Semaphore is free to take,1: Semaphore is taken"
rbitfld.long 0x00 16.--17. "OWNER_ID,Current domain that owns semaphore This field is meaningless when MUTEX is 0" "0: OWNER_ID_0,1: OWNER_ID_1,2: OWNER_ID_2,3: OWNER_ID_3"
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bitfld.long 0x00 12.--15. "DOMAIN3_INFO,Information from domain 3 to pass to others This field can only be changed by domain 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DOMAIN2_INFO,Information from domain 2 to pass to others This field can only be changed by domain 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DOMAIN1_INFO,Information from domain 1 to pass to others This field can only be changed by domain 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DOMAIN0_INFO,Information from domain 0 to pass to others This field can only be changed by domain 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "CCM_ANALOG"
base ad:0x30360000
group.long 0x00++0x03
line.long 0x00 "AUDIO_PLL1_GEN_CTRL,AUDIO PLL1 General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 16. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
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bitfld.long 0x00 13. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
bitfld.long 0x00 12. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
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bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
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bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
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bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x04++0x03
line.long 0x00 "AUDIO_PLL1_FDIV_CTL0,AUDIO PLL1 Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "AUDIO_PLL1_FDIV_CTL1,AUDIO PLL1 Divide and Fraction Data Control 1 Register"
hexmask.long.word 0x00 0.--15. 1. "PLL_DSM,Value of the DSM"
group.long 0x0C++0x03
line.long 0x00 "AUDIO_PLL1_SSCG_CTRL,AUDIO PLL1 PLL SSCG Control Register"
bitfld.long 0x00 31. "SSCG_EN,SSCG Enable" "0: Disable Spread Spectrum Mode,1: Enable Spread Spectrum Mode"
hexmask.long.byte 0x00 12.--19. 1. "PLL_MFREQ_CTL,Value of modulation frequency control Modulation Frequency MF is determined by the following equation: MF = FFIN/p/mfr/(2^5) Hz FFIN is the PLL input clock frequency mfr is the decimal value for PLL_MFREQ_CTL[7:0] and p is the decimal.."
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bitfld.long 0x00 4.--9. "PLL_MRAT_CTL,Value of modulation rate control Modulation rate (pk-pk) MR is determined by the following equation: MR = mfr x mrr /m /(2^6) x 100 [%] mfr is the decimal value of PLL_MFREQ_CTL mrr is the decimal value for PLL_MRAT_CTL[5:0] and m is the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "SEL_PF,Value of modulation method control" "0: Down spread,1: Up spread,2: Center spread,3: Center spread"
group.long 0x10++0x03
line.long 0x00 "AUDIO_PLL1_MNIT_CTRL,AUDIO PLL1 PLL Monitoring Control Register"
bitfld.long 0x00 20. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 19. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
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bitfld.long 0x00 18. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 17. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
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bitfld.long 0x00 15. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 14. "FEED_EN,FEED_OUT enable pin" "0,1"
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bitfld.long 0x00 4.--8. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
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bitfld.long 0x00 0.--2. "ICP,Controls the charge-pump current" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "AUDIO_PLL2_GEN_CTRL,AUDIO PLL2 General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 16. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
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bitfld.long 0x00 13. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
bitfld.long 0x00 12. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
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bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
newline
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
newline
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x18++0x03
line.long 0x00 "AUDIO_PLL2_FDIV_CTL0,AUDIO PLL2 Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x1C++0x03
line.long 0x00 "AUDIO_PLL2_FDIV_CTL1,AUDIO PLL2 Divide and Fraction Data Control 1 Register"
hexmask.long.word 0x00 0.--15. 1. "PLL_DSM,Value of the DSM"
group.long 0x20++0x03
line.long 0x00 "AUDIO_PLL2_SSCG_CTRL,AUDIO PLL2 PLL SSCG Control Register"
bitfld.long 0x00 31. "SSCG_EN,SSCG Enable" "0: Disable Spread Spectrum Mode,1: Enable Spread Spectrum Mode"
hexmask.long.byte 0x00 12.--19. 1. "PLL_MFREQ_CTL,Value of modulation frequency control Modulation Frequency MF is determined by the following equation: MF = FFIN/p/mfr/(2^5) Hz FFIN is the PLL input clock frequency mfr is the decimal value for PLL_MFREQ_CTL[7:0] and p is the decimal.."
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bitfld.long 0x00 4.--9. "PLL_MRAT_CTL,Value of modulation rate control Modulation rate (pk-pk) MR is determined by the following equation: MR = mfr x mrr /m /(2^6) x 100 [%] mfr is the decimal value of PLL_MFREQ_CTL mrr is the decimal value for PLL_MRAT_CTL[5:0] and m is the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "SEL_PF,Value of modulation method control" "0: Down spread,1: Up spread,2: Center spread,3: Center spread"
group.long 0x24++0x03
line.long 0x00 "AUDIO_PLL2_MNIT_CTRL,AUDIO PLL2 PLL Monitoring Control Register"
bitfld.long 0x00 20. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 19. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
newline
bitfld.long 0x00 18. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 17. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
newline
bitfld.long 0x00 15. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 14. "FEED_EN,FEED_OUT enable pin" "0,1"
newline
bitfld.long 0x00 4.--8. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
newline
bitfld.long 0x00 0.--2. "ICP,Controls the charge-pump current" "0,1,2,3,4,5,6,7"
group.long 0x28++0x03
line.long 0x00 "VIDEO_PLL1_GEN_CTRL,VIDEO PLL1 General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 16. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
newline
bitfld.long 0x00 13. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
bitfld.long 0x00 12. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
newline
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
newline
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
newline
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x2C++0x03
line.long 0x00 "VIDEO_PLL1_FDIV_CTL0,VIDEO PLL1 Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x30++0x03
line.long 0x00 "VIDEO_PLL1_FDIV_CTL1,VIDEO PLL1 Divide and Fraction Data Control 1 Register"
hexmask.long.word 0x00 0.--15. 1. "PLL_DSM,Value of the DSM"
group.long 0x34++0x03
line.long 0x00 "VIDEO_PLL1_SSCG_CTRL,VIDEO PLL1 PLL SSCG Control Register"
bitfld.long 0x00 31. "SSCG_EN,SSCG Enable" "0: Disable Spread Spectrum Mode,1: Enable Spread Spectrum Mode"
hexmask.long.byte 0x00 12.--19. 1. "PLL_MFREQ_CTL,Value of modulation frequency control Modulation Frequency MF is determined by the following equation: MF = FFIN/p/mfr/(2^5) Hz FFIN is the PLL input clock frequency mfr is the decimal value for PLL_MFREQ_CTL[7:0] and p is the decimal.."
newline
bitfld.long 0x00 4.--9. "PLL_MRAT_CTL,Value of modulation rate control Modulation rate (pk-pk) MR is determined by the following equation: MR = mfr x mrr /m /(2^6) x 100 [%] mfr is the decimal value of PLL_MFREQ_CTL mrr is the decimal value for PLL_MRAT_CTL[5:0] and m is the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "SEL_PF,Value of modulation method control" "0: Down spread,1: Up spread,2: Center spread,3: Center spread"
group.long 0x38++0x03
line.long 0x00 "VIDEO_PLL1_MNIT_CTRL,VIDEO PLL1 PLL Monitoring Control Register"
bitfld.long 0x00 20. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 19. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
newline
bitfld.long 0x00 18. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 17. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
newline
bitfld.long 0x00 15. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 14. "FEED_EN,FEED_OUT enable pin" "0,1"
newline
bitfld.long 0x00 4.--8. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
newline
bitfld.long 0x00 0.--2. "ICP,Controls the charge-pump current" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "DRAM_PLL_GEN_CTRL,DRAM PLL General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 16. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
newline
bitfld.long 0x00 13. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
bitfld.long 0x00 12. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
newline
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
newline
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
newline
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x54++0x03
line.long 0x00 "DRAM_PLL_FDIV_CTL0,DRAM PLL Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x58++0x03
line.long 0x00 "DRAM_PLL_FDIV_CTL1,DRAM PLL Divide and Fraction Data Control 1 Register"
hexmask.long.word 0x00 0.--15. 1. "PLL_DSM,Value of the DSM"
group.long 0x5C++0x03
line.long 0x00 "DRAM_PLL_SSCG_CTRL,DRAM PLL PLL SSCG Control Register"
bitfld.long 0x00 31. "SSCG_EN,SSCG Enable" "0: Disable Spread Spectrum Mode,1: Enable Spread Spectrum Mode"
hexmask.long.byte 0x00 12.--19. 1. "PLL_MFREQ_CTL,Value of modulation frequency control Modulation Frequency MF is determined by the following equation: MF = FFIN/p/mfr/(2^5) Hz FFIN is the PLL input clock frequency mfr is the decimal value for PLL_MFREQ_CTL[7:0] and p is the decimal.."
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bitfld.long 0x00 4.--9. "PLL_MRAT_CTL,Value of modulation rate control Modulation rate (pk-pk) MR is determined by the following equation: MR = mfr x mrr /m /(2^6) x 100 [%] mfr is the decimal value of PLL_MFREQ_CTL mrr is the decimal value for PLL_MRAT_CTL[5:0] and m is the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "SEL_PF,Value of modulation method control" "0: Down spread,1: Up spread,2: Center spread,3: Center spread"
group.long 0x60++0x03
line.long 0x00 "DRAM_PLL_MNIT_CTRL,DRAM PLL PLL Monitoring Control Register"
bitfld.long 0x00 20. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 19. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
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bitfld.long 0x00 18. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 17. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
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bitfld.long 0x00 15. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 14. "FEED_EN,FEED_OUT enable pin" "0,1"
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bitfld.long 0x00 4.--8. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
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bitfld.long 0x00 0.--2. "ICP,Controls the charge-pump current" "0,1,2,3,4,5,6,7"
group.long 0x64++0x03
line.long 0x00 "GPU_PLL_GEN_CTRL,GPU PLL General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 29. "PLL_LOCK_SEL,PLL lock select" "0: Using PLL maximum lock time,1: Using PLL output lock"
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bitfld.long 0x00 28. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
bitfld.long 0x00 11. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
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bitfld.long 0x00 10. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
newline
bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
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bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x68++0x03
line.long 0x00 "GPU_PLL_FDIV_CTL0,GPU PLL Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x6C++0x03
line.long 0x00 "GPU_PLL_LOCKD_CTRL,PLL Lock Detector Control Register"
bitfld.long 0x00 4.--5. "LOCK_CON_DLY,Lock detector setting of the detection resolution" "0,1,2,3"
bitfld.long 0x00 2.--3. "LOCK_CON_OUT,Lock detector setting of the output margin" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "LOCK_CON_IN,Lock detector setting of the input margin" "0,1,2,3"
group.long 0x70++0x03
line.long 0x00 "GPU_PLL_MNIT_CTRL,PLL Monitoring Control Register"
bitfld.long 0x00 21. "LRD_EN,Monitoring pin" "0,1"
bitfld.long 0x00 20. "FOUT_MASK,Scaler's re-initialization time control pin[3]" "0,1"
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bitfld.long 0x00 19. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 18. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
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bitfld.long 0x00 17. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 16. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
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bitfld.long 0x00 14. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 13. "FEED_EN,FEED_OUT enable pin" "0,1"
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bitfld.long 0x00 3.--7. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
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bitfld.long 0x00 0.--1. "ICP,Controls the charge-pump current" "0,1,2,3"
group.long 0x74++0x03
line.long 0x00 "VPU_PLL_GEN_CTRL,VPU PLL General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 29. "PLL_LOCK_SEL,PLL lock select" "0: Using PLL maximum lock time,1: Using PLL output lock"
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bitfld.long 0x00 28. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
bitfld.long 0x00 11. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
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bitfld.long 0x00 10. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
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bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
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bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x78++0x03
line.long 0x00 "VPU_PLL_FDIV_CTL0,VPU PLL Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x7C++0x03
line.long 0x00 "VPU_PLL_LOCKD_CTRL,PLL Lock Detector Control Register"
bitfld.long 0x00 4.--5. "LOCK_CON_DLY,Lock detector setting of the detection resolution" "0,1,2,3"
bitfld.long 0x00 2.--3. "LOCK_CON_OUT,Lock detector setting of the output margin" "0,1,2,3"
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bitfld.long 0x00 0.--1. "LOCK_CON_IN,Lock detector setting of the input margin" "0,1,2,3"
group.long 0x80++0x03
line.long 0x00 "VPU_PLL_MNIT_CTRL,PLL Monitoring Control Register"
bitfld.long 0x00 21. "LRD_EN,Monitoring pin" "0,1"
bitfld.long 0x00 20. "FOUT_MASK,Scaler's re-initialization time control pin[3]" "0,1"
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bitfld.long 0x00 19. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 18. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
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bitfld.long 0x00 17. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 16. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
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bitfld.long 0x00 14. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 13. "FEED_EN,FEED_OUT enable pin" "0,1"
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bitfld.long 0x00 3.--7. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
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bitfld.long 0x00 0.--1. "ICP,Controls the charge-pump current" "0,1,2,3"
group.long 0x84++0x03
line.long 0x00 "ARM_PLL_GEN_CTRL,ARM PLL General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 29. "PLL_LOCK_SEL,PLL lock select" "0: Using PLL maximum lock time,1: Using PLL output lock"
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bitfld.long 0x00 28. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
bitfld.long 0x00 11. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
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bitfld.long 0x00 10. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
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bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
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bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x88++0x03
line.long 0x00 "ARM_PLL_FDIV_CTL0,ARM PLL Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x8C++0x03
line.long 0x00 "ARM_PLL_LOCKD_CTRL,PLL Lock Detector Control Register"
bitfld.long 0x00 4.--5. "LOCK_CON_DLY,Lock detector setting of the detection resolution" "0,1,2,3"
bitfld.long 0x00 2.--3. "LOCK_CON_OUT,Lock detector setting of the output margin" "0,1,2,3"
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bitfld.long 0x00 0.--1. "LOCK_CON_IN,Lock detector setting of the input margin" "0,1,2,3"
group.long 0x90++0x03
line.long 0x00 "ARM_PLL_MNIT_CTRL,PLL Monitoring Control Register"
bitfld.long 0x00 21. "LRD_EN,Monitoring pin" "0,1"
bitfld.long 0x00 20. "FOUT_MASK,Scaler's re-initialization time control pin[3]" "0,1"
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bitfld.long 0x00 19. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 18. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
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bitfld.long 0x00 17. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 16. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
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bitfld.long 0x00 14. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 13. "FEED_EN,FEED_OUT enable pin" "0,1"
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bitfld.long 0x00 3.--7. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
newline
bitfld.long 0x00 0.--1. "ICP,Controls the charge-pump current" "0,1,2,3"
group.long 0x94++0x03
line.long 0x00 "SYS_PLL1_GEN_CTRL,SYS PLL1 General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 29. "PLL_LOCK_SEL,PLL lock select" "0: Using PLL maximum lock time,1: Using PLL output lock"
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bitfld.long 0x00 28. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
bitfld.long 0x00 27. "PLL_DIV20_CLKE,PLL clock divided by 20 output gating enable" "0,1"
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bitfld.long 0x00 26. "PLL_DIV20_CLKE_OVERRIDE,PLL clock divided by 20 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 25. "PLL_DIV10_CLKE,PLL clock divided by 10 output gating enable" "0,1"
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bitfld.long 0x00 24. "PLL_DIV10_CLKE_OVERRIDE,PLL clock divided by 10 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 23. "PLL_DIV8_CLKE,PLL clock divided by 8 output gating enable" "0,1"
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bitfld.long 0x00 22. "PLL_DIV8_CLKE_OVERRIDE,PLL clock divided by 8 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 21. "PLL_DIV6_CLKE,PLL clock divided by 6 output gating enable" "0,1"
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bitfld.long 0x00 20. "PLL_DIV6_CLKE_OVERRIDE,PLL clock divided by 6 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 19. "PLL_DIV5_CLKE,PLL clock divided by 5 output gating enable" "0,1"
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bitfld.long 0x00 18. "PLL_DIV5_CLKE_OVERRIDE,PLL clock divided by 5 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 17. "PLL_DIV4_CLKE,PLL clock divided by 4 output gating enable" "0,1"
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bitfld.long 0x00 16. "PLL_DIV4_CLKE_OVERRIDE,PLL clock divided by 4 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 15. "PLL_DIV3_CLKE,PLL clock divided by 3 output gating enable" "0,1"
newline
bitfld.long 0x00 14. "PLL_DIV3_CLKE_OVERRIDE,PLL clock divided by 3 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 13. "PLL_DIV2_CLKE,PLL clock divided by 2 output gating enable" "0,1"
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bitfld.long 0x00 12. "PLL_DIV2_CLKE_OVERRIDE,PLL clock divided by 2 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 11. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
newline
bitfld.long 0x00 10. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
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bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
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bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x98++0x03
line.long 0x00 "SYS_PLL1_FDIV_CTL0,SYS PLL1 Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x9C++0x03
line.long 0x00 "SYS_PLL1_LOCKD_CTRL,PLL Lock Detector Control Register"
bitfld.long 0x00 4.--5. "LOCK_CON_DLY,Lock detector setting of the detection resolution" "0,1,2,3"
bitfld.long 0x00 2.--3. "LOCK_CON_OUT,Lock detector setting of the output margin" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "LOCK_CON_IN,Lock detector setting of the input margin" "0,1,2,3"
group.long 0x100++0x03
line.long 0x00 "SYS_PLL1_MNIT_CTRL,PLL Monitoring Control Register"
bitfld.long 0x00 21. "LRD_EN,Monitoring pin" "0,1"
bitfld.long 0x00 20. "FOUT_MASK,Scaler's re-initialization time control pin[3]" "0,1"
newline
bitfld.long 0x00 19. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 18. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
newline
bitfld.long 0x00 17. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 16. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
newline
bitfld.long 0x00 14. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 13. "FEED_EN,FEED_OUT enable pin" "0,1"
newline
bitfld.long 0x00 3.--7. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
newline
bitfld.long 0x00 0.--1. "ICP,Controls the charge-pump current" "0,1,2,3"
group.long 0x104++0x03
line.long 0x00 "SYS_PLL2_GEN_CTRL,SYS PLL2 General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 29. "PLL_LOCK_SEL,PLL lock select" "0: Using PLL maximum lock time,1: Using PLL output lock"
newline
bitfld.long 0x00 28. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
bitfld.long 0x00 27. "PLL_DIV20_CLKE,PLL clock divided by 20 output gating enable" "0,1"
newline
bitfld.long 0x00 26. "PLL_DIV20_CLKE_OVERRIDE,PLL clock divided by 20 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 25. "PLL_DIV10_CLKE,PLL clock divided by 10 output gating enable" "0,1"
newline
bitfld.long 0x00 24. "PLL_DIV10_CLKE_OVERRIDE,PLL clock divided by 10 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 23. "PLL_DIV8_CLKE,PLL clock divided by 8 output gating enable" "0,1"
newline
bitfld.long 0x00 22. "PLL_DIV8_CLKE_OVERRIDE,PLL clock divided by 8 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 21. "PLL_DIV6_CLKE,PLL clock divided by 6 output gating enable" "0,1"
newline
bitfld.long 0x00 20. "PLL_DIV6_CLKE_OVERRIDE,PLL clock divided by 6 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 19. "PLL_DIV5_CLKE,PLL clock divided by 5 output gating enable" "0,1"
newline
bitfld.long 0x00 18. "PLL_DIV5_CLKE_OVERRIDE,PLL clock divided by 5 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 17. "PLL_DIV4_CLKE,PLL clock divided by 4 output gating enable" "0,1"
newline
bitfld.long 0x00 16. "PLL_DIV4_CLKE_OVERRIDE,PLL clock divided by 4 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 15. "PLL_DIV3_CLKE,PLL clock divided by 3 output gating enable" "0,1"
newline
bitfld.long 0x00 14. "PLL_DIV3_CLKE_OVERRIDE,PLL clock divided by 3 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 13. "PLL_DIV2_CLKE,PLL clock divided by 2 output gating enable" "0,1"
newline
bitfld.long 0x00 12. "PLL_DIV2_CLKE_OVERRIDE,PLL clock divided by 2 output gating enable overrided by CCM" "0,1"
bitfld.long 0x00 11. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
newline
bitfld.long 0x00 10. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
newline
bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
newline
bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x108++0x03
line.long 0x00 "SYS_PLL2_FDIV_CTL0,SYS PLL2 Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x10C++0x03
line.long 0x00 "SYS_PLL2_LOCKD_CTRL,PLL Lock Detector Control Register"
bitfld.long 0x00 4.--5. "LOCK_CON_DLY,Lock detector setting of the detection resolution" "0,1,2,3"
bitfld.long 0x00 2.--3. "LOCK_CON_OUT,Lock detector setting of the output margin" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "LOCK_CON_IN,Lock detector setting of the input margin" "0,1,2,3"
group.long 0x110++0x03
line.long 0x00 "SYS_PLL2_MNIT_CTRL,PLL Monitoring Control Register"
bitfld.long 0x00 21. "LRD_EN,Monitoring pin" "0,1"
bitfld.long 0x00 20. "FOUT_MASK,Scaler's re-initialization time control pin[3]" "0,1"
newline
bitfld.long 0x00 19. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 18. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
newline
bitfld.long 0x00 17. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 16. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
newline
bitfld.long 0x00 14. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 13. "FEED_EN,FEED_OUT enable pin" "0,1"
newline
bitfld.long 0x00 3.--7. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
newline
bitfld.long 0x00 0.--1. "ICP,Controls the charge-pump current" "0,1,2,3"
group.long 0x114++0x03
line.long 0x00 "SYS_PLL3_GEN_CTRL,SYS PLL3 General Function Control Register"
rbitfld.long 0x00 31. "PLL_LOCK,PLL lock signal" "0,1"
bitfld.long 0x00 29. "PLL_LOCK_SEL,PLL lock select" "0: Using PLL maximum lock time,1: Using PLL output lock"
newline
bitfld.long 0x00 28. "PLL_EXT_BYPASS,PLL analog block bypass clock output traces to PLL source" "0,1"
bitfld.long 0x00 11. "PLL_CLKE,PLL output clock clock gating enable" "0,1"
newline
bitfld.long 0x00 10. "PLL_CLKE_OVERRIDE,Override the PLL_CLKE clock gating enable signal from CCM" "0,1"
bitfld.long 0x00 9. "PLL_RST,PLL reset (active low)" "0,1"
newline
bitfld.long 0x00 8. "PLL_RST_OVERRIDE,PLL reset overrided by CCM" "0,1"
bitfld.long 0x00 4. "PLL_BYPASS,PLL output clock bypass" "0,1"
newline
bitfld.long 0x00 2.--3. "PAD_CLK_SEL,PAD clock select PAD_CLK is an alternate input reference clock for the PLL" "0: CLKIN1 XOR CLKIN2,1: PAD_CLK_SEL_1,2: PAD_CLK_SEL_2,?..."
bitfld.long 0x00 0.--1. "PLL_REF_CLK_SEL,PLL reference clock select" "0: PLL_REF_CLK_SEL_0,1: PLL_REF_CLK_SEL_1,?..."
group.long 0x118++0x03
line.long 0x00 "SYS_PLL3_FDIV_CTL0,SYS PLL3 Divide and Fraction Data Control 0 Register"
hexmask.long.word 0x00 12.--21. 1. "PLL_MAIN_DIV,Value of the main-divider"
bitfld.long 0x00 4.--9. "PLL_PRE_DIV,Value of the pre-divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "PLL_POST_DIV,Value of the post-divider" "0,1,2,3,4,5,6,7"
group.long 0x11C++0x03
line.long 0x00 "SYS_PLL3_LOCKD_CTRL,PLL Lock Detector Control Register"
bitfld.long 0x00 4.--5. "LOCK_CON_DLY,Lock detector setting of the detection resolution" "0,1,2,3"
bitfld.long 0x00 2.--3. "LOCK_CON_OUT,Lock detector setting of the output margin" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "LOCK_CON_IN,Lock detector setting of the input margin" "0,1,2,3"
group.long 0x120++0x03
line.long 0x00 "SYS_PLL3_MNIT_CTRL,PLL Monitoring Control Register"
bitfld.long 0x00 21. "LRD_EN,Monitoring pin" "0,1"
bitfld.long 0x00 20. "FOUT_MASK,Scaler's re-initialization time control pin[3]" "0,1"
newline
bitfld.long 0x00 19. "AFC_SEL,AFC Mode select" "0,1"
bitfld.long 0x00 18. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0: PBIAS_CTRL_0,1: PBIAS_CTRL_1"
newline
bitfld.long 0x00 17. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin" "0,1"
bitfld.long 0x00 16. "AFCINIT_SEL,AFC initial delay select pin" "0: AFCINIT_SEL_0,1: nominal delay * 2"
newline
bitfld.long 0x00 14. "FSEL,Monitoring frequency select pin" "0: FEED_OUT = FREF,1: FEED_OUT = FEED"
bitfld.long 0x00 13. "FEED_EN,FEED_OUT enable pin" "0,1"
newline
bitfld.long 0x00 3.--7. "EXTAFC,Monitoring pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "AFC_EN,If AFC_ENB=0 AFC is enabled and VCO is calibrated automatically" "0,1"
newline
bitfld.long 0x00 0.--1. "ICP,Controls the charge-pump current" "0,1,2,3"
group.long 0x124++0x03
line.long 0x00 "OSC_MISC_CFG,Osc Misc Configuration Register"
bitfld.long 0x00 0. "OSC_32K_SEL,32KHz OSC input select" "0: Divided by 24M clock,1: 32K Oscillator"
group.long 0x128++0x03
line.long 0x00 "ANAMIX_PLL_MNIT_CTL,PLL Clock Output for Test Enable and Select Register"
bitfld.long 0x00 24. "CLKOUT2_OUTPUT_CKE,CLKOUT2 Monitor output enable" "0,1"
bitfld.long 0x00 20.--23. "CLKOUT2_OUTPUT_SEL,CLKOUT2 Monitor output clock select" "0: audio_pll1_clk,1: audio_pll2_clk,2: video_pll1_clk,3: hsio_pll_clk,4: misc_mnit_clk,5: gpu_pll_clk,6: vpu_pll_clk,7: arm_pll_clk,8: system_pll1_clk,9: system_pll2_clk,10: system_pll3_clk,11: CLKIN1,12: CLKIN2,13: sysosc_24m_clk,14: sai_pll_clk,15: osc_32k_clk"
newline
bitfld.long 0x00 16.--19. "CLKOUT2_OUTPUT_DIV_VAL,CLKOUT2 output divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8. "CLKOUT1_OUTPUT_CKE,CLKOUT1 Monitor output enable" "0,1"
newline
bitfld.long 0x00 4.--7. "CLKOUT1_OUTPUT_SEL,CLKOUT1 Monitor output clock select" "0: audio_pll1_clk,1: audio_pll2_clk,2: video_pll1_clk,3: hsio_pll_clk,4: misc_mnit_clk,5: gpu_pll_clk,6: vpu_pll_clk,7: arm_pll_clk,8: system_pll1_clk,9: system_pll2_clk,10: system_pll3_clk,11: CLKIN1,12: CLKIN2,13: sysosc_24m_clk,14: sai_pll_clk,15: osc_32k_clk"
bitfld.long 0x00 0.--3. "CLKOUT1_OUTPUT_DIV_VAL,CLKOUT1 output divide value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x800++0x03
line.long 0x00 "DIGPROG,DIGPROG Register"
hexmask.long.byte 0x00 16.--23. 1. "DIGPROG_MAJOR_UPPER,Bit[7:4] is 0x8 stands for i.MX8 Bit[3:0] is 0x2 stands for M"
hexmask.long.byte 0x00 8.--15. 1. "DIGPROG_MAJOR_LOWER,Bit[7:4] is 0x4 stands for Quad Bit[3:0] is 0x3 stands for Plus"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIGPROG_MINOR,Bit[7:4] is the base layer revision Bit[3:0] is the metal layer revision 0x10 stands for Tapeout 1"
tree.end
tree "CEC"
base ad:0x32FDFD00
group.byte 0x00++0x00
line.byte 0x00 "cec_ctrl,CEC Control Register This register handles the main control of the CEC initiator"
bitfld.byte 0x00 5. "slowdrvsupport_disable," "0,1"
bitfld.byte 0x00 4. "standby," "0,1"
newline
bitfld.byte 0x00 3. "bc_nack," "0,1"
bitfld.byte 0x00 1.--2. "frame_typ," "0,1,2,3"
newline
bitfld.byte 0x00 0. "send," "0,1"
group.byte 0x02++0x00
line.byte 0x00 "cec_mask,CEC Interrupt Mask Register This read/write register masks/unmasks the interrupt events"
bitfld.byte 0x00 6. "wakeup,Follower wake-up signal mask" "0,1"
bitfld.byte 0x00 5. "error_flow,An error is notified by a follower" "0,1"
newline
bitfld.byte 0x00 4. "error_initiator,An error is detected on a CEC line (for initiator only)" "0,1"
bitfld.byte 0x00 3. "arb_lost,The initiator losses the CEC line arbitration to a second initiator" "0,1"
newline
bitfld.byte 0x00 2. "nack,A frame is not acknowledged in a directly addressed message" "0,1"
bitfld.byte 0x00 1. "eom,EOM is detected so that the received data is ready in the receiver data buffer (for follower only)" "0,1"
newline
bitfld.byte 0x00 0. "done,The current transmission is successful (for initiator only)" "0,1"
group.byte 0x05++0x00
line.byte 0x00 "cec_addr_l,CEC Logical Address Register Low This register indicates the logical address(es) allocated to the CEC device"
bitfld.byte 0x00 7. "cec_addr_l_7,Logical address" "0,1"
bitfld.byte 0x00 6. "cec_addr_l_6,Logical address" "0,1"
newline
bitfld.byte 0x00 5. "cec_addr_l_5,Logical address" "0,1"
bitfld.byte 0x00 4. "cec_addr_l_4,Logical address" "0,1"
newline
bitfld.byte 0x00 3. "cec_addr_l_3,Logical address" "0,1"
bitfld.byte 0x00 2. "cec_addr_l_2,Logical address" "0,1"
newline
bitfld.byte 0x00 1. "cec_addr_l_1,Logical address" "0,1"
bitfld.byte 0x00 0. "cec_addr_l_0,Logical address" "0,1"
group.byte 0x06++0x00
line.byte 0x00 "cec_addr_h,CEC Logical Address Register High This register indicates the logical address(es) allocated to the CEC device"
bitfld.byte 0x00 7. "cec_addr_h_7,Logical address" "0,1"
bitfld.byte 0x00 6. "cec_addr_h_6,Logical address" "0,1"
newline
bitfld.byte 0x00 5. "cec_addr_h_5,Logical address" "0,1"
bitfld.byte 0x00 4. "cec_addr_h_4,Logical address" "0,1"
newline
bitfld.byte 0x00 3. "cec_addr_h_3,Logical address" "0,1"
bitfld.byte 0x00 2. "cec_addr_h_2,Logical address" "0,1"
newline
bitfld.byte 0x00 1. "cec_addr_h_1,Logical address" "0,1"
bitfld.byte 0x00 0. "cec_addr_h_0,Logical address" "0,1"
group.byte 0x07++0x00
line.byte 0x00 "cec_tx_cnt,CEC TX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks) which are available in the transmitter data buffer"
bitfld.byte 0x00 0.--4. "cec_tx_cnt,CEC Transmitter Counter register 5'd0: No data needs to be transmitted 5'd1: Frame size is 1 byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.byte 0x08++0x00
line.byte 0x00 "cec_rx_cnt,CEC RX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks) which are available in the receiver data buffer"
bitfld.byte 0x00 0.--4. "cec_rx_cnt,CEC Receiver Counter register: 5'd0: No data received 5'd1: 1-byte data is received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x30++0x00
line.byte 0x00 "cec_lock,CEC Buffer Lock Register"
bitfld.byte 0x00 0. "locked_buffer,When a frame is received this bit would be active" "0,1"
group.byte 0x31++0x00
line.byte 0x00 "cec_wakeupctrl,CEC Wake-up Control Register After receiving a message in the CEC_RX_DATA1 (OPCODE) registers the CEC engine verifies the message opcode[7:0] against one of the previously defined values to generate the wake-up status: Wakeupstatus is 1.."
bitfld.byte 0x00 7. "opcode0x86en,OPCODE 0x86 wake up enable" "0,1"
bitfld.byte 0x00 6. "opcode0x82en,OPCODE 0x82 wake up enable" "0,1"
newline
bitfld.byte 0x00 5. "opcode0x70en,OPCODE 0x70 wake up enable" "0,1"
bitfld.byte 0x00 4. "opcode0x44en,OPCODE 0x44 wake up enable" "0,1"
newline
bitfld.byte 0x00 3. "opcode0x42en,OPCODE 0x42 wake up enable" "0,1"
bitfld.byte 0x00 2. "opcode0x41en,OPCODE 0x41 wake up enable" "0,1"
newline
bitfld.byte 0x00 1. "opcode0x0Den,OPCODE 0x0D wake up enable" "0,1"
bitfld.byte 0x00 0. "opcode0x04en,OPCODE 0x04 wake up enable" "0,1"
tree.end
tree "COLORSPACECONVERTER (ColorSpaceConverter)"
base ad:0x32FDC100
group.byte 0x00++0x00
line.byte 0x00 "csc_cfg,Color Space Converter Interpolation and Decimation Configuration Register"
bitfld.byte 0x00 7. "csc_limit,When set (1'b1) the range limitation values defined in registers csc_mat_uplim and csc_mat_dnlim are applied to the output of the Color Space Conversion matrix" "0,1"
bitfld.byte 0x00 6. "spare_2,Reserved as spare register with no associated functionality" "0,1"
newline
bitfld.byte 0x00 4.--5. "intmode,Chroma interpolation configuration: intmode[1:0] | Chroma Interpolation 00 | interpolation disabled 01 | Hu (z) =1 + z^(-1) 10 | Hu(z)=1/ 2 + z^(-11)+1/2 z^(-2) 11 | interpolation disabled" "0,1,2,3"
bitfld.byte 0x00 2.--3. "spare_1,Reserved as spare register with no associated functionality" "0,1,2,3"
newline
bitfld.byte 0x00 0.--1. "decmode,Chroma decimation configuration: decmode[1:0] | Chroma Decimation 00 | decimation disabled 01 | Hd (z) =1 10 | Hd(z)=1/ 4 + 1/2z^(-1 )+1/4 z^(-2) 11 | Hd(z)x2^(11)= -5+12z^(-2) - 22z^(-4)+39z^(-8) +109z^(-10) -204z^(-12)+648z^(-14) + 1024z^(-15).." "0,1,2,3"
group.byte 0x01++0x00
line.byte 0x00 "csc_scale,Color Space Converter Scale and Deep Color Configuration Register"
bitfld.byte 0x00 4.--7. "csc_color_depth,Color space converter color depth configuration: csc_colordepth[3:0] | Action 0000 | 24 bit per pixel video (8 bit per component)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 2.--3. "spare,The is a Reserved as spare register with no associated functionality" "0,1,2,3"
newline
bitfld.byte 0x00 0.--1. "cscscale,Defines the cscscale[1:0] scale factor to apply to all coefficients in Color Space Conversion" "0,1,2,3"
group.byte 0x02++0x00
line.byte 0x00 "csc_coef_a1_msb,Color Space Converter Matrix A1 Coefficient Register MSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a1_msb,Color Space Converter Matrix A1 Coefficient Register MSB"
group.byte 0x03++0x00
line.byte 0x00 "csc_coef_a1_lsb,Color Space Converter Matrix A1 Coefficient Register LSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a1_lsb,Color Space Converter Matrix A1 Coefficient Register LSB"
group.byte 0x04++0x00
line.byte 0x00 "csc_coef_a2_msb,Color Space Converter Matrix A2 Coefficient Register MSB Color Space Conversion A2 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a2_msb,Color Space Converter Matrix A2 Coefficient Register MSB"
group.byte 0x05++0x00
line.byte 0x00 "csc_coef_a2_lsb,Color Space Converter Matrix A2 Coefficient Register LSB Color Space Conversion A2 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a2_lsb,Color Space Converter Matrix A2 Coefficient Register LSB"
group.byte 0x06++0x00
line.byte 0x00 "csc_coef_a3_msb,Color Space Converter Matrix A3 Coefficient Register MSB Color Space Conversion A3 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a3_msb,Color Space Converter Matrix A3 Coefficient Register MSB"
group.byte 0x07++0x00
line.byte 0x00 "csc_coef_a3_lsb,Color Space Converter Matrix A3 Coefficient Register LSB Color Space Conversion A3 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a3_lsb,Color Space Converter Matrix A3 Coefficient Register LSB"
group.byte 0x08++0x00
line.byte 0x00 "csc_coef_a4_msb,Color Space Converter Matrix A4 Coefficient Register MSB Color Space Conversion A4 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a4_msb,Color Space Converter Matrix A4 Coefficient Register MSB"
group.byte 0x09++0x00
line.byte 0x00 "csc_coef_a4_lsb,Color Space Converter Matrix A4 Coefficient Register LSB Color Space Conversion A4 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_a4_lsb,Color Space Converter Matrix A4 Coefficient Register LSB"
group.byte 0x0A++0x00
line.byte 0x00 "csc_coef_b1_msb,Color Space Converter Matrix B1 Coefficient Register MSB Color Space Conversion B1 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b1_msb,Color Space Converter Matrix B1 Coefficient Register MSB"
group.byte 0x0B++0x00
line.byte 0x00 "csc_coef_b1_lsb,Color Space Converter Matrix B1 Coefficient Register LSB Color Space Conversion B1 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b1_lsb,Color Space Converter Matrix B1 Coefficient Register LSB"
group.byte 0x0C++0x00
line.byte 0x00 "csc_coef_b2_msb,Color Space Converter Matrix B2 Coefficient Register MSB Color Space Conversion B2 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b2_msb,Color Space Converter Matrix B2 Coefficient Register MSB"
group.byte 0x0D++0x00
line.byte 0x00 "csc_coef_b2_lsb,Color Space Converter Matrix B2 Coefficient Register LSB Color Space Conversion B2 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b2_lsb,Color Space Converter Matrix B2 Coefficient Register LSB"
group.byte 0x0E++0x00
line.byte 0x00 "csc_coef_b3_msb,Color Space Converter Matrix B3 Coefficient Register MSB Color Space Conversion B3 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b3_msb,Color Space Converter Matrix B3 Coefficient Register MSB"
group.byte 0x0F++0x00
line.byte 0x00 "csc_coef_b3_lsb,Color Space Converter Matrix B3 Coefficient Register LSB Color Space Conversion B3 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b3_lsb,Color Space Converter Matrix B3 Coefficient Register LSB"
group.byte 0x10++0x00
line.byte 0x00 "csc_coef_b4_msb,Color Space Converter Matrix B4 Coefficient Register MSB Color Space Conversion B4 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b4_msb,Color Space Converter Matrix B4 Coefficient Register MSB"
group.byte 0x11++0x00
line.byte 0x00 "csc_coef_b4_lsb,Color Space Converter Matrix B4 Coefficient Register LSB Color Space Conversion B4 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_b4_lsb,Color Space Converter Matrix B4 Coefficient Register LSB"
group.byte 0x12++0x00
line.byte 0x00 "csc_coef_c1_msb,Color Space Converter Matrix C1 Coefficient Register MSB Color Space Conversion C1 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c1_msb,Color Space Converter Matrix C1 Coefficient Register MSB"
group.byte 0x13++0x00
line.byte 0x00 "csc_coef_c1_lsb,Color Space Converter Matrix C1 Coefficient Register LSB Color Space Conversion C1 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c1_lsb,Color Space Converter Matrix C1 Coefficient Register LSB"
group.byte 0x14++0x00
line.byte 0x00 "csc_coef_c2_msb,Color Space Converter Matrix C2 Coefficient Register MSB Color Space Conversion C2 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c2_msb,Color Space Converter Matrix C2 Coefficient Register MSB"
group.byte 0x15++0x00
line.byte 0x00 "csc_coef_c2_lsb,Color Space Converter Matrix C2 Coefficient Register LSB Color Space Conversion C2 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c2_lsb,Color Space Converter Matrix C2 Coefficient Register LSB"
group.byte 0x16++0x00
line.byte 0x00 "csc_coef_c3_msb,Color Space Converter Matrix C3 Coefficient Register MSB Color Space Conversion C3 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c3_msb,Color Space Converter Matrix C3 Coefficient Register MSB"
group.byte 0x17++0x00
line.byte 0x00 "csc_coef_c3_lsb,Color Space Converter Matrix C3 Coefficient Register LSB Color Space Conversion C3 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c3_lsb,Color Space Converter Matrix C3 Coefficient Register LSB"
group.byte 0x18++0x00
line.byte 0x00 "csc_coef_c4_msb,Color Space Converter Matrix C4 Coefficient Register MSB Color Space Conversion C4 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c4_msb,Color Space Converter Matrix C4 Coefficient Register MSB"
group.byte 0x19++0x00
line.byte 0x00 "csc_coef_c4_lsb,Color Space Converter Matrix C4 Coefficient Register LSB Color Space Conversion C4 coefficient"
hexmask.byte 0x00 0.--7. 1. "csc_coef_c4_lsb,Color Space Converter Matrix C4 Coefficient Register LSB"
group.byte 0x1A++0x00
line.byte 0x00 "csc_limit_up_msb,Color Space Converter Matrix Output Up Limit Register MSB For more details refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "csc_limit_up_msb,Color Space Converter Matrix Output Upper Limit Register MSB"
group.byte 0x1B++0x00
line.byte 0x00 "csc_limit_up_lsb,Color Space Converter Matrix output Up Limit Register LSB For more details refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "csc_limit_up_lsb,Color Space Converter Matrix Output Upper Limit Register LSB"
group.byte 0x1C++0x00
line.byte 0x00 "csc_limit_dn_msb,Color Space Converter Matrix output Down Limit Register MSB For more details refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "csc_limit_dn_msb,Color Space Converter Matrix output Down Limit Register MSB"
group.byte 0x1D++0x00
line.byte 0x00 "csc_limit_dn_lsb,Color Space Converter Matrix output Down Limit Register LSB For more details refer to the HDMI 1"
hexmask.byte 0x00 0.--7. 1. "csc_limit_dn_lsb,Color Space Converter Matrix Output Down Limit Register LSB"
tree.end
tree "DDR_BLK_CTL"
base ad:0x3D000000
group.long 0x100++0x03
line.long 0x00 "DDR_SS_GPR0,DDR Subsystem General Purpose Register 0"
hexmask.long 0x00 0.--31. 1. "DDR_MODE,DDR Mode"
tree.end
tree "DDRC (DDR Controller)"
base ad:0x3D400000
group.long 0x00++0x03
line.long 0x00 "MSTR,Master Register0"
bitfld.long 0x00 30.--31. "device_config,Indicates the configuration of the device used in the system" "0: device_config_0,1: device_config_1,2: device_config_2,3: device_config_3"
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bitfld.long 0x00 29. "frequency_mode,Choose which registers are used" "0: Original Registers,1: frequency_mode_1"
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bitfld.long 0x00 24.--25. "active_ranks,Only present for multi-rank configurations" "0,1,2,3"
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bitfld.long 0x00 16.--19. "burst_rdwr,SDRAM burst length used" "?,1: Burst length of 2 (only supported for mDDR),2: Burst length of 4,?,4: Burst length of 8,?,?,?,8: Burst length of 16 (only supported for mDDR..,?..."
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bitfld.long 0x00 12.--13. "data_bus_width,Selects proportion of DQ bus width that is used by the SDRAM" "0: Full DQ bus width to SDRAM,1: Half DQ bus width to SDRAM,2: Quarter DQ bus width to SDRAM,3: Reserved"
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bitfld.long 0x00 11. "geardown_mode,1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N)" "0,1"
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bitfld.long 0x00 9. "burstchop,When set enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4" "0,1"
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bitfld.long 0x00 5. "lpddr4,Select LPDDR4 SDRAM" "0: non-LPDDR4 device in use Present only in..,1: LPDDR4 SDRAM device in use"
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bitfld.long 0x00 4. "ddr4,Select DDR4 SDRAM" "0: non-DDR4 device in use Present only in designs,1: DDR4 SDRAM device in use"
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bitfld.long 0x00 3. "lpddr3,Select LPDDR3 SDRAM" "0: non-LPDDR3 device in use Present only in..,1: LPDDR3 SDRAM device in use"
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bitfld.long 0x00 2. "lpddr2,Select LPDDR2 SDRAM" "0: non-LPDDR2 device in use Present only in..,1: LPDDR2 SDRAM device in use"
rgroup.long 0x04++0x03
line.long 0x00 "STAT,Operating Mode Status Register"
bitfld.long 0x00 8.--9. "selfref_state,Self refresh state" "0: SDRAM is not in Self Refresh,1: selfref_state_1,2: Self refresh power down,3: selfref_state_3"
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bitfld.long 0x00 4.--5. "selfref_type,Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not" "0: SDRAM is not in Self Refresh (except LPDDR4)..,?,2: SDRAM is in Self Refresh (except LPDDR4) or..,3: SDRAM is in Self Refresh (except LPDDR4) or.."
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bitfld.long 0x00 0.--2. "operating_mode,Operating mode" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "MSTR1,Operating Mode Status Register"
bitfld.long 0x00 16. "alt_addrmap_en,Enable Alternative Address Map" "0: Disable Alternative Address Map,1: Enable Alternative Address Map"
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bitfld.long 0x00 0.--1. "rank_tmgreg_sel,rank_tmgreg_sel" "0: USE DRAMTMGx registers for the rank,1: USE MRAMTMGx registers for the rank,?..."
group.long 0x0C++0x03
line.long 0x00 "MRCTRL3,Operating Mode Status Register"
bitfld.long 0x00 0.--1. "mr_rank_sel,mr_rank_sel" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "MRCTRL0,Mode Register Read/Write Control Register 0"
bitfld.long 0x00 31. "mr_wr,Setting this register bit to 1 triggers a mode register read or write operation" "0,1"
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bitfld.long 0x00 30. "pba_mode,Indicates whether PBA access is executed" "0: Per DRAM Addressability mode,1: Per Buffer Addressability mode The completion.."
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bitfld.long 0x00 12.--15. "mr_addr,Address of the mode register that is to be written to" "0: mr_addr_0,1: mr_addr_1,2: mr_addr_2,3: mr_addr_3,4: mr_addr_4,5: mr_addr_5,6: mr_addr_6,7: mr_addr_7,?..."
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bitfld.long 0x00 4.--5. "mr_rank,Controls which rank is accessed by MRCTRL0.mr_wr" "?,1: select rank 0 only,2: select rank 1 only,?..."
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bitfld.long 0x00 3. "sw_init_int,Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not" "0: Software intervention is not allowed,1: Software intervention is allowed"
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bitfld.long 0x00 2. "pda_en,Indicates whether the mode register operation is MRS in PDA mode or not" "0: pda_en_0,1: MRS in Per DRAM Addressability"
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bitfld.long 0x00 1. "mpr_en,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4)" "0: mpr_en_0,1: WR/RD for MPR"
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bitfld.long 0x00 0. "mr_type,Indicates whether the mode register operation is read or write" "0: mr_type_0,1: mr_type_1"
group.long 0x14++0x03
line.long 0x00 "MRCTRL1,Mode Register Read/Write Control Register 1"
hexmask.long.tbyte 0x00 0.--17. 1. "mr_data,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes"
rgroup.long 0x18++0x03
line.long 0x00 "MRSTAT,Mode Register Read/Write Status Register"
bitfld.long 0x00 8. "pda_done,The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is low" "0: Indicates that mode register write operation..,1: Indicates that mode register write operation.."
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bitfld.long 0x00 0. "mr_wr_busy,The SoC core may initiate a MR write operation only if this signal is low" "0: Indicates that the SoC core can initiate a..,1: Indicates that mode register write operation.."
group.long 0x1C++0x03
line.long 0x00 "MRCTRL2,Mode Register Read/Write Control Register 2"
hexmask.long 0x00 0.--31. 1. "mr_device_sel,Indicates the device(s) to be selected during the MRS that happens in PDA mode"
group.long 0x20++0x03
line.long 0x00 "DERATEEN,Temperature Derate Enable Register"
bitfld.long 0x00 8.--9. "rc_derate_value,Derate value of tRC for LPDDR4" "0: rc_derate_value_0,1: rc_derate_value_1,2: rc_derate_value_2,3: rc_derate_value_3"
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bitfld.long 0x00 4.--7. "derate_byte,Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. "derate_value,Derate value" "0: Derating uses +1,1: Derating uses +2"
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bitfld.long 0x00 0. "derate_enable,Enables derating" "0: Timing parameter derating is disabled,1: Timing parameter derating is enabled using.."
group.long 0x24++0x03
line.long 0x00 "DERATEINT,Temperature Derate Interval Register"
hexmask.long 0x00 0.--31. 1. "mr4_read_interval,Interval between two MR4 reads used to derate the timing parameters"
group.long 0x30++0x03
line.long 0x00 "PWRCTL,Low Power Control Register"
bitfld.long 0x00 6. "stay_in_selfref,Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state for LPDDR4" "0: no description available,1: no description available"
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bitfld.long 0x00 5. "selfref_sw,A value of 1 to this register causes system to move to Self Refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode" "0: Software Exit from Self Refresh,1: Software Entry to Self Refresh"
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bitfld.long 0x00 4. "mpsm_en,When this is 1 the DDRC puts the SDRAM into maximum power saving mode when the transaction store is empty" "0,1"
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bitfld.long 0x00 3. "en_dfi_dram_clk_disable,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "0,1"
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bitfld.long 0x00 2. "deeppowerdown_en,When this is 1 DDRC puts the SDRAM into deep power-down mode when the transaction store is empty" "0,1"
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bitfld.long 0x00 1. "powerdown_en,If true then the DDRC goes into power-down after a programmable number of cycles maximum idle clocks before power down (PWRTMG.powerdown_to_x32)" "0,1"
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bitfld.long 0x00 0. "selfref_en,If true then the DDRC puts the SDRAM into Self Refresh after a programmable number of cycles maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)" "0,1"
group.long 0x34++0x03
line.long 0x00 "PWRTMG,Low Power Timing Register"
hexmask.long.byte 0x00 16.--23. 1. "selfref_to_x32,After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into Self Refresh"
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hexmask.long.byte 0x00 8.--15. 1. "t_dpd_x4096,Minimum deep power-down time"
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bitfld.long 0x00 0.--4. "powerdown_to_x32,After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x03
line.long 0x00 "HWLPCTL,Hardware Low Power Control Register"
hexmask.long.word 0x00 16.--27. 1. "hw_lp_idle_x32,Hardware idle period"
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bitfld.long 0x00 1. "hw_lp_exit_idle_en,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes" "0,1"
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bitfld.long 0x00 0. "hw_lp_en,Enable for Hardware Low Power Interface" "0,1"
group.long 0x50++0x03
line.long 0x00 "RFSHCTL0,Refresh Control Register 0"
bitfld.long 0x00 20.--23. "refresh_margin,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--16. "refresh_to_x32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once but it has not expired (RFSHCTL0.refresh_burst+1) times yet then a speculative refresh may be performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--8. "refresh_burst,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0: single refresh,1: burst-of-2 refresh,?,?,?,?,?,7: burst-of-8 refresh For information on burst,?..."
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bitfld.long 0x00 2. "per_bank_refresh,Per bank refresh allows traffic to flow to other banks" "0: per_bank_refresh_0,1: per_bank_refresh_1"
group.long 0x54++0x03
line.long 0x00 "RFSHCTL1,Refresh Control Register 1"
hexmask.long.word 0x00 16.--27. 1. "refresh_timer1_start_value_x32,Refresh timer start for rank 1 (only present in multi-rank configurations)"
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hexmask.long.word 0x00 0.--11. 1. "refresh_timer0_start_value_x32,Refresh timer start for rank 0 (only present in multi-rank configurations)"
group.long 0x60++0x03
line.long 0x00 "RFSHCTL3,Refresh Control Register 3"
bitfld.long 0x00 4.--6. "refresh_mode,Fine Granularity Refresh Mode" "0: Fixed 1x (Normal mode),1: Fixed 2x,2: Fixed 4x,?,?,5: Enable on the fly 2x (not supported),6: Enable on the fly 4x (not supported),?..."
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bitfld.long 0x00 1. "refresh_update_level,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated" "0,1"
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bitfld.long 0x00 0. "dis_auto_refresh,When '1' disable auto-refresh generated by the DDRC" "0,1"
group.long 0x64++0x03
line.long 0x00 "RFSHTMG,Refresh Timing Register"
hexmask.long.word 0x00 16.--27. 1. "t_rfc_nom_x32,tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4)"
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bitfld.long 0x00 15. "lpddr3_trefbw_en,Used only when LPDDR3 memory type is connected" "0: tREFBW parameter not used,1: tREFBW parameter used"
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hexmask.long.word 0x00 0.--9. 1. "t_rfc_min,tRFC (min): Minimum time from refresh to refresh or activate"
group.long 0x70++0x03
line.long 0x00 "ECCCFG0,ECC Configuration Register 0"
bitfld.long 0x00 30.--31. "ecc_region_map_granu,Indicates granularity of selectable protected region" "0,1,2,3"
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bitfld.long 0x00 29. "ecc_region_map_other,When ECCCFG0[ecc_region_map_granu] > 0 there is a region which is not controlled by ecc_region_map" "0,1"
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bitfld.long 0x00 24.--26. "ecc_ap_err_threshold,Sets threshold for address parity error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--21. "blk_channel_idle_time_x32,Indicates the number of cycles on HIF interface with no access to protected regions which causes flush of all the block channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 8.--14. 1. "ecc_region_map,Selectable Protected Region setting"
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bitfld.long 0x00 7. "ecc_region_remap_en,Enables remapping ECC region feature" "0,1"
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bitfld.long 0x00 6. "ecc_ap_en,Enables address protection feature" "0,1"
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bitfld.long 0x00 4. "dis_scrub,Disables ECC scrubs" "0,1"
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bitfld.long 0x00 0.--2. "ecc_mode,ECC mode indicator" "0,1,2,3,4,5,6,7"
group.long 0x74++0x03
line.long 0x00 "ECCCFG1,ECC Configuration Register 1"
bitfld.long 0x00 8.--11. "active_blk_channel,Indicated the number of active block channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "blk_channel_active_term,If enabled block channel is terminated when full block write or full block read is performed (all address within block are written or read)" "0,1"
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bitfld.long 0x00 5. "ecc_region_waste_lock,Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock" "0,1"
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bitfld.long 0x00 4. "ecc_region_parity_lock,Locks the parity section of the ECC region (hole) which is the highest system address part of the memory that stores ECC parity for protected region" "0,1"
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bitfld.long 0x00 2. "poison_chip_en,Indicates the data poison based on chip (that is persistently poisons the DRAM data once its cs is selected to mimic chip failure)" "0,1"
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bitfld.long 0x00 1. "data_poison_bit,Selects whether to poison 1 or 2 bits" "0,1"
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bitfld.long 0x00 0. "data_poison_en,Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers" "0,1"
group.long 0xD0++0x03
line.long 0x00 "INIT0,SDRAM Initialization Register 0"
bitfld.long 0x00 30.--31. "skip_dram_init,If lower bit is enabled the SDRAM initialization routine is skipped" "0: SDRAM Initialization routine is run after..,1: SDRAM Initialization routine is skipped after..,2: SDRAM Initialization routine is run after..,3: SDRAM Initialization routine is skipped after.."
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hexmask.long.word 0x00 16.--25. 1. "post_cke_x1024,Cycles to wait after driving CKE high to start the SDRAM initialization sequence"
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hexmask.long.word 0x00 0.--11. 1. "pre_cke_x1024,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence"
group.long 0xD4++0x03
line.long 0x00 "INIT1,SDRAM Initialization Register 1"
hexmask.long.word 0x00 16.--24. 1. "dram_rstn_x1024,Number of cycles to assert SDRAM reset signal during init sequence"
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bitfld.long 0x00 0.--3. "pre_ocd_x32,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD8++0x03
line.long 0x00 "INIT2,SDRAM Initialization Register 2"
hexmask.long.byte 0x00 8.--15. 1. "idle_after_reset_x32,Idle time after the reset command tINIT4"
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bitfld.long 0x00 0.--3. "min_stable_clock_x1,Time to wait after the first CKE high tINIT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xDC++0x03
line.long 0x00 "INIT3,SDRAM Initialization Register 3"
hexmask.long.word 0x00 16.--31. 1. "mr,DDR2: Value to write to MR register"
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hexmask.long.word 0x00 0.--15. 1. "emr,DDR2: Value to write to EMR register"
group.long 0xE0++0x03
line.long 0x00 "INIT4,SDRAM Initialization Register 4"
hexmask.long.word 0x00 16.--31. 1. "emr2,DDR2: Value to write to EMR2 register"
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hexmask.long.word 0x00 0.--15. 1. "emr3,DDR2: Value to write to EMR3 register"
group.long 0xE4++0x03
line.long 0x00 "INIT5,SDRAM Initialization Register 5"
hexmask.long.byte 0x00 16.--23. 1. "dev_zqinit_x32,ZQ initial calibration tZQINIT"
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hexmask.long.word 0x00 0.--9. 1. "max_auto_init_x1024,Maximum duration of the auto initialization tINIT5"
group.long 0xE8++0x03
line.long 0x00 "INIT6,SDRAM Initialization Register 6"
hexmask.long.word 0x00 16.--31. 1. "mr4,DDR4- Value to be loaded into SDRAM MR4 registers"
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hexmask.long.word 0x00 0.--15. 1. "mr5,DDR4- Value to be loaded into SDRAM MR5 registers"
group.long 0xEC++0x03
line.long 0x00 "INIT7,SDRAM Initialization Register 7"
hexmask.long.word 0x00 16.--31. 1. "mr6,DDR4- Value to be loaded into SDRAM MR6 registers"
group.long 0xF0++0x03
line.long 0x00 "DIMMCTL,DIMM Control Register"
bitfld.long 0x00 6. "lrdimm_bcom_cmd_prot,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification" "0,1"
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bitfld.long 0x00 5. "dimm_dis_bg_mirroring,Disabling Address Mirroring for BG bits" "0: BG0 and BG1 are swapped if address mirroring..,1: BG0 and BG1 are NOT swapped"
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bitfld.long 0x00 4. "mrs_bg1_en,Enable for BG1 bit of MRS command" "0: mrs_bg1_en_0,1: mrs_bg1_en_1"
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bitfld.long 0x00 3. "mrs_a17_en,Enable for A17 bit of MRS command" "0: mrs_a17_en_0,1: mrs_a17_en_1"
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bitfld.long 0x00 2. "dimm_output_inv_en,Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only)" "0: Do not implement output inversion for B-side..,1: Implement output inversion for B-side DRAMs"
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bitfld.long 0x00 1. "dimm_addr_mirr_en,Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations)" "0: Do not implement address mirroring,1: For odd ranks implement address mirroring for.."
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bitfld.long 0x00 0. "dimm_stagger_cs_en,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only)" "0: Do not stagger accesses,1: (non-DDR4) Send all commands to even and odd.."
group.long 0xF4++0x03
line.long 0x00 "RANKCTL,Rank Control Register"
bitfld.long 0x00 8.--11. "diff_rank_wr_gap,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "diff_rank_rd_gap,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "max_rank_rd,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x100++0x03
line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0"
hexmask.long.byte 0x00 24.--30. 1. "wr2pre,Minimum time between write and precharge to same bank"
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bitfld.long 0x00 16.--21. "t_faw,tFAW Valid only when 8 or more banks(or banks x bank groups) are present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 8.--14. 1. "t_ras_max,tRAS(max): Maximum time between activate and precharge to same bank"
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bitfld.long 0x00 0.--5. "t_ras_min,tRAS(min): Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x104++0x03
line.long 0x00 "DRAMTMG1,SDRAM Timing Register 1"
bitfld.long 0x00 16.--20. "t_xp,tXP: Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--13. "rd2pre,tRTP: Minimum time from read to precharge of same bank" "?,?,2: DDR3,?,4: LPDDR4,?..."
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hexmask.long.byte 0x00 0.--6. 1. "t_rc,tRC: Minimum time between activates to same bank"
group.long 0x108++0x03
line.long 0x00 "DRAMTMG2,SDRAM Timing Register 2"
bitfld.long 0x00 24.--29. "write_latency,Set to WL Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "read_latency,Set to RL Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "rd2wr,DDR2/3/mDDR: RL + BL/2 +" "?,1: WL LPDDR4(DQ ODT is Disabled),2: WL DDR4,?..."
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bitfld.long 0x00 0.--5. "wr2rd,DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10C++0x03
line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3"
hexmask.long.word 0x00 20.--29. 1. "t_mrw,Time to wait after a mode register write or read (MRW or MRR)"
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bitfld.long 0x00 12.--17. "t_mrd,tMRD: Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--9. 1. "t_mod,tMOD: Parameter used only in DDR3 and DDR4"
group.long 0x110++0x03
line.long 0x00 "DRAMTMG4,SDRAM Timing Register 4"
bitfld.long 0x00 24.--28. "t_rcd,tRCD - tAL: Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--19. "t_ccd,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "t_rrd,DDR4: tRRD_L: Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--4. "t_rp,tRP: Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x114++0x03
line.long 0x00 "DRAMTMG5,SDRAM Timing Register 5"
bitfld.long 0x00 24.--27. "t_cksrx,This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX" "?,1: DDR3,2: LPDDR4,?..."
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bitfld.long 0x00 16.--19. "t_cksre,This is the time after Self Refresh Down Entry that CK is maintained as a valid clock" "0: LPDDR2,1: DDR3,2: LPDDR4,?..."
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bitfld.long 0x00 8.--13. "t_ckesr,Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--4. "t_cke,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x118++0x03
line.long 0x00 "DRAMTMG6,SDRAM Timing Register 6"
bitfld.long 0x00 24.--27. "t_ckdpde,This is the time after Deep Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR3,?..."
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bitfld.long 0x00 16.--19. "t_ckdpdx,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "?,1: LPDDR2,2: LPDDR3,?..."
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bitfld.long 0x00 0.--3. "t_ckcsx,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit" "?,1: LPDDR2,2: LPDDR4,?..."
group.long 0x11C++0x03
line.long 0x00 "DRAMTMG7,SDRAM Timing Register 7"
bitfld.long 0x00 8.--11. "t_ckpde,This is the time after Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR4,?..."
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bitfld.long 0x00 0.--3. "t_ckpdx,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0: LPDDR2,?,2: LPDDR4,?..."
group.long 0x120++0x03
line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8"
hexmask.long.byte 0x00 24.--30. 1. "t_xs_fast_x32,tXS_FAST: Exit Self Refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode)"
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hexmask.long.byte 0x00 16.--22. 1. "t_xs_abort_x32,tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort"
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hexmask.long.byte 0x00 8.--14. 1. "t_xs_dll_x32,tXSDLL: Exit Self Refresh to commands requiring a locked DLL"
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hexmask.long.byte 0x00 0.--6. 1. "t_xs_x32,tXS: Exit Self Refresh to commands not requiring a locked DLL"
group.long 0x124++0x03
line.long 0x00 "DRAMTMG9,SDRAM Timing Register 9"
bitfld.long 0x00 30. "ddr4_wr_preamble,DDR4 Write preamble mode" "0: 1tCK preamble,1: 2tCK preamble Present only with"
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bitfld.long 0x00 16.--18. "t_ccd_s,tCCD_S: This is the minimum time between two reads or two writes for different bank group" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "t_rrd_s,tRRD_S: Minimum time between activates from bank a to bank b for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--5. "wr2rd_s,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "DRAMTMG10,SDRAM Timing Register 10"
bitfld.long 0x00 16.--20. "t_sync_gear,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "t_cmd_gear,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 2.--3. "t_gear_setup,Geardown setup time" "0,1,2,3"
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bitfld.long 0x00 0.--1. "t_gear_hold,Geardown hold time" "0,1,2,3"
group.long 0x12C++0x03
line.long 0x00 "DRAMTMG11,SDRAM Timing Register 11"
hexmask.long.byte 0x00 24.--30. 1. "post_mpsm_gap_x32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL"
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bitfld.long 0x00 16.--20. "t_mpx_lh,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "t_mpx_s,tMPX_S: Minimum time CS setup time to CKE" "0,1,2,3"
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bitfld.long 0x00 0.--4. "t_ckmpe,tCKMPE: Minimum valid clock requirement after MPSM entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x130++0x03
line.long 0x00 "DRAMTMG12,SDRAM Timing Register 12"
bitfld.long 0x00 16.--17. "t_cmdcke,tCMDCKE: Delay from valid command to CKE input LOW" "0,1,2,3"
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bitfld.long 0x00 8.--11. "t_ckehcmd,tCKEHCMD: Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--4. "t_mrd_pda,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x134++0x03
line.long 0x00 "DRAMTMG13,SDRAM Timing Register 13"
hexmask.long.byte 0x00 24.--30. 1. "odtloff,LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference"
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bitfld.long 0x00 16.--21. "t_ccd_mw,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--2. "t_ppd,LPDDR4: tPPD: This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7"
group.long 0x138++0x03
line.long 0x00 "DRAMTMG14,SDRAM Timing Register 14"
hexmask.long.word 0x00 0.--11. 1. "t_xsr,tXSR: Exit Self Refresh to any command"
group.long 0x13C++0x03
line.long 0x00 "DRAMTMG15,SDRAM Timing Register 15"
bitfld.long 0x00 31. "en_dfi_lp_t_stab,Enable DFI tSTAB" "0: Disable using tSTAB when exiting DFI LP,1: Enable using tSTAB when exiting DFI LP"
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hexmask.long.byte 0x00 0.--7. 1. "t_stab_x32,tSTAB: Stabilization time"
group.long 0x180++0x03
line.long 0x00 "ZQCTL0,ZQ Control Register 0"
bitfld.long 0x00 31. "dis_auto_zq,Disable Auto ZQCS/MPC" "0: Internally generate ZQCS/MPC(ZQ calibration)..,1: Disable DDRC generation of ZQCS/MPC(ZQ.."
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bitfld.long 0x00 30. "dis_srx_zqcl,Disable ZQCL/MPC" "0: Enable issuing of ZQCL/MPC(ZQ calibration)..,1: Disable issuing of ZQCL/MPC(ZQ calibration).."
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bitfld.long 0x00 29. "zq_resistor_shared,ZQ resistor sharing" "0: ZQ resistor is not shared,1: Denotes that ZQ resistor is shared between.."
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bitfld.long 0x00 28. "dis_mpsmx_zqcl,Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set" "0: Enable issuing of ZQCL command at Maximum..,1: Disable issuing of ZQCL command at Maximum.."
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hexmask.long.word 0x00 16.--26. 1. "t_zq_long_nop,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM"
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hexmask.long.word 0x00 0.--9. 1. "t_zq_short_nop,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM"
group.long 0x184++0x03
line.long 0x00 "ZQCTL1,ZQ Control Register 1"
hexmask.long.word 0x00 20.--29. 1. "t_zq_reset_nop,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM"
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hexmask.long.tbyte 0x00 0.--19. 1. "t_zq_short_interval_x1024,Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices"
group.long 0x188++0x03
line.long 0x00 "ZQCTL2,ZQ Control Register 2"
bitfld.long 0x00 0. "zq_reset,Setting this register bit to 1 triggers a ZQ Reset operation" "0,1"
rgroup.long 0x18C++0x03
line.long 0x00 "ZQSTAT,ZQ Status Register"
bitfld.long 0x00 0. "zq_reset_busy,SoC core may initiate a ZQ Reset operation only if this signal is low" "0: Indicates that the SoC core can initiate a ZQ..,1: Indicates that ZQ Reset operation is in.."
group.long 0x190++0x03
line.long 0x00 "DFITMG0,DFI Timing Register 0"
bitfld.long 0x00 24.--28. "dfi_t_ctrl_delay,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "dfi_rddata_use_sdr,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "0,1"
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hexmask.long.byte 0x00 16.--22. 1. "dfi_t_rddata_en,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal"
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bitfld.long 0x00 15. "dfi_wrdata_use_sdr,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles.." "0,1"
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bitfld.long 0x00 8.--13. "dfi_tphy_wrdata,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "dfi_tphy_wrlat,Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x194++0x03
line.long 0x00 "DFITMG1,DFI Timing Register 1"
bitfld.long 0x00 28.--31. "dfi_t_cmd_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--25. "dfi_t_parin_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3"
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bitfld.long 0x00 16.--20. "dfi_t_wrdata_delay,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "dfi_t_dram_clk_disable,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "dfi_t_dram_clk_enable,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x198++0x03
line.long 0x00 "DFILPCFG0,DFI Low Power Configuration Register 0"
bitfld.long 0x00 24.--28. "dfi_tlp_resp,Setting in DFI clock cycles for DFI's tlp_resp time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 20.--23. "dfi_lp_wakeup_dpd,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered" "0: dfi_lp_wakeup_dpd_0,1: dfi_lp_wakeup_dpd_1,2: dfi_lp_wakeup_dpd_2,3: dfi_lp_wakeup_dpd_3,4: dfi_lp_wakeup_dpd_4,5: dfi_lp_wakeup_dpd_5,6: dfi_lp_wakeup_dpd_6,7: dfi_lp_wakeup_dpd_7,8: dfi_lp_wakeup_dpd_8,9: dfi_lp_wakeup_dpd_9,10: dfi_lp_wakeup_dpd_10,11: dfi_lp_wakeup_dpd_11,12: dfi_lp_wakeup_dpd_12,13: dfi_lp_wakeup_dpd_13,14: dfi_lp_wakeup_dpd_14,15: dfi_lp_wakeup_dpd_15"
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bitfld.long 0x00 16. "dfi_lp_en_dpd,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit" "0: Disabled,1: Enabled This is only present"
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bitfld.long 0x00 12.--15. "dfi_lp_wakeup_sr,Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "0: dfi_lp_wakeup_sr_0,1: dfi_lp_wakeup_sr_1,2: dfi_lp_wakeup_sr_2,3: dfi_lp_wakeup_sr_3,4: dfi_lp_wakeup_sr_4,5: dfi_lp_wakeup_sr_5,6: dfi_lp_wakeup_sr_6,7: dfi_lp_wakeup_sr_7,8: dfi_lp_wakeup_sr_8,9: dfi_lp_wakeup_sr_9,10: dfi_lp_wakeup_sr_10,11: dfi_lp_wakeup_sr_11,12: dfi_lp_wakeup_sr_12,13: dfi_lp_wakeup_sr_13,14: dfi_lp_wakeup_sr_14,15: dfi_lp_wakeup_sr_15"
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bitfld.long 0x00 8. "dfi_lp_en_sr,Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit" "0: dfi_lp_en_sr_0,1: dfi_lp_en_sr_1"
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bitfld.long 0x00 4.--7. "dfi_lp_wakeup_pd,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered" "0: dfi_lp_wakeup_pd_0,1: dfi_lp_wakeup_pd_1,2: dfi_lp_wakeup_pd_2,3: dfi_lp_wakeup_pd_3,4: dfi_lp_wakeup_pd_4,5: dfi_lp_wakeup_pd_5,6: dfi_lp_wakeup_pd_6,7: dfi_lp_wakeup_pd_7,8: dfi_lp_wakeup_pd_8,9: dfi_lp_wakeup_pd_9,10: dfi_lp_wakeup_pd_10,11: dfi_lp_wakeup_pd_11,12: dfi_lp_wakeup_pd_12,13: dfi_lp_wakeup_pd_13,14: dfi_lp_wakeup_pd_14,15: dfi_lp_wakeup_pd_15"
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bitfld.long 0x00 0. "dfi_lp_en_pd,Enables DFI Low Power interface handshaking during Power Down Entry/Exit" "0: Disabled,1: Enabled"
group.long 0x19C++0x03
line.long 0x00 "DFILPCFG1,DFI Low Power Configuration Register 1"
bitfld.long 0x00 4.--7. "dfi_lp_wakeup_mpsm,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered" "0: dfi_lp_wakeup_mpsm_0,1: dfi_lp_wakeup_mpsm_1,2: dfi_lp_wakeup_mpsm_2,3: dfi_lp_wakeup_mpsm_3,4: dfi_lp_wakeup_mpsm_4,5: dfi_lp_wakeup_mpsm_5,6: dfi_lp_wakeup_mpsm_6,7: dfi_lp_wakeup_mpsm_7,8: dfi_lp_wakeup_mpsm_8,9: dfi_lp_wakeup_mpsm_9,10: dfi_lp_wakeup_mpsm_10,11: dfi_lp_wakeup_mpsm_11,12: dfi_lp_wakeup_mpsm_12,13: dfi_lp_wakeup_mpsm_13,14: dfi_lp_wakeup_mpsm_14,15: dfi_lp_wakeup_mpsm_15"
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bitfld.long 0x00 0. "dfi_lp_en_mpsm,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit" "0: Disabled,1: Enabled This is only present"
group.long 0x1A0++0x03
line.long 0x00 "DFIUPD0,DFI Update Register 0"
bitfld.long 0x00 31. "dis_auto_ctrlupd,automatic dfi_ctrlupd_req generation by the DDRC" "0: DDRC issues dfi_ctrlupd_req periodically,1: disable the automatic dfi_ctrlupd_req.."
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bitfld.long 0x00 30. "dis_auto_ctrlupd_srx,Auto ctrlupd request generation" "0: DDRC issues a dfi_ctrlupd_req before or after..,1: disable the automatic dfi_ctrlupd_req.."
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bitfld.long 0x00 29. "ctrlupd_pre_srx,Selects dfi_ctrlupd_req requirements at SRX" "0: send ctrlupd after SRX,1: send ctrlupd before SRX"
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hexmask.long.word 0x00 16.--25. 1. "dfi_t_ctrlup_max,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert"
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hexmask.long.word 0x00 0.--9. 1. "dfi_t_ctrlup_min,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted"
group.long 0x1A4++0x03
line.long 0x00 "DFIUPD1,DFI Update Register 1"
hexmask.long.byte 0x00 16.--23. 1. "dfi_t_ctrlupd_interval_min_x1024,This is the minimum amount of time between DDRC initiated DFI update requests (which is executed whenever the DDRC is idle)"
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hexmask.long.byte 0x00 0.--7. 1. "dfi_t_ctrlupd_interval_max_x1024,This is the maximum amount of time between DDRC initiated DFI update requests"
group.long 0x1A8++0x03
line.long 0x00 "DFIUPD2,DFI Update Register 2"
bitfld.long 0x00 31. "dfi_phyupd_en,Enables the support for acknowledging PHY-initiated updates" "0: dfi_phyupd_en_0,1: dfi_phyupd_en_1"
group.long 0x1B0++0x03
line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register"
bitfld.long 0x00 8.--12. "dfi_frequency,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "dfi_init_start,PHY init start request signal.When asserted it triggers the PHY init start request" "0,1"
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bitfld.long 0x00 4. "ctl_idle_en,Enables support of ctl_idle signal which is non-DFI related pin specific to certain PHYs" "0,1"
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bitfld.long 0x00 2. "dfi_data_cs_polarity,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "0: dfi_data_cs_polarity_0,1: Signals are active high"
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bitfld.long 0x00 1. "phy_dbi_mode,DBI implemented in DDRC or PHY" "0: DDRC implements DBI functionality,1: PHY implements DBI functionality"
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bitfld.long 0x00 0. "dfi_init_complete_en,PHY initialization complete enable signal" "0,1"
group.long 0x1B4++0x03
line.long 0x00 "DFITMG2,DFI Timing Register 2"
hexmask.long.byte 0x00 8.--14. 1. "dfi_tphy_rdcslat,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted"
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bitfld.long 0x00 0.--5. "dfi_tphy_wrcslat,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1B8++0x03
line.long 0x00 "DFITMG3,DFI Timing Register 3"
bitfld.long 0x00 0.--4. "dfi_t_geardown_delay,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x1BC++0x03
line.long 0x00 "DFISTAT,DFI Status Register"
bitfld.long 0x00 1. "dfi_lp_ack,Stores the value of the dfi_lp_ack input to the controller" "0,1"
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bitfld.long 0x00 0. "dfi_init_complete,The status flag register which announces when the DFI initialization has been completed" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DBICTL,DM/DBI Control Register"
bitfld.long 0x00 2. "rd_dbi_en,Read DBI enable signal in DDRC" "0: Read DBI is disabled,1: Read DBI is enabled"
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bitfld.long 0x00 1. "wr_dbi_en,This signal must be set the same value as DRAM's mode register" "0: Write DBI is disabled,1: Write DBI is enabled"
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bitfld.long 0x00 0. "dm_en,DM enable signal in DDRC" "0: DM is disabled,1: DM is enabled"
group.long 0x200++0x03
line.long 0x00 "ADDRMAP0,Address Map Register 0"
bitfld.long 0x00 0.--4. "addrmap_cs_bit0,Selects the HIF address bit used as rank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x204++0x03
line.long 0x00 "ADDRMAP1,Address Map Register 1"
bitfld.long 0x00 16.--20. "addrmap_bank_b2,Selects the HIF address bit used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "addrmap_bank_b1,Selects the HIF address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "addrmap_bank_b0,Selects the HIF address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x208++0x03
line.long 0x00 "ADDRMAP2,Address Map Register 2"
bitfld.long 0x00 24.--27. "addrmap_col_b5,- Full bus width mode: Selects the HIF address bit used as column address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "addrmap_col_b4,- Full bus width mode: Selects the HIF address bit used as column address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "addrmap_col_b3,- Full bus width mode: Selects the HIF address bit used as column address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_col_b2,- Full bus width mode: Selects the HIF address bit used as column address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20C++0x03
line.long 0x00 "ADDRMAP3,Address Map Register 3"
bitfld.long 0x00 24.--27. "addrmap_col_b9,- Full bus width mode: Selects the HIF address bit used as column address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "addrmap_col_b8,- Full bus width mode: Selects the HIF address bit used as column address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "addrmap_col_b7,- Full bus width mode: Selects the HIF address bit used as column address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_col_b6,- Full bus width mode: Selects the HIF address bit used as column address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x210++0x03
line.long 0x00 "ADDRMAP4,Address Map Register 4"
bitfld.long 0x00 8.--11. "addrmap_col_b11,- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_col_b10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x214++0x03
line.long 0x00 "ADDRMAP5,Address Map Register 5"
bitfld.long 0x00 24.--27. "addrmap_row_b11,Selects the HIF address bit used as row address bit 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "addrmap_row_b2_10,Selects the HIF address bits used as row address bits 2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "addrmap_row_b1,Selects the HIF address bits used as row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_row_b0,Selects the HIF address bits used as row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x218++0x03
line.long 0x00 "ADDRMAP6,Address Map Register 6"
bitfld.long 0x00 31. "lpddr3_6gb_12gb,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use" "0: non-LPDDR3 6Gb/12Gb device in use,1: LPDDR3 SDRAM 6Gb/12Gb device in use"
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bitfld.long 0x00 24.--27. "addrmap_row_b15,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "addrmap_row_b14,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "addrmap_row_b13,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_row_b12,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21C++0x03
line.long 0x00 "ADDRMAP7,Address Map Register 7"
bitfld.long 0x00 8.--11. "addrmap_row_b17,Selects the HIF address bit used as row address bit 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_row_b16,Selects the HIF address bit used as row address bit 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x220++0x03
line.long 0x00 "ADDRMAP8,Address Map Register 8"
bitfld.long 0x00 8.--13. "addrmap_bg_b1,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--4. "addrmap_bg_b0,Selects the HIF address bits used as bank group address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x224++0x03
line.long 0x00 "ADDRMAP9,Address Map Register 9"
bitfld.long 0x00 24.--27. "addrmap_row_b5,Selects the HIF address bits used as row address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "addrmap_row_b4,Selects the HIF address bits used as row address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "addrmap_row_b3,Selects the HIF address bits used as row address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_row_b2,Selects the HIF address bits used as row address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x228++0x03
line.long 0x00 "ADDRMAP10,Address Map Register 10"
bitfld.long 0x00 24.--27. "addrmap_row_b9,Selects the HIF address bits used as row address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "addrmap_row_b8,Selects the HIF address bits used as row address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "addrmap_row_b7,Selects the HIF address bits used as row address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "addrmap_row_b6,Selects the HIF address bits used as row address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x22C++0x03
line.long 0x00 "ADDRMAP11,Address Map Register 11"
bitfld.long 0x00 0.--3. "addrmap_row_b10,Selects the HIF address bits used as row address bit 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x03
line.long 0x00 "ODTCFG,ODT Configuration Register"
bitfld.long 0x00 24.--27. "wr_odt_hold,DFI PHY clock cycles to hold ODT for a write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--20. "wr_odt_delay,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--11. "rd_odt_hold,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2.--6. "rd_odt_delay,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x244++0x03
line.long 0x00 "ODTMAP,ODT/Rank Map Register"
bitfld.long 0x00 12.--13. "rank1_rd_odt,Indicates which remote ODTs must be turned on during a read from rank 1" "0,1,2,3"
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bitfld.long 0x00 8.--9. "rank1_wr_odt,Indicates which remote ODTs must be turned on during a write to rank 1" "0,1,2,3"
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bitfld.long 0x00 4.--5. "rank0_rd_odt,Indicates which remote ODTs must be turned on during a read from rank 0" "0,1,2,3"
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bitfld.long 0x00 0.--1. "rank0_wr_odt,Indicates which remote ODTs must be turned on during a write to rank 0" "0,1,2,3"
group.long 0x250++0x03
line.long 0x00 "SCHED,Scheduler Control Register"
hexmask.long.byte 0x00 24.--30. 1. "rdwr_idle_gap,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty"
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hexmask.long.byte 0x00 16.--23. 1. "go2critical_hysteresis,UNUSED"
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bitfld.long 0x00 8.--12. "lpr_num_entries,Number of entries in the low priority transaction store is this value + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 2. "pageclose,If true bank is kept open only while there are page hit transactions available in the CAM to that bank" "0,1"
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bitfld.long 0x00 1. "prefer_write,If set then the bank selector prefers writes over reads" "0,1"
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bitfld.long 0x00 0. "force_low_pri_n,Active low signal" "0,1"
group.long 0x254++0x03
line.long 0x00 "SCHED1,Scheduler Control Register 1"
hexmask.long.byte 0x00 0.--7. 1. "pageclose_timer,This field works in conjunction with SCHED.pageclose"
group.long 0x25C++0x03
line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1"
hexmask.long.byte 0x00 24.--31. 1. "hpr_xact_run_length,Number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available"
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hexmask.long.word 0x00 0.--15. 1. "hpr_max_starve,Number of DFI clocks that the HPR queue can be starved before it goes critical"
group.long 0x264++0x03
line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1"
hexmask.long.byte 0x00 24.--31. 1. "lpr_xact_run_length,Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available"
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hexmask.long.word 0x00 0.--15. 1. "lpr_max_starve,Number of DFI clocks that the LPR queue can be starved before it goes critical"
group.long 0x26C++0x03
line.long 0x00 "PERFWR1,Write CAM Register 1"
hexmask.long.byte 0x00 24.--31. 1. "w_xact_run_length,Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available"
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hexmask.long.word 0x00 0.--15. 1. "w_max_starve,Number of DFI clocks that the WR queue can be starved before it goes critical"
group.long 0x300++0x03
line.long 0x00 "DBG0,Debug Register 0"
bitfld.long 0x00 4. "dis_collision_page_opt,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case" "0,1"
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bitfld.long 0x00 2. "dis_act_bypass,Only present in designs supporting activate bypass" "0,1"
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bitfld.long 0x00 1. "dis_rd_bypass,Only present in designs supporting read bypass" "0,1"
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bitfld.long 0x00 0. "dis_wc,When 1 disable write combine" "0,1"
group.long 0x304++0x03
line.long 0x00 "DBG1,Debug Register 1"
bitfld.long 0x00 1. "dis_hif,When 1 DDRC asserts the HIF command signal hif_cmd_stall" "0,1"
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bitfld.long 0x00 0. "dis_dq,When 1 DDRC will not de-queue any transactions from the CAM" "0,1"
rgroup.long 0x308++0x03
line.long 0x00 "DBGCAM,CAM Debug Register"
bitfld.long 0x00 31. "dbg_stall_rd,Stall for Read channel FOR DEBUG ONLY" "0,1"
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bitfld.long 0x00 30. "dbg_stall_wr,Stall for Write channel FOR DEBUG ONLY" "0,1"
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bitfld.long 0x00 29. "wr_data_pipeline_empty,This bit indicates that the write data pipeline on the DFI interface is empty" "0,1"
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bitfld.long 0x00 28. "rd_data_pipeline_empty,This bit indicates that the read data pipeline on the DFI interface is empty" "0,1"
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bitfld.long 0x00 26. "dbg_wr_q_empty,When 1 all the Write command queues and Write data buffers inside DDRC are empty" "0,1"
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bitfld.long 0x00 25. "dbg_rd_q_empty,When 1 all the Read command queues and Read data buffers inside DDRC are empty" "0,1"
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bitfld.long 0x00 24. "dbg_stall,Stall FOR DEBUG ONLY" "0,1"
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bitfld.long 0x00 16.--21. "dbg_w_q_depth,Write queue depth The last entry of WR queue is reserved for ECC SCRUB operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "dbg_lpr_q_depth,Low priority read queue depth The last entry of Lpr queue is reserved for ECC SCRUB operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "dbg_hpr_q_depth,High priority read queue depth FOR DEBUG ONLY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x30C++0x03
line.long 0x00 "DBGCMD,Command Debug Register"
bitfld.long 0x00 5. "ctrlupd,Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "0,1"
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bitfld.long 0x00 4. "zq_calib_short,Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM" "0,1"
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bitfld.long 0x00 1. "rank1_refresh,Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 1" "0,1"
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bitfld.long 0x00 0. "rank0_refresh,Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 0" "0,1"
rgroup.long 0x310++0x03
line.long 0x00 "DBGSTAT,Status Debug Register"
bitfld.long 0x00 5. "ctrlupd_busy,SoC core may initiate a ctrlupd operation only if this signal is low" "0: Indicates that the SoC core can initiate a,1: Indicates that ctrlupd operation has not been"
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bitfld.long 0x00 4. "zq_calib_short_busy,SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low" "0: Indicates that the SoC core can initiate a ZQCS,1: Indicates that ZQCS operation has not been"
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bitfld.long 0x00 1. "rank1_refresh_busy,SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low" "0: Indicates that the SoC core can initiate a,1: Indicates that rank1_refresh operation has not"
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bitfld.long 0x00 0. "rank0_refresh_busy,SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low" "0: Indicates that the SoC core can initiate a,1: Indicates that rank0_refresh operation has not"
group.long 0x320++0x03
line.long 0x00 "SWCTL,Software Register Programming Control Enable"
bitfld.long 0x00 0. "sw_done,Enable quasi-dynamic register programming outside reset" "0,1"
rgroup.long 0x324++0x03
line.long 0x00 "SWSTAT,Software Register Programming Control Status"
bitfld.long 0x00 0. "sw_done_ack,Register programming done" "0,1"
group.long 0x36C++0x03
line.long 0x00 "POISONCFG,AXI Poison Configuration Register"
bitfld.long 0x00 24. "rd_poison_intr_clr,Interrupt clear for read transaction poisoning" "0,1"
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bitfld.long 0x00 20. "rd_poison_intr_en,If set to 1 enables interrupts for read transaction poisoning" "0,1"
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bitfld.long 0x00 16. "rd_poison_slverr_en,If set to 1 enables SLVERR response for read transaction poisoning" "0,1"
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bitfld.long 0x00 8. "wr_poison_intr_clr,Interrupt clear for write transaction poisoning" "0,1"
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bitfld.long 0x00 4. "wr_poison_intr_en,If set to 1 enables interrupts for write transaction poisoning" "0,1"
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bitfld.long 0x00 0. "wr_poison_slverr_en,If set to 1 enables SLVERR response for write transaction poisoning" "0,1"
rgroup.long 0x370++0x03
line.long 0x00 "POISONSTAT,AXI Poison Status Register"
bitfld.long 0x00 16. "rd_poison_intr_0,Read transaction poisoning error interrupt for port 0" "0,1"
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bitfld.long 0x00 0. "wr_poison_intr_0,Write transaction poisoning error interrupt for port 0" "0,1"
rgroup.long 0x3FC++0x03
line.long 0x00 "PSTAT,Port Status Register"
bitfld.long 0x00 16. "wr_port_busy_0,Indicates if there are outstanding writes for AXI port 0" "0,1"
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bitfld.long 0x00 0. "rd_port_busy_0,Indicates if there are outstanding reads for AXI port 0" "0,1"
group.long 0x400++0x03
line.long 0x00 "PCCFG,Port Common Configuration Register"
bitfld.long 0x00 8. "bl_exp_mode,Burst length expansion mode" "0,1"
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bitfld.long 0x00 4. "pagematch_limit,Page match four limit" "0,1"
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bitfld.long 0x00 0. "go2critical_en,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master" "0,1"
group.long 0x404++0x03
line.long 0x00 "PCFGR_0,Port n Configuration Read Register"
bitfld.long 0x00 16. "rdwr_ordered_en,Enable ordered read/writes" "0,1"
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bitfld.long 0x00 14. "rd_port_pagematch_en,If set to 1 enables the Page Match feature" "0,1"
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bitfld.long 0x00 13. "rd_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (arurgent)" "0,1"
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bitfld.long 0x00 12. "rd_port_aging_en,If set to 1 enables aging function for the read channel of the port" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "rd_port_priority,Determines the initial load value of read aging counters"
group.long 0x408++0x03
line.long 0x00 "PCFGW_0,Port n Configuration Write Register"
bitfld.long 0x00 14. "wr_port_pagematch_en,If set to 1 enables the Page Match feature" "0,1"
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bitfld.long 0x00 13. "wr_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (awurgent)" "0,1"
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bitfld.long 0x00 12. "wr_port_aging_en,If set to 1 enables aging function for the write channel of the port" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "wr_port_priority,Determines the initial load value of write aging counters"
group.long 0x490++0x03
line.long 0x00 "PCTRL_0,Port n Control Register"
bitfld.long 0x00 0. "port_en,Enables AXI port n" "0,1"
group.long 0x494++0x03
line.long 0x00 "PCFGQOS0_0,Port n Read QoS Configuration Register 0"
bitfld.long 0x00 20.--21. "rqos_map_region1,This bitfield indicates the traffic class of region 1" "0: LPR and,1: VPR only,2: HPR,?..."
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bitfld.long 0x00 16.--17. "rqos_map_region0,This bitfield indicates the traffic class of region 0" "0: LPR and,1: VPR only,2: HPR,?..."
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bitfld.long 0x00 0.--3. "rqos_map_level1,Separation level1 indicating the end of region0 mapping start of region0 is 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x498++0x03
line.long 0x00 "PCFGQOS1_0,Port n Read QoS Configuration Register 1"
hexmask.long.word 0x00 16.--26. 1. "rqos_map_timeoutr,Specifies the timeout value for transactions mapped to the red address queue"
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hexmask.long.word 0x00 0.--10. 1. "rqos_map_timeoutb,Specifies the timeout value for transactions mapped to the blue address queue"
group.long 0x49C++0x03
line.long 0x00 "PCFGWQOS0_0,Port n Write QoS Configuration Register 0"
bitfld.long 0x00 20.--21. "wqos_map_region1,This bitfield indicates the traffic class of region 1" "0: NPW,1: VPW,?..."
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bitfld.long 0x00 16.--17. "wqos_map_region0,This bitfield indicates the traffic class of region 0" "0: NPW,1: VPW,?..."
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bitfld.long 0x00 0.--3. "wqos_map_level,Separation level indicating the end of region0 mapping start of region0 is 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4A0++0x03
line.long 0x00 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1"
hexmask.long.word 0x00 0.--10. 1. "wqos_map_timeout,Specifies the timeout value for write transactions"
group.long 0x2020++0x03
line.long 0x00 "DERATEEN_SHADOW,[SHADOW] Temperature Derate Enable Register"
bitfld.long 0x00 8.--9. "rc_derate_value,Derate value of tRC for LPDDR4" "0: Derating uses +1,1: Derating uses +2,2: Derating uses +3,3: Derating uses +4"
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bitfld.long 0x00 4.--7. "derate_byte,Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. "derate_value,Derate value" "0: Derating uses +1,1: Derating uses +2"
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bitfld.long 0x00 0. "derate_enable,Enables derating" "0: Timing parameter derating is disabled,1: Timing parameter derating is enabled using MR4"
group.long 0x2024++0x03
line.long 0x00 "DERATEINT_SHADOW,[SHADOW] Temperature Derate Interval Register"
hexmask.long 0x00 0.--31. 1. "mr4_read_interval,Interval between two MR4 reads used to derate the timing parameters"
group.long 0x2050++0x03
line.long 0x00 "RFSHCTL0_SHADOW,[SHADOW] Refresh Control Register 0"
bitfld.long 0x00 20.--23. "refresh_margin,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--16. "refresh_to_x32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once but it has not expired (RFSHCTL0.refresh_burst+1) times yet then a speculative refresh may be performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--8. "refresh_burst,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0: single refresh,1: burst-of-2 refresh,?,?,?,?,?,7: burst-of-8 refresh For information on burst,?..."
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bitfld.long 0x00 2. "per_bank_refresh," "0: All bank refresh,1: Per bank refresh"
group.long 0x2064++0x03
line.long 0x00 "RFSHTMG_SHADOW,[SHADOW] Refresh Timing Register"
hexmask.long.word 0x00 16.--27. 1. "t_rfc_nom_x32,tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4)"
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bitfld.long 0x00 15. "lpddr3_trefbw_en,Used only when LPDDR3 memory type is connected" "0: tREFBW parameter not used,1: tREFBW parameter used"
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hexmask.long.word 0x00 0.--9. 1. "t_rfc_min,tRFC (min): Minimum time from refresh to refresh or activate"
group.long 0x20DC++0x03
line.long 0x00 "INIT3_SHADOW,[SHADOW] SDRAM Initialization Register 3"
hexmask.long.word 0x00 16.--31. 1. "mr,DDR2: Value to write to MR register"
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hexmask.long.word 0x00 0.--15. 1. "emr,DDR2: Value to write to EMR register"
group.long 0x20E0++0x03
line.long 0x00 "INIT4_SHADOW,[SHADOW] SDRAM Initialization Register 4"
hexmask.long.word 0x00 16.--31. 1. "emr2,DDR2: Value to write to EMR2 register"
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hexmask.long.word 0x00 0.--15. 1. "emr3,DDR2: Value to write to EMR3 register"
group.long 0x20E8++0x03
line.long 0x00 "INIT6_SHADOW,[SHADOW] SDRAM Initialization Register 6"
hexmask.long.word 0x00 16.--31. 1. "mr4,DDR4- Value to be loaded into SDRAM MR4 registers"
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hexmask.long.word 0x00 0.--15. 1. "mr5,DDR4- Value to be loaded into SDRAM MR5 registers"
group.long 0x20EC++0x03
line.long 0x00 "INIT7_SHADOW,[SHADOW] SDRAM Initialization Register 7"
hexmask.long.word 0x00 16.--31. 1. "mr6,DDR4- Value to be loaded into SDRAM MR6 registers"
group.long 0x2100++0x03
line.long 0x00 "DRAMTMG0_SHADOW,[SHADOW] SDRAM Timing Register 0"
hexmask.long.byte 0x00 24.--30. 1. "wr2pre,Minimum time between write and precharge to same bank"
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bitfld.long 0x00 16.--21. "t_faw,tFAW Valid only when 8 or more banks(or banks x bank groups) are present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 8.--14. 1. "t_ras_max,tRAS(max): Maximum time between activate and precharge to same bank"
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bitfld.long 0x00 0.--5. "t_ras_min,tRAS(min): Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2104++0x03
line.long 0x00 "DRAMTMG1_SHADOW,[SHADOW] SDRAM Timing Register 1"
bitfld.long 0x00 16.--20. "t_xp,tXP: Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--13. "rd2pre,tRTP: Minimum time from read to precharge of same bank" "?,?,2: DDR3,?,4: LPDDR4,?..."
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hexmask.long.byte 0x00 0.--6. 1. "t_rc,tRC: Minimum time between activates to same bank"
group.long 0x2108++0x03
line.long 0x00 "DRAMTMG2_SHADOW,[SHADOW] SDRAM Timing Register 2"
bitfld.long 0x00 24.--29. "write_latency,Set to WL Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "read_latency,Set to RL Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "rd2wr,DDR2/3/mDDR: RL + BL/2 +" "?,1: WL LPDDR4(DQ ODT is Disabled),2: WL DDR4,?..."
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bitfld.long 0x00 0.--5. "wr2rd,DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x210C++0x03
line.long 0x00 "DRAMTMG3_SHADOW,[SHADOW] SDRAM Timing Register 3"
hexmask.long.word 0x00 20.--29. 1. "t_mrw,Time to wait after a mode register write or read (MRW or MRR)"
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bitfld.long 0x00 12.--17. "t_mrd,tMRD: Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--9. 1. "t_mod,tMOD: Parameter used only in DDR3 and DDR4"
group.long 0x2110++0x03
line.long 0x00 "DRAMTMG4_SHADOW,[SHADOW] SDRAM Timing Register 4"
bitfld.long 0x00 24.--28. "t_rcd,tRCD - tAL: Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--19. "t_ccd,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "t_rrd,DDR4: tRRD_L: Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--4. "t_rp,tRP: Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2114++0x03
line.long 0x00 "DRAMTMG5_SHADOW,[SHADOW] SDRAM Timing Register 5"
bitfld.long 0x00 24.--27. "t_cksrx,This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX" "?,1: DDR3,2: LPDDR4,?..."
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bitfld.long 0x00 16.--19. "t_cksre,This is the time after Self Refresh Down Entry that CK is maintained as a valid clock" "0: LPDDR2,1: DDR3,2: LPDDR4,?..."
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bitfld.long 0x00 8.--13. "t_ckesr,Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--4. "t_cke,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2118++0x03
line.long 0x00 "DRAMTMG6_SHADOW,[SHADOW] SDRAM Timing Register 6"
bitfld.long 0x00 24.--27. "t_ckdpde,This is the time after Deep Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR3,?..."
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bitfld.long 0x00 16.--19. "t_ckdpdx,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "?,1: LPDDR2,2: LPDDR3,?..."
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bitfld.long 0x00 0.--3. "t_ckcsx,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit" "?,1: LPDDR2,2: LPDDR4,?..."
group.long 0x211C++0x03
line.long 0x00 "DRAMTMG7_SHADOW,[SHADOW] SDRAM Timing Register 7"
bitfld.long 0x00 8.--11. "t_ckpde,This is the time after Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR4,?..."
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bitfld.long 0x00 0.--3. "t_ckpdx,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0: LPDDR2,?,2: LPDDR4,?..."
group.long 0x2120++0x03
line.long 0x00 "DRAMTMG8_SHADOW,[SHADOW] SDRAM Timing Register 8"
hexmask.long.byte 0x00 24.--30. 1. "t_xs_fast_x32,tXS_FAST: Exit Self Refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode)"
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hexmask.long.byte 0x00 16.--22. 1. "t_xs_abort_x32,tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort"
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hexmask.long.byte 0x00 8.--14. 1. "t_xs_dll_x32,tXSDLL: Exit Self Refresh to commands requiring a locked DLL"
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hexmask.long.byte 0x00 0.--6. 1. "t_xs_x32,tXS: Exit Self Refresh to commands not requiring a locked DLL"
group.long 0x2124++0x03
line.long 0x00 "DRAMTMG9_SHADOW,[SHADOW] SDRAM Timing Register 9"
bitfld.long 0x00 30. "ddr4_wr_preamble,DDR4 Write preamble mode" "0: 1tCK preamble,1: 2tCK preamble Present only with"
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bitfld.long 0x00 16.--18. "t_ccd_s,tCCD_S: This is the minimum time between two reads or two writes for different bank group" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "t_rrd_s,tRRD_S: Minimum time between activates from bank a to bank b for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--5. "wr2rd_s,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2128++0x03
line.long 0x00 "DRAMTMG10_SHADOW,[SHADOW] SDRAM Timing Register 10"
bitfld.long 0x00 16.--20. "t_sync_gear,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "t_cmd_gear,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 2.--3. "t_gear_setup,Geardown setup time" "0,1,2,3"
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bitfld.long 0x00 0.--1. "t_gear_hold,Geardown hold time" "0,1,2,3"
group.long 0x212C++0x03
line.long 0x00 "DRAMTMG11_SHADOW,[SHADOW] SDRAM Timing Register 11"
hexmask.long.byte 0x00 24.--30. 1. "post_mpsm_gap_x32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL"
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bitfld.long 0x00 16.--20. "t_mpx_lh,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "t_mpx_s,tMPX_S: Minimum time CS setup time to CKE" "0,1,2,3"
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bitfld.long 0x00 0.--4. "t_ckmpe,tCKMPE: Minimum valid clock requirement after MPSM entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2130++0x03
line.long 0x00 "DRAMTMG12_SHADOW,[SHADOW] SDRAM Timing Register 12"
bitfld.long 0x00 16.--17. "t_cmdcke,tCMDCKE: Delay from valid command to CKE input LOW" "0,1,2,3"
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bitfld.long 0x00 8.--11. "t_ckehcmd,tCKEHCMD: Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--4. "t_mrd_pda,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2134++0x03
line.long 0x00 "DRAMTMG13_SHADOW,[SHADOW] SDRAM Timing Register 13"
hexmask.long.byte 0x00 24.--30. 1. "odtloff,LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference"
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bitfld.long 0x00 16.--21. "t_ccd_mw,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--2. "t_ppd,LPDDR4: tPPD: This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7"
group.long 0x2138++0x03
line.long 0x00 "DRAMTMG14_SHADOW,[SHADOW] SDRAM Timing Register 14"
hexmask.long.word 0x00 0.--11. 1. "t_xsr,tXSR: Exit Self Refresh to any command"
group.long 0x213C++0x03
line.long 0x00 "DRAMTMG15_SHADOW,[SHADOW] SDRAM Timing Register 15"
bitfld.long 0x00 31. "en_dfi_lp_t_stab," "0: Disable using tSTAB when exiting DFI LP,1: Enable using tSTAB when exiting DFI LP"
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hexmask.long.byte 0x00 0.--7. 1. "t_stab_x32,tSTAB: Stabilization time"
group.long 0x2180++0x03
line.long 0x00 "ZQCTL0_SHADOW,[SHADOW] ZQ Control Register 0"
bitfld.long 0x00 31. "dis_auto_zq," "0: Internally generate ZQCS/MPC(ZQ calibration),1: Disable DDRC generation of ZQCS/MPC(ZQ"
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bitfld.long 0x00 30. "dis_srx_zqcl," "0: Enable issuing of ZQCL/MPC(ZQ calibration),1: Disable issuing of ZQCL/MPC(ZQ calibration)"
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bitfld.long 0x00 29. "zq_resistor_shared," "0: ZQ resistor is not shared,1: Denotes that ZQ resistor is shared between.."
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bitfld.long 0x00 28. "dis_mpsmx_zqcl," "0: Enable issuing of ZQCL command at Maximum Power,1: Disable issuing of ZQCL command at Maximum.."
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hexmask.long.word 0x00 16.--26. 1. "t_zq_long_nop,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM"
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hexmask.long.word 0x00 0.--9. 1. "t_zq_short_nop,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM"
group.long 0x2190++0x03
line.long 0x00 "DFITMG0_SHADOW,[SHADOW] DFI Timing Register 0"
bitfld.long 0x00 24.--28. "dfi_t_ctrl_delay,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "dfi_rddata_use_sdr,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "0,1"
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hexmask.long.byte 0x00 16.--22. 1. "dfi_t_rddata_en,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal"
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bitfld.long 0x00 15. "dfi_wrdata_use_sdr,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles.." "0,1"
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bitfld.long 0x00 8.--13. "dfi_tphy_wrdata,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "dfi_tphy_wrlat,Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2194++0x03
line.long 0x00 "DFITMG1_SHADOW,[SHADOW] DFI Timing Register 1"
bitfld.long 0x00 28.--31. "dfi_t_cmd_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--25. "dfi_t_parin_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3"
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bitfld.long 0x00 16.--20. "dfi_t_wrdata_delay,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "dfi_t_dram_clk_disable,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "dfi_t_dram_clk_enable,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21B4++0x03
line.long 0x00 "DFITMG2_SHADOW,[SHADOW] DFI Timing Register 2"
hexmask.long.byte 0x00 8.--14. 1. "dfi_tphy_rdcslat,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted"
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bitfld.long 0x00 0.--5. "dfi_tphy_wrcslat,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x21B8++0x03
line.long 0x00 "DFITMG3_SHADOW,[SHADOW] DFI Timing Register 3"
bitfld.long 0x00 0.--4. "dfi_t_geardown_delay,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2240++0x03
line.long 0x00 "ODTCFG_SHADOW,[SHADOW] ODT Configuration Register"
bitfld.long 0x00 24.--27. "wr_odt_hold,DFI PHY clock cycles to hold ODT for a write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--20. "wr_odt_delay,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--11. "rd_odt_hold,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2.--6. "rd_odt_delay,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "DMA (DMA MP)"
base ad:0x30E30000
group.long 0x00++0x03
line.long 0x00 "MP_CSR,Management Page Control"
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
rbitfld.long 0x00 24.--28. "ACTIVE_ID,Active Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
bitfld.long 0x00 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer"
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bitfld.long 0x00 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and.."
bitfld.long 0x00 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by.."
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bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
bitfld.long 0x00 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1"
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bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled"
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled"
rgroup.long 0x04++0x03
line.long 0x00 "MP_ES,Management Page Error Status"
bitfld.long 0x00 31. "VLD,Valid" "0: No ERR fields are set to 1,1: At least one ERR field is set to 1 indicating.."
bitfld.long 0x00 24.--28. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer.."
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
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bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
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bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to.."
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bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source"
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bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.."
rgroup.long 0x08++0x03
line.long 0x00 "MP_INT,Management Page Interrupt Request Status"
hexmask.long 0x00 0.--31. 1. "INT,Interrupt Request Status"
rgroup.long 0x0C++0x03
line.long 0x00 "MP_HRS,Management Page Hardware Request Status"
hexmask.long 0x00 0.--31. 1. "HRS,Hardware Request Status"
repeat 32. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "CH_GRPRI[$1],Channel Arbitration Group $1"
bitfld.long 0x00 0.--4. "GRPRI,Arbitration Group For Channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
group.long 0x10000++0x03
line.long 0x00 "CH0_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
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bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
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bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x10004++0x03
line.long 0x00 "CH0_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
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rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
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rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
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rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
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rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x10008++0x03
line.long 0x00 "CH0_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1000C++0x03
line.long 0x00 "CH0_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
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rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10010++0x03
line.long 0x00 "CH0_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
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bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x10020++0x03
line.long 0x00 "TCD0_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x10024++0x01
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x10026++0x01
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
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bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x10028++0x03
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
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hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x10028++0x03
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
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hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1002C++0x03
line.long 0x00 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x10030++0x03
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x10034++0x01
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x10036++0x01
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x10036++0x01
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x10038++0x03
line.long 0x00 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1003C++0x01
line.word 0x00 "TCD0_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
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bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
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bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
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bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1003E++0x01
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1003E++0x01
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x11000++0x03
line.long 0x00 "CH1_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x11004++0x03
line.long 0x00 "CH1_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x11008++0x03
line.long 0x00 "CH1_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1100C++0x03
line.long 0x00 "CH1_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x11010++0x03
line.long 0x00 "CH1_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x11020++0x03
line.long 0x00 "TCD1_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x11024++0x01
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x11026++0x01
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x11028++0x03
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x11028++0x03
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1102C++0x03
line.long 0x00 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x11030++0x03
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x11034++0x01
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x11036++0x01
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x11036++0x01
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x11038++0x03
line.long 0x00 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1103C++0x01
line.word 0x00 "TCD1_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1103E++0x01
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1103E++0x01
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x12000++0x03
line.long 0x00 "CH2_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x12004++0x03
line.long 0x00 "CH2_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x12008++0x03
line.long 0x00 "CH2_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1200C++0x03
line.long 0x00 "CH2_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x12010++0x03
line.long 0x00 "CH2_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x12020++0x03
line.long 0x00 "TCD2_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x12024++0x01
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x12026++0x01
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x12028++0x03
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x12028++0x03
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1202C++0x03
line.long 0x00 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x12030++0x03
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x12034++0x01
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x12036++0x01
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x12036++0x01
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x12038++0x03
line.long 0x00 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1203C++0x01
line.word 0x00 "TCD2_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1203E++0x01
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1203E++0x01
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x13000++0x03
line.long 0x00 "CH3_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x13004++0x03
line.long 0x00 "CH3_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x13008++0x03
line.long 0x00 "CH3_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1300C++0x03
line.long 0x00 "CH3_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x13010++0x03
line.long 0x00 "CH3_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x13020++0x03
line.long 0x00 "TCD3_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x13024++0x01
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x13026++0x01
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
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bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x13028++0x03
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x13028++0x03
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1302C++0x03
line.long 0x00 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x13030++0x03
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x13034++0x01
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x13036++0x01
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x13036++0x01
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x13038++0x03
line.long 0x00 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1303C++0x01
line.word 0x00 "TCD3_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1303E++0x01
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1303E++0x01
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x14000++0x03
line.long 0x00 "CH4_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
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bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
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bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x14004++0x03
line.long 0x00 "CH4_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
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rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x14008++0x03
line.long 0x00 "CH4_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1400C++0x03
line.long 0x00 "CH4_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14010++0x03
line.long 0x00 "CH4_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x14020++0x03
line.long 0x00 "TCD4_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x14024++0x01
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x14026++0x01
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x14028++0x03
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x14028++0x03
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1402C++0x03
line.long 0x00 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x14030++0x03
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x14034++0x01
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x14036++0x01
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x14036++0x01
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x14038++0x03
line.long 0x00 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1403C++0x01
line.word 0x00 "TCD4_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1403E++0x01
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1403E++0x01
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x15000++0x03
line.long 0x00 "CH5_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x15004++0x03
line.long 0x00 "CH5_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x15008++0x03
line.long 0x00 "CH5_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1500C++0x03
line.long 0x00 "CH5_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x15010++0x03
line.long 0x00 "CH5_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x15020++0x03
line.long 0x00 "TCD5_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x15024++0x01
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x15026++0x01
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x15028++0x03
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x15028++0x03
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1502C++0x03
line.long 0x00 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x15030++0x03
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x15034++0x01
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x15036++0x01
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x15036++0x01
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x15038++0x03
line.long 0x00 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1503C++0x01
line.word 0x00 "TCD5_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1503E++0x01
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1503E++0x01
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x16000++0x03
line.long 0x00 "CH6_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x16004++0x03
line.long 0x00 "CH6_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
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rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x16008++0x03
line.long 0x00 "CH6_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1600C++0x03
line.long 0x00 "CH6_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x16010++0x03
line.long 0x00 "CH6_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x16020++0x03
line.long 0x00 "TCD6_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x16024++0x01
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x16026++0x01
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x16028++0x03
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x16028++0x03
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1602C++0x03
line.long 0x00 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x16030++0x03
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x16034++0x01
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x16036++0x01
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x16036++0x01
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x16038++0x03
line.long 0x00 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1603C++0x01
line.word 0x00 "TCD6_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1603E++0x01
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1603E++0x01
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x17000++0x03
line.long 0x00 "CH7_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x17004++0x03
line.long 0x00 "CH7_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x17008++0x03
line.long 0x00 "CH7_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1700C++0x03
line.long 0x00 "CH7_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x17010++0x03
line.long 0x00 "CH7_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x17020++0x03
line.long 0x00 "TCD7_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x17024++0x01
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x17026++0x01
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x17028++0x03
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x17028++0x03
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1702C++0x03
line.long 0x00 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x17030++0x03
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x17034++0x01
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x17036++0x01
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x17036++0x01
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x17038++0x03
line.long 0x00 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1703C++0x01
line.word 0x00 "TCD7_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1703E++0x01
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1703E++0x01
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x18000++0x03
line.long 0x00 "CH8_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x18004++0x03
line.long 0x00 "CH8_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x18008++0x03
line.long 0x00 "CH8_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1800C++0x03
line.long 0x00 "CH8_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18010++0x03
line.long 0x00 "CH8_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x18020++0x03
line.long 0x00 "TCD8_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x18024++0x01
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x18026++0x01
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x18028++0x03
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x18028++0x03
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1802C++0x03
line.long 0x00 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x18030++0x03
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x18034++0x01
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x18036++0x01
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x18036++0x01
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x18038++0x03
line.long 0x00 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1803C++0x01
line.word 0x00 "TCD8_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1803E++0x01
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1803E++0x01
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x19000++0x03
line.long 0x00 "CH9_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x19004++0x03
line.long 0x00 "CH9_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x19008++0x03
line.long 0x00 "CH9_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1900C++0x03
line.long 0x00 "CH9_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x19010++0x03
line.long 0x00 "CH9_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x19020++0x03
line.long 0x00 "TCD9_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x19024++0x01
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x19026++0x01
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x19028++0x03
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x19028++0x03
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1902C++0x03
line.long 0x00 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x19030++0x03
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x19034++0x01
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x19036++0x01
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x19036++0x01
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x19038++0x03
line.long 0x00 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1903C++0x01
line.word 0x00 "TCD9_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1903E++0x01
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1903E++0x01
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x1A000++0x03
line.long 0x00 "CH10_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x1A004++0x03
line.long 0x00 "CH10_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x1A008++0x03
line.long 0x00 "CH10_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1A00C++0x03
line.long 0x00 "CH10_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1A010++0x03
line.long 0x00 "CH10_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x1A020++0x03
line.long 0x00 "TCD10_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x1A024++0x01
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x1A026++0x01
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x1A028++0x03
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1A028++0x03
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1A02C++0x03
line.long 0x00 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x1A030++0x03
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x1A034++0x01
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x1A036++0x01
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x1A036++0x01
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x1A038++0x03
line.long 0x00 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1A03C++0x01
line.word 0x00 "TCD10_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1A03E++0x01
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1A03E++0x01
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x1B000++0x03
line.long 0x00 "CH11_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x1B004++0x03
line.long 0x00 "CH11_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x1B008++0x03
line.long 0x00 "CH11_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1B00C++0x03
line.long 0x00 "CH11_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1B010++0x03
line.long 0x00 "CH11_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x1B020++0x03
line.long 0x00 "TCD11_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x1B024++0x01
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x1B026++0x01
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x1B028++0x03
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1B028++0x03
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1B02C++0x03
line.long 0x00 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x1B030++0x03
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x1B034++0x01
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x1B036++0x01
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x1B036++0x01
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x1B038++0x03
line.long 0x00 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1B03C++0x01
line.word 0x00 "TCD11_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1B03E++0x01
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1B03E++0x01
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x1C000++0x03
line.long 0x00 "CH12_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x1C004++0x03
line.long 0x00 "CH12_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x1C008++0x03
line.long 0x00 "CH12_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1C00C++0x03
line.long 0x00 "CH12_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C010++0x03
line.long 0x00 "CH12_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x1C020++0x03
line.long 0x00 "TCD12_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x1C024++0x01
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x1C026++0x01
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x1C028++0x03
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1C028++0x03
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1C02C++0x03
line.long 0x00 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x1C030++0x03
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x1C034++0x01
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x1C036++0x01
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x1C036++0x01
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x1C038++0x03
line.long 0x00 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1C03C++0x01
line.word 0x00 "TCD12_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1C03E++0x01
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1C03E++0x01
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x1D000++0x03
line.long 0x00 "CH13_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x1D004++0x03
line.long 0x00 "CH13_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x1D008++0x03
line.long 0x00 "CH13_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1D00C++0x03
line.long 0x00 "CH13_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1D010++0x03
line.long 0x00 "CH13_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x1D020++0x03
line.long 0x00 "TCD13_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x1D024++0x01
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x1D026++0x01
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x1D028++0x03
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1D028++0x03
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1D02C++0x03
line.long 0x00 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x1D030++0x03
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x1D034++0x01
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x1D036++0x01
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x1D036++0x01
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x1D038++0x03
line.long 0x00 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1D03C++0x01
line.word 0x00 "TCD13_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1D03E++0x01
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1D03E++0x01
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x1E000++0x03
line.long 0x00 "CH14_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x1E004++0x03
line.long 0x00 "CH14_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x1E008++0x03
line.long 0x00 "CH14_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1E00C++0x03
line.long 0x00 "CH14_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1E010++0x03
line.long 0x00 "CH14_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x1E020++0x03
line.long 0x00 "TCD14_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x1E024++0x01
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x1E026++0x01
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x1E028++0x03
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1E028++0x03
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1E02C++0x03
line.long 0x00 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x1E030++0x03
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x1E034++0x01
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x1E036++0x01
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x1E036++0x01
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x1E038++0x03
line.long 0x00 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1E03C++0x01
line.word 0x00 "TCD14_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1E03E++0x01
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1E03E++0x01
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x1F000++0x03
line.long 0x00 "CH15_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x1F004++0x03
line.long 0x00 "CH15_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x1F008++0x03
line.long 0x00 "CH15_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1F00C++0x03
line.long 0x00 "CH15_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1F010++0x03
line.long 0x00 "CH15_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x1F020++0x03
line.long 0x00 "TCD15_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x1F024++0x01
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x1F026++0x01
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x1F028++0x03
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1F028++0x03
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1F02C++0x03
line.long 0x00 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x1F030++0x03
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x1F034++0x01
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x1F036++0x01
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x1F036++0x01
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x1F038++0x03
line.long 0x00 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1F03C++0x01
line.word 0x00 "TCD15_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1F03E++0x01
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1F03E++0x01
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x20000++0x03
line.long 0x00 "CH16_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x20004++0x03
line.long 0x00 "CH16_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x20008++0x03
line.long 0x00 "CH16_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2000C++0x03
line.long 0x00 "CH16_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20010++0x03
line.long 0x00 "CH16_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x20020++0x03
line.long 0x00 "TCD16_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x20024++0x01
line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x20026++0x01
line.word 0x00 "TCD16_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x20028++0x03
line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x20028++0x03
line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2002C++0x03
line.long 0x00 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x20030++0x03
line.long 0x00 "TCD16_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x20034++0x01
line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x20036++0x01
line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x20036++0x01
line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x20038++0x03
line.long 0x00 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2003C++0x01
line.word 0x00 "TCD16_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2003E++0x01
line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2003E++0x01
line.word 0x00 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x21000++0x03
line.long 0x00 "CH17_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x21004++0x03
line.long 0x00 "CH17_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x21008++0x03
line.long 0x00 "CH17_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2100C++0x03
line.long 0x00 "CH17_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21010++0x03
line.long 0x00 "CH17_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x21020++0x03
line.long 0x00 "TCD17_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x21024++0x01
line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x21026++0x01
line.word 0x00 "TCD17_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x21028++0x03
line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x21028++0x03
line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2102C++0x03
line.long 0x00 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x21030++0x03
line.long 0x00 "TCD17_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x21034++0x01
line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x21036++0x01
line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x21036++0x01
line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x21038++0x03
line.long 0x00 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2103C++0x01
line.word 0x00 "TCD17_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2103E++0x01
line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2103E++0x01
line.word 0x00 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x22000++0x03
line.long 0x00 "CH18_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x22004++0x03
line.long 0x00 "CH18_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x22008++0x03
line.long 0x00 "CH18_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2200C++0x03
line.long 0x00 "CH18_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22010++0x03
line.long 0x00 "CH18_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x22020++0x03
line.long 0x00 "TCD18_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x22024++0x01
line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x22026++0x01
line.word 0x00 "TCD18_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x22028++0x03
line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x22028++0x03
line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2202C++0x03
line.long 0x00 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x22030++0x03
line.long 0x00 "TCD18_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x22034++0x01
line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x22036++0x01
line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x22036++0x01
line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x22038++0x03
line.long 0x00 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2203C++0x01
line.word 0x00 "TCD18_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2203E++0x01
line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2203E++0x01
line.word 0x00 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x23000++0x03
line.long 0x00 "CH19_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x23004++0x03
line.long 0x00 "CH19_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x23008++0x03
line.long 0x00 "CH19_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2300C++0x03
line.long 0x00 "CH19_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x23010++0x03
line.long 0x00 "CH19_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x23020++0x03
line.long 0x00 "TCD19_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x23024++0x01
line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x23026++0x01
line.word 0x00 "TCD19_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x23028++0x03
line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x23028++0x03
line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2302C++0x03
line.long 0x00 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x23030++0x03
line.long 0x00 "TCD19_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x23034++0x01
line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x23036++0x01
line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x23036++0x01
line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x23038++0x03
line.long 0x00 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2303C++0x01
line.word 0x00 "TCD19_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2303E++0x01
line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2303E++0x01
line.word 0x00 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x24000++0x03
line.long 0x00 "CH20_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x24004++0x03
line.long 0x00 "CH20_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x24008++0x03
line.long 0x00 "CH20_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2400C++0x03
line.long 0x00 "CH20_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x24010++0x03
line.long 0x00 "CH20_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x24020++0x03
line.long 0x00 "TCD20_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x24024++0x01
line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x24026++0x01
line.word 0x00 "TCD20_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x24028++0x03
line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x24028++0x03
line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2402C++0x03
line.long 0x00 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x24030++0x03
line.long 0x00 "TCD20_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x24034++0x01
line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x24036++0x01
line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x24036++0x01
line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x24038++0x03
line.long 0x00 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2403C++0x01
line.word 0x00 "TCD20_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2403E++0x01
line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2403E++0x01
line.word 0x00 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x25000++0x03
line.long 0x00 "CH21_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x25004++0x03
line.long 0x00 "CH21_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x25008++0x03
line.long 0x00 "CH21_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2500C++0x03
line.long 0x00 "CH21_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x25010++0x03
line.long 0x00 "CH21_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x25020++0x03
line.long 0x00 "TCD21_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x25024++0x01
line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x25026++0x01
line.word 0x00 "TCD21_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x25028++0x03
line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x25028++0x03
line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2502C++0x03
line.long 0x00 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x25030++0x03
line.long 0x00 "TCD21_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x25034++0x01
line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x25036++0x01
line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x25036++0x01
line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x25038++0x03
line.long 0x00 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2503C++0x01
line.word 0x00 "TCD21_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2503E++0x01
line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2503E++0x01
line.word 0x00 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x26000++0x03
line.long 0x00 "CH22_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x26004++0x03
line.long 0x00 "CH22_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x26008++0x03
line.long 0x00 "CH22_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2600C++0x03
line.long 0x00 "CH22_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x26010++0x03
line.long 0x00 "CH22_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x26020++0x03
line.long 0x00 "TCD22_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x26024++0x01
line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x26026++0x01
line.word 0x00 "TCD22_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x26028++0x03
line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x26028++0x03
line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2602C++0x03
line.long 0x00 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x26030++0x03
line.long 0x00 "TCD22_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x26034++0x01
line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x26036++0x01
line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x26036++0x01
line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x26038++0x03
line.long 0x00 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2603C++0x01
line.word 0x00 "TCD22_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2603E++0x01
line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2603E++0x01
line.word 0x00 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x27000++0x03
line.long 0x00 "CH23_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x27004++0x03
line.long 0x00 "CH23_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x27008++0x03
line.long 0x00 "CH23_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2700C++0x03
line.long 0x00 "CH23_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x27010++0x03
line.long 0x00 "CH23_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x27020++0x03
line.long 0x00 "TCD23_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x27024++0x01
line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x27026++0x01
line.word 0x00 "TCD23_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x27028++0x03
line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x27028++0x03
line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2702C++0x03
line.long 0x00 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x27030++0x03
line.long 0x00 "TCD23_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x27034++0x01
line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x27036++0x01
line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x27036++0x01
line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x27038++0x03
line.long 0x00 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2703C++0x01
line.word 0x00 "TCD23_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2703E++0x01
line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2703E++0x01
line.word 0x00 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x28000++0x03
line.long 0x00 "CH24_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x28004++0x03
line.long 0x00 "CH24_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x28008++0x03
line.long 0x00 "CH24_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2800C++0x03
line.long 0x00 "CH24_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x28010++0x03
line.long 0x00 "CH24_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x28020++0x03
line.long 0x00 "TCD24_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x28024++0x01
line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x28026++0x01
line.word 0x00 "TCD24_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x28028++0x03
line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x28028++0x03
line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2802C++0x03
line.long 0x00 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x28030++0x03
line.long 0x00 "TCD24_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x28034++0x01
line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x28036++0x01
line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x28036++0x01
line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x28038++0x03
line.long 0x00 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2803C++0x01
line.word 0x00 "TCD24_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2803E++0x01
line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2803E++0x01
line.word 0x00 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x29000++0x03
line.long 0x00 "CH25_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x29004++0x03
line.long 0x00 "CH25_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x29008++0x03
line.long 0x00 "CH25_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2900C++0x03
line.long 0x00 "CH25_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x29010++0x03
line.long 0x00 "CH25_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x29020++0x03
line.long 0x00 "TCD25_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x29024++0x01
line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x29026++0x01
line.word 0x00 "TCD25_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x29028++0x03
line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x29028++0x03
line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2902C++0x03
line.long 0x00 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x29030++0x03
line.long 0x00 "TCD25_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x29034++0x01
line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x29036++0x01
line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x29036++0x01
line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x29038++0x03
line.long 0x00 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2903C++0x01
line.word 0x00 "TCD25_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2903E++0x01
line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2903E++0x01
line.word 0x00 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x2A000++0x03
line.long 0x00 "CH26_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x2A004++0x03
line.long 0x00 "CH26_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x2A008++0x03
line.long 0x00 "CH26_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2A00C++0x03
line.long 0x00 "CH26_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2A010++0x03
line.long 0x00 "CH26_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x2A020++0x03
line.long 0x00 "TCD26_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x2A024++0x01
line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x2A026++0x01
line.word 0x00 "TCD26_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x2A028++0x03
line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2A028++0x03
line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2A02C++0x03
line.long 0x00 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x2A030++0x03
line.long 0x00 "TCD26_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x2A034++0x01
line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x2A036++0x01
line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x2A036++0x01
line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x2A038++0x03
line.long 0x00 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2A03C++0x01
line.word 0x00 "TCD26_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2A03E++0x01
line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2A03E++0x01
line.word 0x00 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x2B000++0x03
line.long 0x00 "CH27_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x2B004++0x03
line.long 0x00 "CH27_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x2B008++0x03
line.long 0x00 "CH27_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2B00C++0x03
line.long 0x00 "CH27_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2B010++0x03
line.long 0x00 "CH27_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x2B020++0x03
line.long 0x00 "TCD27_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x2B024++0x01
line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x2B026++0x01
line.word 0x00 "TCD27_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x2B028++0x03
line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2B028++0x03
line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2B02C++0x03
line.long 0x00 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x2B030++0x03
line.long 0x00 "TCD27_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x2B034++0x01
line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x2B036++0x01
line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x2B036++0x01
line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x2B038++0x03
line.long 0x00 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2B03C++0x01
line.word 0x00 "TCD27_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2B03E++0x01
line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2B03E++0x01
line.word 0x00 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x2C000++0x03
line.long 0x00 "CH28_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x2C004++0x03
line.long 0x00 "CH28_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x2C008++0x03
line.long 0x00 "CH28_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2C00C++0x03
line.long 0x00 "CH28_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2C010++0x03
line.long 0x00 "CH28_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x2C020++0x03
line.long 0x00 "TCD28_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x2C024++0x01
line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x2C026++0x01
line.word 0x00 "TCD28_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x2C028++0x03
line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2C028++0x03
line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2C02C++0x03
line.long 0x00 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x2C030++0x03
line.long 0x00 "TCD28_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x2C034++0x01
line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x2C036++0x01
line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x2C036++0x01
line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x2C038++0x03
line.long 0x00 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2C03C++0x01
line.word 0x00 "TCD28_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2C03E++0x01
line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2C03E++0x01
line.word 0x00 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x2D000++0x03
line.long 0x00 "CH29_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x2D004++0x03
line.long 0x00 "CH29_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x2D008++0x03
line.long 0x00 "CH29_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2D00C++0x03
line.long 0x00 "CH29_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2D010++0x03
line.long 0x00 "CH29_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x2D020++0x03
line.long 0x00 "TCD29_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x2D024++0x01
line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x2D026++0x01
line.word 0x00 "TCD29_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x2D028++0x03
line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2D028++0x03
line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2D02C++0x03
line.long 0x00 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x2D030++0x03
line.long 0x00 "TCD29_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x2D034++0x01
line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x2D036++0x01
line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x2D036++0x01
line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x2D038++0x03
line.long 0x00 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2D03C++0x01
line.word 0x00 "TCD29_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2D03E++0x01
line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2D03E++0x01
line.word 0x00 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x2E000++0x03
line.long 0x00 "CH30_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x2E004++0x03
line.long 0x00 "CH30_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x2E008++0x03
line.long 0x00 "CH30_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2E00C++0x03
line.long 0x00 "CH30_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2E010++0x03
line.long 0x00 "CH30_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x2E020++0x03
line.long 0x00 "TCD30_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x2E024++0x01
line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x2E026++0x01
line.word 0x00 "TCD30_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x2E028++0x03
line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2E028++0x03
line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2E02C++0x03
line.long 0x00 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x2E030++0x03
line.long 0x00 "TCD30_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x2E034++0x01
line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x2E036++0x01
line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x2E036++0x01
line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x2E038++0x03
line.long 0x00 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2E03C++0x01
line.word 0x00 "TCD30_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2E03E++0x01
line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2E03E++0x01
line.word 0x00 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x2F000++0x03
line.long 0x00 "CH31_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x2F004++0x03
line.long 0x00 "CH31_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x2F008++0x03
line.long 0x00 "CH31_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2F00C++0x03
line.long 0x00 "CH31_SBR,Channel System Bus"
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
newline
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2F010++0x03
line.long 0x00 "CH31_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x2F020++0x03
line.long 0x00 "TCD31_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x2F024++0x01
line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x2F026++0x01
line.word 0x00 "TCD31_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x2F028++0x03
line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2F028++0x03
line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2F02C++0x03
line.long 0x00 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x2F030++0x03
line.long 0x00 "TCD31_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x2F034++0x01
line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x2F036++0x01
line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x2F036++0x01
line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x2F038++0x03
line.long 0x00 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2F03C++0x01
line.word 0x00 "TCD31_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
newline
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
newline
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
newline
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2F03E++0x01
line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2F03E++0x01
line.word 0x00 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
tree.end
tree "DWC_DDRPHYA_ANIB"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9.) (list ad:0x3C000000 ad:0x3C001000 ad:0x3C002000 ad:0x3C003000 ad:0x3C004000 ad:0x3C005000 ad:0x3C006000 ad:0x3C007000 ad:0x3C008000 ad:0x3C009000)
tree "DWC_DDRPHYA_ANIB$1"
base $2
group.word 0x34++0x01
line.word 0x00 "MtestMuxSel,Digital Observation Pin control"
bitfld.word 0x00 0.--5. "MtestMuxSel,Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x4E++0x01
line.word 0x00 "AForceDrvCont,Force Address/Command Driven (Lanes A3-A0)"
bitfld.word 0x00 0.--3. "AForceDrvCont,Force continuous drive per-lane of the ACX4 instance controlled by this register Setting this register will cause the PHY to drive the target lane when dfi_init_complete==1 Bit [0] = controls lane 0 of the target ACX4 block Bit [1] =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x50++0x01
line.word 0x00 "AForceTriCont,Force Address/Command Tristate (Lanes A3-A0)"
bitfld.word 0x00 0.--3. "AForceTriCont,Force tristate control per-lane of the ACX4 instance controlled by this register Setting this register will cause the PHY to tristate the target lane when dfi_init_complete==1 Bit [0] = controls lane 0 of the target ACX4 block Bit [1] =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x86++0x01
line.word 0x00 "ATxImpedance,Address TX impedance controls"
bitfld.word 0x00 5.--9. "ADrvStrenN,5 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--4. "ADrvStrenP,5 bit bus used to select the target pull up output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.word 0xA6++0x01
line.word 0x00 "ATestPrbsErr,Address Loopback PRBS Error status for an entire ACX4 block"
bitfld.word 0x00 0.--3. "ATestPrbsErr,Overall error indicator for each prbs bump checker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xAA++0x01
line.word 0x00 "ATxSlewRate,Address TX slew rate and predriver controls"
bitfld.word 0x00 8.--10. "ATxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "ATxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "ATxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.word 0xAC++0x01
line.word 0x00 "ATestPrbsErrCnt,Address Loopback Test Result register"
hexmask.word 0x00 0.--15. 1. "ATestPrbsErrCnt,Overall error indicator for each prbs bump checker"
group.word 0x100++0x01
line.word 0x00 "ATxDly_p0,Address/Command Delay per pstate"
hexmask.word.byte 0x00 0.--6. 1. "ATxDly_p0,Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs per ACX4"
group.word 0x200100++0x01
line.word 0x00 "ATxDly_p1,Address/Command Delay per pstate"
hexmask.word.byte 0x00 0.--6. 1. "ATxDly_p1,Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs per ACX4"
group.word 0x400100++0x01
line.word 0x00 "ATxDly_p2,Address/Command Delay per pstate"
hexmask.word.byte 0x00 0.--6. 1. "ATxDly_p2,Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs per ACX4"
group.word 0x600100++0x01
line.word 0x00 "ATxDly_p3,Address/Command Delay per pstate"
hexmask.word.byte 0x00 0.--6. 1. "ATxDly_p3,Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs per ACX4"
tree.end
repeat.end
tree.end
tree "DWC_DDRPHYA_APBONLY"
base ad:0x3C0D0000
group.word 0x00++0x01
line.word 0x00 "MicroContMuxSel,PMU Config Mux Select"
bitfld.word 0x00 0. "MicroContMuxSel,This register controls access to the PHY configuration registers" "0,1"
rgroup.word 0x08++0x01
line.word 0x00 "UctShadowRegs,PMU/Controller Protocol - Controller Read-only Shadow"
bitfld.word 0x00 1. "UctDatWriteProtShadow,Reserved for future use" "0,1"
bitfld.word 0x00 0. "UctWriteProtShadow,When set to 0 the PMU has a message for the user" "0,1"
group.word 0x60++0x01
line.word 0x00 "DctWriteOnly,Reserved for future use"
hexmask.word 0x00 0.--15. 1. "DctWriteOnly,Reserved for future use"
group.word 0x62++0x01
line.word 0x00 "DctWriteProt,DCT downstream mailbox protocol CSR"
bitfld.word 0x00 0. "DctWriteProt,By setting this register to 0 the user acknowledges the receipt of the message" "0,1"
rgroup.word 0x64++0x01
line.word 0x00 "UctWriteOnlyShadow,Read-only view of the csr UctDatWriteOnly"
hexmask.word 0x00 0.--15. 1. "UctWriteOnlyShadow,Used to pass the message ID for major messages"
rgroup.word 0x68++0x01
line.word 0x00 "UctDatWriteOnlyShadow,Read-only view of the csr UctDatWriteOnly"
hexmask.word 0x00 0.--15. 1. "UctDatWriteOnlyShadow,Used to pass the upper 16 bits for streaming messages"
group.word 0x6E++0x01
line.word 0x00 "DfiCfgRdDataValidTicks,Number of DfiClk ticks required for valid csr Rd Data"
bitfld.word 0x00 0.--5. "DfiCfgRdDataValidTicks,Roundtrip delay of a register read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x132++0x01
line.word 0x00 "MicroReset,Controls reset and clock shutdown on the local microcontroller"
bitfld.word 0x00 3. "ResetToMicro,Set this bit to apply synchronous reset to the microcontroller" "0,1"
bitfld.word 0x00 2. "RSVDMicro,RSVD" "0,1"
newline
bitfld.word 0x00 1. "TestWakeup,Reserved" "0,1"
bitfld.word 0x00 0. "StallToMicro,Set this bit to stall the microcontroller by hardware" "0,1"
rgroup.word 0x1F4++0x01
line.word 0x00 "DfiInitCompleteShadow,dfi_init_complete - Controller Read-only Shadow"
bitfld.word 0x00 0. "DfiInitCompleteShadow,This csr presents a read-only view (a shadow) of the Register DfiInitComplete which is used by the sequencer to control the state of dfi_init_complete" "0,1"
tree.end
tree "DWC_DDRPHYA_DBYTE"
repeat 4. (list 0. 1. 2. 3.) (list ad:0x3C010000 ad:0x3C011000 ad:0x3C012000 ad:0x3C013000)
tree "DWC_DDRPHYA_DBYTE$1"
base $2
group.word 0x00++0x01
line.word 0x00 "DbyteMiscMode,DBYTE Module Disable"
bitfld.word 0x00 2. "DByteDisable,Controls whether this DBYTE module is disabled" "0,1"
group.word 0x34++0x01
line.word 0x00 "MtestMuxSel,Digital Observation Pin control"
bitfld.word 0x00 0.--5. "MtestMuxSel,Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40++0x01
line.word 0x00 "DFIMRL_p0,DFI MaxReadLatency"
bitfld.word 0x00 0.--4. "DFIMRL_p0,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x60++0x01
line.word 0x00 "VrefDAC1_r0,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0x80++0x01
line.word 0x00 "VrefDAC0_r0,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0x82++0x01
line.word 0x00 "TxImpedanceCtrl0_b0_p0,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x86++0x01
line.word 0x00 "DqDqsRcvCntrl_b0_p0,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
newline
bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x90++0x01
line.word 0x00 "TxEqualizationMode_p0,Tx dq driver equalization mode controls"
bitfld.word 0x00 0.--1. "TxEqMode,no description available" "0,1,2,3"
group.word 0x92++0x01
line.word 0x00 "TxImpedanceCtrl1_b0_p0,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x94++0x01
line.word 0x00 "DqDqsRcvCntrl1,Dq/Dqs receiver control"
bitfld.word 0x00 11. "EnLPReqPDR,Reserved for future use" "0,1"
bitfld.word 0x00 10. "RxPadStandbyEn,Enables the rxdq/rxdqs StandBy power savings per pad-group" "0,1"
newline
bitfld.word 0x00 9. "PowerDownRcvrDqs,Active high signal which powers down the receiver" "0,1"
hexmask.word 0x00 0.--8. 1. "PowerDownRcvr,Active high signal which powers down the receiver"
group.word 0x96++0x01
line.word 0x00 "TxImpedanceCtrl2_b0_p0,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x98++0x01
line.word 0x00 "DqDqsRcvCntrl2_p0,Dq/Dqs receiver control"
bitfld.word 0x00 0. "EnRxAgressivePDR,reserved" "0,1"
group.word 0x9A++0x01
line.word 0x00 "TxOdtDrvStren_b0_p0,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0xAC++0x01
line.word 0x00 "RxFifoCheckStatus,Status of RX FIFO Consistency Checks"
bitfld.word 0x00 3. "RxFifoWrLocUErr,If set the write pointer (DQS side) on the read FIFO associated with data bits [7:4] has a non-zero value at least once" "0,1"
bitfld.word 0x00 2. "RxFifoRdLocUErr,If set the read pointer (DFI side) on the read FIFO associated with data bits [7:4] has a non-zero value at least once" "0,1"
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bitfld.word 0x00 1. "RxFifoWrLocErr,If set the write pointer (DQS side) on the read FIFO associated with data bits [3:0] has a non-zero value at least once" "0,1"
bitfld.word 0x00 0. "RxFifoRdLocErr,If set the read pointer (DFI side) on the read FIFO associated with data bits [3:0] had a non-zero value at least once" "0,1"
rgroup.word 0xAE++0x01
line.word 0x00 "RxFifoCheckErrValues,Contains the captured values associated with an RxFifo consistency error"
bitfld.word 0x00 12.--15. "RxFifoWrLocUErrValue,The first error value captured for the write pointer (DQS side) on the read FIFO associated with data bits [7:4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "RxFifoRdLocUErrValue,The first error value captured for the read pointer (DFI side) on the read FIFO associated with data bits [7:4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 4.--7. "RxFifoWrLocErrValue,The first error value captured for the write pointer (DQS side) on the read FIFO associated with data bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "RxFifoRdLocErrValue,The first error value captured for the read pointer (DFI side) on the read FIFO associated with data bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.word 0xB0++0x01
line.word 0x00 "RxFifoInfo,Data Receive FIFO Pointer Values"
bitfld.word 0x00 12.--15. "RxFifoWrLocU,The Mission mode write pointer of the upper-nibble Rx fifo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "RxFifoRdLocU,The Mission mode read pointer of the upper-nibble Rx fifo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "RxFifoWrLoc,The Mission mode write pointer of the lower-nibble Rx fifo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "RxFifoRdLoc,The Mission mode read pointer of the lower-nibble Rx fifo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xB2++0x01
line.word 0x00 "RxFifoVisibility,RX FIFO visibility"
bitfld.word 0x00 4. "RxFifoRdEn,Pulse set 0-->1-->0 this bit to capture the Fifo Contents" "0,1"
bitfld.word 0x00 3. "RxFifoRdPtrOvr," "0,1"
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bitfld.word 0x00 0.--2. "RxFifoRdPtr,If CSR RxFifoRdPtrOVr is set then this CSR selects the rxfifo entry is visible in CSR This 3b field addresses 4b units of the 8x4b (32entry) fifo that is rdfifo_nibble_address[2:0]=csrRxFifoRdPtr[2:0] For example Register RxFifoRdPtr[2:0]=2.." "0,1,2,3,4,5,6,7"
rgroup.word 0xB4++0x01
line.word 0x00 "RxFifoContentsDQ3210,RX FIFO contents lane[3:0]"
hexmask.word 0x00 0.--15. 1. "RxFifoContentsDQ3210,A window into the contents of the RxFifo as controlled by CSR RxFifoVisibility This register reads 4b at a time from lane0"
rgroup.word 0xB6++0x01
line.word 0x00 "RxFifoContentsDQ7654,RX FIFO contents lane[7:4]"
hexmask.word 0x00 0.--15. 1. "RxFifoContentsDQ7654,A window into the contents of the RxFifo as controlled by CSR RxFifoVisibility This register reads 4b at a time from lane4"
rgroup.word 0xB8++0x01
line.word 0x00 "RxFifoContentsDBI,RX FIFO contents dbi"
bitfld.word 0x00 0.--3. "RxFifoContentsDBI,A window into the contents of the RxFifo as controlled by CSR RxFifoVisibility This register reads 4b at a time from DBI from the four fifo entries addressed by rdfifo_nibble_address[2:0]=RxFifoRdPtr[2:0] Register [ 3: 0] = dbi_ui3.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xBE++0x01
line.word 0x00 "TxSlewRate_b0_p0,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xD0++0x01
line.word 0x00 "RxPBDlyTg0_r0,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0xD2++0x01
line.word 0x00 "RxPBDlyTg1_r0,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0xD4++0x01
line.word 0x00 "RxPBDlyTg2_r0,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0xD6++0x01
line.word 0x00 "RxPBDlyTg3_r0,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0x100++0x01
line.word 0x00 "RxEnDlyTg0_u0_p0,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x102++0x01
line.word 0x00 "RxEnDlyTg1_u0_p0,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x104++0x01
line.word 0x00 "RxEnDlyTg2_u0_p0,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x106++0x01
line.word 0x00 "RxEnDlyTg3_u0_p0,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x118++0x01
line.word 0x00 "RxClkDlyTg0_u0_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x11A++0x01
line.word 0x00 "RxClkDlyTg1_u0_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x11C++0x01
line.word 0x00 "RxClkDlyTg2_u0_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x11E++0x01
line.word 0x00 "RxClkDlyTg3_u0_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x120++0x01
line.word 0x00 "RxClkcDlyTg0_u0_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x122++0x01
line.word 0x00 "RxClkcDlyTg1_u0_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x124++0x01
line.word 0x00 "RxClkcDlyTg2_u0_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x128++0x01
line.word 0x00 "RxClkcDlyTg3_u0_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 8. (increment 0 1) (increment 0 0x02)
group.word ($2+0x140)++0x01
line.word 0x00 "DqLnSel[$1],Maps Phy DQ lane to memory DQ0"
bitfld.word 0x00 0.--2. "DqLnSel,Supports mapping of PHY dq to dram dq within a byte (swizzle)" "0,1,2,3,4,5,6,7"
repeat.end
group.word 0x180++0x01
line.word 0x00 "TxDqDlyTg0_r0_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x182++0x01
line.word 0x00 "TxDqDlyTg1_r0_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x184++0x01
line.word 0x00 "TxDqDlyTg2_r0_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x186++0x01
line.word 0x00 "TxDqDlyTg3_r0_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x1A0++0x01
line.word 0x00 "TxDqsDlyTg0_u0_p0,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x1A2++0x01
line.word 0x00 "TxDqsDlyTg1_u0_p0,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x1A4++0x01
line.word 0x00 "TxDqsDlyTg2_u0_p0,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x1A6++0x01
line.word 0x00 "TxDqsDlyTg3_u0_p0,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
rgroup.word 0x1C8++0x01
line.word 0x00 "DxLcdlStatus,Debug status of the DBYTE LCDL"
bitfld.word 0x00 13. "DxLcdlLiveLock,present value of whether the LCDL is locked valid when LcdlTstEnable=1" "0,1"
bitfld.word 0x00 12. "DxLcdlStickyUnlock,latched value of whether the LCDL ever lost lock after the assertion of LcdlTstEnable" "0,1"
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bitfld.word 0x00 11. "DxLcdlStickyLock,latched value of whether the LCDL ever achieved lock after the assertion of LcdlTstEnable" "0,1"
bitfld.word 0x00 10. "DxLcdlPhdSnapVal,Value of the LCDL phase-detector output latched by pulse on csr LcdlFineSnap" "0,1"
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hexmask.word 0x00 0.--9. 1. "DxLcdlFineSnapVal,Value of the LCDL 1UI estimate code latched by pulse on csr LcdlFineSnap while csr LcdlTstEnable=1"
group.word 0x260++0x01
line.word 0x00 "VrefDAC1_r1,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0x280++0x01
line.word 0x00 "VrefDAC0_r1,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0x282++0x01
line.word 0x00 "TxImpedanceCtrl0_b1_p0,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x286++0x01
line.word 0x00 "DqDqsRcvCntrl_b1_p0,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
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bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x292++0x01
line.word 0x00 "TxImpedanceCtrl1_b1_p0,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x296++0x01
line.word 0x00 "TxImpedanceCtrl2_b1_p0,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x29A++0x01
line.word 0x00 "TxOdtDrvStren_b1_p0,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x2BE++0x01
line.word 0x00 "TxSlewRate_b1_p0,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x2D0++0x01
line.word 0x00 "RxPBDlyTg0_r1,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0x2D2++0x01
line.word 0x00 "RxPBDlyTg1_r1,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0x2D4++0x01
line.word 0x00 "RxPBDlyTg2_r1,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0x2D6++0x01
line.word 0x00 "RxPBDlyTg3_r1,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0x300++0x01
line.word 0x00 "RxEnDlyTg0_u1_p0,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x302++0x01
line.word 0x00 "RxEnDlyTg1_u1_p0,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x304++0x01
line.word 0x00 "RxEnDlyTg2_u1_p0,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x306++0x01
line.word 0x00 "RxEnDlyTg3_u1_p0,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x318++0x01
line.word 0x00 "RxClkDlyTg0_u1_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x31A++0x01
line.word 0x00 "RxClkDlyTg1_u1_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x31C++0x01
line.word 0x00 "RxClkDlyTg2_u1_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x31E++0x01
line.word 0x00 "RxClkDlyTg3_u1_p0,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x320++0x01
line.word 0x00 "RxClkcDlyTg0_u1_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x322++0x01
line.word 0x00 "RxClkcDlyTg1_u1_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x324++0x01
line.word 0x00 "RxClkcDlyTg2_u1_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x328++0x01
line.word 0x00 "RxClkcDlyTg3_u1_p0,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x380++0x01
line.word 0x00 "TxDqDlyTg0_r1_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x382++0x01
line.word 0x00 "TxDqDlyTg1_r1_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x384++0x01
line.word 0x00 "TxDqDlyTg2_r1_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x386++0x01
line.word 0x00 "TxDqDlyTg3_r1_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x3A0++0x01
line.word 0x00 "TxDqsDlyTg0_u1_p0,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x3A2++0x01
line.word 0x00 "TxDqsDlyTg1_u1_p0,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x3A4++0x01
line.word 0x00 "TxDqsDlyTg2_u1_p0,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x3A6++0x01
line.word 0x00 "TxDqsDlyTg3_u1_p0,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
group.word 0x460++0x01
line.word 0x00 "VrefDAC1_r2,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0x480++0x01
line.word 0x00 "VrefDAC0_r2,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0x4D0++0x01
line.word 0x00 "RxPBDlyTg0_r2,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0x4D2++0x01
line.word 0x00 "RxPBDlyTg1_r2,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0x4D4++0x01
line.word 0x00 "RxPBDlyTg2_r2,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0x4D6++0x01
line.word 0x00 "RxPBDlyTg3_r2,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0x580++0x01
line.word 0x00 "TxDqDlyTg0_r2_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x582++0x01
line.word 0x00 "TxDqDlyTg1_r2_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x584++0x01
line.word 0x00 "TxDqDlyTg2_r2_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x586++0x01
line.word 0x00 "TxDqDlyTg3_r2_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x660++0x01
line.word 0x00 "VrefDAC1_r3,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0x680++0x01
line.word 0x00 "VrefDAC0_r3,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0x6D0++0x01
line.word 0x00 "RxPBDlyTg0_r3,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0x6D2++0x01
line.word 0x00 "RxPBDlyTg1_r3,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0x6D4++0x01
line.word 0x00 "RxPBDlyTg2_r3,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0x6D6++0x01
line.word 0x00 "RxPBDlyTg3_r3,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0x780++0x01
line.word 0x00 "TxDqDlyTg0_r3_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x782++0x01
line.word 0x00 "TxDqDlyTg1_r3_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x784++0x01
line.word 0x00 "TxDqDlyTg2_r3_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x786++0x01
line.word 0x00 "TxDqDlyTg3_r3_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x860++0x01
line.word 0x00 "VrefDAC1_r4,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0x880++0x01
line.word 0x00 "VrefDAC0_r4,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0x8D0++0x01
line.word 0x00 "RxPBDlyTg0_r4,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0x8D2++0x01
line.word 0x00 "RxPBDlyTg1_r4,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0x8D4++0x01
line.word 0x00 "RxPBDlyTg2_r4,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0x8D6++0x01
line.word 0x00 "RxPBDlyTg3_r4,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0x980++0x01
line.word 0x00 "TxDqDlyTg0_r4_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x982++0x01
line.word 0x00 "TxDqDlyTg1_r4_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x984++0x01
line.word 0x00 "TxDqDlyTg2_r4_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x986++0x01
line.word 0x00 "TxDqDlyTg3_r4_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0xA60++0x01
line.word 0x00 "VrefDAC1_r5,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0xA80++0x01
line.word 0x00 "VrefDAC0_r5,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0xAD0++0x01
line.word 0x00 "RxPBDlyTg0_r5,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0xAD2++0x01
line.word 0x00 "RxPBDlyTg1_r5,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0xAD4++0x01
line.word 0x00 "RxPBDlyTg2_r5,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0xAD6++0x01
line.word 0x00 "RxPBDlyTg3_r5,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0xB80++0x01
line.word 0x00 "TxDqDlyTg0_r5_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0xB82++0x01
line.word 0x00 "TxDqDlyTg1_r5_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0xB84++0x01
line.word 0x00 "TxDqDlyTg2_r5_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0xB86++0x01
line.word 0x00 "TxDqDlyTg3_r5_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0xC60++0x01
line.word 0x00 "VrefDAC1_r6,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0xC80++0x01
line.word 0x00 "VrefDAC0_r6,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0xCD0++0x01
line.word 0x00 "RxPBDlyTg0_r6,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0xCD2++0x01
line.word 0x00 "RxPBDlyTg1_r6,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0xCD4++0x01
line.word 0x00 "RxPBDlyTg2_r6,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0xCD6++0x01
line.word 0x00 "RxPBDlyTg3_r6,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0xD80++0x01
line.word 0x00 "TxDqDlyTg0_r6_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0xD82++0x01
line.word 0x00 "TxDqDlyTg1_r6_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0xD84++0x01
line.word 0x00 "TxDqDlyTg2_r6_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0xD86++0x01
line.word 0x00 "TxDqDlyTg3_r6_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0xE60++0x01
line.word 0x00 "VrefDAC1_r7,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0xE80++0x01
line.word 0x00 "VrefDAC0_r7,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0xED0++0x01
line.word 0x00 "RxPBDlyTg0_r7,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0xED2++0x01
line.word 0x00 "RxPBDlyTg1_r7,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0xED4++0x01
line.word 0x00 "RxPBDlyTg2_r7,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0xED6++0x01
line.word 0x00 "RxPBDlyTg3_r7,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0xF80++0x01
line.word 0x00 "TxDqDlyTg0_r7_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0xF82++0x01
line.word 0x00 "TxDqDlyTg1_r7_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0xF84++0x01
line.word 0x00 "TxDqDlyTg2_r7_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0xF86++0x01
line.word 0x00 "TxDqDlyTg3_r7_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x1060++0x01
line.word 0x00 "VrefDAC1_r8,VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4)"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC1_rx,VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is enabled in DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode settings for.."
group.word 0x1080++0x01
line.word 0x00 "VrefDAC0_r8,VrefDAC0 control for DQ Receiver"
hexmask.word.byte 0x00 0.--6. 1. "VrefDAC0_rx,PHY RX VREF DAC control for rxdq cell internal VREF (used only when 2D training is enabled in LPDDR4 DDR4) DAC control for rxdq cell internal VREF trained by Firmware The VREF generators have different ranges depending on the Mission Mode.."
group.word 0x10D0++0x01
line.word 0x00 "RxPBDlyTg0_r8,Read DQ per-bit BDL delay (Timing Group 0)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg0_rx,Read DQ per-bit BDL delay (Timing Group 0)"
group.word 0x10D2++0x01
line.word 0x00 "RxPBDlyTg1_r8,Read DQ per-bit BDL delay (Timing Group 1)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg1_rx,Read DQ per-bit BDL delay (Timing Group 1)"
group.word 0x10D4++0x01
line.word 0x00 "RxPBDlyTg2_r8,Read DQ per-bit BDL delay (Timing Group 2)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg2_rx,Read DQ per-bit BDL delay (Timing Group 2)"
group.word 0x10D6++0x01
line.word 0x00 "RxPBDlyTg3_r8,Read DQ per-bit BDL delay (Timing Group 3)"
hexmask.word.byte 0x00 0.--6. 1. "RxPBDlyTg3_rx,Read DQ per-bit BDL delay (Timing Group 3)"
group.word 0x1180++0x01
line.word 0x00 "TxDqDlyTg0_r8_p0,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x1182++0x01
line.word 0x00 "TxDqDlyTg1_r8_p0,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x1184++0x01
line.word 0x00 "TxDqDlyTg2_r8_p0,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x1186++0x01
line.word 0x00 "TxDqDlyTg3_r8_p0,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x200040++0x01
line.word 0x00 "DFIMRL_p1,DFI MaxReadLatency"
bitfld.word 0x00 0.--4. "DFIMRL_p1,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x200082++0x01
line.word 0x00 "TxImpedanceCtrl0_b0_p1,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200086++0x01
line.word 0x00 "DqDqsRcvCntrl_b0_p1,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
newline
bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x200090++0x01
line.word 0x00 "TxEqualizationMode_p1,Tx dq driver equalization mode controls"
bitfld.word 0x00 0.--1. "TxEqMode,no description available" "0,1,2,3"
group.word 0x200092++0x01
line.word 0x00 "TxImpedanceCtrl1_b0_p1,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200096++0x01
line.word 0x00 "TxImpedanceCtrl2_b0_p1,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200098++0x01
line.word 0x00 "DqDqsRcvCntrl2_p1,Dq/Dqs receiver control"
bitfld.word 0x00 0. "EnRxAgressivePDR,reserved" "0,1"
group.word 0x20009A++0x01
line.word 0x00 "TxOdtDrvStren_b0_p1,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x2000BE++0x01
line.word 0x00 "TxSlewRate_b0_p1,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x200100++0x01
line.word 0x00 "RxEnDlyTg0_u0_p1,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200102++0x01
line.word 0x00 "RxEnDlyTg1_u0_p1,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200104++0x01
line.word 0x00 "RxEnDlyTg2_u0_p1,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200106++0x01
line.word 0x00 "RxEnDlyTg3_u0_p1,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200118++0x01
line.word 0x00 "RxClkDlyTg0_u0_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20011A++0x01
line.word 0x00 "RxClkDlyTg1_u0_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20011C++0x01
line.word 0x00 "RxClkDlyTg2_u0_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20011E++0x01
line.word 0x00 "RxClkDlyTg3_u0_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200120++0x01
line.word 0x00 "RxClkcDlyTg0_u0_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200122++0x01
line.word 0x00 "RxClkcDlyTg1_u0_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200124++0x01
line.word 0x00 "RxClkcDlyTg2_u0_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200128++0x01
line.word 0x00 "RxClkcDlyTg3_u0_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200180++0x01
line.word 0x00 "TxDqDlyTg0_r0_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200182++0x01
line.word 0x00 "TxDqDlyTg1_r0_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200184++0x01
line.word 0x00 "TxDqDlyTg2_r0_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200186++0x01
line.word 0x00 "TxDqDlyTg3_r0_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x2001A0++0x01
line.word 0x00 "TxDqsDlyTg0_u0_p1,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x2001A2++0x01
line.word 0x00 "TxDqsDlyTg1_u0_p1,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x2001A4++0x01
line.word 0x00 "TxDqsDlyTg2_u0_p1,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x2001A6++0x01
line.word 0x00 "TxDqsDlyTg3_u0_p1,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
group.word 0x200282++0x01
line.word 0x00 "TxImpedanceCtrl0_b1_p1,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200286++0x01
line.word 0x00 "DqDqsRcvCntrl_b1_p1,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
newline
bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x200292++0x01
line.word 0x00 "TxImpedanceCtrl1_b1_p1,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200296++0x01
line.word 0x00 "TxImpedanceCtrl2_b1_p1,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20029A++0x01
line.word 0x00 "TxOdtDrvStren_b1_p1,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x2002BE++0x01
line.word 0x00 "TxSlewRate_b1_p1,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x200300++0x01
line.word 0x00 "RxEnDlyTg0_u1_p1,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200302++0x01
line.word 0x00 "RxEnDlyTg1_u1_p1,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200304++0x01
line.word 0x00 "RxEnDlyTg2_u1_p1,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200306++0x01
line.word 0x00 "RxEnDlyTg3_u1_p1,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x200318++0x01
line.word 0x00 "RxClkDlyTg0_u1_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20031A++0x01
line.word 0x00 "RxClkDlyTg1_u1_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20031C++0x01
line.word 0x00 "RxClkDlyTg2_u1_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20031E++0x01
line.word 0x00 "RxClkDlyTg3_u1_p1,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200320++0x01
line.word 0x00 "RxClkcDlyTg0_u1_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200322++0x01
line.word 0x00 "RxClkcDlyTg1_u1_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200324++0x01
line.word 0x00 "RxClkcDlyTg2_u1_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200328++0x01
line.word 0x00 "RxClkcDlyTg3_u1_p1,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x200380++0x01
line.word 0x00 "TxDqDlyTg0_r1_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200382++0x01
line.word 0x00 "TxDqDlyTg1_r1_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200384++0x01
line.word 0x00 "TxDqDlyTg2_r1_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200386++0x01
line.word 0x00 "TxDqDlyTg3_r1_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x2003A0++0x01
line.word 0x00 "TxDqsDlyTg0_u1_p1,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x2003A2++0x01
line.word 0x00 "TxDqsDlyTg1_u1_p1,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x2003A4++0x01
line.word 0x00 "TxDqsDlyTg2_u1_p1,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x2003A6++0x01
line.word 0x00 "TxDqsDlyTg3_u1_p1,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
group.word 0x200580++0x01
line.word 0x00 "TxDqDlyTg0_r2_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200582++0x01
line.word 0x00 "TxDqDlyTg1_r2_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200584++0x01
line.word 0x00 "TxDqDlyTg2_r2_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200586++0x01
line.word 0x00 "TxDqDlyTg3_r2_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x200780++0x01
line.word 0x00 "TxDqDlyTg0_r3_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200782++0x01
line.word 0x00 "TxDqDlyTg1_r3_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200784++0x01
line.word 0x00 "TxDqDlyTg2_r3_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200786++0x01
line.word 0x00 "TxDqDlyTg3_r3_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x200980++0x01
line.word 0x00 "TxDqDlyTg0_r4_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200982++0x01
line.word 0x00 "TxDqDlyTg1_r4_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200984++0x01
line.word 0x00 "TxDqDlyTg2_r4_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200986++0x01
line.word 0x00 "TxDqDlyTg3_r4_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x200B80++0x01
line.word 0x00 "TxDqDlyTg0_r5_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200B82++0x01
line.word 0x00 "TxDqDlyTg1_r5_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200B84++0x01
line.word 0x00 "TxDqDlyTg2_r5_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200B86++0x01
line.word 0x00 "TxDqDlyTg3_r5_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x200D80++0x01
line.word 0x00 "TxDqDlyTg0_r6_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200D82++0x01
line.word 0x00 "TxDqDlyTg1_r6_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200D84++0x01
line.word 0x00 "TxDqDlyTg2_r6_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200D86++0x01
line.word 0x00 "TxDqDlyTg3_r6_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x200F80++0x01
line.word 0x00 "TxDqDlyTg0_r7_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x200F82++0x01
line.word 0x00 "TxDqDlyTg1_r7_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x200F84++0x01
line.word 0x00 "TxDqDlyTg2_r7_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x200F86++0x01
line.word 0x00 "TxDqDlyTg3_r7_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x201180++0x01
line.word 0x00 "TxDqDlyTg0_r8_p1,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x201182++0x01
line.word 0x00 "TxDqDlyTg1_r8_p1,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x201184++0x01
line.word 0x00 "TxDqDlyTg2_r8_p1,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x201186++0x01
line.word 0x00 "TxDqDlyTg3_r8_p1,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x400040++0x01
line.word 0x00 "DFIMRL_p2,DFI MaxReadLatency"
bitfld.word 0x00 0.--4. "DFIMRL_p2,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x400082++0x01
line.word 0x00 "TxImpedanceCtrl0_b0_p2,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400086++0x01
line.word 0x00 "DqDqsRcvCntrl_b0_p2,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
newline
bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x400090++0x01
line.word 0x00 "TxEqualizationMode_p2,Tx dq driver equalization mode controls"
bitfld.word 0x00 0.--1. "TxEqMode,no description available" "0,1,2,3"
group.word 0x400092++0x01
line.word 0x00 "TxImpedanceCtrl1_b0_p2,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400096++0x01
line.word 0x00 "TxImpedanceCtrl2_b0_p2,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400098++0x01
line.word 0x00 "DqDqsRcvCntrl2_p2,Dq/Dqs receiver control"
bitfld.word 0x00 0. "EnRxAgressivePDR,reserved" "0,1"
group.word 0x40009A++0x01
line.word 0x00 "TxOdtDrvStren_b0_p2,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x4000BE++0x01
line.word 0x00 "TxSlewRate_b0_p2,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x400100++0x01
line.word 0x00 "RxEnDlyTg0_u0_p2,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400102++0x01
line.word 0x00 "RxEnDlyTg1_u0_p2,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400104++0x01
line.word 0x00 "RxEnDlyTg2_u0_p2,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400106++0x01
line.word 0x00 "RxEnDlyTg3_u0_p2,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400118++0x01
line.word 0x00 "RxClkDlyTg0_u0_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40011A++0x01
line.word 0x00 "RxClkDlyTg1_u0_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40011C++0x01
line.word 0x00 "RxClkDlyTg2_u0_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40011E++0x01
line.word 0x00 "RxClkDlyTg3_u0_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400120++0x01
line.word 0x00 "RxClkcDlyTg0_u0_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400122++0x01
line.word 0x00 "RxClkcDlyTg1_u0_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400124++0x01
line.word 0x00 "RxClkcDlyTg2_u0_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400128++0x01
line.word 0x00 "RxClkcDlyTg3_u0_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40015C++0x01
line.word 0x00 "PptDqsCntInvTrnTg0_p2,DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation"
hexmask.word 0x00 0.--15. 1. "PptDqsCntInvTrnTg0_p2,Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation"
group.word 0x40015E++0x01
line.word 0x00 "PptDqsCntInvTrnTg1_p2,DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation"
hexmask.word 0x00 0.--15. 1. "PptDqsCntInvTrnTg1_p2,Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation"
group.word 0x400180++0x01
line.word 0x00 "TxDqDlyTg0_r0_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400182++0x01
line.word 0x00 "TxDqDlyTg1_r0_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400184++0x01
line.word 0x00 "TxDqDlyTg2_r0_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400186++0x01
line.word 0x00 "TxDqDlyTg3_r0_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x4001A0++0x01
line.word 0x00 "TxDqsDlyTg0_u0_p2,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x4001A2++0x01
line.word 0x00 "TxDqsDlyTg1_u0_p2,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x4001A4++0x01
line.word 0x00 "TxDqsDlyTg2_u0_p2,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x4001A6++0x01
line.word 0x00 "TxDqsDlyTg3_u0_p2,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
group.word 0x400282++0x01
line.word 0x00 "TxImpedanceCtrl0_b1_p2,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400286++0x01
line.word 0x00 "DqDqsRcvCntrl_b1_p2,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
newline
bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x400292++0x01
line.word 0x00 "TxImpedanceCtrl1_b1_p2,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400296++0x01
line.word 0x00 "TxImpedanceCtrl2_b1_p2,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40029A++0x01
line.word 0x00 "TxOdtDrvStren_b1_p2,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x4002BE++0x01
line.word 0x00 "TxSlewRate_b1_p2,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x400300++0x01
line.word 0x00 "RxEnDlyTg0_u1_p2,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400302++0x01
line.word 0x00 "RxEnDlyTg1_u1_p2,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400304++0x01
line.word 0x00 "RxEnDlyTg2_u1_p2,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400306++0x01
line.word 0x00 "RxEnDlyTg3_u1_p2,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x400318++0x01
line.word 0x00 "RxClkDlyTg0_u1_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40031A++0x01
line.word 0x00 "RxClkDlyTg1_u1_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40031C++0x01
line.word 0x00 "RxClkDlyTg2_u1_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40031E++0x01
line.word 0x00 "RxClkDlyTg3_u1_p2,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400320++0x01
line.word 0x00 "RxClkcDlyTg0_u1_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400322++0x01
line.word 0x00 "RxClkcDlyTg1_u1_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400324++0x01
line.word 0x00 "RxClkcDlyTg2_u1_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400328++0x01
line.word 0x00 "RxClkcDlyTg3_u1_p2,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x400380++0x01
line.word 0x00 "TxDqDlyTg0_r1_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400382++0x01
line.word 0x00 "TxDqDlyTg1_r1_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400384++0x01
line.word 0x00 "TxDqDlyTg2_r1_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400386++0x01
line.word 0x00 "TxDqDlyTg3_r1_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x4003A0++0x01
line.word 0x00 "TxDqsDlyTg0_u1_p2,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x4003A2++0x01
line.word 0x00 "TxDqsDlyTg1_u1_p2,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x4003A4++0x01
line.word 0x00 "TxDqsDlyTg2_u1_p2,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x4003A6++0x01
line.word 0x00 "TxDqsDlyTg3_u1_p2,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
group.word 0x400580++0x01
line.word 0x00 "TxDqDlyTg0_r2_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400582++0x01
line.word 0x00 "TxDqDlyTg1_r2_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400584++0x01
line.word 0x00 "TxDqDlyTg2_r2_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400586++0x01
line.word 0x00 "TxDqDlyTg3_r2_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x400780++0x01
line.word 0x00 "TxDqDlyTg0_r3_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400782++0x01
line.word 0x00 "TxDqDlyTg1_r3_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400784++0x01
line.word 0x00 "TxDqDlyTg2_r3_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400786++0x01
line.word 0x00 "TxDqDlyTg3_r3_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x400980++0x01
line.word 0x00 "TxDqDlyTg0_r4_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400982++0x01
line.word 0x00 "TxDqDlyTg1_r4_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400984++0x01
line.word 0x00 "TxDqDlyTg2_r4_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400986++0x01
line.word 0x00 "TxDqDlyTg3_r4_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x400B80++0x01
line.word 0x00 "TxDqDlyTg0_r5_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400B82++0x01
line.word 0x00 "TxDqDlyTg1_r5_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400B84++0x01
line.word 0x00 "TxDqDlyTg2_r5_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400B86++0x01
line.word 0x00 "TxDqDlyTg3_r5_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x400D80++0x01
line.word 0x00 "TxDqDlyTg0_r6_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400D82++0x01
line.word 0x00 "TxDqDlyTg1_r6_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400D84++0x01
line.word 0x00 "TxDqDlyTg2_r6_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400D86++0x01
line.word 0x00 "TxDqDlyTg3_r6_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x400F80++0x01
line.word 0x00 "TxDqDlyTg0_r7_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x400F82++0x01
line.word 0x00 "TxDqDlyTg1_r7_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x400F84++0x01
line.word 0x00 "TxDqDlyTg2_r7_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x400F86++0x01
line.word 0x00 "TxDqDlyTg3_r7_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x401180++0x01
line.word 0x00 "TxDqDlyTg0_r8_p2,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x401182++0x01
line.word 0x00 "TxDqDlyTg1_r8_p2,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x401184++0x01
line.word 0x00 "TxDqDlyTg2_r8_p2,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x401186++0x01
line.word 0x00 "TxDqDlyTg3_r8_p2,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x600040++0x01
line.word 0x00 "DFIMRL_p3,DFI MaxReadLatency"
bitfld.word 0x00 0.--4. "DFIMRL_p3,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x600082++0x01
line.word 0x00 "TxImpedanceCtrl0_b0_p3,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600086++0x01
line.word 0x00 "DqDqsRcvCntrl_b0_p3,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
newline
bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x600090++0x01
line.word 0x00 "TxEqualizationMode_p3,Tx dq driver equalization mode controls"
bitfld.word 0x00 0.--1. "TxEqMode,no description available" "0,1,2,3"
group.word 0x600092++0x01
line.word 0x00 "TxImpedanceCtrl1_b0_p3,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600096++0x01
line.word 0x00 "TxImpedanceCtrl2_b0_p3,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600098++0x01
line.word 0x00 "DqDqsRcvCntrl2_p3,Dq/Dqs receiver control"
bitfld.word 0x00 0. "EnRxAgressivePDR,reserved" "0,1"
group.word 0x60009A++0x01
line.word 0x00 "TxOdtDrvStren_b0_p3,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x6000BE++0x01
line.word 0x00 "TxSlewRate_b0_p3,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x600100++0x01
line.word 0x00 "RxEnDlyTg0_u0_p3,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600102++0x01
line.word 0x00 "RxEnDlyTg1_u0_p3,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600104++0x01
line.word 0x00 "RxEnDlyTg2_u0_p3,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600106++0x01
line.word 0x00 "RxEnDlyTg3_u0_p3,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600118++0x01
line.word 0x00 "RxClkDlyTg0_u0_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60011A++0x01
line.word 0x00 "RxClkDlyTg1_u0_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60011C++0x01
line.word 0x00 "RxClkDlyTg2_u0_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60011E++0x01
line.word 0x00 "RxClkDlyTg3_u0_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600120++0x01
line.word 0x00 "RxClkcDlyTg0_u0_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600122++0x01
line.word 0x00 "RxClkcDlyTg1_u0_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600124++0x01
line.word 0x00 "RxClkcDlyTg2_u0_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600128++0x01
line.word 0x00 "RxClkcDlyTg3_u0_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60015C++0x01
line.word 0x00 "PptDqsCntInvTrnTg0_p3,DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation"
hexmask.word 0x00 0.--15. 1. "PptDqsCntInvTrnTg0_p3,Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation"
group.word 0x60015E++0x01
line.word 0x00 "PptDqsCntInvTrnTg1_p3,DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation"
hexmask.word 0x00 0.--15. 1. "PptDqsCntInvTrnTg1_p3,Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation"
group.word 0x600180++0x01
line.word 0x00 "TxDqDlyTg0_r0_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600182++0x01
line.word 0x00 "TxDqDlyTg1_r0_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600184++0x01
line.word 0x00 "TxDqDlyTg2_r0_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600186++0x01
line.word 0x00 "TxDqDlyTg3_r0_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x6001A0++0x01
line.word 0x00 "TxDqsDlyTg0_u0_p3,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x6001A2++0x01
line.word 0x00 "TxDqsDlyTg1_u0_p3,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x6001A4++0x01
line.word 0x00 "TxDqsDlyTg2_u0_p3,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x6001A6++0x01
line.word 0x00 "TxDqsDlyTg3_u0_p3,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
group.word 0x600282++0x01
line.word 0x00 "TxImpedanceCtrl0_b1_p3,Data TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600286++0x01
line.word 0x00 "DqDqsRcvCntrl_b1_p3,Dq/Dqs receiver control"
bitfld.word 0x00 7.--11. "GainCurrAdj,Adjust gain current of RX amplifier stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 4.--6. "MajorModeDbyte,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 2.--3. "DfeCtrl,DFE may be used with MajorModeDbyte=011 only" "0: DFE off,1: DFE on,2: Train DFE0 Amplifier,3: Train DFE1 Amplifier These"
bitfld.word 0x00 1. "ExtVrefRange,Extends the range available in the local per-bit VREF generator" "0,1"
newline
bitfld.word 0x00 0. "SelAnalogVref,Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers" "0,1"
group.word 0x600292++0x01
line.word 0x00 "TxImpedanceCtrl1_b1_p3,TX impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenFSDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenFSDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600296++0x01
line.word 0x00 "TxImpedanceCtrl2_b1_p3,TX equalization impedance controls"
bitfld.word 0x00 6.--11. "DrvStrenEQLoDqN,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull down output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "DrvStrenEQHiDqP,Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus used to select the target pull up output impedance used in equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60029A++0x01
line.word 0x00 "TxOdtDrvStren_b1_p3,TX ODT driver strength control"
bitfld.word 0x00 6.--11. "ODTStrenN,Selects the ODT pull-down impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "ODTStrenP,Selects the ODT pull-up impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x6002BE++0x01
line.word 0x00 "TxSlewRate_b1_p3,TX slew rate controls"
bitfld.word 0x00 8.--10. "TxPreDrvMode,Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4.--7. "TxPreN,4 bit binary trim for the driver pull down slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "TxPreP,4 bit binary trim for the driver pull up slew rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x600300++0x01
line.word 0x00 "RxEnDlyTg0_u1_p3,Trained Receive Enable Delay (For Timing Group 0)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg0_un_px,Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600302++0x01
line.word 0x00 "RxEnDlyTg1_u1_p3,Trained Receive Enable Delay (For Timing Group 1)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg1_un_px,Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600304++0x01
line.word 0x00 "RxEnDlyTg2_u1_p3,Trained Receive Enable Delay (For Timing Group 2)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg2_un_px,Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600306++0x01
line.word 0x00 "RxEnDlyTg3_u1_p3,Trained Receive Enable Delay (For Timing Group 3)"
hexmask.word 0x00 0.--10. 1. "RxEnDlyTg3_un_px,Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay from the memory-read command to the signal enabling the read DQS to generate read-data strobes"
group.word 0x600318++0x01
line.word 0x00 "RxClkDlyTg0_u1_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkDlyTg0_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60031A++0x01
line.word 0x00 "RxClkDlyTg1_u1_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=1)"
bitfld.word 0x00 0.--5. "RxClkDlyTg1_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60031C++0x01
line.word 0x00 "RxClkDlyTg2_u1_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkDlyTg2_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60031E++0x01
line.word 0x00 "RxClkDlyTg3_u1_p3,Trained Read DQS to RxClk Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkDlyTg3_un_px,Trained Read DQS to RxClk Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600320++0x01
line.word 0x00 "RxClkcDlyTg0_u1_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg0_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600322++0x01
line.word 0x00 "RxClkcDlyTg1_u1_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg1_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600324++0x01
line.word 0x00 "RxClkcDlyTg2_u1_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg2_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600328++0x01
line.word 0x00 "RxClkcDlyTg3_u1_p3,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)"
bitfld.word 0x00 0.--5. "RxClkcDlyTg3_un_px,Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x600380++0x01
line.word 0x00 "TxDqDlyTg0_r1_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600382++0x01
line.word 0x00 "TxDqDlyTg1_r1_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600384++0x01
line.word 0x00 "TxDqDlyTg2_r1_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600386++0x01
line.word 0x00 "TxDqDlyTg3_r1_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x6003A0++0x01
line.word 0x00 "TxDqsDlyTg0_u1_p3,Write DQS Delay (Timing Group DEST=0)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg0_un_px,Write DQS Delay (Timing Group DEST=0)"
group.word 0x6003A2++0x01
line.word 0x00 "TxDqsDlyTg1_u1_p3,Write DQS Delay (Timing Group DEST=1)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg1_un_px,Write DQS Delay (Timing Group DEST=1)"
group.word 0x6003A4++0x01
line.word 0x00 "TxDqsDlyTg2_u1_p3,Write DQS Delay (Timing Group DEST=2)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg2_un_px,Write DQS Delay (Timing Group DEST=2)"
group.word 0x6003A6++0x01
line.word 0x00 "TxDqsDlyTg3_u1_p3,Write DQS Delay (Timing Group DEST=3)"
hexmask.word 0x00 0.--9. 1. "TxDqsDlyTg3_un_px,Write DQS Delay (Timing Group DEST=3)"
group.word 0x600580++0x01
line.word 0x00 "TxDqDlyTg0_r2_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600582++0x01
line.word 0x00 "TxDqDlyTg1_r2_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600584++0x01
line.word 0x00 "TxDqDlyTg2_r2_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600586++0x01
line.word 0x00 "TxDqDlyTg3_r2_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x600780++0x01
line.word 0x00 "TxDqDlyTg0_r3_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600782++0x01
line.word 0x00 "TxDqDlyTg1_r3_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600784++0x01
line.word 0x00 "TxDqDlyTg2_r3_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600786++0x01
line.word 0x00 "TxDqDlyTg3_r3_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x600980++0x01
line.word 0x00 "TxDqDlyTg0_r4_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600982++0x01
line.word 0x00 "TxDqDlyTg1_r4_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600984++0x01
line.word 0x00 "TxDqDlyTg2_r4_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600986++0x01
line.word 0x00 "TxDqDlyTg3_r4_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x600B80++0x01
line.word 0x00 "TxDqDlyTg0_r5_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600B82++0x01
line.word 0x00 "TxDqDlyTg1_r5_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600B84++0x01
line.word 0x00 "TxDqDlyTg2_r5_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600B86++0x01
line.word 0x00 "TxDqDlyTg3_r5_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x600D80++0x01
line.word 0x00 "TxDqDlyTg0_r6_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600D82++0x01
line.word 0x00 "TxDqDlyTg1_r6_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600D84++0x01
line.word 0x00 "TxDqDlyTg2_r6_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600D86++0x01
line.word 0x00 "TxDqDlyTg3_r6_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x600F80++0x01
line.word 0x00 "TxDqDlyTg0_r7_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x600F82++0x01
line.word 0x00 "TxDqDlyTg1_r7_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x600F84++0x01
line.word 0x00 "TxDqDlyTg2_r7_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x600F86++0x01
line.word 0x00 "TxDqDlyTg3_r7_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
group.word 0x601180++0x01
line.word 0x00 "TxDqDlyTg0_r8_p3,Write DQ Delay (Timing Group 0)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg0_rn_px,Write DQ Delay (Timing Group 0)"
group.word 0x601182++0x01
line.word 0x00 "TxDqDlyTg1_r8_p3,Write DQ Delay (Timing Group 1)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg1_rn_px,Write DQ Delay (Timing Group 1)"
group.word 0x601184++0x01
line.word 0x00 "TxDqDlyTg2_r8_p3,Write DQ Delay (Timing Group 2)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg2_rn_px,Write DQ Delay (Timing Group 2)"
group.word 0x601186++0x01
line.word 0x00 "TxDqDlyTg3_r8_p3,Write DQ Delay (Timing Group 3)"
hexmask.word 0x00 0.--8. 1. "TxDqDlyTg3_rn_px,Write DQ Delay (Timing Group 3)"
tree.end
repeat.end
tree.end
tree "DWC_DDRPHYA_DRTUB"
base ad:0x3C0C0000
group.word 0x100++0x01
line.word 0x00 "UcclkHclkEnables,Ucclk and Hclk enables"
bitfld.word 0x00 1. "HclkEn,When training has completed (and assuming no further need for the training hardware) the enable should be set to 0 to reduce power" "0,1"
bitfld.word 0x00 0. "UcclkEn,When training has completed (and assuming no further need for the microcontroller) the enable should be set to 0 to reduce power" "0,1"
group.word 0x102++0x01
line.word 0x00 "CurPstate0b,PIE current Pstate value"
bitfld.word 0x00 0.--3. "CurPstate0b,PIE current Pstate value This register is used to select values for writing by the Pstate sequencer and is written in the beginning of the Pstate switch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.word 0x1DA++0x01
line.word 0x00 "CUSTPUBREV,Customer settable by the customer"
bitfld.word 0x00 0.--5. "CUSTPUBREV,The customer settable PUB version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x1DC++0x01
line.word 0x00 "PUBREV,The hardware version of this PUB excluding the PHY"
hexmask.word.byte 0x00 8.--15. 1. "PUBMJR,Indicates major revision of the PUB"
bitfld.word 0x00 4.--7. "PUBMDR,Indicates moderate revision of the PUB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "PUBMNR,Indicates minor update of the PUB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "DWC_DDRPHYA_INITENG"
base ad:0x3C090000
group.word 0x50++0x01
line.word 0x00 "PhyInLP3,Indicator for PIE Lower Power 3 (LP3) Status"
bitfld.word 0x00 0. "PhyInLP3,Read Only" "0,1"
tree.end
tree "DWC_DDRPHYA_MASTER"
base ad:0x3C020000
group.word 0x00++0x01
line.word 0x00 "RxFifoInit,Rx FIFO pointer initialization control"
bitfld.word 0x00 1. "InhibitRxFifoRd,This field is reserved for training FW use" "0,1"
newline
bitfld.word 0x00 0. "RxFifoInitPtr,Setting this bit will reset the PHY RXDATAFIFO read and write pointers" "0,1"
group.word 0x02++0x01
line.word 0x00 "ForceClkDisable,Clock gating control"
bitfld.word 0x00 0.--3. "ForceClkDisable,This CSR forces the gating of MEMCLKs driven from the PHY ForceClkDisable[0] - controls CLK_H/L0 ForceClkDisable[1] - controls CLK_H/L1 (if present) ForceClkDisable[2] - controls CLK_H/L2 (if present) ForceClkDisable[3] - controls.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x06++0x01
line.word 0x00 "ForceInternalUpdate,This Register used by Training Firmware to force an internal PHY Update Event"
bitfld.word 0x00 0. "ForceInternalUpdate,This Register is used by Training Firmware to force an internal PHY Update Event" "0,1"
rgroup.word 0x08++0x01
line.word 0x00 "PhyConfig,Read Only displays PHY Configuration"
bitfld.word 0x00 8.--9. "PhyConfigDfi,Returns the following value" "0,1,2,3"
newline
bitfld.word 0x00 4.--7. "PhyConfigDbytes,Returns the following value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "PhyConfigAnibs,Returns the following value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x0A++0x01
line.word 0x00 "PGCR,PHY General Configuration Register(PGCR)"
bitfld.word 0x00 0. "RxClkRiseFallMode,This register field controls independent training for RxClk_c and RxClk_t" "0,1"
group.word 0x0E++0x01
line.word 0x00 "TestBumpCntrl1,Test Bump Control1"
bitfld.word 0x00 15. "TestPowerGateEn,Do not use for debug only" "0,1"
newline
bitfld.word 0x00 14. "TestExtVrefRange,Setting this bit will extend the VREF DAC range for debug" "0,1"
newline
bitfld.word 0x00 13. "TestSelExternalVref,Do not use for debug only" "0,1"
newline
bitfld.word 0x00 8.--12. "TestGainCurrAdj,Adjust gain and current of analog observe RX amplifier stage at analog test point Recommended mission mode default = 5'b01011" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 4.--7. "TestAnalogOutCtrl,Select receiver internal analog signals to monitor at analog test point 0xxx: AnalogTestOut=HiZ" "?,?,?,?,?,?,?,?,8: AnalogTestOut=VSS,9: AnalogTestOut=vref_dfe0 -- observe by sweeping,10: AnalogTestOut=vref_dfe1 -- observe by sweeping,11: AnalogTestOut=VSS,12: AnalogTestOut=vstg2,13: AnalogTestOut=vcasc_cs1,14: AnalogTestOut=vbias_cs1 Recommended mission..,?..."
newline
bitfld.word 0x00 3. "TestBiasBypassEn,Do not use for debug only" "0,1"
newline
bitfld.word 0x00 0.--2. "TestMajorMode,Selects the major mode of operation for the receiver" "0,1,2,3,4,5,6,7"
group.word 0x10++0x01
line.word 0x00 "CalUclkInfo_p0,Impedance Calibration Clock Ratio"
hexmask.word 0x00 0.--9. 1. "CalUClkTicksPer1uS,Must be programmed to the number of DfiClks in 1us (rounded up) with minimum value of 24"
group.word 0x14++0x01
line.word 0x00 "TestBumpCntrl,Test Bump Control"
bitfld.word 0x00 9. "ForceMtestOnAlert,When set causes the Digital Observation output pin to be driven onto BP_ALERT_N" "0,1"
newline
bitfld.word 0x00 3.--8. "TestBumpDataSel,RVSD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 2. "TestBumpToggle,This field controls the output function of the signal Digital Observation Pin if available in the configuration of the PHY" "0,1"
newline
bitfld.word 0x00 0.--1. "TestBumpEn,Field TestBumpEn[1:0] controls the output function of: the signal BP_ALERT_N" "0,1,2,3"
group.word 0x16++0x01
line.word 0x00 "Seq0BDLY0_p0,PHY Initialization Engine (PIE) Delay Register 0"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY0_p0,PHY Initialization Engine (PIE) Delay Register 0 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x18++0x01
line.word 0x00 "Seq0BDLY1_p0,PHY Initialization Engine (PIE) Delay Register 1"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY1_p0,PHY Initialization Engine (PIE) Delay Register 1 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x1A++0x01
line.word 0x00 "Seq0BDLY2_p0,PHY Initialization Engine (PIE) Delay Register 2"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY2_p0,PHY Initialization Engine (PIE) Delay Register 2 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x1C++0x01
line.word 0x00 "Seq0BDLY3_p0,PHY Initialization Engine (PIE) Delay Register 3"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY3_p0,PHY Initialization Engine (PIE) Delay Register 3 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
rgroup.word 0x1E++0x01
line.word 0x00 "PhyAlertStatus,PHY Alert status bit"
bitfld.word 0x00 0. "PhyAlert,Current state of ALERT_N" "0,1"
group.word 0x20++0x01
line.word 0x00 "PPTTrainSetup_p0,Setup Intervals for DFI PHY Master operations"
bitfld.word 0x00 4.--6. "PhyMstrMaxReqToAck,Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 0.--3. "PhyMstrTrainInterval,Bits 3:0 of this register specifies the time between the end of one training and the start of the next" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x24++0x01
line.word 0x00 "ATestMode,ATestMode control"
bitfld.word 0x00 2.--4. "ATestModeSel,Master Mode select for ATest (Loopback)" "0: Mission mode all ATest disabled loopback,1: External Loopback mode [Single data rate..,2: Internal Loopback mode [Single data rate..,3: Internal Loopback mode [Double data rate..,4: External Loopback mode [Single data rate..,?..."
newline
bitfld.word 0x00 1. "ATestClkEn,Enables the clock for loopback PRBS7 testing for all BP_A* pins" "0,1"
newline
bitfld.word 0x00 0. "ATestPrbsEn,Enables loopback PRBS7 testing of all the DDR output pins in this chiplet" "0,1"
rgroup.word 0x28++0x01
line.word 0x00 "TxCalBinP,TX P Impedance Calibration observation"
bitfld.word 0x00 0.--4. "TxCalBinP,This csr holds the binary result of the 31 bit thermometer pullup code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.word 0x2A++0x01
line.word 0x00 "TxCalBinN,TX N Impedance Calibration observation"
bitfld.word 0x00 0.--4. "TxCalBinN,This csr holds the binary result of the 31 bit thermometer pulldown code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2C++0x01
line.word 0x00 "TxCalPOvr,TX P Impedance Calibration override"
bitfld.word 0x00 5. "TxCalBinPOvrEn," "0,1"
newline
bitfld.word 0x00 0.--4. "TxCalBinPOvrVal,The binary value which can overide the Register TxCalBinP calibrator results if Register TxCalBinPOvrEn is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2E++0x01
line.word 0x00 "TxCalNOvr,TX N Impedance Calibration override"
bitfld.word 0x00 5. "TxCalBinNOvrEn," "0,1"
newline
bitfld.word 0x00 0.--4. "TxCalBinNOvrVal,The binary value which can overide the Register TxCalBinN calibrator results if Register TxCalBinPOvrEn is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x30++0x01
line.word 0x00 "DfiMode,Enables for update and low-power interfaces for DFI0 and DFI1"
bitfld.word 0x00 2. "Dfi1Override,DFI0 is used to control the PHY logic associated with both DFI0 and DFI1" "0,1"
newline
bitfld.word 0x00 1. "Dfi1Enable,Enables operation for the PHY logic associated with DFI1" "0,1"
newline
bitfld.word 0x00 0. "Dfi0Enable,Enables operation for the PHY logic associated with DFI0" "0,1"
group.word 0x32++0x01
line.word 0x00 "TristateModeCA_p0,Mode select register for MEMCLK/Address/Command Tristates"
bitfld.word 0x00 2.--3. "CkDisVal,The PHY provides 4 memory clocks n=0" "0,1,2,3"
newline
bitfld.word 0x00 1. "DDR2TMode,Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode" "0,1"
newline
bitfld.word 0x00 0. "DisDynAdrTri,When DisDynAdrTri=1 Dynamic Tristating is disabled" "0,1"
group.word 0x34++0x01
line.word 0x00 "MtestMuxSel,Digital Observation Pin control"
bitfld.word 0x00 0.--5. "MtestMuxSel,Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x36++0x01
line.word 0x00 "MtestPgmInfo,Digital Observation Pin program info for debug"
bitfld.word 0x00 0. "MtestPgmInfo,The value of this csr may be driven onto the Digital Observation Pin" "0,1"
group.word 0x38++0x01
line.word 0x00 "DynPwrDnUp,Dynaimc Power Up/Down control"
bitfld.word 0x00 0. "DynPowerDown," "0,1"
group.word 0x3C++0x01
line.word 0x00 "PhyTID,PHY Technology ID Register"
hexmask.word 0x00 0.--15. 1. "PhyTID,This register is a placeholder to store technology-specific information"
group.word 0x40++0x01
line.word 0x00 "HwtMRL_p0,HWT MaxReadLatency"
bitfld.word 0x00 0.--4. "HwtMRL_p0,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x42++0x01
line.word 0x00 "DFIPHYUPD,DFI PhyUpdate Request time counter (in MEMCLKs)"
bitfld.word 0x00 12.--15. "DFIPHYUPDINTTHRESHOLD,This subfield is similar to DFIPHYUPDTHRESHOLD except that rather than affecting the Phy Update request it affects only the threshold used to generate the VT Drift Alarm Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 8.--11. "DFIPHYUPDTHRESHOLD,4'h0 Disable Threshold-based Phy Update Requests when DFIPHYUPDMODE==1'b1 Nonzero codes are the threshold value for the change in the master LCDL 1UI phase code since the last Phy Update Request that will trigger a new Phy Update.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 7. "DFIPHYUPDMODE,1'b0 [Default] deterministic timer-based Phy Update Requests enables multi-channel/multi-phy lockstep operation" "0,1"
newline
bitfld.word 0x00 4.--6. "DFIPHYUPDRESP,Enforces the t_phyupd_resp time the maximum time that is allowed to controller to respond to the request for a PHY update" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 0.--3. "DFIPHYUPDCNT,This controls the interval between the end of a phyupdate transaction and a subsequent request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x44++0x01
line.word 0x00 "PdaMrsWriteMode,Controls the write DQ generation for Per-Dram-Addressing of MRS"
bitfld.word 0x00 0. "PdaMrsWriteMode,Controls the write DQ generation per the timing requirements on the DQ signals used for Per-Dram-Addressing mode of MRS commands" "0,1"
group.word 0x46++0x01
line.word 0x00 "DFIGEARDOWNCTL,Controls whether dfi_geardown_en will cause CS and CKE timing to change"
bitfld.word 0x00 0.--1. "DFIGEARDOWNCTL,DFIGEARDOWNCTL[0] controls whether dfi_geardown_en will cause chip-select (CS) timing to change" "0,1,2,3"
group.word 0x48++0x01
line.word 0x00 "DqsPreambleControl_p0,Control the PHY logic related to the read and write DQS preamble"
bitfld.word 0x00 8. "WDQSEXTENSION,When set DQS_T and DQS_C will be driven differentially to 0 and 1 respectively before and after a write burst except during a memory read transaction" "0,1"
newline
bitfld.word 0x00 7. "LP4SttcPreBridgeRxEn,Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads to the same timing group when the bubble is 1 memclk" "0,1"
newline
bitfld.word 0x00 6. "LP4PostambleExt,In LPDDR4 mode must be set to extend the write postamble" "0,1"
newline
bitfld.word 0x00 5. "LP4TglTwoTckTxDqsPre,Used in LPDDR4 mode to modify the early preamble when Register TwoTckTxDqsPre=1" "0: level first-memclk preamble,1: toggling first-memclk preamble"
newline
bitfld.word 0x00 2.--4. "PositionDfeInit,For DDR4 phy only when receive DFE is enabled" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 1. "TwoTckTxDqsPre," "0,1"
newline
bitfld.word 0x00 0. "TwoTckRxDqsPre,Widens the RxDqsEn window to allow larger drift in the incoming read DQS to take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read.." "0,1"
group.word 0x4A++0x01
line.word 0x00 "MasterX4Config,DBYTE module controls to select X4 Dram device mode"
bitfld.word 0x00 0.--3. "X4TG,Set to 1 if this Timing Group/Rank is x4 (as opposed to x8) memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4C++0x01
line.word 0x00 "WrLevBits,Write level feedback DQ observability select"
bitfld.word 0x00 4.--7. "WrLevForDQSU,Indicates which DQ bit is used for Write Levelization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "WrLevForDQSL,Indicates which DQ bit is used for Write Levelization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4E++0x01
line.word 0x00 "EnableCsMulticast,In DDR4 Mode this controls whether CS_N[3:2] should be multicast on CID[1:0]"
bitfld.word 0x00 0. "EnableCsMulticast,In DDR4 Mode this controls whether CS_N[3:2] should be multicast on CID[1:0]" "0: Do not override pins corresponding to cid[1:0],1: Overrirde pins corresponding to cid[1:0] with"
group.word 0x50++0x01
line.word 0x00 "HwtLpCsMultiCast,Drives cs_n[0] onto cs_n[1] during training"
bitfld.word 0x00 0. "HwtLpCsMultiCast,When set drives cs_n[0] onto cs_n[1] during training" "0,1"
group.word 0x58++0x01
line.word 0x00 "Acx4AnibDis,Disable for unused ACX Nibbles"
hexmask.word 0x00 0.--11. 1. "Acx4AnibDis,When a bit is set the corresponding ACX nibble is disabled (specifically the I/O OE is disabled as is the Dfi-side FIFO clock"
group.word 0x5A++0x01
line.word 0x00 "DMIPinPresent_p0,This Register is used to enable the Read-DBI function in each DBYTE"
bitfld.word 0x00 0. "RdDbiEnabled,This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device" "0,1"
group.word 0x5C++0x01
line.word 0x00 "ARdPtrInitVal_p0,Address/Command FIFO ReadPointer Initial Value"
bitfld.word 0x00 0.--3. "ARdPtrInitVal_p0,This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x74++0x01
line.word 0x00 "DbyteDllModeCntrl,DLL Mode control CSR for DBYTEs"
bitfld.word 0x00 1. "DllRxPreambleMode,Must be set to 1 if read DQS preamble contains a toggle for example DDR4 or LPDDR4 read toggling preambe mode" "0,1"
group.word 0x8A++0x01
line.word 0x00 "CalOffsets,Impedance Calibration offsets control"
bitfld.word 0x00 10.--13. "CalDrvPuThOffset,This value adjusts the driver pullup calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 6.--9. "CalDrvPdThOffset,This value adjusts the driver pulldown calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--5. "CalCmpr5Offset,This value adjusts the offset-compensated DAC code for the cmpana circuit at VRef == 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x8E++0x01
line.word 0x00 "SarInitVals,Sar Init Vals"
bitfld.word 0x00 6.--8. "SarInitPEXT,Specify the SAR starting value for PEXT calibration" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. "SarInitNINT,Specify the SAR starting value for NINT calibration" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. "SarInitOFFSET05,Specify the SAR starting value for OFFSET05 calibration" "0,1,2,3,4,5,6,7"
group.word 0x92++0x01
line.word 0x00 "CalPExtOvr,Impedance Calibration PExt Override control"
bitfld.word 0x00 0.--4. "CalPExtOvr,If the CSR CalPExtDis is set then the value provided here by software will be used instead of the automatically generated value which is visible via CSR CalPExt This CSR may only be written when the calibrator is not running" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x94++0x01
line.word 0x00 "CalCmpr5Ovr,Impedance Calibration Cmpr 50 control"
hexmask.word.byte 0x00 0.--7. 1. "CalCmpr5Ovr,If the CSR CalCmpr5Dis is set then the value provided here by software will be used instead of the automatically generated value which is visible via CSR CalCmpr5 This CSR may only be written when the calibrator is not running"
group.word 0x96++0x01
line.word 0x00 "CalNIntOvr,Impedance Calibration NInt Override control"
bitfld.word 0x00 0.--4. "CalNIntOvr,If the CSR CalNIntDis is set then the value provided here by software will be used instead of the automatically generated value which is visible via CSR CalNInt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0xA0++0x01
line.word 0x00 "CalDrvStr0,Impedance Calibration driver strength control"
bitfld.word 0x00 4.--7. "CalDrvStrPu50,3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "CalDrvStrPd50,3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xAC++0x01
line.word 0x00 "ProcOdtTimeCtl_p0,READ DATA On-Die Termination Timing Control (by PHY)"
bitfld.word 0x00 2.--3. "POdtStartDelay,controls the start of ProcOdt units of UI 3 delay start 2 UI maximum delay of start of ProcOdt 2 delay start 1 UI 1 delay start 0 UI default 0 early by 1 UI The time from ProcODT assertion to opening the window to receive DQS is (10 -.." "0,1,2,3"
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bitfld.word 0x00 0.--1. "POdtTailWidth,controls the length of the tail of ProcOdt units of UI 3 tail 3UI more than for Register POdtTailWidth=0 maximum 2 tail 2UI more than for Register POdtTailWidth=0 default 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length.." "0,1,2,3"
group.word 0xB6++0x01
line.word 0x00 "MemAlertControl,This Register is used to configure the MemAlert Receiver"
bitfld.word 0x00 15. "MALERTForceError,When MALERTForceError is set this CSR state is used to force parity error to memory" "0,1"
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bitfld.word 0x00 14. "MALERTDisableVal,When MALERTRxEn is not set this CSR state is used to drive dfi_alert_n" "0,1"
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bitfld.word 0x00 13. "MALERTRxEn," "0,1"
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bitfld.word 0x00 12. "MALERTPuEn,When set enables the Pull-up termination on MALERT" "0,1"
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bitfld.word 0x00 8.--11. "MALERTPuStren,Controls the Pull-up termination on MALERT ========================================== bit[8] - controls a 240 Ohm Pull-up leg bit[9] - controls a 240 Ohm Pull-up leg bit[10] - controls a 120 Ohm Pull-up leg bit[11] - controls a 120 Ohm.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 7. "MALERTVrefExtEn,When set for test/debug selects external Vref source This should not be set in mission mode" "0,1"
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hexmask.word.byte 0x00 0.--6. 1. "MALERTVrefLevel,Sets the vref level of internal VREF DAC"
group.word 0xB8++0x01
line.word 0x00 "MemAlertControl2,This Register is used to configure the MemAlert Receiver"
bitfld.word 0x00 0. "MALERTSyncBypass,MALERTSyncBypass==[0] the phy will drive dfi_alert_n with a synchronized value of the ALERT_N receiver" "0,1"
group.word 0xC0++0x01
line.word 0x00 "MemResetL,Protection and control of BP_MemReset_L"
bitfld.word 0x00 1. "ProtectMemReset,Control the MemResetL output of the PHY" "0,1"
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bitfld.word 0x00 0. "MemResetLValue,Control the MemResetL output of the PHY" "0,1"
group.word 0xDA++0x01
line.word 0x00 "DriveCSLowOntoHigh,Drive CS_N 3:0 onto CS_N 7:4"
bitfld.word 0x00 0. "CsLowOntoHigh,When this is set to a 1 CS[3:0] from the ACSM are driven to CS[7:4] pins and CS[3:0] are deasserted" "0,1"
group.word 0xDC++0x01
line.word 0x00 "PUBMODE,PUBMODE - HWT Mux Select"
bitfld.word 0x00 0. "HwtMemSrc,When this is set to a 1 the mux that switches between DCT and HWT for the source of memory transactions is switched to HWT" "0,1"
rgroup.word 0xDE++0x01
line.word 0x00 "MiscPhyStatus,Misc PHY status bits"
bitfld.word 0x00 1. "PORMemReset,Returns the active-high value used by the custom circuit which drives the memory RESET signal" "0,1"
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bitfld.word 0x00 0. "DctSane,Returns the status of the custom circuit which protects the MemResetL output of the PHY on initial power-on or reset" "0,1"
group.word 0xE0++0x01
line.word 0x00 "CoreLoopbackSel,Controls whether the loopback path bypasses the final PAD node"
bitfld.word 0x00 0. "CoreLoopbackSel,This register is controlled by the PHY test firmware This register enables Core-Side loopback operation of the PHY" "0,1"
group.word 0xE2++0x01
line.word 0x00 "DllTrainParam,DLL Various Training Parameters"
bitfld.word 0x00 0.--1. "ExtendPhdTime,Used by the PHY firmware locking the LCDL delay cells" "0,1,2,3"
group.word 0xE8++0x01
line.word 0x00 "HwtLpCsEnBypass,CSn Disable Bypass for LPDDR3/4"
bitfld.word 0x00 0. "HwtLpCsEnBypass,When set these bits disable LpCsEn function for LPDDR3/4" "0,1"
group.word 0xEA++0x01
line.word 0x00 "DfiCAMode,Dfi Command/Address Mode"
bitfld.word 0x00 3. "DfiD4AltCAMode,Enable D4-Alt Mode" "0: D4-Altmode disabled,1: D4-Altmode enabled"
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bitfld.word 0x00 2. "DfiLp4CAMode,Enable LP4 Mode" "0: LP4 mode disabled,1: LP4 mode enabled"
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bitfld.word 0x00 1. "DfiD4CAMode,Enable D4 Mode" "0: D4 mode disabled,1: D4 mode enabled"
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bitfld.word 0x00 0. "DfiLp3CAMode,Controls the output data-rate of the AC module Command/Address pins" "0: LP3 DDR address mode disabled,1: LP3 DDR address mode enabled"
group.word 0xF0++0x01
line.word 0x00 "DllControl,DLL Lock State machine control register"
bitfld.word 0x00 2. "DllResetRSVD,RSVD for future use" "0,1"
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bitfld.word 0x00 1. "DllResetSlave,Reserved" "0,1"
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bitfld.word 0x00 0. "DllResetRelock,Used to reset the DDL/LCDL lock state machine Deasserting starts locking sequence" "0,1"
group.word 0xF2++0x01
line.word 0x00 "PulseDllUpdatePhase,DLL update phase control"
bitfld.word 0x00 7. "AlwaysUpdateLcdlPhase,Causes each new operation to reload the LcdlPhase will increase bubbles" "0,1"
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bitfld.word 0x00 6. "TrainUpdatePhaseOnLongBubble,Causes LongBubble to update the dbyte & anib LDCL Phase" "0,1"
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bitfld.word 0x00 3.--5. "UpdatePhaseDestReserved,reserved not used" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 2. "PulseACaDllUpdatePhase,Causes an AC module CA (command/address/cke/odt) DLL phase update" "0,1"
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bitfld.word 0x00 1. "PulseACkDllUpdatePhase,Causes an AC module CK (memck) DLL phase update" "0,1"
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bitfld.word 0x00 0. "PulseDbyteDllUpdatePhase,Causes a LongBubble to the DBYTE modules which causes a update of the DBYTE module DLLs (tx rxen rxclk)" "0,1"
group.word 0xF8++0x01
line.word 0x00 "DllGainCtl_p0,DLL gain control"
bitfld.word 0x00 8.--11. "DllSeedSel,Reserved must be configured to be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DllGainTV,Terminal value of DllGain ie the value in effect when locking is done and the value used for maintaining lock ie tracking pclk variation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DllGainIV,Initial value of DllGain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x110++0x01
line.word 0x00 "CalRate,Impedance Calibration Control"
bitfld.word 0x00 6. "DisableBackgroundZQUpdates," "0,1"
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bitfld.word 0x00 5. "CalOnce,The setting of this CSR changes the behaviour of CSR CalRun" "0,1"
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bitfld.word 0x00 4. "CalRun," "0,1"
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bitfld.word 0x00 0.--3. "CalInterval,This CSR specifies the interval between successive calibrations in mS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x112++0x01
line.word 0x00 "CalZap,Impedance Calibration Zap/Reset"
bitfld.word 0x00 0. "CalZap,NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten" "0,1"
group.word 0x116++0x01
line.word 0x00 "PState,PSTATE Selection"
bitfld.word 0x00 0.--3. "PState,NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x11A++0x01
line.word 0x00 "PllOutGateControl,PLL Output Control"
bitfld.word 0x00 0. "PclkGateEn,Reserved" "0,1"
group.word 0x120++0x01
line.word 0x00 "PorControl,PMU Power-on Reset Control (PLL/DLL Lock Done)"
bitfld.word 0x00 0. "PllDllLockDone,Set by the PIE to 1 after it has finished the PLL/DLL lock sequence" "0,1"
rgroup.word 0x12E++0x01
line.word 0x00 "CalBusy,Impedance Calibration Busy Status"
bitfld.word 0x00 0. "CalBusy,Read 1 if the calibrator is actively calibrating" "0,1"
group.word 0x130++0x01
line.word 0x00 "CalMisc2,Miscellaneous impedance calibration controls"
bitfld.word 0x00 14. "CalSlowCmpana,When set this CSR increases the time allowed for the cmpana cell to settle by 50%" "0,1"
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bitfld.word 0x00 13. "CalCancelRoundErrDis,The PEXT calibration result and NINT calibration results naturally include a rounding error which manifests as a change of impedance at the pad" "0,1"
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bitfld.word 0x00 12. "CalCmptrResTrim,Reserved for future use" "0,1"
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bitfld.word 0x00 0.--2. "CalNumVotes,This CSR controls the number of consecutive comparator output bits over which majority voting is done" "0,1,2,3,4,5,6,7"
group.word 0x134++0x01
line.word 0x00 "CalMisc,Controls for disabling the impedance calibration of certain targets"
bitfld.word 0x00 2. "CalPExtDis,Setting this CSR prevents the calibration engine from overwriting the CSRs TxCalBinP and TxCalThP with an automatically generated value in which case a value must be supplied by software" "0,1"
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bitfld.word 0x00 1. "CalNIntDis,Setting this CSR prevents the calibration engine from overwriting the CSRs TxCalBinN and TxCalThN with an automatically generated value in which case a value must be supplied by software" "0,1"
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bitfld.word 0x00 0. "CalCmpr5Dis,Setting this CSR prevents the calibration engine from using the result from the CalCmpr5 stage of calibration" "0,1"
rgroup.word 0x136++0x01
line.word 0x00 "CalVRefs,no description available"
bitfld.word 0x00 0.--1. "CalVRefs,This CSR drives the Cmpdig_CalRef pin of the cmpana cell at various stages of calibration" "0,1,2,3"
rgroup.word 0x138++0x01
line.word 0x00 "CalCmpr5,Impedance Calibration Cmpr control"
hexmask.word.byte 0x00 0.--7. 1. "CalCmpr5,Returns the offset-compensated DAC code for the cmpana circuit at VRef == 0"
rgroup.word 0x13A++0x01
line.word 0x00 "CalNInt,Impedance Calibration NInt control"
bitfld.word 0x00 0.--4. "CalNIntThB,The value here is the number of thermometer bits which are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.word 0x13C++0x01
line.word 0x00 "CalPExt,Impedance Calibration PExt control"
bitfld.word 0x00 0.--4. "CalPExtThB,The value here is the number of thermometer bits which are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x150++0x01
line.word 0x00 "CalCmpInvert,Impedance Calibration Cmp Invert control"
bitfld.word 0x00 4. "CmpInvertCalOdtPu,Impedance Calibration Cmp Invert control" "0,1"
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bitfld.word 0x00 3. "CmpInvertCalOdtPd,Impedance Calibration Cmp Invert control" "0,1"
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bitfld.word 0x00 2. "CmpInvertCalDrvPu50,Impedance Calibration Cmp Invert control" "0,1"
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bitfld.word 0x00 1. "CmpInvertCalDrvPd50,Impedance Calibration Cmp Invert control" "0,1"
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bitfld.word 0x00 0. "CmpInvertCalDac50,Impedance Calibration Cmp Invert control" "0,1"
group.word 0x15C++0x01
line.word 0x00 "CalCmpanaCntrl,Impedance Calibration Cmpana control"
bitfld.word 0x00 9. "CmprBiasBypassEn,Impedance Calibration Cmpana control" "0,1"
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bitfld.word 0x00 8. "CmprGainResAdj,Impedance Calibration Cmpana control" "0,1"
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hexmask.word.byte 0x00 0.--7. 1. "CmprGainCurrAdj,Impedance Calibration Cmpana control"
group.word 0x160++0x01
line.word 0x00 "DfiRdDataCsDestMap_p0,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiRdDestm3,Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example if 3 dfi_rddata_cs_n_p0[3] will use Register RxEn ClkDlyTg3 timing" "0,1,2,3"
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bitfld.word 0x00 4.--5. "DfiRdDestm2,Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example if 2 dfi_rddata_cs_n_p0[2] will use Register RxEn ClkDlyTg2 timing" "0,1,2,3"
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bitfld.word 0x00 2.--3. "DfiRdDestm1,Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example if 1 dfi_rddata_cs_n[_p01] will use Register RxEn ClkDlyTg1 timing" "0,1,2,3"
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bitfld.word 0x00 0.--1. "DfiRdDestm0,Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example if 0 dfi_rddata_cs_n_p0[0] will use Register RxEn ClkDlyTg0 timing" "0,1,2,3"
group.word 0x164++0x01
line.word 0x00 "VrefInGlobal_p0,PHY Global Vref Controls"
bitfld.word 0x00 14. "GlobalVrefInMode,RSVD" "0,1"
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bitfld.word 0x00 10.--13. "GlobalVrefInTrim,RSVD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.word.byte 0x00 3.--9. 1. "GlobalVrefInDAC,DAC code for internal Vref generation The DAC has two ranges the range is set by GlobalVrefInSel[2] ========================================================== RANGE0 : DDR3 DDR4 LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage =.."
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bitfld.word 0x00 0.--2. "GlobalVrefInSel,GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin ==========================================================" "0: PHY Vref DAC Range0 -- BP_VREF = Hi-Z,1: Reserved Encoding,2: PHY Vref DAC Range0 -- BP_VREF connected to PLL,3: PHY Vref DAC Range0 -- BP_VREF connected to PHY,?..."
group.word 0x168++0x01
line.word 0x00 "DfiWrDataCsDestMap_p0,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiWrDestm3,Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register TxDq DqsDlyTg3) For example if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg3 timing" "0,1,2,3"
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bitfld.word 0x00 4.--5. "DfiWrDestm2,Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example if 2 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg2 timing" "0,1,2,3"
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bitfld.word 0x00 2.--3. "DfiWrDestm1,Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example if 1 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg1 timing" "0,1,2,3"
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bitfld.word 0x00 0.--1. "DfiWrDestm0,Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example if 0 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg0 timing" "0,1,2,3"
rgroup.word 0x16A++0x01
line.word 0x00 "MasUpdGoodCtr,Counts successful PHY Master Interface Updates (PPTs)"
hexmask.word 0x00 0.--15. 1. "MasUpdGoodCtr,This register increments whenever the Memory Controller acknowledges a PHY Master Interface request (i"
rgroup.word 0x16C++0x01
line.word 0x00 "PhyUpd0GoodCtr,Counts successful PHY-initiated DFI0 Interface Updates"
hexmask.word 0x00 0.--15. 1. "PhyUpd0GoodCtr,This register increments whenever the Memory Controller acknowledges a PHY-initiated DFI0 interface update request"
rgroup.word 0x16E++0x01
line.word 0x00 "PhyUpd1GoodCtr,Counts successful PHY-initiated DFI1 Interface Updates"
hexmask.word 0x00 0.--15. 1. "PhyUpd1GoodCtr,This register increments whenever the Memory Controller acknowledges a PHY-initiated DFI1 interface update request"
rgroup.word 0x170++0x01
line.word 0x00 "CtlUpd0GoodCtr,Counts successful Memory Controller DFI0 Interface Updates"
hexmask.word 0x00 0.--15. 1. "CtlUpd0GoodCtr,This register increments whenever the PHY acknowledges a Memory Controller-initiated DFI0 interface update request"
rgroup.word 0x172++0x01
line.word 0x00 "CtlUpd1GoodCtr,Counts successful Memory Controller DFI1 Interface Updates"
hexmask.word 0x00 0.--15. 1. "CtlUpd1GoodCtr,This register increments whenever the PHY acknowledges a Memory Controller-initiated DFI1 interface update request"
rgroup.word 0x174++0x01
line.word 0x00 "MasUpdFailCtr,Counts unsuccessful PHY Master Interface Updates"
hexmask.word 0x00 0.--15. 1. "MasUpdFailCtr,This register increments whenever the PHY asserts a PHY Master Interface request but the Memory Controller doesn't acknowledge the request within the allowed interval"
rgroup.word 0x176++0x01
line.word 0x00 "PhyUpd0FailCtr,Counts unsuccessful PHY-initiated DFI0 Interface Updates"
hexmask.word 0x00 0.--15. 1. "PhyUpd0FailCtr,This register increments whenever the PHY asserts a DFI0 Interface update request but the Memory Controller doesn't acknowledge the request within the allowed interval"
rgroup.word 0x178++0x01
line.word 0x00 "PhyUpd1FailCtr,Counts unsuccessful PHY-initiated DFI1 Interface Updates"
hexmask.word 0x00 0.--15. 1. "PhyUpd1FailCtr,This register increments whenever the PHY asserts a DFI1 Interface update request but the Memory Controller doesn't acknowledge the request within the allowed interval"
group.word 0x17A++0x01
line.word 0x00 "PhyPerfCtrEnable,Enables for Performance Counters"
bitfld.word 0x00 7. "PhyUpd1FailCtl,Enables PhyUpd1FailCtr" "0,1"
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bitfld.word 0x00 6. "PhyUpd0FailCtl,Enables PhyUpd0FailCtr" "0,1"
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bitfld.word 0x00 5. "MasUpdFailCtl,Enables MasUpdFailCtr" "0,1"
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bitfld.word 0x00 4. "CtlUpd1GoodCtl,Enables CtlUpd1GoodCtr" "0,1"
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bitfld.word 0x00 3. "CtlUpd0GoodCtl,Enables CtlUpd0GoodCtr" "0,1"
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bitfld.word 0x00 2. "PhyUpd1GoodCtl,Enables PhyUpd1GoodCtr" "0,1"
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bitfld.word 0x00 1. "PhyUpd0GoodCtl,Enables PhyUpd0GoodCtr" "0,1"
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bitfld.word 0x00 0. "MasUpdGoodCtl,Enables MasUpdGoodCtr" "0,1"
group.word 0x186++0x01
line.word 0x00 "PllPwrDn,PLL Power Down"
bitfld.word 0x00 0. "PllPwrDn,NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten" "0,1"
group.word 0x188++0x01
line.word 0x00 "PllReset,PLL Reset"
bitfld.word 0x00 0. "PllReset,Reserved" "0,1"
group.word 0x18A++0x01
line.word 0x00 "PllCtrl2_p0,PState dependent PLL Control Register 2"
bitfld.word 0x00 0.--4. "PllFreqSel,Adjusts the loop parameters to compensate for different VCO bias points and input/output clock division ratios" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x18C++0x01
line.word 0x00 "PllCtrl0,PLL Control Register 0"
bitfld.word 0x00 15. "PllSpareCtrl0,Spare bits for PLL control" "0,1"
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bitfld.word 0x00 13.--14. "PllLockPhSel,Lock detect phase selection" "0,1,2,3"
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bitfld.word 0x00 12. "PllLockCntSel,Lock detect counter selection" "0,1"
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bitfld.word 0x00 11. "PllGearShift,Puts PLL in fast re-locking mode" "0: default normal mode,1: fast relock gear"
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bitfld.word 0x00 9.--10. "PllReserved10x9,for future use" "0,1,2,3"
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bitfld.word 0x00 8. "PllSyncBusByp,When asserted bypasses the Pll SyncPulse and uses a synchronizer of the same latency" "0,1"
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bitfld.word 0x00 7. "PllSyncBusFlush,Used to flush the syncbus logic of the PLL during PHY initialization or LP3 Exit sequence" "0,1"
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bitfld.word 0x00 6. "PllSelDfiFreqRatio,reserved" "0,1"
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bitfld.word 0x00 5. "PllBypassMode,PLL Bypass clock mux control" "0,1"
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bitfld.word 0x00 4. "PllPreset,Put PLL in preset mode" "0,1"
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bitfld.word 0x00 3. "PllOutBypEn,Controls the antiglitch mux on the pllout_x1x2x4 path" "0: pllout_x1x2x4 = VCO (SCD) (selected by x2_mode),1: pllout_x1x2x4 = byp_pllin_x1"
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bitfld.word 0x00 2. "PllX2Mode,conects to x2_mode pins of PLL" "0,1"
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bitfld.word 0x00 1. "PllBypSel,Reserved" "0,1"
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bitfld.word 0x00 0. "PllStandby,Connects directly to standby pin of PLL" "0,1"
group.word 0x18E++0x01
line.word 0x00 "PllCtrl1_p0,PState dependent PLL Control Register 1"
bitfld.word 0x00 5.--8. "PllCpPropCtrl,connects directly to cp_prop_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--4. "PllCpIntCtrl,connects directly to cp_int_cntrl<1:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x190++0x01
line.word 0x00 "PllTst,PLL Testing Control Register"
bitfld.word 0x00 5.--8. "PllDigTstSel,Connects directly to pll_dig_test_sel<2:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 1.--4. "PllAnaTstSel,Connects directly to pll_ana_test_sel<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0. "PllAnaTstEn,Connects directly to pll_ana_test_en of PLL" "0,1"
rgroup.word 0x192++0x01
line.word 0x00 "PllLockStatus,PLL's pll_lock pin output"
bitfld.word 0x00 0. "PllLockStatus,Directly connected to the pll_Lock output" "0,1"
group.word 0x194++0x01
line.word 0x00 "PllTestMode_p0,Additional controls for PLL CP/VCO modes of operation"
hexmask.word 0x00 0.--15. 1. "PllTestMode_p0,It is required to use default values for this CSR unless directed otherwise by Synopsys"
group.word 0x196++0x01
line.word 0x00 "PllCtrl3,PLL Control Register 3"
bitfld.word 0x00 15. "PllEnCal,Calibration will run at standby rising edge if en_cal=1 if en_cal=0 calibration will not run" "0,1"
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bitfld.word 0x00 14. "PllForceCal,connects directly to force_cal of PLL" "0,1"
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bitfld.word 0x00 9.--13. "PllDacValIn,connects directly to dacval_in<4:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 4.--8. "PllMaxRange,connects directly to maxrange of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 0.--3. "PllSpare,Spare bits for future PLL control modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x198++0x01
line.word 0x00 "PllCtrl4_p0,PState dependent PLL Control Register 4"
bitfld.word 0x00 5.--8. "PllCpPropGsCtrl,connects directly to cp_prop_gs_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--4. "PllCpIntGsCtrl,connects directly to cp_int_gs_cntrl<4:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.word 0x19A++0x01
line.word 0x00 "PllEndofCal,PLL's eoc (end of calibration) output"
bitfld.word 0x00 0. "PllEndofCal,Directly connected to the pll's eoc output" "0,1"
rgroup.word 0x19C++0x01
line.word 0x00 "PllStandbyEff,PLL's standby_eff (effective standby) output"
bitfld.word 0x00 0. "PllStandbyEff,Returns state off PLL standby" "0,1"
rgroup.word 0x19E++0x01
line.word 0x00 "PllDacValOut,PLL's Dacval_out output"
bitfld.word 0x00 0.--4. "PllDacValOut,Directly connected to the pll's dacval_out output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1C6++0x01
line.word 0x00 "LcdlDbgCntl,Controls for use in observing and testing the LCDLs"
bitfld.word 0x00 12.--15. "LcdlStatusSel,Selects the LCDL status from among the status for the 16 LCDLs in the DBYTE for reading via Register DxLcdlStatus and an LCDL from among the LCDLs in the ANIB for reading via Register AcLcdlStatus LcdlStatusSel source for DxLcdlStatus.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 11. "LcdlTstEnable,Enables the debug/test operations and status Ovr Snap StickyLock StickyUnlock and LiveLock" "0,1"
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bitfld.word 0x00 10. "LcdlFineSnap,Latch enable for reading the present LCDL 1UI estimate code in LcdlFineSnapVal and the present phase-detector value in LcdlPhdSnapVal" "0,1"
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bitfld.word 0x00 9. "LcdlFineOvr,Forces the value of the present LCDL 1UI estimate code to be LcdlFineOvrVal for all LCDLs" "0,1"
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hexmask.word 0x00 0.--8. 1. "LcdlFineOvrVal,Value forced as the initial value while LcdlTstEnable=1 and LcdlFineOvr"
rgroup.word 0x1C8++0x01
line.word 0x00 "AcLcdlStatus,Debug status of the DBYTE LCDL"
bitfld.word 0x00 13. "AcLcdlLiveLock,present value of whether the LCDL is locked valid when LcdlTstEnable=1" "0,1"
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bitfld.word 0x00 12. "AcLcdlStickyUnlock,latched value of whether the LCDL ever lost lock after the assertion of LcdlTstEnable" "0,1"
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bitfld.word 0x00 11. "AcLcdlStickyLock,latched value of whether the LCDL ever achieved lock after the assertion of LcdlTstEnable" "0,1"
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bitfld.word 0x00 10. "AcLcdlPhdSnapVal,Value of the LCDL phase-detector output latched by pulse on LcdlFineSnap while csr LcdlTstEnable=1" "0,1"
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hexmask.word 0x00 0.--9. 1. "AcLcdlFineSnapVal,Value of the LCDL 1UI estimate code latched by pulse on csrLcdlFineSnap while csr LcdlTstEnable=1"
rgroup.word 0x1DA++0x01
line.word 0x00 "CUSTPHYREV,Customer settable by the customer"
bitfld.word 0x00 0.--5. "CUSTPHYREV,The customer settable PHY version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x1DC++0x01
line.word 0x00 "PHYREV,The hardware version of this PHY excluding the PUB"
hexmask.word.byte 0x00 8.--15. 1. "PHYMJR,Indicates major revision of the PHY"
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bitfld.word 0x00 4.--7. "PHYMDR,Indicates moderate revision of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "PHYMNR,Indicates minor update of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1DE++0x01
line.word 0x00 "LP3ExitSeq0BStartVector,Start vector value to be used for LP3-exit or Init PIE Sequence"
bitfld.word 0x00 4.--7. "LP3ExitSeq0BStartVecPllBypassed,PIE Start Vector value to be used for LP3-exit or Init and target P-state has PLL bypassed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "LP3ExitSeq0BStartVecPllEnabled,PIE Start Vector value to be used for LP3-exit or Init and target P-state has PLL enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1E0++0x01
line.word 0x00 "DfiFreqXlat0,DFI Frequency Translation Register 0"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal3,The sequencer start vector used when dfi_freq value is 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal2,The sequencer start vector used when dfi_freq value is 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal1,The sequencer start vector used when dfi_freq value is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal0,The sequencer start vector used when dfi_freq value is 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1E2++0x01
line.word 0x00 "DfiFreqXlat1,DFI Frequency Translation Register 1"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal7,The sequencer start vector used when dfi_freq value is 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal6,The sequencer start vector used when dfi_freq value is 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal5,The sequencer start vector used when dfi_freq value is 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal4,The sequencer start vector used when dfi_freq value is 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1E4++0x01
line.word 0x00 "DfiFreqXlat2,DFI Frequency Translation Register 2"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal11,The sequencer start vector used when dfi_freq value is 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal10,The sequencer start vector used when dfi_freq value is 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal9,The sequencer start vector used when dfi_freq value is 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal8,The sequencer start vector used when dfi_freq value is 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1E6++0x01
line.word 0x00 "DfiFreqXlat3,DFI Frequency Translation Register 3"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal15,The sequencer start vector used when dfi_freq value is 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal14,The sequencer start vector used when dfi_freq value is 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal13,The sequencer start vector used when dfi_freq value is 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal12,The sequencer start vector used when dfi_freq value is 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1E8++0x01
line.word 0x00 "DfiFreqXlat4,DFI Frequency Translation Register 4"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal19,The sequencer start vector used when dfi_freq value is 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal18,The sequencer start vector used when dfi_freq value is 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal17,The sequencer start vector used when dfi_freq value is 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal16,The sequencer start vector used when dfi_freq value is 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1EA++0x01
line.word 0x00 "DfiFreqXlat5,DFI Frequency Translation Register 5"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal23,The sequencer start vector used when dfi_freq value is 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal22,The sequencer start vector used when dfi_freq value is 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal21,The sequencer start vector used when dfi_freq value is 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal20,The sequencer start vector used when dfi_freq value is 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1EC++0x01
line.word 0x00 "DfiFreqXlat6,DFI Frequency Translation Register 6"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal27,The sequencer start vector used when dfi_freq value is 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal26,The sequencer start vector used when dfi_freq value is 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal25,The sequencer start vector used when dfi_freq value is 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal24,The sequencer start vector used when dfi_freq value is 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1EE++0x01
line.word 0x00 "DfiFreqXlat7,DFI Frequency Translation Register 7"
bitfld.word 0x00 12.--15. "DfiFreqXlatVal31,The sequencer start vector used when dfi_freq value is 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "DfiFreqXlatVal30,The sequencer start vector used when dfi_freq value is 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DfiFreqXlatVal29,The sequencer start vector used when dfi_freq value is 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DfiFreqXlatVal28,The sequencer start vector used when dfi_freq value is 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1F0++0x01
line.word 0x00 "TxRdPtrInit,TxRdPtrInit control register"
bitfld.word 0x00 0. "TxRdPtrInit,This register directly controls TxRdPtrInit and is meant to be written by the PState sequencer as part of the power state switching sequence" "0,1"
group.word 0x1F2++0x01
line.word 0x00 "DfiInitComplete,DFI Init Complete control"
bitfld.word 0x00 0. "DfiInitComplete,This register directly controls DfiInitComplete and is meant to be written by the PState sequencer as part of the power state switching sequence" "0,1"
group.word 0x1F4++0x01
line.word 0x00 "DfiFreqRatio_p0,DFI Frequency Ratio"
bitfld.word 0x00 0.--1. "DfiFreqRatio_p0,Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals" "0: 1:1 mode,1: 1:2 mode 1x = 1:4,?..."
group.word 0x1F6++0x01
line.word 0x00 "RxFifoChecks,Enable more frequent consistency checks of the RX FIFOs"
bitfld.word 0x00 0. "DoFrequentRxFifoChecks,When 0 read data FIFO pointer consistency checks are performed only during sideband transactions (i" "0,1"
group.word 0x1FE++0x01
line.word 0x00 "MTestDtoCtrl,no description available"
bitfld.word 0x00 0. "MTestDtoCtrl,MTESTdtoEn==[0] dwc_ddrphy_dto will be squelched (0) MTESTdtoEn==[1] dwc_ddrphy_dto will reflect the observability signal multiplexed on MTestCombo" "0,1"
group.word 0x200++0x01
line.word 0x00 "MapCAA0toDfi,Maps PHY CAA lane 0 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA0toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x202++0x01
line.word 0x00 "MapCAA1toDfi,Maps PHY CAA lane 1 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA1toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x204++0x01
line.word 0x00 "MapCAA2toDfi,Maps PHY CAA lane 2 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA2toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x206++0x01
line.word 0x00 "MapCAA3toDfi,Maps PHY CAA lane 3 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA3toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x208++0x01
line.word 0x00 "MapCAA4toDfi,Maps PHY CAA lane 4 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA4toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x20A++0x01
line.word 0x00 "MapCAA5toDfi,Maps PHY CAA lane 5 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA5toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x20C++0x01
line.word 0x00 "MapCAA6toDfi,Maps PHY CAA lane 6 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA6toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x20E++0x01
line.word 0x00 "MapCAA7toDfi,Maps PHY CAA lane 7 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA7toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x210++0x01
line.word 0x00 "MapCAA8toDfi,Maps PHY CAA lane 8 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA8toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x212++0x01
line.word 0x00 "MapCAA9toDfi,Maps PHY CAA lane 9 from dfi0_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAA9toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi0_address to CAA 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x220++0x01
line.word 0x00 "MapCAB0toDfi,Maps PHY CAB lane 0 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB0toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x222++0x01
line.word 0x00 "MapCAB1toDfi,Maps PHY CAB lane 1 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB1toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x224++0x01
line.word 0x00 "MapCAB2toDfi,Maps PHY CAB lane 2 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB2toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x226++0x01
line.word 0x00 "MapCAB3toDfi,Maps PHY CAB lane 3 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB3toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x228++0x01
line.word 0x00 "MapCAB4toDfi,Maps PHY CAB lane 4 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB4toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x22A++0x01
line.word 0x00 "MapCAB5toDfi,Maps PHY CAB lane 5 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB5toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x22C++0x01
line.word 0x00 "MapCAB6toDfi,Maps PHY CAB lane 6 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB6toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x22E++0x01
line.word 0x00 "MapCAB7toDfi,Maps PHY CAB lane 7 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB7toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x230++0x01
line.word 0x00 "MapCAB8toDfi,Maps PHY CAB lane 8 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB8toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x232++0x01
line.word 0x00 "MapCAB9toDfi,Maps PHY CAB lane 9 from dfi1_address of the index of the register contents"
bitfld.word 0x00 0.--3. "MapCAB9toDfi,For LPDDR3 and LPDDR4 applications these CSRs map a dfi1_address to CAB 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x236++0x01
line.word 0x00 "PhyInterruptEnable,Interrupt Enable Bits"
bitfld.word 0x00 11.--15. "PhyHWReservedEn,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 10. "PhyRxFifoCheckEn,Enable for the RxFifo Pointers Check Interrupt" "0: Interrupt not enabled,1: Interrupt enabled"
newline
bitfld.word 0x00 8.--9. "PhyVTDriftAlarmEn,Enable for the PHY VT Drift Alarm interrupts" "0,1,2,3"
newline
bitfld.word 0x00 3.--7. "PhyFWReservedEn,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 2. "PhyTrngFailEn,Enable for the PHY Training Failure interrupt" "0,1"
newline
bitfld.word 0x00 1. "PhyInitCmpltEn,Enable for the PHY Initialization Complete interrupt" "0,1"
newline
bitfld.word 0x00 0. "PhyTrngCmpltEn,Enable for the PHY Training Complete interrupt" "0,1"
group.word 0x238++0x01
line.word 0x00 "PhyInterruptFWControl,Interrupt Firmware Control Bits"
bitfld.word 0x00 3.--7. "PhyFWReservedFW,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 2. "PhyTrngFailFW,PHY Training Failure Firmware interrupt" "0,1"
newline
bitfld.word 0x00 1. "PhyInitCmpltFW,PHY Initialization Complete Firmware interrupt" "0,1"
newline
bitfld.word 0x00 0. "PhyTrngCmpltFW,PHY Training Complete Firmware interrupt" "0,1"
group.word 0x23A++0x01
line.word 0x00 "PhyInterruptMask,Interrupt Mask Bits"
bitfld.word 0x00 11.--15. "PhyHWReservedMsk,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 10. "PhyRxFifoCheckMsk,Mask for the RxFifo Pointers Check Interrupt" "0: Interrupt not masked,1: Interrupt masked"
newline
bitfld.word 0x00 8.--9. "PhyVTDriftAlarmMsk,Mask for the PHY VT Drift Alarm interrupts" "0,1,2,3"
newline
bitfld.word 0x00 3.--7. "PhyFWReservedMsk,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 2. "PhyTrngFailMsk,Mask for the PHY Training Failure interrupt" "0,1"
newline
bitfld.word 0x00 1. "PhyInitCmpltMsk,Mask for the PHY Initialization Complete interrupt" "0,1"
newline
bitfld.word 0x00 0. "PhyTrngCmpltMsk,Mask for the PHY Training Complete interrupt" "0,1"
group.word 0x23C++0x01
line.word 0x00 "PhyInterruptClear,Interrupt Clear Bits"
bitfld.word 0x00 11.--15. "PhyHWReservedClr,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 10. "PhyRxFifoCheckClr,Clear for the RxFifo Pointers Check Interrupt" "0: Interrupt not affected,1: Interrupt cleared"
newline
bitfld.word 0x00 8.--9. "PhyVTDriftAlarmClr,Clear for the PHY VT Drift Alarm interrupt" "0,1,2,3"
newline
bitfld.word 0x00 3.--7. "PhyFWReservedClr,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 2. "PhyTrngFailClr,Clear for the PHY Training Failure interrupt" "0,1"
newline
bitfld.word 0x00 1. "PhyInitCmpltClr,Clear for the PHY Initialization Complete interrupt" "0,1"
newline
bitfld.word 0x00 0. "PhyTrngCmpltClr,Clear for the PHY Training Complete interrupt" "0,1"
rgroup.word 0x23E++0x01
line.word 0x00 "PhyInterruptStatus,Interrupt Status Bits"
bitfld.word 0x00 11.--15. "PhyHWReserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 10. "PhyRxFifoCheck,A mechanism in the PHY checks the Read Fifo pointers for consistency at times they are idle" "0,1"
newline
bitfld.word 0x00 8.--9. "VTDriftAlarm,PHY VT Drift Alarm interrupt" "0,1,2,3"
newline
bitfld.word 0x00 3.--7. "PhyFWReserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 2. "PhyTrngFail,PHY Training Failure interrupt" "0,1"
newline
bitfld.word 0x00 1. "PhyInitCmplt,PHY Initialization Complete interrupt" "0,1"
newline
bitfld.word 0x00 0. "PhyTrngCmplt,PHY Training Complete interrupt" "0,1"
group.word 0x240++0x01
line.word 0x00 "HwtSwizzleHwtAddress0,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress0,This set of registers is used in DDR3/DDR4 mode where a user has re-mapped the DFI inputs to the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x242++0x01
line.word 0x00 "HwtSwizzleHwtAddress1,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress1,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x244++0x01
line.word 0x00 "HwtSwizzleHwtAddress2,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress2,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x246++0x01
line.word 0x00 "HwtSwizzleHwtAddress3,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress3,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x248++0x01
line.word 0x00 "HwtSwizzleHwtAddress4,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress4,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x24A++0x01
line.word 0x00 "HwtSwizzleHwtAddress5,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress5,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x24C++0x01
line.word 0x00 "HwtSwizzleHwtAddress6,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress6,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x24E++0x01
line.word 0x00 "HwtSwizzleHwtAddress7,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress7,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x250++0x01
line.word 0x00 "HwtSwizzleHwtAddress8,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress8,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x252++0x01
line.word 0x00 "HwtSwizzleHwtAddress9,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress9,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x254++0x01
line.word 0x00 "HwtSwizzleHwtAddress10,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress10,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x256++0x01
line.word 0x00 "HwtSwizzleHwtAddress11,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress11,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x258++0x01
line.word 0x00 "HwtSwizzleHwtAddress12,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress12,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x25A++0x01
line.word 0x00 "HwtSwizzleHwtAddress13,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress13,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x25C++0x01
line.word 0x00 "HwtSwizzleHwtAddress14,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress14,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x25E++0x01
line.word 0x00 "HwtSwizzleHwtAddress15,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress15,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x260++0x01
line.word 0x00 "HwtSwizzleHwtAddress17,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtAddress17,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x262++0x01
line.word 0x00 "HwtSwizzleHwtActN,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtActN,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x264++0x01
line.word 0x00 "HwtSwizzleHwtBank0,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtBank0,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x266++0x01
line.word 0x00 "HwtSwizzleHwtBank1,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtBank1,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x268++0x01
line.word 0x00 "HwtSwizzleHwtBank2,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtBank2,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x26A++0x01
line.word 0x00 "HwtSwizzleHwtBg0,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtBg0,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x26C++0x01
line.word 0x00 "HwtSwizzleHwtBg1,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtBg1,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x26E++0x01
line.word 0x00 "HwtSwizzleHwtCasN,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtCasN,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x270++0x01
line.word 0x00 "HwtSwizzleHwtRasN,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtRasN,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x272++0x01
line.word 0x00 "HwtSwizzleHwtWeN,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtWeN,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x274++0x01
line.word 0x00 "HwtSwizzleHwtParityIn,Signal swizzle selection for HWT swizzle"
bitfld.word 0x00 0.--4. "HwtSwizzleHwtParityIn,See Description of HwtSwizzleHwtAddress0 for details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x278++0x01
line.word 0x00 "DfiHandshakeDelays0,Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays"
bitfld.word 0x00 12.--15. "CtrlUpdReqDelay0,Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities before deasserting dfi0_ctrlupd_ack" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "CtrlUpdAckDelay0,Adds 0-15 DfiClks of delay after dfi0_ctrlupd_req asserts before the PHY takes any action" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "PhyUpdReqDelay0,Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities before deasserting dfi0_phyupd_req" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "PhyUpdAckDelay0,Adds 0-15 DfiClks of delay after dfi0_phyupd_ack asserts before the PHY takes any action (such as starting DDL calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x27A++0x01
line.word 0x00 "DfiHandshakeDelays1,Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays"
bitfld.word 0x00 12.--15. "CtrlUpdReqDelay1,Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities before deasserting dfi1_ctrlupd_ack" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. "CtrlUpdAckDelay1,Adds 0-15 DfiClks of delay after dfi1_ctrlupd_req asserts before the PHY takes any action" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "PhyUpdReqDelay1,Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities before deasserting dfi1_phyupd_req" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "PhyUpdAckDelay1,Adds 0-15 DfiClks of delay after dfi1_phyupd_ack asserts before the PHY takes any action (such as starting DDL calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x200010++0x01
line.word 0x00 "CalUclkInfo_p1,Impedance Calibration Clock Ratio"
hexmask.word 0x00 0.--9. 1. "CalUClkTicksPer1uS,Must be programmed to the number of DfiClks in 1us (rounded up) with minimum value of 24"
group.word 0x200016++0x01
line.word 0x00 "Seq0BDLY0_p1,PHY Initialization Engine (PIE) Delay Register 0"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY0_p1,PHY Initialization Engine (PIE) Delay Register 0 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x200018++0x01
line.word 0x00 "Seq0BDLY1_p1,PHY Initialization Engine (PIE) Delay Register 1"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY1_p1,PHY Initialization Engine (PIE) Delay Register 1 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x20001A++0x01
line.word 0x00 "Seq0BDLY2_p1,PHY Initialization Engine (PIE) Delay Register 2"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY2_p1,PHY Initialization Engine (PIE) Delay Register 2 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x20001C++0x01
line.word 0x00 "Seq0BDLY3_p1,PHY Initialization Engine (PIE) Delay Register 3"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY3_p1,PHY Initialization Engine (PIE) Delay Register 3 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x200020++0x01
line.word 0x00 "PPTTrainSetup_p1,Setup Intervals for DFI PHY Master operations"
bitfld.word 0x00 4.--6. "PhyMstrMaxReqToAck,Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--3. "PhyMstrTrainInterval,Bits 3:0 of this register specifies the time between the end of one training and the start of the next" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x200032++0x01
line.word 0x00 "TristateModeCA_p1,Mode select register for MEMCLK/Address/Command Tristates"
bitfld.word 0x00 2.--3. "CkDisVal,The PHY provides 4 memory clocks n=0" "0,1,2,3"
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bitfld.word 0x00 1. "DDR2TMode,Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode" "0,1"
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bitfld.word 0x00 0. "DisDynAdrTri,When DisDynAdrTri=1 Dynamic Tristating is disabled" "0,1"
group.word 0x200040++0x01
line.word 0x00 "HwtMRL_p1,HWT MaxReadLatency"
bitfld.word 0x00 0.--4. "HwtMRL_p1,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x200048++0x01
line.word 0x00 "DqsPreambleControl_p1,Control the PHY logic related to the read and write DQS preamble"
bitfld.word 0x00 8. "WDQSEXTENSION,When set DQS_T and DQS_C will be driven differentially to 0 and 1 respectively before and after a write burst except during a memory read transaction" "0,1"
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bitfld.word 0x00 7. "LP4SttcPreBridgeRxEn,Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads to the same timing group when the bubble is 1 memclk" "0,1"
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bitfld.word 0x00 6. "LP4PostambleExt,In LPDDR4 mode must be set to extend the write postamble" "0,1"
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bitfld.word 0x00 5. "LP4TglTwoTckTxDqsPre,Used in LPDDR4 mode to modify the early preamble when Register TwoTckTxDqsPre=1" "0: level first-memclk preamble,1: toggling first-memclk preamble"
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bitfld.word 0x00 2.--4. "PositionDfeInit,For DDR4 phy only when receive DFE is enabled" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 1. "TwoTckTxDqsPre," "0,1"
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bitfld.word 0x00 0. "TwoTckRxDqsPre,Widens the RxDqsEn window to allow larger drift in the incoming read DQS to take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read.." "0,1"
group.word 0x20005A++0x01
line.word 0x00 "DMIPinPresent_p1,This Register is used to enable the Read-DBI function in each DBYTE"
bitfld.word 0x00 0. "RdDbiEnabled,This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device" "0,1"
group.word 0x20005C++0x01
line.word 0x00 "ARdPtrInitVal_p1,Address/Command FIFO ReadPointer Initial Value"
bitfld.word 0x00 0.--3. "ARdPtrInitVal_p1,This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x2000AC++0x01
line.word 0x00 "ProcOdtTimeCtl_p1,READ DATA On-Die Termination Timing Control (by PHY)"
bitfld.word 0x00 2.--3. "POdtStartDelay,controls the start of ProcOdt units of UI 3 delay start 2 UI maximum delay of start of ProcOdt 2 delay start 1 UI 1 delay start 0 UI default 0 early by 1 UI The time from ProcODT assertion to opening the window to receive DQS is (10 -.." "0,1,2,3"
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bitfld.word 0x00 0.--1. "POdtTailWidth,controls the length of the tail of ProcOdt units of UI 3 tail 3UI more than for Register POdtTailWidth=0 maximum 2 tail 2UI more than for Register POdtTailWidth=0 default 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length.." "0,1,2,3"
group.word 0x2000F8++0x01
line.word 0x00 "DllGainCtl_p1,DLL gain control"
bitfld.word 0x00 8.--11. "DllSeedSel,Reserved must be configured to be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DllGainTV,Terminal value of DllGain ie the value in effect when locking is done and the value used for maintaining lock ie tracking pclk variation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DllGainIV,Initial value of DllGain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x200160++0x01
line.word 0x00 "DfiRdDataCsDestMap_p1,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiRdDestm3,Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example if 3 dfi_rddata_cs_n_p0[3] will use Register RxEn ClkDlyTg3 timing" "0,1,2,3"
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bitfld.word 0x00 4.--5. "DfiRdDestm2,Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example if 2 dfi_rddata_cs_n_p0[2] will use Register RxEn ClkDlyTg2 timing" "0,1,2,3"
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bitfld.word 0x00 2.--3. "DfiRdDestm1,Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example if 1 dfi_rddata_cs_n[_p01] will use Register RxEn ClkDlyTg1 timing" "0,1,2,3"
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bitfld.word 0x00 0.--1. "DfiRdDestm0,Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example if 0 dfi_rddata_cs_n_p0[0] will use Register RxEn ClkDlyTg0 timing" "0,1,2,3"
group.word 0x200164++0x01
line.word 0x00 "VrefInGlobal_p1,PHY Global Vref Controls"
bitfld.word 0x00 14. "GlobalVrefInMode,RSVD" "0,1"
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bitfld.word 0x00 10.--13. "GlobalVrefInTrim,RSVD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.word.byte 0x00 3.--9. 1. "GlobalVrefInDAC,DAC code for internal Vref generation The DAC has two ranges the range is set by GlobalVrefInSel[2] ========================================================== RANGE0 : DDR3 DDR4 LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage =.."
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bitfld.word 0x00 0.--2. "GlobalVrefInSel,GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin ==========================================================" "0: PHY Vref DAC Range0 -- BP_VREF = Hi-Z,1: Reserved Encoding,2: PHY Vref DAC Range0 -- BP_VREF connected to PLL,3: PHY Vref DAC Range0 -- BP_VREF connected to PHY,?..."
group.word 0x200168++0x01
line.word 0x00 "DfiWrDataCsDestMap_p1,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiWrDestm3,Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register TxDq DqsDlyTg3) For example if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg3 timing" "0,1,2,3"
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bitfld.word 0x00 4.--5. "DfiWrDestm2,Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example if 2 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg2 timing" "0,1,2,3"
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bitfld.word 0x00 2.--3. "DfiWrDestm1,Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example if 1 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg1 timing" "0,1,2,3"
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bitfld.word 0x00 0.--1. "DfiWrDestm0,Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example if 0 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg0 timing" "0,1,2,3"
group.word 0x20018A++0x01
line.word 0x00 "PllCtrl2_p1,PState dependent PLL Control Register 2"
bitfld.word 0x00 0.--4. "PllFreqSel,Adjusts the loop parameters to compensate for different VCO bias points and input/output clock division ratios" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20018E++0x01
line.word 0x00 "PllCtrl1_p1,PState dependent PLL Control Register 1"
bitfld.word 0x00 5.--8. "PllCpPropCtrl,connects directly to cp_prop_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--4. "PllCpIntCtrl,connects directly to cp_int_cntrl<1:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x200194++0x01
line.word 0x00 "PllTestMode_p1,Additional controls for PLL CP/VCO modes of operation"
hexmask.word 0x00 0.--15. 1. "PllTestMode_p1,It is required to use default values for this CSR unless directed otherwise by Synopsys"
group.word 0x200198++0x01
line.word 0x00 "PllCtrl4_p1,PState dependent PLL Control Register 4"
bitfld.word 0x00 5.--8. "PllCpPropGsCtrl,connects directly to cp_prop_gs_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--4. "PllCpIntGsCtrl,connects directly to cp_int_gs_cntrl<4:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2001F4++0x01
line.word 0x00 "DfiFreqRatio_p1,DFI Frequency Ratio"
bitfld.word 0x00 0.--1. "DfiFreqRatio_p1,Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals" "0: 1:1 mode,1: 1:2 mode 1x = 1:4,?..."
group.word 0x400010++0x01
line.word 0x00 "CalUclkInfo_p2,Impedance Calibration Clock Ratio"
hexmask.word 0x00 0.--9. 1. "CalUClkTicksPer1uS,Must be programmed to the number of DfiClks in 1us (rounded up) with minimum value of 24"
group.word 0x400016++0x01
line.word 0x00 "Seq0BDLY0_p2,PHY Initialization Engine (PIE) Delay Register 0"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY0_p2,PHY Initialization Engine (PIE) Delay Register 0 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x400018++0x01
line.word 0x00 "Seq0BDLY1_p2,PHY Initialization Engine (PIE) Delay Register 1"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY1_p2,PHY Initialization Engine (PIE) Delay Register 1 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x40001A++0x01
line.word 0x00 "Seq0BDLY2_p2,PHY Initialization Engine (PIE) Delay Register 2"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY2_p2,PHY Initialization Engine (PIE) Delay Register 2 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x40001C++0x01
line.word 0x00 "Seq0BDLY3_p2,PHY Initialization Engine (PIE) Delay Register 3"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY3_p2,PHY Initialization Engine (PIE) Delay Register 3 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x400020++0x01
line.word 0x00 "PPTTrainSetup_p2,Setup Intervals for DFI PHY Master operations"
bitfld.word 0x00 4.--6. "PhyMstrMaxReqToAck,Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--3. "PhyMstrTrainInterval,Bits 3:0 of this register specifies the time between the end of one training and the start of the next" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x400032++0x01
line.word 0x00 "TristateModeCA_p2,Mode select register for MEMCLK/Address/Command Tristates"
bitfld.word 0x00 2.--3. "CkDisVal,The PHY provides 4 memory clocks n=0" "0,1,2,3"
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bitfld.word 0x00 1. "DDR2TMode,Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode" "0,1"
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bitfld.word 0x00 0. "DisDynAdrTri,When DisDynAdrTri=1 Dynamic Tristating is disabled" "0,1"
group.word 0x400040++0x01
line.word 0x00 "HwtMRL_p2,HWT MaxReadLatency"
bitfld.word 0x00 0.--4. "HwtMRL_p2,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x400048++0x01
line.word 0x00 "DqsPreambleControl_p2,Control the PHY logic related to the read and write DQS preamble"
bitfld.word 0x00 8. "WDQSEXTENSION,When set DQS_T and DQS_C will be driven differentially to 0 and 1 respectively before and after a write burst except during a memory read transaction" "0,1"
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bitfld.word 0x00 7. "LP4SttcPreBridgeRxEn,Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads to the same timing group when the bubble is 1 memclk" "0,1"
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bitfld.word 0x00 6. "LP4PostambleExt,In LPDDR4 mode must be set to extend the write postamble" "0,1"
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bitfld.word 0x00 5. "LP4TglTwoTckTxDqsPre,Used in LPDDR4 mode to modify the early preamble when Register TwoTckTxDqsPre=1" "0: level first-memclk preamble,1: toggling first-memclk preamble"
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bitfld.word 0x00 2.--4. "PositionDfeInit,For DDR4 phy only when receive DFE is enabled" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 1. "TwoTckTxDqsPre," "0,1"
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bitfld.word 0x00 0. "TwoTckRxDqsPre,Widens the RxDqsEn window to allow larger drift in the incoming read DQS to take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read.." "0,1"
group.word 0x40005A++0x01
line.word 0x00 "DMIPinPresent_p2,This Register is used to enable the Read-DBI function in each DBYTE"
bitfld.word 0x00 0. "RdDbiEnabled,This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device" "0,1"
group.word 0x40005C++0x01
line.word 0x00 "ARdPtrInitVal_p2,Address/Command FIFO ReadPointer Initial Value"
bitfld.word 0x00 0.--3. "ARdPtrInitVal_p2,This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4000AC++0x01
line.word 0x00 "ProcOdtTimeCtl_p2,READ DATA On-Die Termination Timing Control (by PHY)"
bitfld.word 0x00 2.--3. "POdtStartDelay,controls the start of ProcOdt units of UI 3 delay start 2 UI maximum delay of start of ProcOdt 2 delay start 1 UI 1 delay start 0 UI default 0 early by 1 UI The time from ProcODT assertion to opening the window to receive DQS is (10 -.." "0,1,2,3"
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bitfld.word 0x00 0.--1. "POdtTailWidth,controls the length of the tail of ProcOdt units of UI 3 tail 3UI more than for Register POdtTailWidth=0 maximum 2 tail 2UI more than for Register POdtTailWidth=0 default 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length.." "0,1,2,3"
group.word 0x4000F8++0x01
line.word 0x00 "DllGainCtl_p2,DLL gain control"
bitfld.word 0x00 8.--11. "DllSeedSel,Reserved must be configured to be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DllGainTV,Terminal value of DllGain ie the value in effect when locking is done and the value used for maintaining lock ie tracking pclk variation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "DllGainIV,Initial value of DllGain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x400160++0x01
line.word 0x00 "DfiRdDataCsDestMap_p2,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiRdDestm3,Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example if 3 dfi_rddata_cs_n_p0[3] will use Register RxEn ClkDlyTg3 timing" "0,1,2,3"
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bitfld.word 0x00 4.--5. "DfiRdDestm2,Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example if 2 dfi_rddata_cs_n_p0[2] will use Register RxEn ClkDlyTg2 timing" "0,1,2,3"
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bitfld.word 0x00 2.--3. "DfiRdDestm1,Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example if 1 dfi_rddata_cs_n[_p01] will use Register RxEn ClkDlyTg1 timing" "0,1,2,3"
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bitfld.word 0x00 0.--1. "DfiRdDestm0,Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example if 0 dfi_rddata_cs_n_p0[0] will use Register RxEn ClkDlyTg0 timing" "0,1,2,3"
group.word 0x400164++0x01
line.word 0x00 "VrefInGlobal_p2,PHY Global Vref Controls"
bitfld.word 0x00 14. "GlobalVrefInMode,RSVD" "0,1"
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bitfld.word 0x00 10.--13. "GlobalVrefInTrim,RSVD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.word.byte 0x00 3.--9. 1. "GlobalVrefInDAC,DAC code for internal Vref generation The DAC has two ranges the range is set by GlobalVrefInSel[2] ========================================================== RANGE0 : DDR3 DDR4 LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage =.."
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bitfld.word 0x00 0.--2. "GlobalVrefInSel,GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin ==========================================================" "0: PHY Vref DAC Range0 -- BP_VREF = Hi-Z,1: Reserved Encoding,2: PHY Vref DAC Range0 -- BP_VREF connected to PLL,3: PHY Vref DAC Range0 -- BP_VREF connected to PHY,?..."
group.word 0x400168++0x01
line.word 0x00 "DfiWrDataCsDestMap_p2,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiWrDestm3,Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register TxDq DqsDlyTg3) For example if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg3 timing" "0,1,2,3"
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bitfld.word 0x00 4.--5. "DfiWrDestm2,Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example if 2 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg2 timing" "0,1,2,3"
newline
bitfld.word 0x00 2.--3. "DfiWrDestm1,Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example if 1 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg1 timing" "0,1,2,3"
newline
bitfld.word 0x00 0.--1. "DfiWrDestm0,Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example if 0 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg0 timing" "0,1,2,3"
group.word 0x40018A++0x01
line.word 0x00 "PllCtrl2_p2,PState dependent PLL Control Register 2"
bitfld.word 0x00 0.--4. "PllFreqSel,Adjusts the loop parameters to compensate for different VCO bias points and input/output clock division ratios" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x40018E++0x01
line.word 0x00 "PllCtrl1_p2,PState dependent PLL Control Register 1"
bitfld.word 0x00 5.--8. "PllCpPropCtrl,connects directly to cp_prop_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--4. "PllCpIntCtrl,connects directly to cp_int_cntrl<1:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x400194++0x01
line.word 0x00 "PllTestMode_p2,Additional controls for PLL CP/VCO modes of operation"
hexmask.word 0x00 0.--15. 1. "PllTestMode_p2,It is required to use default values for this CSR unless directed otherwise by Synopsys"
group.word 0x400198++0x01
line.word 0x00 "PllCtrl4_p2,PState dependent PLL Control Register 4"
bitfld.word 0x00 5.--8. "PllCpPropGsCtrl,connects directly to cp_prop_gs_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--4. "PllCpIntGsCtrl,connects directly to cp_int_gs_cntrl<4:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4001F4++0x01
line.word 0x00 "DfiFreqRatio_p2,DFI Frequency Ratio"
bitfld.word 0x00 0.--1. "DfiFreqRatio_p2,Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals" "0: 1:1 mode,1: 1:2 mode 1x = 1:4,?..."
group.word 0x600010++0x01
line.word 0x00 "CalUclkInfo_p3,Impedance Calibration Clock Ratio"
hexmask.word 0x00 0.--9. 1. "CalUClkTicksPer1uS,Must be programmed to the number of DfiClks in 1us (rounded up) with minimum value of 24"
group.word 0x600016++0x01
line.word 0x00 "Seq0BDLY0_p3,PHY Initialization Engine (PIE) Delay Register 0"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY0_p3,PHY Initialization Engine (PIE) Delay Register 0 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x600018++0x01
line.word 0x00 "Seq0BDLY1_p3,PHY Initialization Engine (PIE) Delay Register 1"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY1_p3,PHY Initialization Engine (PIE) Delay Register 1 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x60001A++0x01
line.word 0x00 "Seq0BDLY2_p3,PHY Initialization Engine (PIE) Delay Register 2"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY2_p3,PHY Initialization Engine (PIE) Delay Register 2 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x60001C++0x01
line.word 0x00 "Seq0BDLY3_p3,PHY Initialization Engine (PIE) Delay Register 3"
hexmask.word 0x00 0.--15. 1. "Seq0BDLY3_p3,PHY Initialization Engine (PIE) Delay Register 3 This register is available for selection by the NOP and WAIT instructions in the PIE for the delay value"
group.word 0x600020++0x01
line.word 0x00 "PPTTrainSetup_p3,Setup Intervals for DFI PHY Master operations"
bitfld.word 0x00 4.--6. "PhyMstrMaxReqToAck,Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--3. "PhyMstrTrainInterval,Bits 3:0 of this register specifies the time between the end of one training and the start of the next" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x600032++0x01
line.word 0x00 "TristateModeCA_p3,Mode select register for MEMCLK/Address/Command Tristates"
bitfld.word 0x00 2.--3. "CkDisVal,The PHY provides 4 memory clocks n=0" "0,1,2,3"
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bitfld.word 0x00 1. "DDR2TMode,Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode" "0,1"
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bitfld.word 0x00 0. "DisDynAdrTri,When DisDynAdrTri=1 Dynamic Tristating is disabled" "0,1"
group.word 0x600040++0x01
line.word 0x00 "HwtMRL_p3,HWT MaxReadLatency"
bitfld.word 0x00 0.--4. "HwtMRL_p3,This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read until after all dbytes have their read data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x600048++0x01
line.word 0x00 "DqsPreambleControl_p3,Control the PHY logic related to the read and write DQS preamble"
bitfld.word 0x00 8. "WDQSEXTENSION,When set DQS_T and DQS_C will be driven differentially to 0 and 1 respectively before and after a write burst except during a memory read transaction" "0,1"
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bitfld.word 0x00 7. "LP4SttcPreBridgeRxEn,Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads to the same timing group when the bubble is 1 memclk" "0,1"
newline
bitfld.word 0x00 6. "LP4PostambleExt,In LPDDR4 mode must be set to extend the write postamble" "0,1"
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bitfld.word 0x00 5. "LP4TglTwoTckTxDqsPre,Used in LPDDR4 mode to modify the early preamble when Register TwoTckTxDqsPre=1" "0: level first-memclk preamble,1: toggling first-memclk preamble"
newline
bitfld.word 0x00 2.--4. "PositionDfeInit,For DDR4 phy only when receive DFE is enabled" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 1. "TwoTckTxDqsPre," "0,1"
newline
bitfld.word 0x00 0. "TwoTckRxDqsPre,Widens the RxDqsEn window to allow larger drift in the incoming read DQS to take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read.." "0,1"
group.word 0x60005A++0x01
line.word 0x00 "DMIPinPresent_p3,This Register is used to enable the Read-DBI function in each DBYTE"
bitfld.word 0x00 0. "RdDbiEnabled,This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device" "0,1"
group.word 0x60005C++0x01
line.word 0x00 "ARdPtrInitVal_p3,Address/Command FIFO ReadPointer Initial Value"
bitfld.word 0x00 0.--3. "ARdPtrInitVal_p3,This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x6000AC++0x01
line.word 0x00 "ProcOdtTimeCtl_p3,READ DATA On-Die Termination Timing Control (by PHY)"
bitfld.word 0x00 2.--3. "POdtStartDelay,controls the start of ProcOdt units of UI 3 delay start 2 UI maximum delay of start of ProcOdt 2 delay start 1 UI 1 delay start 0 UI default 0 early by 1 UI The time from ProcODT assertion to opening the window to receive DQS is (10 -.." "0,1,2,3"
newline
bitfld.word 0x00 0.--1. "POdtTailWidth,controls the length of the tail of ProcOdt units of UI 3 tail 3UI more than for Register POdtTailWidth=0 maximum 2 tail 2UI more than for Register POdtTailWidth=0 default 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length.." "0,1,2,3"
group.word 0x6000F8++0x01
line.word 0x00 "DllGainCtl_p3,DLL gain control"
bitfld.word 0x00 8.--11. "DllSeedSel,Reserved must be configured to be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. "DllGainTV,Terminal value of DllGain ie the value in effect when locking is done and the value used for maintaining lock ie tracking pclk variation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "DllGainIV,Initial value of DllGain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x600160++0x01
line.word 0x00 "DfiRdDataCsDestMap_p3,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiRdDestm3,Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example if 3 dfi_rddata_cs_n_p0[3] will use Register RxEn ClkDlyTg3 timing" "0,1,2,3"
newline
bitfld.word 0x00 4.--5. "DfiRdDestm2,Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example if 2 dfi_rddata_cs_n_p0[2] will use Register RxEn ClkDlyTg2 timing" "0,1,2,3"
newline
bitfld.word 0x00 2.--3. "DfiRdDestm1,Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example if 1 dfi_rddata_cs_n[_p01] will use Register RxEn ClkDlyTg1 timing" "0,1,2,3"
newline
bitfld.word 0x00 0.--1. "DfiRdDestm0,Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example if 0 dfi_rddata_cs_n_p0[0] will use Register RxEn ClkDlyTg0 timing" "0,1,2,3"
group.word 0x600164++0x01
line.word 0x00 "VrefInGlobal_p3,PHY Global Vref Controls"
bitfld.word 0x00 14. "GlobalVrefInMode,RSVD" "0,1"
newline
bitfld.word 0x00 10.--13. "GlobalVrefInTrim,RSVD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.word.byte 0x00 3.--9. 1. "GlobalVrefInDAC,DAC code for internal Vref generation The DAC has two ranges the range is set by GlobalVrefInSel[2] ========================================================== RANGE0 : DDR3 DDR4 LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage =.."
newline
bitfld.word 0x00 0.--2. "GlobalVrefInSel,GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin ==========================================================" "0: PHY Vref DAC Range0 -- BP_VREF = Hi-Z,1: Reserved Encoding,2: PHY Vref DAC Range0 -- BP_VREF connected to PLL,3: PHY Vref DAC Range0 -- BP_VREF connected to PHY,?..."
group.word 0x600168++0x01
line.word 0x00 "DfiWrDataCsDestMap_p3,Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM"
bitfld.word 0x00 6.--7. "DfiWrDestm3,Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register TxDq DqsDlyTg3) For example if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg3 timing" "0,1,2,3"
newline
bitfld.word 0x00 4.--5. "DfiWrDestm2,Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example if 2 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg2 timing" "0,1,2,3"
newline
bitfld.word 0x00 2.--3. "DfiWrDestm1,Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example if 1 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg1 timing" "0,1,2,3"
newline
bitfld.word 0x00 0.--1. "DfiWrDestm0,Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example if 0 dfi_wrdata_cs_n_p0[0] will use Register TxDq DqsDlyTg0 timing" "0,1,2,3"
group.word 0x60018A++0x01
line.word 0x00 "PllCtrl2_p3,PState dependent PLL Control Register 2"
bitfld.word 0x00 0.--4. "PllFreqSel,Adjusts the loop parameters to compensate for different VCO bias points and input/output clock division ratios" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x60018E++0x01
line.word 0x00 "PllCtrl1_p3,PState dependent PLL Control Register 1"
bitfld.word 0x00 5.--8. "PllCpPropCtrl,connects directly to cp_prop_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--4. "PllCpIntCtrl,connects directly to cp_int_cntrl<1:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x600194++0x01
line.word 0x00 "PllTestMode_p3,Additional controls for PLL CP/VCO modes of operation"
hexmask.word 0x00 0.--15. 1. "PllTestMode_p3,It is required to use default values for this CSR unless directed otherwise by Synopsys"
group.word 0x600198++0x01
line.word 0x00 "PllCtrl4_p3,PState dependent PLL Control Register 4"
bitfld.word 0x00 5.--8. "PllCpPropGsCtrl,connects directly to cp_prop_gs_cntrl<3:0> of PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--4. "PllCpIntGsCtrl,connects directly to cp_int_gs_cntrl<4:0> in PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x6001F4++0x01
line.word 0x00 "DfiFreqRatio_p3,DFI Frequency Ratio"
bitfld.word 0x00 0.--1. "DfiFreqRatio_p3,Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals" "0: 1:1 mode,1: 1:2 mode 1x = 1:4,?..."
tree.end
tree "EARC"
base ad:0x30CC0000
group.long 0x00++0x03
line.long 0x00 "VERSION,Version control register"
hexmask.long 0x00 0.--31. 1. "VERID,Version ID"
group.long 0x10++0x03
line.long 0x00 "EXT_CTRL,External control register"
bitfld.long 0x00 31. "CORE_RESET,M0+ Reset" "0,1"
bitfld.long 0x00 30. "RX_CMDC_RESET,Soft reset to the eARC Common mode Receiver" "0,1"
newline
bitfld.long 0x00 29. "TX_CMDC_RESET,Soft reset to the eARC Common mode Transmitter" "0,1"
bitfld.long 0x00 28. "RX_DPATH_RESET,Soft reset to the eARC Differential data Receiver" "0,1"
newline
bitfld.long 0x00 27. "TX_DPATH_RESET,Soft reset to the Datapath for Transmit" "0,1"
bitfld.long 0x00 25. "SDMA_RD_REQ_DIS,SDMA RD REQ disable" "0,1"
newline
bitfld.long 0x00 24. "SDMA_WR_REQ_DIS,SDMA WR REQ disable" "0,1"
bitfld.long 0x00 23. "SPDIF_MODE,Indicates SPDIF output mode" "0,1"
newline
bitfld.long 0x00 22. "CORE_WAIT,Stop executing code" "0,1"
bitfld.long 0x00 21. "CORE_SLEEP_HOLD_REQ_B,Hold core from going to sleep mode when 0" "0,1"
newline
bitfld.long 0x00 16.--19. "PAGE,Page Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "FABRIC_RR_SEL,Selects Arbitration mode of crossbar switch" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "RX_FIFO_WMARK,Audio Receive FIFO Watermark Level"
hexmask.long.byte 0x00 0.--6. 1. "TX_FIFO_WMARK,Audio Transmit FIFO Watermark Level"
group.long 0x14++0x03
line.long 0x00 "EXT_CTRL_SET,External control register"
bitfld.long 0x00 31. "CORE_RESET,M0+ Reset" "0,1"
bitfld.long 0x00 30. "RX_CMDC_RESET,Soft reset to the eARC Common mode Receiver" "0,1"
newline
bitfld.long 0x00 29. "TX_CMDC_RESET,Soft reset to the eARC Common mode Transmitter" "0,1"
bitfld.long 0x00 28. "RX_DPATH_RESET,Soft reset to the eARC Differential data Receiver" "0,1"
newline
bitfld.long 0x00 27. "TX_DPATH_RESET,Soft reset to the Datapath for Transmit" "0,1"
bitfld.long 0x00 25. "SDMA_RD_REQ_DIS,SDMA RD REQ disable" "0,1"
newline
bitfld.long 0x00 24. "SDMA_WR_REQ_DIS,SDMA WR REQ disable" "0,1"
bitfld.long 0x00 23. "SPDIF_MODE,Indicates SPDIF output mode" "0,1"
newline
bitfld.long 0x00 22. "CORE_WAIT,Stop executing code" "0,1"
bitfld.long 0x00 21. "CORE_SLEEP_HOLD_REQ_B,Hold core from going to sleep mode when 0" "0,1"
newline
bitfld.long 0x00 16.--19. "PAGE,Page Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "FABRIC_RR_SEL,Selects Arbitration mode of crossbar switch" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "RX_FIFO_WMARK,Audio Receive FIFO Watermark Level"
hexmask.long.byte 0x00 0.--6. 1. "TX_FIFO_WMARK,Audio Transmit FIFO Watermark Level"
group.long 0x18++0x03
line.long 0x00 "EXT_CTRL_CLR,External control register"
eventfld.long 0x00 31. "CORE_RESET,M0+ Reset" "0,1"
eventfld.long 0x00 30. "RX_CMDC_RESET,Soft reset to the eARC Common mode Receiver" "0,1"
newline
eventfld.long 0x00 29. "TX_CMDC_RESET,Soft reset to the eARC Common mode Transmitter" "0,1"
eventfld.long 0x00 28. "RX_DPATH_RESET,Soft reset to the eARC Differential data Receiver" "0,1"
newline
eventfld.long 0x00 27. "TX_DPATH_RESET,Soft reset to the Datapath for Transmit" "0,1"
eventfld.long 0x00 25. "SDMA_RD_REQ_DIS,SDMA RD REQ disable" "0,1"
newline
eventfld.long 0x00 24. "SDMA_WR_REQ_DIS,SDMA WR REQ disable" "0,1"
eventfld.long 0x00 23. "SPDIF_MODE,Indicates SPDIF output mode" "0,1"
newline
eventfld.long 0x00 22. "CORE_WAIT,Stop executing code" "0,1"
eventfld.long 0x00 21. "CORE_SLEEP_HOLD_REQ_B,Hold core from going to sleep mode when 0" "0,1"
newline
eventfld.long 0x00 16.--19. "PAGE,Page Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
eventfld.long 0x00 15. "FABRIC_RR_SEL,Selects Arbitration mode of crossbar switch" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "RX_FIFO_WMARK,Audio Receive FIFO Watermark Level"
hexmask.long.byte 0x00 0.--6. 1. "TX_FIFO_WMARK,Audio Transmit FIFO Watermark Level"
group.long 0x1C++0x03
line.long 0x00 "EXT_CTRL_TOG,External control register"
bitfld.long 0x00 31. "CORE_RESET,M0+ Reset" "0,1"
bitfld.long 0x00 30. "RX_CMDC_RESET,Soft reset to the eARC Common mode Receiver" "0,1"
newline
bitfld.long 0x00 29. "TX_CMDC_RESET,Soft reset to the eARC Common mode Transmitter" "0,1"
bitfld.long 0x00 28. "RX_DPATH_RESET,Soft reset to the eARC Differential data Receiver" "0,1"
newline
bitfld.long 0x00 27. "TX_DPATH_RESET,Soft reset to the Datapath for Transmit" "0,1"
bitfld.long 0x00 25. "SDMA_RD_REQ_DIS,SDMA RD REQ disable" "0,1"
newline
bitfld.long 0x00 24. "SDMA_WR_REQ_DIS,SDMA WR REQ disable" "0,1"
bitfld.long 0x00 23. "SPDIF_MODE,Indicates SPDIF output mode" "0,1"
newline
bitfld.long 0x00 22. "CORE_WAIT,Stop executing code" "0,1"
bitfld.long 0x00 21. "CORE_SLEEP_HOLD_REQ_B,Hold core from going to sleep mode when 0" "0,1"
newline
bitfld.long 0x00 16.--19. "PAGE,Page Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "FABRIC_RR_SEL,Selects Arbitration mode of crossbar switch" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "RX_FIFO_WMARK,Audio Receive FIFO Watermark Level"
hexmask.long.byte 0x00 0.--6. 1. "TX_FIFO_WMARK,Audio Transmit FIFO Watermark Level"
group.long 0x20++0x03
line.long 0x00 "EXT_STATUS,External Status register"
rbitfld.long 0x00 31. "HPD_I,HPD Input status" "0,1"
bitfld.long 0x00 30. "NEW_UD6_REC,New user data" "0,1"
newline
bitfld.long 0x00 29. "NEW_UD5_REC,New user data" "0,1"
bitfld.long 0x00 28. "NEW_UD4_REC,New user data" "0,1"
newline
bitfld.long 0x00 27. "HEARTBEAT_STATUS,Earc Connection Status" "0,1"
bitfld.long 0x00 25. "RX_CMDC_COMMA_TO,Receiver CMDC comma timeout Interrupt" "0,1"
newline
eventfld.long 0x00 23. "RX_CMDC_RESP_TO,CMDC Response not sent in programmed time" "0,1"
rbitfld.long 0x00 21. "TX_PIPE_EMPTY,Indicates TX pipe status" "0,1"
newline
rbitfld.long 0x00 18. "CM0_SLEEP_HOLD_ACK_B,Sleep extension acknowledge" "0,1"
rbitfld.long 0x00 17. "CM0_DEEP_SLEEP,CM0 is in deep sleep mode" "0,1"
newline
rbitfld.long 0x00 16. "CM0_SLEEPING,CM0 is in Sleep mode" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "NO_RX_FIFO_ENTRIES,RX FIFO entries"
newline
hexmask.long.byte 0x00 0.--7. 1. "NO_TX_FIFO_ENTRIES,TX FIFO entries"
group.long 0x24++0x03
line.long 0x00 "EXT_STATUS_SET,External Status register"
rbitfld.long 0x00 31. "HPD_I,HPD Input status" "0,1"
bitfld.long 0x00 30. "NEW_UD6_REC,New user data" "0,1"
newline
bitfld.long 0x00 29. "NEW_UD5_REC,New user data" "0,1"
bitfld.long 0x00 28. "NEW_UD4_REC,New user data" "0,1"
newline
bitfld.long 0x00 27. "HEARTBEAT_STATUS,Earc Connection Status" "0,1"
bitfld.long 0x00 25. "RX_CMDC_COMMA_TO,Receiver CMDC comma timeout Interrupt" "0,1"
newline
bitfld.long 0x00 23. "RX_CMDC_RESP_TO,CMDC Response not sent in programmed time" "0,1"
rbitfld.long 0x00 21. "TX_PIPE_EMPTY,Indicates TX pipe status" "0,1"
newline
rbitfld.long 0x00 18. "CM0_SLEEP_HOLD_ACK_B,Sleep extension acknowledge" "0,1"
rbitfld.long 0x00 17. "CM0_DEEP_SLEEP,CM0 is in deep sleep mode" "0,1"
newline
rbitfld.long 0x00 16. "CM0_SLEEPING,CM0 is in Sleep mode" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "NO_RX_FIFO_ENTRIES,RX FIFO entries"
newline
hexmask.long.byte 0x00 0.--7. 1. "NO_TX_FIFO_ENTRIES,TX FIFO entries"
group.long 0x28++0x03
line.long 0x00 "EXT_STATUS_CLR,External Status register"
eventfld.long 0x00 31. "HPD_I,HPD Input status" "0,1"
eventfld.long 0x00 30. "NEW_UD6_REC,New user data" "0,1"
newline
eventfld.long 0x00 29. "NEW_UD5_REC,New user data" "0,1"
eventfld.long 0x00 28. "NEW_UD4_REC,New user data" "0,1"
newline
eventfld.long 0x00 27. "HEARTBEAT_STATUS,Earc Connection Status" "0,1"
eventfld.long 0x00 25. "RX_CMDC_COMMA_TO,Receiver CMDC comma timeout Interrupt" "0,1"
newline
eventfld.long 0x00 23. "RX_CMDC_RESP_TO,CMDC Response not sent in programmed time" "0,1"
eventfld.long 0x00 21. "TX_PIPE_EMPTY,Indicates TX pipe status" "0,1"
newline
eventfld.long 0x00 18. "CM0_SLEEP_HOLD_ACK_B,Sleep extension acknowledge" "0,1"
eventfld.long 0x00 17. "CM0_DEEP_SLEEP,CM0 is in deep sleep mode" "0,1"
newline
eventfld.long 0x00 16. "CM0_SLEEPING,CM0 is in Sleep mode" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "NO_RX_FIFO_ENTRIES,RX FIFO entries"
newline
hexmask.long.byte 0x00 0.--7. 1. "NO_TX_FIFO_ENTRIES,TX FIFO entries"
group.long 0x2C++0x03
line.long 0x00 "EXT_STATUS_TOG,External Status register"
rbitfld.long 0x00 31. "HPD_I,HPD Input status" "0,1"
bitfld.long 0x00 30. "NEW_UD6_REC,New user data" "0,1"
newline
bitfld.long 0x00 29. "NEW_UD5_REC,New user data" "0,1"
bitfld.long 0x00 28. "NEW_UD4_REC,New user data" "0,1"
newline
bitfld.long 0x00 27. "HEARTBEAT_STATUS,Earc Connection Status" "0,1"
bitfld.long 0x00 25. "RX_CMDC_COMMA_TO,Receiver CMDC comma timeout Interrupt" "0,1"
newline
bitfld.long 0x00 23. "RX_CMDC_RESP_TO,CMDC Response not sent in programmed time" "0,1"
rbitfld.long 0x00 21. "TX_PIPE_EMPTY,Indicates TX pipe status" "0,1"
newline
rbitfld.long 0x00 18. "CM0_SLEEP_HOLD_ACK_B,Sleep extension acknowledge" "0,1"
rbitfld.long 0x00 17. "CM0_DEEP_SLEEP,CM0 is in deep sleep mode" "0,1"
newline
rbitfld.long 0x00 16. "CM0_SLEEPING,CM0 is in Sleep mode" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "NO_RX_FIFO_ENTRIES,RX FIFO entries"
newline
hexmask.long.byte 0x00 0.--7. 1. "NO_TX_FIFO_ENTRIES,TX FIFO entries"
group.long 0x30++0x03
line.long 0x00 "EXT_IER0,Interrupt enables for interrupt 0"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_0,Spare interrupts"
bitfld.long 0x00 22. "CH_UD_OFLOW_IE_0,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "ARC_MODE_IE_0,Interrupt to indicate ARC mode setup" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC_IE_0,Interrupt enable for Unexpected preamble received" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_IE_0,Interrupt enable for preamble match received" "0,1"
bitfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_0,Bi-phase mark encoding error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ_IE_0,Request to write data to FIFO" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ_IE_0,Request to read data from FIFO" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_IE_0,Update request for chip temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_0,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG_IE_0,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_0,Indicates DMAC format change was detected" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_0,Indicates no DMAC data is received" "0,1"
bitfld.long 0x00 8. "OHPD_IE_0,Output HPD interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP_IE_0,Host wakeup on CEC match interrupt enable" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_0,Receive FIFO overflow error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_0,Preamble mismatch interrupt enable" "0,1"
bitfld.long 0x00 4. "ECC_ERR_IE_0,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMDC_RESP_TO_IE_0,Receiver CMDC data response timeout interrupt enable" "0,1"
bitfld.long 0x00 2. "MUTE_IE_0,Enable for Mute detected interrupt" "0,1"
newline
bitfld.long 0x00 1. "NEW_UD_IE_0,Enable for new user data received interrupt" "0,1"
bitfld.long 0x00 0. "NEW_CS_IE_0,Enable for New channel status block received interrupt" "0,1"
group.long 0x34++0x03
line.long 0x00 "EXT_IER0_SET,Interrupt enables for interrupt 0"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_0,Spare interrupts"
bitfld.long 0x00 22. "CH_UD_OFLOW_IE_0,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "ARC_MODE_IE_0,Interrupt to indicate ARC mode setup" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC_IE_0,Interrupt enable for Unexpected preamble received" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_IE_0,Interrupt enable for preamble match received" "0,1"
bitfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_0,Bi-phase mark encoding error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ_IE_0,Request to write data to FIFO" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ_IE_0,Request to read data from FIFO" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_IE_0,Update request for chip temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_0,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG_IE_0,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_0,Indicates DMAC format change was detected" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_0,Indicates no DMAC data is received" "0,1"
bitfld.long 0x00 8. "OHPD_IE_0,Output HPD interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP_IE_0,Host wakeup on CEC match interrupt enable" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_0,Receive FIFO overflow error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_0,Preamble mismatch interrupt enable" "0,1"
bitfld.long 0x00 4. "ECC_ERR_IE_0,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMDC_RESP_TO_IE_0,Receiver CMDC data response timeout interrupt enable" "0,1"
bitfld.long 0x00 2. "MUTE_IE_0,Enable for Mute detected interrupt" "0,1"
newline
bitfld.long 0x00 1. "NEW_UD_IE_0,Enable for new user data received interrupt" "0,1"
bitfld.long 0x00 0. "NEW_CS_IE_0,Enable for New channel status block received interrupt" "0,1"
group.long 0x38++0x03
line.long 0x00 "EXT_IER0_CLR,Interrupt enables for interrupt 0"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_0,Spare interrupts"
eventfld.long 0x00 22. "CH_UD_OFLOW_IE_0,Channel status or used data could not be stored" "0,1"
newline
eventfld.long 0x00 21. "ARC_MODE_IE_0,Interrupt to indicate ARC mode setup" "0,1"
eventfld.long 0x00 20. "UNEXP_PRE_REC_IE_0,Interrupt enable for Unexpected preamble received" "0,1"
newline
eventfld.long 0x00 19. "B_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
eventfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
eventfld.long 0x00 17. "PREAMBLE_MATCH_IE_0,Interrupt enable for preamble match received" "0,1"
eventfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_0,Bi-phase mark encoding error" "0,1"
newline
eventfld.long 0x00 15. "DMA_WR_REQ_IE_0,Request to write data to FIFO" "0,1"
eventfld.long 0x00 14. "DMA_RD_REQ_IE_0,Request to read data from FIFO" "0,1"
newline
eventfld.long 0x00 13. "TEMP_UPDATE_IE_0,Update request for chip temperature value" "0,1"
eventfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_0,Interrupt enable for CMDC status register update" "0,1"
newline
eventfld.long 0x00 11. "HB_STATE_CHG_IE_0,Interrupt enable for Heartbeat status change" "0,1"
eventfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_0,Indicates DMAC format change was detected" "0,1"
newline
eventfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_0,Indicates no DMAC data is received" "0,1"
eventfld.long 0x00 8. "OHPD_IE_0,Output HPD interrupt enable" "0,1"
newline
eventfld.long 0x00 7. "HOST_WAKEUP_IE_0,Host wakeup on CEC match interrupt enable" "0,1"
eventfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_0,Receive FIFO overflow error interrupt enable" "0,1"
newline
eventfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_0,Preamble mismatch interrupt enable" "0,1"
eventfld.long 0x00 4. "ECC_ERR_IE_0,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
eventfld.long 0x00 3. "CMDC_RESP_TO_IE_0,Receiver CMDC data response timeout interrupt enable" "0,1"
eventfld.long 0x00 2. "MUTE_IE_0,Enable for Mute detected interrupt" "0,1"
newline
eventfld.long 0x00 1. "NEW_UD_IE_0,Enable for new user data received interrupt" "0,1"
eventfld.long 0x00 0. "NEW_CS_IE_0,Enable for New channel status block received interrupt" "0,1"
group.long 0x3C++0x03
line.long 0x00 "EXT_IER0_TOG,Interrupt enables for interrupt 0"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_0,Spare interrupts"
bitfld.long 0x00 22. "CH_UD_OFLOW_IE_0,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "ARC_MODE_IE_0,Interrupt to indicate ARC mode setup" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC_IE_0,Interrupt enable for Unexpected preamble received" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_0,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_IE_0,Interrupt enable for preamble match received" "0,1"
bitfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_0,Bi-phase mark encoding error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ_IE_0,Request to write data to FIFO" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ_IE_0,Request to read data from FIFO" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_IE_0,Update request for chip temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_0,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG_IE_0,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_0,Indicates DMAC format change was detected" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_0,Indicates no DMAC data is received" "0,1"
bitfld.long 0x00 8. "OHPD_IE_0,Output HPD interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP_IE_0,Host wakeup on CEC match interrupt enable" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_0,Receive FIFO overflow error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_0,Preamble mismatch interrupt enable" "0,1"
bitfld.long 0x00 4. "ECC_ERR_IE_0,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMDC_RESP_TO_IE_0,Receiver CMDC data response timeout interrupt enable" "0,1"
bitfld.long 0x00 2. "MUTE_IE_0,Enable for Mute detected interrupt" "0,1"
newline
bitfld.long 0x00 1. "NEW_UD_IE_0,Enable for new user data received interrupt" "0,1"
bitfld.long 0x00 0. "NEW_CS_IE_0,Enable for New channel status block received interrupt" "0,1"
group.long 0x40++0x03
line.long 0x00 "EXT_IER1,Interrupt enables for interrupt 1"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_1,Spare interrupt enables"
bitfld.long 0x00 22. "CH_UD_OFLOW_IE_1,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "ARC_MODE_IE_1,Interrupt to indicate ARC mode setup" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC_IE_1,Interrupt enable for Unexpected preamble received" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_IE_1,Interrupt enable for preamble match received" "0,1"
bitfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_1,Bi-phase mark encoding error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ_IE_1,Request to write data to FIFO" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ_IE_1,Request to read data from FIFO" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_IE_1,Update request for chip temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_1,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG_IE_1,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_1,Indicates DMAC format change was detected" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_1,Indicates no DMAC data is received" "0,1"
bitfld.long 0x00 8. "OHPD_IE_1,Output HPD interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP_IE_1,Host wakeup on CEC match interrupt enable" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_1,Receive FIFO overflow error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_1,Preamble mismatch interrupt enable" "0,1"
bitfld.long 0x00 4. "ECC_ERR_IE_1,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMDC_RESP_TO_IE_1,Receiver CMDC data response timeout interrupt enable" "0,1"
bitfld.long 0x00 2. "MUTE_IE_1,Enable for Mute detected interrupt" "0,1"
newline
bitfld.long 0x00 1. "NEW_UD_IE_1,Enable for new user data received interrupt" "0,1"
bitfld.long 0x00 0. "NEW_CS_IE_1,Enable for New channel status block received interrupt" "0,1"
group.long 0x44++0x03
line.long 0x00 "EXT_IER1_SET,Interrupt enables for interrupt 1"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_1,Spare interrupt enables"
bitfld.long 0x00 22. "CH_UD_OFLOW_IE_1,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "ARC_MODE_IE_1,Interrupt to indicate ARC mode setup" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC_IE_1,Interrupt enable for Unexpected preamble received" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_IE_1,Interrupt enable for preamble match received" "0,1"
bitfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_1,Bi-phase mark encoding error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ_IE_1,Request to write data to FIFO" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ_IE_1,Request to read data from FIFO" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_IE_1,Update request for chip temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_1,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG_IE_1,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_1,Indicates DMAC format change was detected" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_1,Indicates no DMAC data is received" "0,1"
bitfld.long 0x00 8. "OHPD_IE_1,Output HPD interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP_IE_1,Host wakeup on CEC match interrupt enable" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_1,Receive FIFO overflow error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_1,Preamble mismatch interrupt enable" "0,1"
bitfld.long 0x00 4. "ECC_ERR_IE_1,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMDC_RESP_TO_IE_1,Receiver CMDC data response timeout interrupt enable" "0,1"
bitfld.long 0x00 2. "MUTE_IE_1,Enable for Mute detected interrupt" "0,1"
newline
bitfld.long 0x00 1. "NEW_UD_IE_1,Enable for new user data received interrupt" "0,1"
bitfld.long 0x00 0. "NEW_CS_IE_1,Enable for New channel status block received interrupt" "0,1"
group.long 0x48++0x03
line.long 0x00 "EXT_IER1_CLR,Interrupt enables for interrupt 1"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_1,Spare interrupt enables"
eventfld.long 0x00 22. "CH_UD_OFLOW_IE_1,Channel status or used data could not be stored" "0,1"
newline
eventfld.long 0x00 21. "ARC_MODE_IE_1,Interrupt to indicate ARC mode setup" "0,1"
eventfld.long 0x00 20. "UNEXP_PRE_REC_IE_1,Interrupt enable for Unexpected preamble received" "0,1"
newline
eventfld.long 0x00 19. "B_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
eventfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
eventfld.long 0x00 17. "PREAMBLE_MATCH_IE_1,Interrupt enable for preamble match received" "0,1"
eventfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_1,Bi-phase mark encoding error" "0,1"
newline
eventfld.long 0x00 15. "DMA_WR_REQ_IE_1,Request to write data to FIFO" "0,1"
eventfld.long 0x00 14. "DMA_RD_REQ_IE_1,Request to read data from FIFO" "0,1"
newline
eventfld.long 0x00 13. "TEMP_UPDATE_IE_1,Update request for chip temperature value" "0,1"
eventfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_1,Interrupt enable for CMDC status register update" "0,1"
newline
eventfld.long 0x00 11. "HB_STATE_CHG_IE_1,Interrupt enable for Heartbeat status change" "0,1"
eventfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_1,Indicates DMAC format change was detected" "0,1"
newline
eventfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_1,Indicates no DMAC data is received" "0,1"
eventfld.long 0x00 8. "OHPD_IE_1,Output HPD interrupt enable" "0,1"
newline
eventfld.long 0x00 7. "HOST_WAKEUP_IE_1,Host wakeup on CEC match interrupt enable" "0,1"
eventfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_1,Receive FIFO overflow error interrupt enable" "0,1"
newline
eventfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_1,Preamble mismatch interrupt enable" "0,1"
eventfld.long 0x00 4. "ECC_ERR_IE_1,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
eventfld.long 0x00 3. "CMDC_RESP_TO_IE_1,Receiver CMDC data response timeout interrupt enable" "0,1"
eventfld.long 0x00 2. "MUTE_IE_1,Enable for Mute detected interrupt" "0,1"
newline
eventfld.long 0x00 1. "NEW_UD_IE_1,Enable for new user data received interrupt" "0,1"
eventfld.long 0x00 0. "NEW_CS_IE_1,Enable for New channel status block received interrupt" "0,1"
group.long 0x4C++0x03
line.long 0x00 "EXT_IER1_TOG,Interrupt enables for interrupt 1"
hexmask.long.word 0x00 23.--31. 1. "SPARE_IE_1,Spare interrupt enables"
bitfld.long 0x00 22. "CH_UD_OFLOW_IE_1,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "ARC_MODE_IE_1,Interrupt to indicate ARC mode setup" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC_IE_1,Interrupt enable for Unexpected preamble received" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame B preamble mismatch received" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH_IE_1,Interrupt enable for sub-frame M/W preamble mismatch received" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_IE_1,Interrupt enable for preamble match received" "0,1"
bitfld.long 0x00 16. "DMAC_RX_BME_ERR_IE_1,Bi-phase mark encoding error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ_IE_1,Request to write data to FIFO" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ_IE_1,Request to read data from FIFO" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_IE_1,Update request for chip temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE_IE_1,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG_IE_1,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "DMAC_FMT_CHG_DET_IE_1,Indicates DMAC format change was detected" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC_IE_1,Indicates no DMAC data is received" "0,1"
bitfld.long 0x00 8. "OHPD_IE_1,Output HPD interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP_IE_1,Host wakeup on CEC match interrupt enable" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR_IE_1,Receive FIFO overflow error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH_IE_1,Preamble mismatch interrupt enable" "0,1"
bitfld.long 0x00 4. "ECC_ERR_IE_1,60958 Compressed data uncorrectable error interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMDC_RESP_TO_IE_1,Receiver CMDC data response timeout interrupt enable" "0,1"
bitfld.long 0x00 2. "MUTE_IE_1,Enable for Mute detected interrupt" "0,1"
newline
bitfld.long 0x00 1. "NEW_UD_IE_1,Enable for new user data received interrupt" "0,1"
bitfld.long 0x00 0. "NEW_CS_IE_1,Enable for New channel status block received interrupt" "0,1"
group.long 0x50++0x03
line.long 0x00 "EXT_ISR,External Interrupt Status register"
hexmask.long.word 0x00 23.--31. 1. "SPARE_INT,Extra interrupt"
bitfld.long 0x00 22. "CS_OR_UD_OFLOW,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "SEL_ARC_MODE,Set when CMDC SM falls out of eARC mode" "0,1"
eventfld.long 0x00 20. "UNEXP_PRE_REC,Set when DMAC preamble was received after unexpected number of input bits" "0,1"
newline
eventfld.long 0x00 19. "B_PRE_MISMATCH,Set when DMAC preamble of B has an error" "0,1"
eventfld.long 0x00 18. "M_W_PRE_MISMATCH,Set when DMAC preamble of M/W has an error" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_INT,Interrupt to indicate PA PB / DTC CD preamble match was detected" "0,1"
eventfld.long 0x00 16. "DMAC_BME_BIT_ERR,Set when DMAC BME data has an error" "0,1"
newline
eventfld.long 0x00 15. "DMA_WR_REQ,Set when DMA write request is asserted" "0,1"
eventfld.long 0x00 14. "DMA_RD_REQ,Set when DMA read request is asserted" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_INT,Interrupt to get the new temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG,Interrupt enable for Heartbeat status change" "0,1"
eventfld.long 0x00 10. "FMT_CHG_DET,Format change detect interrupt" "0,1"
newline
eventfld.long 0x00 9. "DMAC_NO_DATA_REC,No DMAC data is received for 1us" "0,1"
bitfld.long 0x00 8. "OHPD,HPD output driver" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP,Host wakeup on CEC OPCODE match interrupt" "0,1"
eventfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR,Receive FIFO overflow error interrupt" "0,1"
newline
eventfld.long 0x00 5. "PREAMBLE_MISMATCH,Preamble mismatch interrupt" "0,1"
eventfld.long 0x00 4. "ECC_ERR,60958 Compressed data uncorrectable error interrupt" "0,1"
newline
rbitfld.long 0x00 3. "CMDC_RESP_TO_ERR,CMDC response timeout interrupt" "0,1"
eventfld.long 0x00 2. "MUTE_DET,Interrupt to indicate HW mute bit was detected" "0,1"
newline
bitfld.long 0x00 1. "RX_NEW_USR_DATA,Received new User data Information" "0,1"
bitfld.long 0x00 0. "RX_NEW_CH_STAT,Received new channel status block" "0,1"
group.long 0x54++0x03
line.long 0x00 "EXT_ISR_SET,External Interrupt Status register"
hexmask.long.word 0x00 23.--31. 1. "SPARE_INT,Extra interrupt"
bitfld.long 0x00 22. "CS_OR_UD_OFLOW,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "SEL_ARC_MODE,Set when CMDC SM falls out of eARC mode" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC,Set when DMAC preamble was received after unexpected number of input bits" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH,Set when DMAC preamble of B has an error" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH,Set when DMAC preamble of M/W has an error" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_INT,Interrupt to indicate PA PB / DTC CD preamble match was detected" "0,1"
bitfld.long 0x00 16. "DMAC_BME_BIT_ERR,Set when DMAC BME data has an error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ,Set when DMA write request is asserted" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ,Set when DMA read request is asserted" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_INT,Interrupt to get the new temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "FMT_CHG_DET,Format change detect interrupt" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC,No DMAC data is received for 1us" "0,1"
bitfld.long 0x00 8. "OHPD,HPD output driver" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP,Host wakeup on CEC OPCODE match interrupt" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR,Receive FIFO overflow error interrupt" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH,Preamble mismatch interrupt" "0,1"
bitfld.long 0x00 4. "ECC_ERR,60958 Compressed data uncorrectable error interrupt" "0,1"
newline
rbitfld.long 0x00 3. "CMDC_RESP_TO_ERR,CMDC response timeout interrupt" "0,1"
bitfld.long 0x00 2. "MUTE_DET,Interrupt to indicate HW mute bit was detected" "0,1"
newline
bitfld.long 0x00 1. "RX_NEW_USR_DATA,Received new User data Information" "0,1"
bitfld.long 0x00 0. "RX_NEW_CH_STAT,Received new channel status block" "0,1"
group.long 0x58++0x03
line.long 0x00 "EXT_ISR_CLR,External Interrupt Status register"
hexmask.long.word 0x00 23.--31. 1. "SPARE_INT,Extra interrupt"
eventfld.long 0x00 22. "CS_OR_UD_OFLOW,Channel status or used data could not be stored" "0,1"
newline
eventfld.long 0x00 21. "SEL_ARC_MODE,Set when CMDC SM falls out of eARC mode" "0,1"
eventfld.long 0x00 20. "UNEXP_PRE_REC,Set when DMAC preamble was received after unexpected number of input bits" "0,1"
newline
eventfld.long 0x00 19. "B_PRE_MISMATCH,Set when DMAC preamble of B has an error" "0,1"
eventfld.long 0x00 18. "M_W_PRE_MISMATCH,Set when DMAC preamble of M/W has an error" "0,1"
newline
eventfld.long 0x00 17. "PREAMBLE_MATCH_INT,Interrupt to indicate PA PB / DTC CD preamble match was detected" "0,1"
eventfld.long 0x00 16. "DMAC_BME_BIT_ERR,Set when DMAC BME data has an error" "0,1"
newline
eventfld.long 0x00 15. "DMA_WR_REQ,Set when DMA write request is asserted" "0,1"
eventfld.long 0x00 14. "DMA_RD_REQ,Set when DMA read request is asserted" "0,1"
newline
eventfld.long 0x00 13. "TEMP_UPDATE_INT,Interrupt to get the new temperature value" "0,1"
eventfld.long 0x00 12. "CMDC_STATUS_UPDATE,Interrupt enable for CMDC status register update" "0,1"
newline
eventfld.long 0x00 11. "HB_STATE_CHG,Interrupt enable for Heartbeat status change" "0,1"
eventfld.long 0x00 10. "FMT_CHG_DET,Format change detect interrupt" "0,1"
newline
eventfld.long 0x00 9. "DMAC_NO_DATA_REC,No DMAC data is received for 1us" "0,1"
eventfld.long 0x00 8. "OHPD,HPD output driver" "0,1"
newline
eventfld.long 0x00 7. "HOST_WAKEUP,Host wakeup on CEC OPCODE match interrupt" "0,1"
eventfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR,Receive FIFO overflow error interrupt" "0,1"
newline
eventfld.long 0x00 5. "PREAMBLE_MISMATCH,Preamble mismatch interrupt" "0,1"
eventfld.long 0x00 4. "ECC_ERR,60958 Compressed data uncorrectable error interrupt" "0,1"
newline
eventfld.long 0x00 3. "CMDC_RESP_TO_ERR,CMDC response timeout interrupt" "0,1"
eventfld.long 0x00 2. "MUTE_DET,Interrupt to indicate HW mute bit was detected" "0,1"
newline
eventfld.long 0x00 1. "RX_NEW_USR_DATA,Received new User data Information" "0,1"
eventfld.long 0x00 0. "RX_NEW_CH_STAT,Received new channel status block" "0,1"
group.long 0x5C++0x03
line.long 0x00 "EXT_ISR_TOG,External Interrupt Status register"
hexmask.long.word 0x00 23.--31. 1. "SPARE_INT,Extra interrupt"
bitfld.long 0x00 22. "CS_OR_UD_OFLOW,Channel status or used data could not be stored" "0,1"
newline
bitfld.long 0x00 21. "SEL_ARC_MODE,Set when CMDC SM falls out of eARC mode" "0,1"
bitfld.long 0x00 20. "UNEXP_PRE_REC,Set when DMAC preamble was received after unexpected number of input bits" "0,1"
newline
bitfld.long 0x00 19. "B_PRE_MISMATCH,Set when DMAC preamble of B has an error" "0,1"
bitfld.long 0x00 18. "M_W_PRE_MISMATCH,Set when DMAC preamble of M/W has an error" "0,1"
newline
bitfld.long 0x00 17. "PREAMBLE_MATCH_INT,Interrupt to indicate PA PB / DTC CD preamble match was detected" "0,1"
bitfld.long 0x00 16. "DMAC_BME_BIT_ERR,Set when DMAC BME data has an error" "0,1"
newline
bitfld.long 0x00 15. "DMA_WR_REQ,Set when DMA write request is asserted" "0,1"
bitfld.long 0x00 14. "DMA_RD_REQ,Set when DMA read request is asserted" "0,1"
newline
bitfld.long 0x00 13. "TEMP_UPDATE_INT,Interrupt to get the new temperature value" "0,1"
bitfld.long 0x00 12. "CMDC_STATUS_UPDATE,Interrupt enable for CMDC status register update" "0,1"
newline
bitfld.long 0x00 11. "HB_STATE_CHG,Interrupt enable for Heartbeat status change" "0,1"
bitfld.long 0x00 10. "FMT_CHG_DET,Format change detect interrupt" "0,1"
newline
bitfld.long 0x00 9. "DMAC_NO_DATA_REC,No DMAC data is received for 1us" "0,1"
bitfld.long 0x00 8. "OHPD,HPD output driver" "0,1"
newline
bitfld.long 0x00 7. "HOST_WAKEUP,Host wakeup on CEC OPCODE match interrupt" "0,1"
bitfld.long 0x00 6. "FIFO_OFLOW_UFLOW_ERR,Receive FIFO overflow error interrupt" "0,1"
newline
bitfld.long 0x00 5. "PREAMBLE_MISMATCH,Preamble mismatch interrupt" "0,1"
bitfld.long 0x00 4. "ECC_ERR,60958 Compressed data uncorrectable error interrupt" "0,1"
newline
rbitfld.long 0x00 3. "CMDC_RESP_TO_ERR,CMDC response timeout interrupt" "0,1"
bitfld.long 0x00 2. "MUTE_DET,Interrupt to indicate HW mute bit was detected" "0,1"
newline
bitfld.long 0x00 1. "RX_NEW_USR_DATA,Received new User data Information" "0,1"
bitfld.long 0x00 0. "RX_NEW_CH_STAT,Received new channel status block" "0,1"
group.long 0x70++0x03
line.long 0x00 "IER,Interrupt enable register for M0+"
bitfld.long 0x00 25. "TEMP_UPDATED_IE,Interrupt enable to allow SW to indicate new temperature value is available" "0,1"
bitfld.long 0x00 24. "SW_HPD_TGL_IE,Interrupt enable to allow SW to assert HPD" "0,1"
newline
bitfld.long 0x00 23. "SET_ARC_SE_IE,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
bitfld.long 0x00 22. "SET_ARC_CM_IE,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
bitfld.long 0x00 21. "SET_SPDIF_TX_IE,Interrupt enable to set up SPDIF TX mode" "0,1"
bitfld.long 0x00 20. "SET_SPDIF_RX_IE,Interrupt enable to set up SPDIF RX mode" "0,1"
newline
bitfld.long 0x00 19. "DMAC_SPARE_IE,Spare Interrupt" "0,1"
bitfld.long 0x00 18. "FMT_CHG_IE,Format Chnage interrupt" "0,1"
newline
bitfld.long 0x00 17. "DATA_BLK_REC_IE,60958 block of data received interrupt enable" "0,1"
bitfld.long 0x00 16. "PA_PB_DET_IE,PA PB detected in Compressed mode interrupt enable" "0,1"
newline
bitfld.long 0x00 15. "HPD_TGL_IE,HPD pin level change interrupt enable" "0,1"
bitfld.long 0x00 8. "CMDC_SPARE_IE,Spare Interrupt" "0,1"
newline
bitfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR_IE,Recevier mode Response timeout error interrupt enable" "0,1"
bitfld.long 0x00 0. "RX_CMDC_RX_DATA_IE,RX mode CMDC Receive data interrupt enable" "0,1"
group.long 0x74++0x03
line.long 0x00 "IER_SET,Interrupt enable register for M0+"
bitfld.long 0x00 25. "TEMP_UPDATED_IE,Interrupt enable to allow SW to indicate new temperature value is available" "0,1"
bitfld.long 0x00 24. "SW_HPD_TGL_IE,Interrupt enable to allow SW to assert HPD" "0,1"
newline
bitfld.long 0x00 23. "SET_ARC_SE_IE,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
bitfld.long 0x00 22. "SET_ARC_CM_IE,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
bitfld.long 0x00 21. "SET_SPDIF_TX_IE,Interrupt enable to set up SPDIF TX mode" "0,1"
bitfld.long 0x00 20. "SET_SPDIF_RX_IE,Interrupt enable to set up SPDIF RX mode" "0,1"
newline
bitfld.long 0x00 19. "DMAC_SPARE_IE,Spare Interrupt" "0,1"
bitfld.long 0x00 18. "FMT_CHG_IE,Format Chnage interrupt" "0,1"
newline
bitfld.long 0x00 17. "DATA_BLK_REC_IE,60958 block of data received interrupt enable" "0,1"
bitfld.long 0x00 16. "PA_PB_DET_IE,PA PB detected in Compressed mode interrupt enable" "0,1"
newline
bitfld.long 0x00 15. "HPD_TGL_IE,HPD pin level change interrupt enable" "0,1"
bitfld.long 0x00 8. "CMDC_SPARE_IE,Spare Interrupt" "0,1"
newline
bitfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR_IE,Recevier mode Response timeout error interrupt enable" "0,1"
bitfld.long 0x00 0. "RX_CMDC_RX_DATA_IE,RX mode CMDC Receive data interrupt enable" "0,1"
group.long 0x78++0x03
line.long 0x00 "IER_CLR,Interrupt enable register for M0+"
eventfld.long 0x00 25. "TEMP_UPDATED_IE,Interrupt enable to allow SW to indicate new temperature value is available" "0,1"
eventfld.long 0x00 24. "SW_HPD_TGL_IE,Interrupt enable to allow SW to assert HPD" "0,1"
newline
eventfld.long 0x00 23. "SET_ARC_SE_IE,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
eventfld.long 0x00 22. "SET_ARC_CM_IE,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
eventfld.long 0x00 21. "SET_SPDIF_TX_IE,Interrupt enable to set up SPDIF TX mode" "0,1"
eventfld.long 0x00 20. "SET_SPDIF_RX_IE,Interrupt enable to set up SPDIF RX mode" "0,1"
newline
eventfld.long 0x00 19. "DMAC_SPARE_IE,Spare Interrupt" "0,1"
eventfld.long 0x00 18. "FMT_CHG_IE,Format Chnage interrupt" "0,1"
newline
eventfld.long 0x00 17. "DATA_BLK_REC_IE,60958 block of data received interrupt enable" "0,1"
eventfld.long 0x00 16. "PA_PB_DET_IE,PA PB detected in Compressed mode interrupt enable" "0,1"
newline
eventfld.long 0x00 15. "HPD_TGL_IE,HPD pin level change interrupt enable" "0,1"
eventfld.long 0x00 8. "CMDC_SPARE_IE,Spare Interrupt" "0,1"
newline
eventfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR_IE,Recevier mode Response timeout error interrupt enable" "0,1"
eventfld.long 0x00 0. "RX_CMDC_RX_DATA_IE,RX mode CMDC Receive data interrupt enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "IER_TOG,Interrupt enable register for M0+"
bitfld.long 0x00 25. "TEMP_UPDATED_IE,Interrupt enable to allow SW to indicate new temperature value is available" "0,1"
bitfld.long 0x00 24. "SW_HPD_TGL_IE,Interrupt enable to allow SW to assert HPD" "0,1"
newline
bitfld.long 0x00 23. "SET_ARC_SE_IE,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
bitfld.long 0x00 22. "SET_ARC_CM_IE,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
bitfld.long 0x00 21. "SET_SPDIF_TX_IE,Interrupt enable to set up SPDIF TX mode" "0,1"
bitfld.long 0x00 20. "SET_SPDIF_RX_IE,Interrupt enable to set up SPDIF RX mode" "0,1"
newline
bitfld.long 0x00 19. "DMAC_SPARE_IE,Spare Interrupt" "0,1"
bitfld.long 0x00 18. "FMT_CHG_IE,Format Chnage interrupt" "0,1"
newline
bitfld.long 0x00 17. "DATA_BLK_REC_IE,60958 block of data received interrupt enable" "0,1"
bitfld.long 0x00 16. "PA_PB_DET_IE,PA PB detected in Compressed mode interrupt enable" "0,1"
newline
bitfld.long 0x00 15. "HPD_TGL_IE,HPD pin level change interrupt enable" "0,1"
bitfld.long 0x00 8. "CMDC_SPARE_IE,Spare Interrupt" "0,1"
newline
bitfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR_IE,Recevier mode Response timeout error interrupt enable" "0,1"
bitfld.long 0x00 0. "RX_CMDC_RX_DATA_IE,RX mode CMDC Receive data interrupt enable" "0,1"
group.long 0x80++0x03
line.long 0x00 "ISR,Interrupt status register"
bitfld.long 0x00 25. "TEMP_UPDATED,Interrupt to indicate new temperature value is available" "0,1"
bitfld.long 0x00 24. "SW_HPD_TGL_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
newline
bitfld.long 0x00 23. "SET_ARC_SE_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
bitfld.long 0x00 22. "SET_ARC_CM_INT,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
bitfld.long 0x00 21. "SET_SPDIF_TX_MODE,Interrupt to set up PHY and controller in SPDIF TX mode" "0,1"
bitfld.long 0x00 20. "SET_SPDIF_RX_MODE,Interrupt to set up PHY and controller in SPDIF RX mode" "0,1"
newline
bitfld.long 0x00 19. "DMAC_SPARE_INT,Spare Interrupt" "0,1"
eventfld.long 0x00 18. "FMT_CHG_INT,Format Change interrupt" "0,1"
newline
eventfld.long 0x00 17. "DATA_BLK_REC,60958 block of data received interrupt" "0,1"
eventfld.long 0x00 16. "PA_PB_DET,PA PB detected in Compressed mode" "0,1"
newline
eventfld.long 0x00 15. "HPD_TGL,HPD pin level change interrupt" "0,1"
bitfld.long 0x00 8. "CMDC_SPARE_INT,Spare Interrupt" "0,1"
newline
eventfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR,Recevier mode CMDC Response timeout error" "0,1"
eventfld.long 0x00 0. "RX_CMDC_RX_DATA,Receiver mode CMDC Receive data" "0,1"
group.long 0x84++0x03
line.long 0x00 "ISR_SET,Interrupt status register"
bitfld.long 0x00 25. "TEMP_UPDATED,Interrupt to indicate new temperature value is available" "0,1"
bitfld.long 0x00 24. "SW_HPD_TGL_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
newline
bitfld.long 0x00 23. "SET_ARC_SE_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
bitfld.long 0x00 22. "SET_ARC_CM_INT,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
bitfld.long 0x00 21. "SET_SPDIF_TX_MODE,Interrupt to set up PHY and controller in SPDIF TX mode" "0,1"
bitfld.long 0x00 20. "SET_SPDIF_RX_MODE,Interrupt to set up PHY and controller in SPDIF RX mode" "0,1"
newline
bitfld.long 0x00 19. "DMAC_SPARE_INT,Spare Interrupt" "0,1"
bitfld.long 0x00 18. "FMT_CHG_INT,Format Change interrupt" "0,1"
newline
bitfld.long 0x00 17. "DATA_BLK_REC,60958 block of data received interrupt" "0,1"
bitfld.long 0x00 16. "PA_PB_DET,PA PB detected in Compressed mode" "0,1"
newline
bitfld.long 0x00 15. "HPD_TGL,HPD pin level change interrupt" "0,1"
bitfld.long 0x00 8. "CMDC_SPARE_INT,Spare Interrupt" "0,1"
newline
bitfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR,Recevier mode CMDC Response timeout error" "0,1"
bitfld.long 0x00 0. "RX_CMDC_RX_DATA,Receiver mode CMDC Receive data" "0,1"
group.long 0x88++0x03
line.long 0x00 "ISR_CLR,Interrupt status register"
eventfld.long 0x00 25. "TEMP_UPDATED,Interrupt to indicate new temperature value is available" "0,1"
eventfld.long 0x00 24. "SW_HPD_TGL_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
newline
eventfld.long 0x00 23. "SET_ARC_SE_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
eventfld.long 0x00 22. "SET_ARC_CM_INT,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
eventfld.long 0x00 21. "SET_SPDIF_TX_MODE,Interrupt to set up PHY and controller in SPDIF TX mode" "0,1"
eventfld.long 0x00 20. "SET_SPDIF_RX_MODE,Interrupt to set up PHY and controller in SPDIF RX mode" "0,1"
newline
eventfld.long 0x00 19. "DMAC_SPARE_INT,Spare Interrupt" "0,1"
eventfld.long 0x00 18. "FMT_CHG_INT,Format Change interrupt" "0,1"
newline
eventfld.long 0x00 17. "DATA_BLK_REC,60958 block of data received interrupt" "0,1"
eventfld.long 0x00 16. "PA_PB_DET,PA PB detected in Compressed mode" "0,1"
newline
eventfld.long 0x00 15. "HPD_TGL,HPD pin level change interrupt" "0,1"
eventfld.long 0x00 8. "CMDC_SPARE_INT,Spare Interrupt" "0,1"
newline
eventfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR,Recevier mode CMDC Response timeout error" "0,1"
eventfld.long 0x00 0. "RX_CMDC_RX_DATA,Receiver mode CMDC Receive data" "0,1"
group.long 0x8C++0x03
line.long 0x00 "ISR_TOG,Interrupt status register"
bitfld.long 0x00 25. "TEMP_UPDATED,Interrupt to indicate new temperature value is available" "0,1"
bitfld.long 0x00 24. "SW_HPD_TGL_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
newline
bitfld.long 0x00 23. "SET_ARC_SE_INT,Interrupt enable to set up PHY as Single ended mode ARC receiver" "0,1"
bitfld.long 0x00 22. "SET_ARC_CM_INT,Interrupt enable to set up PHY as Common mode ARC receiver" "0,1"
newline
bitfld.long 0x00 21. "SET_SPDIF_TX_MODE,Interrupt to set up PHY and controller in SPDIF TX mode" "0,1"
bitfld.long 0x00 20. "SET_SPDIF_RX_MODE,Interrupt to set up PHY and controller in SPDIF RX mode" "0,1"
newline
bitfld.long 0x00 19. "DMAC_SPARE_INT,Spare Interrupt" "0,1"
bitfld.long 0x00 18. "FMT_CHG_INT,Format Change interrupt" "0,1"
newline
bitfld.long 0x00 17. "DATA_BLK_REC,60958 block of data received interrupt" "0,1"
bitfld.long 0x00 16. "PA_PB_DET,PA PB detected in Compressed mode" "0,1"
newline
bitfld.long 0x00 15. "HPD_TGL,HPD pin level change interrupt" "0,1"
bitfld.long 0x00 8. "CMDC_SPARE_INT,Spare Interrupt" "0,1"
newline
bitfld.long 0x00 2. "RX_CMDC_RESP_TO_ERR,Recevier mode CMDC Response timeout error" "0,1"
bitfld.long 0x00 0. "RX_CMDC_RX_DATA,Receiver mode CMDC Receive data" "0,1"
group.long 0x90++0x03
line.long 0x00 "PHY_AI_CTRL,AI interface control register"
bitfld.long 0x00 31. "AI_RWB,AI Read / write control bit" "0,1"
rbitfld.long 0x00 27. "TOG_DONE_1,AI toggle done bit" "0,1"
newline
bitfld.long 0x00 26. "TOG_1,AI toggle bit" "0,1"
rbitfld.long 0x00 25. "TOG_DONE_0,AI toggle done bit" "0,1"
newline
bitfld.long 0x00 24. "TOG_0,AI toggle bit" "0,1"
bitfld.long 0x00 15. "AI_RESETN,AI reset bit" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "AI_ADDR,AI ADDR value"
group.long 0x94++0x03
line.long 0x00 "PHY_AI_CTRL_SET,AI interface control register"
bitfld.long 0x00 31. "AI_RWB,AI Read / write control bit" "0,1"
rbitfld.long 0x00 27. "TOG_DONE_1,AI toggle done bit" "0,1"
newline
bitfld.long 0x00 26. "TOG_1,AI toggle bit" "0,1"
rbitfld.long 0x00 25. "TOG_DONE_0,AI toggle done bit" "0,1"
newline
bitfld.long 0x00 24. "TOG_0,AI toggle bit" "0,1"
bitfld.long 0x00 15. "AI_RESETN,AI reset bit" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "AI_ADDR,AI ADDR value"
group.long 0x98++0x03
line.long 0x00 "PHY_AI_CTRL_CLR,AI interface control register"
eventfld.long 0x00 31. "AI_RWB,AI Read / write control bit" "0,1"
eventfld.long 0x00 27. "TOG_DONE_1,AI toggle done bit" "0,1"
newline
eventfld.long 0x00 26. "TOG_1,AI toggle bit" "0,1"
eventfld.long 0x00 25. "TOG_DONE_0,AI toggle done bit" "0,1"
newline
eventfld.long 0x00 24. "TOG_0,AI toggle bit" "0,1"
eventfld.long 0x00 15. "AI_RESETN,AI reset bit" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "AI_ADDR,AI ADDR value"
group.long 0x9C++0x03
line.long 0x00 "PHY_AI_CTRL_TOG,AI interface control register"
bitfld.long 0x00 31. "AI_RWB,AI Read / write control bit" "0,1"
rbitfld.long 0x00 27. "TOG_DONE_1,AI toggle done bit" "0,1"
newline
bitfld.long 0x00 26. "TOG_1,AI toggle bit" "0,1"
rbitfld.long 0x00 25. "TOG_DONE_0,AI toggle done bit" "0,1"
newline
bitfld.long 0x00 24. "TOG_0,AI toggle bit" "0,1"
bitfld.long 0x00 15. "AI_RESETN,AI reset bit" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "AI_ADDR,AI ADDR value"
group.long 0xA0++0x03
line.long 0x00 "PHY_AI_WDATA,AI interface WDATA register"
hexmask.long 0x00 0.--31. 1. "WDATA,Write data"
rgroup.long 0xA4++0x03
line.long 0x00 "PHY_AI_RDATA,AI interface RDATA register"
hexmask.long 0x00 0.--31. 1. "RDATA,Read data"
rgroup.long 0xA8++0x03
line.long 0x00 "DPATH_STATUS,Audio XCVR datapath status"
hexmask.long.byte 0x00 8.--15. 1. "TX_FRM_CNT,Count of transmitted frames in a block"
hexmask.long.byte 0x00 0.--7. 1. "RX_FRM_CNT,Count of received frames in a block"
group.long 0xC0++0x03
line.long 0x00 "RX_CMDC_CTRL,CMDC receiver control register"
bitfld.long 0x00 31. "LBACK_EN,Loopback enable" "0,1"
bitfld.long 0x00 20.--22. "TX_DRIVE_STOP,Transmitter bus release time" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "TURNOVER_TIME,Minimum time before a response is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--12. "RESPONSE_TIME,Transmitter response timeout to a received message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7. "COMMA_EN,Enables COMMA pattern generation" "0,1"
bitfld.long 0x00 0.--4. "COMMA_BITS,Number of repeating bits in COMMA pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC4++0x03
line.long 0x00 "RX_CMDC_CTRL_SET,CMDC receiver control register"
bitfld.long 0x00 31. "LBACK_EN,Loopback enable" "0,1"
bitfld.long 0x00 20.--22. "TX_DRIVE_STOP,Transmitter bus release time" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "TURNOVER_TIME,Minimum time before a response is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--12. "RESPONSE_TIME,Transmitter response timeout to a received message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7. "COMMA_EN,Enables COMMA pattern generation" "0,1"
bitfld.long 0x00 0.--4. "COMMA_BITS,Number of repeating bits in COMMA pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC8++0x03
line.long 0x00 "RX_CMDC_CTRL_CLR,CMDC receiver control register"
eventfld.long 0x00 31. "LBACK_EN,Loopback enable" "0,1"
eventfld.long 0x00 20.--22. "TX_DRIVE_STOP,Transmitter bus release time" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 16.--19. "TURNOVER_TIME,Minimum time before a response is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
eventfld.long 0x00 8.--12. "RESPONSE_TIME,Transmitter response timeout to a received message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
eventfld.long 0x00 7. "COMMA_EN,Enables COMMA pattern generation" "0,1"
eventfld.long 0x00 0.--4. "COMMA_BITS,Number of repeating bits in COMMA pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xCC++0x03
line.long 0x00 "RX_CMDC_CTRL_TOG,CMDC receiver control register"
bitfld.long 0x00 31. "LBACK_EN,Loopback enable" "0,1"
bitfld.long 0x00 20.--22. "TX_DRIVE_STOP,Transmitter bus release time" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "TURNOVER_TIME,Minimum time before a response is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--12. "RESPONSE_TIME,Transmitter response timeout to a received message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7. "COMMA_EN,Enables COMMA pattern generation" "0,1"
bitfld.long 0x00 0.--4. "COMMA_BITS,Number of repeating bits in COMMA pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xD0++0x03
line.long 0x00 "RX_CMDC_STATUS,eARC receiver CMDC status"
bitfld.long 0x00 16.--19. "CMDC_STATE,Current state of the RX CDMC control state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE0++0x03
line.long 0x00 "RX_CMDC_TX_DATA,CMDC transmit data register"
bitfld.long 0x00 31. "DATA_VALID,Transmit Data Valid" "0,1"
hexmask.long 0x00 0.--25. 1. "TX_DATA,Transmit data"
rgroup.long 0xF0++0x03
line.long 0x00 "RX_CMDC_RX_DATA,CMDC receive data register"
hexmask.long 0x00 0.--25. 1. "RX_DATA,Receive data"
group.long 0x180++0x03
line.long 0x00 "RX_DATAPATH_CTRL,Data path control register"
bitfld.long 0x00 30.--31. "FSM,IEC60958-1 Frame Synchronization Mode" "0,1,2,3"
bitfld.long 0x00 29. "COMP,Compressed data search mode" "0,1"
newline
bitfld.long 0x00 28. "PRC,Process Compressed" "0,1"
bitfld.long 0x00 27. "LAYB_MODE,Layout B" "0,1"
newline
bitfld.long 0x00 26. "LAYB_CTRL,Layout B mode control" "0,1"
bitfld.long 0x00 25. "FMT_CHG_MODE,Format change detected" "0,1"
newline
bitfld.long 0x00 24. "FMT_CHG_CTRL,Format Change detection control" "0,1"
bitfld.long 0x00 23. "MUTE_MODE,Mute mode control" "0,1"
newline
bitfld.long 0x00 22. "MUTE_CTRL,M0+ mute request" "0,1"
bitfld.long 0x00 21. "BLKC,Block Compressed data" "0,1"
newline
bitfld.long 0x00 20. "DTS_CDS,Enable DTS CD 14 preamble search" "0,1"
bitfld.long 0x00 19. "PABS,Enable preamble search" "0,1"
newline
bitfld.long 0x00 14.--15. "RX_DATA_FMT,Indicates format of data stored in memory" "0,1,2,3"
bitfld.long 0x00 12. "CLR_RX_FIFO,Clear Receive FIFO" "0,1"
newline
bitfld.long 0x00 11. "CSA,Channel Status Acknowledge" "0,1"
bitfld.long 0x00 10. "UDA,User Data Acknowledge" "0,1"
newline
bitfld.long 0x00 9. "CSR,Channel Status reset" "0,1"
bitfld.long 0x00 8. "UDR,User data reset" "0,1"
newline
bitfld.long 0x00 7. "EN_PARITY_CALC,Enable Parity calculation" "0,1"
bitfld.long 0x00 6. "STORE_FMT,Receive Data store format" "0,1"
newline
bitfld.long 0x00 5. "RST_PKT_CNT_FIFO,Resets the packet count fifo" "0,1"
bitfld.long 0x00 4. "EN_COMP_PARITY_CALC,RX_DATAPATH: Enable Compressed mode Parity calculation" "0,1"
newline
bitfld.long 0x00 3. "ECC_VUC_BITS_EN,RX_DATAPATH: Enable VUC bit replacement after ECC correction" "0,1"
rbitfld.long 0x00 0. "PAPB_FIFO_STATUS,This bit is an empty fifo indicator for PaPb match" "0,1"
group.long 0x184++0x03
line.long 0x00 "RX_DATAPATH_CTRL_SET,Data path control register"
bitfld.long 0x00 30.--31. "FSM,IEC60958-1 Frame Synchronization Mode" "0,1,2,3"
bitfld.long 0x00 29. "COMP,Compressed data search mode" "0,1"
newline
bitfld.long 0x00 28. "PRC,Process Compressed" "0,1"
bitfld.long 0x00 27. "LAYB_MODE,Layout B" "0,1"
newline
bitfld.long 0x00 26. "LAYB_CTRL,Layout B mode control" "0,1"
bitfld.long 0x00 25. "FMT_CHG_MODE,Format change detected" "0,1"
newline
bitfld.long 0x00 24. "FMT_CHG_CTRL,Format Change detection control" "0,1"
bitfld.long 0x00 23. "MUTE_MODE,Mute mode control" "0,1"
newline
bitfld.long 0x00 22. "MUTE_CTRL,M0+ mute request" "0,1"
bitfld.long 0x00 21. "BLKC,Block Compressed data" "0,1"
newline
bitfld.long 0x00 20. "DTS_CDS,Enable DTS CD 14 preamble search" "0,1"
bitfld.long 0x00 19. "PABS,Enable preamble search" "0,1"
newline
bitfld.long 0x00 14.--15. "RX_DATA_FMT,Indicates format of data stored in memory" "0,1,2,3"
bitfld.long 0x00 12. "CLR_RX_FIFO,Clear Receive FIFO" "0,1"
newline
bitfld.long 0x00 11. "CSA,Channel Status Acknowledge" "0,1"
bitfld.long 0x00 10. "UDA,User Data Acknowledge" "0,1"
newline
bitfld.long 0x00 9. "CSR,Channel Status reset" "0,1"
bitfld.long 0x00 8. "UDR,User data reset" "0,1"
newline
bitfld.long 0x00 7. "EN_PARITY_CALC,Enable Parity calculation" "0,1"
bitfld.long 0x00 6. "STORE_FMT,Receive Data store format" "0,1"
newline
bitfld.long 0x00 5. "RST_PKT_CNT_FIFO,Resets the packet count fifo" "0,1"
bitfld.long 0x00 4. "EN_COMP_PARITY_CALC,RX_DATAPATH: Enable Compressed mode Parity calculation" "0,1"
newline
bitfld.long 0x00 3. "ECC_VUC_BITS_EN,RX_DATAPATH: Enable VUC bit replacement after ECC correction" "0,1"
rbitfld.long 0x00 0. "PAPB_FIFO_STATUS,This bit is an empty fifo indicator for PaPb match" "0,1"
group.long 0x188++0x03
line.long 0x00 "RX_DATAPATH_CTRL_CLR,Data path control register"
eventfld.long 0x00 30.--31. "FSM,IEC60958-1 Frame Synchronization Mode" "0,1,2,3"
eventfld.long 0x00 29. "COMP,Compressed data search mode" "0,1"
newline
eventfld.long 0x00 28. "PRC,Process Compressed" "0,1"
eventfld.long 0x00 27. "LAYB_MODE,Layout B" "0,1"
newline
eventfld.long 0x00 26. "LAYB_CTRL,Layout B mode control" "0,1"
eventfld.long 0x00 25. "FMT_CHG_MODE,Format change detected" "0,1"
newline
eventfld.long 0x00 24. "FMT_CHG_CTRL,Format Change detection control" "0,1"
eventfld.long 0x00 23. "MUTE_MODE,Mute mode control" "0,1"
newline
eventfld.long 0x00 22. "MUTE_CTRL,M0+ mute request" "0,1"
eventfld.long 0x00 21. "BLKC,Block Compressed data" "0,1"
newline
eventfld.long 0x00 20. "DTS_CDS,Enable DTS CD 14 preamble search" "0,1"
eventfld.long 0x00 19. "PABS,Enable preamble search" "0,1"
newline
eventfld.long 0x00 14.--15. "RX_DATA_FMT,Indicates format of data stored in memory" "0,1,2,3"
eventfld.long 0x00 12. "CLR_RX_FIFO,Clear Receive FIFO" "0,1"
newline
eventfld.long 0x00 11. "CSA,Channel Status Acknowledge" "0,1"
eventfld.long 0x00 10. "UDA,User Data Acknowledge" "0,1"
newline
eventfld.long 0x00 9. "CSR,Channel Status reset" "0,1"
eventfld.long 0x00 8. "UDR,User data reset" "0,1"
newline
eventfld.long 0x00 7. "EN_PARITY_CALC,Enable Parity calculation" "0,1"
eventfld.long 0x00 6. "STORE_FMT,Receive Data store format" "0,1"
newline
eventfld.long 0x00 5. "RST_PKT_CNT_FIFO,Resets the packet count fifo" "0,1"
eventfld.long 0x00 4. "EN_COMP_PARITY_CALC,RX_DATAPATH: Enable Compressed mode Parity calculation" "0,1"
newline
eventfld.long 0x00 3. "ECC_VUC_BITS_EN,RX_DATAPATH: Enable VUC bit replacement after ECC correction" "0,1"
eventfld.long 0x00 0. "PAPB_FIFO_STATUS,This bit is an empty fifo indicator for PaPb match" "0,1"
group.long 0x18C++0x03
line.long 0x00 "RX_DATAPATH_CTRL_TOG,Data path control register"
bitfld.long 0x00 30.--31. "FSM,IEC60958-1 Frame Synchronization Mode" "0,1,2,3"
bitfld.long 0x00 29. "COMP,Compressed data search mode" "0,1"
newline
bitfld.long 0x00 28. "PRC,Process Compressed" "0,1"
bitfld.long 0x00 27. "LAYB_MODE,Layout B" "0,1"
newline
bitfld.long 0x00 26. "LAYB_CTRL,Layout B mode control" "0,1"
bitfld.long 0x00 25. "FMT_CHG_MODE,Format change detected" "0,1"
newline
bitfld.long 0x00 24. "FMT_CHG_CTRL,Format Change detection control" "0,1"
bitfld.long 0x00 23. "MUTE_MODE,Mute mode control" "0,1"
newline
bitfld.long 0x00 22. "MUTE_CTRL,M0+ mute request" "0,1"
bitfld.long 0x00 21. "BLKC,Block Compressed data" "0,1"
newline
bitfld.long 0x00 20. "DTS_CDS,Enable DTS CD 14 preamble search" "0,1"
bitfld.long 0x00 19. "PABS,Enable preamble search" "0,1"
newline
bitfld.long 0x00 14.--15. "RX_DATA_FMT,Indicates format of data stored in memory" "0,1,2,3"
bitfld.long 0x00 12. "CLR_RX_FIFO,Clear Receive FIFO" "0,1"
newline
bitfld.long 0x00 11. "CSA,Channel Status Acknowledge" "0,1"
bitfld.long 0x00 10. "UDA,User Data Acknowledge" "0,1"
newline
bitfld.long 0x00 9. "CSR,Channel Status reset" "0,1"
bitfld.long 0x00 8. "UDR,User data reset" "0,1"
newline
bitfld.long 0x00 7. "EN_PARITY_CALC,Enable Parity calculation" "0,1"
bitfld.long 0x00 6. "STORE_FMT,Receive Data store format" "0,1"
newline
bitfld.long 0x00 5. "RST_PKT_CNT_FIFO,Resets the packet count fifo" "0,1"
bitfld.long 0x00 4. "EN_COMP_PARITY_CALC,RX_DATAPATH: Enable Compressed mode Parity calculation" "0,1"
newline
bitfld.long 0x00 3. "ECC_VUC_BITS_EN,RX_DATAPATH: Enable VUC bit replacement after ECC correction" "0,1"
rbitfld.long 0x00 0. "PAPB_FIFO_STATUS,This bit is an empty fifo indicator for PaPb match" "0,1"
repeat 6. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x190)++0x03
line.long 0x00 "RX_CS_DATA_BITS_[$1],Channel staus bits $1"
hexmask.long 0x00 0.--31. 1. "CS_DATA,Channel Status bits"
repeat.end
repeat 6. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "RX_USER_DATA_BITS_[$1],User data bits $1"
hexmask.long 0x00 0.--31. 1. "U_DATA,User data bits"
repeat.end
group.long 0x1C0++0x03
line.long 0x00 "RX_DPATH_CNTR_CTRL,DMAC counter control register"
bitfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
bitfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
bitfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
bitfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
group.long 0x1C4++0x03
line.long 0x00 "RX_DPATH_CNTR_CTRL_SET,DMAC counter control register"
bitfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
bitfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
bitfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
bitfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
group.long 0x1C8++0x03
line.long 0x00 "RX_DPATH_CNTR_CTRL_CLR,DMAC counter control register"
eventfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
eventfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
eventfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
eventfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
group.long 0x1CC++0x03
line.long 0x00 "RX_DPATH_CNTR_CTRL_TOG,DMAC counter control register"
bitfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
bitfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
bitfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
bitfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
rgroup.long 0x1D0++0x03
line.long 0x00 "RX_DPATH_TSCR,Receive Datapath Timestamp Counter Register"
hexmask.long 0x00 0.--31. 1. "CVAL,Timestamp counter value"
rgroup.long 0x1D4++0x03
line.long 0x00 "RX_DPATH_BCR,Receive Datapath Bit counter register"
hexmask.long 0x00 0.--31. 1. "CVAL,Bit count value"
rgroup.long 0x1D8++0x03
line.long 0x00 "RX_DPATH_BCTR,Receive datapath Bit count timestamp register"
hexmask.long 0x00 0.--31. 1. "BCT_VAL,Bit count timestamp value"
rgroup.long 0x1DC++0x03
line.long 0x00 "RX_DPATH_BCRR,Receive datapath Bit read timestamp register"
hexmask.long 0x00 0.--31. 1. "BCT_VAL,Bit count timestamp value"
group.long 0x1E0++0x03
line.long 0x00 "DMAC_PRE_MATCH_VAL,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "PB_VAL,Preamble PB value"
group.long 0x1E4++0x03
line.long 0x00 "DMAC_PRE_MATCH_VAL_SET,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "PB_VAL,Preamble PB value"
group.long 0x1E8++0x03
line.long 0x00 "DMAC_PRE_MATCH_VAL_CLR,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "PB_VAL,Preamble PB value"
group.long 0x1EC++0x03
line.long 0x00 "DMAC_PRE_MATCH_VAL_TOG,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "PB_VAL,Preamble PB value"
group.long 0x1F0++0x03
line.long 0x00 "DMAC_DTS_PRE_MATCH_VAL,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "DTS_PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "DTS_PB_VAL,Preamble PB value"
group.long 0x1F4++0x03
line.long 0x00 "DMAC_DTS_PRE_MATCH_VAL_SET,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "DTS_PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "DTS_PB_VAL,Preamble PB value"
group.long 0x1F8++0x03
line.long 0x00 "DMAC_DTS_PRE_MATCH_VAL_CLR,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "DTS_PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "DTS_PB_VAL,Preamble PB value"
group.long 0x1FC++0x03
line.long 0x00 "DMAC_DTS_PRE_MATCH_VAL_TOG,Preamble match value register"
hexmask.long.word 0x00 16.--31. 1. "DTS_PA_VAL,Preamble PA value"
hexmask.long.word 0x00 0.--15. 1. "DTS_PB_VAL,Preamble PB value"
group.long 0x200++0x03
line.long 0x00 "RX_DPATH_PRE_ERR,Error count for IEC60958-1 Block Synchronization"
bitfld.long 0x00 31. "CLEAR,Clear bit for error counter" "0,1"
hexmask.long.word 0x00 0.--15. 1. "PRE_ERRS,Preamble Error counter"
group.long 0x204++0x03
line.long 0x00 "RX_DPATH_PARITY_ERR,Parity Error count for IEC60958-1 Blocks"
bitfld.long 0x00 31. "CLEAR,Clear bit for error counter" "0,1"
hexmask.long.word 0x00 0.--15. 1. "PRE_ERRS,Preamble Error counter"
rgroup.long 0x210++0x03
line.long 0x00 "RX_DPATH_PKT_CNT,Receive Data packet count"
hexmask.long 0x00 0.--30. 1. "VAL,Data packet counter"
rgroup.long 0x214++0x03
line.long 0x00 "RX_DPATH_ONE_BIT_ERR_CNT,Receive Data packet Corrected error count"
hexmask.long.word 0x00 0.--15. 1. "VAL,This status provides the number of single bit BCH errors corrected"
rgroup.long 0x218++0x03
line.long 0x00 "DMAC_PRE_MATCH_OFFSET,Preamble match offset value register"
hexmask.long 0x00 0.--31. 1. "PA_OFFSET,Sample count value for PA offset match"
group.long 0x220++0x03
line.long 0x00 "TX_DATAPATH_CTRL,Transmit Data path control register"
bitfld.long 0x00 14. "STRT_DATA_TX,Once Comma pattern is successively received and heartbeat is detected start TX of DMAC data" "0,1"
bitfld.long 0x00 12.--13. "TX_FORMAT,Transmit data format" "0,1,2,3"
newline
bitfld.long 0x00 11. "FRM_FMT,Frame format of input data" "0,1"
bitfld.long 0x00 10. "TX_CLK_RATE,This bit controls the TX clock rate" "0,1"
newline
bitfld.long 0x00 7. "EN_PREAMBLE,Enable preamble insertion" "0,1"
bitfld.long 0x00 6. "EN_PARITY,Enable parity insertion" "0,1"
newline
bitfld.long 0x00 5. "FRM_VLD,Valid bit value" "0,1"
bitfld.long 0x00 4. "VLD_MOD,Enable Valid bit insertion" "0,1"
newline
bitfld.long 0x00 3. "UD_MOD,Enable User Data insertion" "0,1"
bitfld.long 0x00 2. "CS_MOD,Enable Channel Status insertion" "0,1"
newline
bitfld.long 0x00 1. "UD_ACK,User Data ACK" "0,1"
bitfld.long 0x00 0. "CS_ACK,Channel Status ACK" "0,1"
group.long 0x224++0x03
line.long 0x00 "TX_DATAPATH_CTRL_SET,Transmit Data path control register"
bitfld.long 0x00 14. "STRT_DATA_TX,Once Comma pattern is successively received and heartbeat is detected start TX of DMAC data" "0,1"
bitfld.long 0x00 12.--13. "TX_FORMAT,Transmit data format" "0,1,2,3"
newline
bitfld.long 0x00 11. "FRM_FMT,Frame format of input data" "0,1"
bitfld.long 0x00 10. "TX_CLK_RATE,This bit controls the TX clock rate" "0,1"
newline
bitfld.long 0x00 7. "EN_PREAMBLE,Enable preamble insertion" "0,1"
bitfld.long 0x00 6. "EN_PARITY,Enable parity insertion" "0,1"
newline
bitfld.long 0x00 5. "FRM_VLD,Valid bit value" "0,1"
bitfld.long 0x00 4. "VLD_MOD,Enable Valid bit insertion" "0,1"
newline
bitfld.long 0x00 3. "UD_MOD,Enable User Data insertion" "0,1"
bitfld.long 0x00 2. "CS_MOD,Enable Channel Status insertion" "0,1"
newline
bitfld.long 0x00 1. "UD_ACK,User Data ACK" "0,1"
bitfld.long 0x00 0. "CS_ACK,Channel Status ACK" "0,1"
group.long 0x228++0x03
line.long 0x00 "TX_DATAPATH_CTRL_CLR,Transmit Data path control register"
eventfld.long 0x00 14. "STRT_DATA_TX,Once Comma pattern is successively received and heartbeat is detected start TX of DMAC data" "0,1"
eventfld.long 0x00 12.--13. "TX_FORMAT,Transmit data format" "0,1,2,3"
newline
eventfld.long 0x00 11. "FRM_FMT,Frame format of input data" "0,1"
eventfld.long 0x00 10. "TX_CLK_RATE,This bit controls the TX clock rate" "0,1"
newline
eventfld.long 0x00 7. "EN_PREAMBLE,Enable preamble insertion" "0,1"
eventfld.long 0x00 6. "EN_PARITY,Enable parity insertion" "0,1"
newline
eventfld.long 0x00 5. "FRM_VLD,Valid bit value" "0,1"
eventfld.long 0x00 4. "VLD_MOD,Enable Valid bit insertion" "0,1"
newline
eventfld.long 0x00 3. "UD_MOD,Enable User Data insertion" "0,1"
eventfld.long 0x00 2. "CS_MOD,Enable Channel Status insertion" "0,1"
newline
eventfld.long 0x00 1. "UD_ACK,User Data ACK" "0,1"
eventfld.long 0x00 0. "CS_ACK,Channel Status ACK" "0,1"
group.long 0x22C++0x03
line.long 0x00 "TX_DATAPATH_CTRL_TOG,Transmit Data path control register"
bitfld.long 0x00 14. "STRT_DATA_TX,Once Comma pattern is successively received and heartbeat is detected start TX of DMAC data" "0,1"
bitfld.long 0x00 12.--13. "TX_FORMAT,Transmit data format" "0,1,2,3"
newline
bitfld.long 0x00 11. "FRM_FMT,Frame format of input data" "0,1"
bitfld.long 0x00 10. "TX_CLK_RATE,This bit controls the TX clock rate" "0,1"
newline
bitfld.long 0x00 7. "EN_PREAMBLE,Enable preamble insertion" "0,1"
bitfld.long 0x00 6. "EN_PARITY,Enable parity insertion" "0,1"
newline
bitfld.long 0x00 5. "FRM_VLD,Valid bit value" "0,1"
bitfld.long 0x00 4. "VLD_MOD,Enable Valid bit insertion" "0,1"
newline
bitfld.long 0x00 3. "UD_MOD,Enable User Data insertion" "0,1"
bitfld.long 0x00 2. "CS_MOD,Enable Channel Status insertion" "0,1"
newline
bitfld.long 0x00 1. "UD_ACK,User Data ACK" "0,1"
bitfld.long 0x00 0. "CS_ACK,Channel Status ACK" "0,1"
repeat 6. (increment 0 1) (increment 0 0x04)
group.long ($2+0x230)++0x03
line.long 0x00 "TX_CS_DATA_BITS_[$1],Channel staus bits $1"
hexmask.long 0x00 0.--31. 1. "CS_DATA,Channel Status bits / block"
repeat.end
repeat 6. (increment 0 1) (increment 0 0x04)
group.long ($2+0x248)++0x03
line.long 0x00 "TX_USER_DATA_BITS_[$1],User data bits $1"
hexmask.long 0x00 0.--31. 1. "U_DATA,User data bits/block"
repeat.end
group.long 0x260++0x03
line.long 0x00 "TX_DPATH_CNTR_CTRL,DMAC counter control register"
bitfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
bitfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
bitfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
bitfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
group.long 0x264++0x03
line.long 0x00 "TX_DPATH_CNTR_CTRL_SET,DMAC counter control register"
bitfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
bitfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
bitfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
bitfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
group.long 0x268++0x03
line.long 0x00 "TX_DPATH_CNTR_CTRL_CLR,DMAC counter control register"
eventfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
eventfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
eventfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
eventfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
group.long 0x26C++0x03
line.long 0x00 "TX_DPATH_CNTR_CTRL_TOG,DMAC counter control register"
bitfld.long 0x00 9. "RST_TS_CNTR,Reset timestamp counter" "0,1"
bitfld.long 0x00 8. "RST_BIT_CNTR,Reset bit counter" "0,1"
newline
bitfld.long 0x00 1. "TS_INC,Timestamp Increment" "0,1"
bitfld.long 0x00 0. "TS_EN,Timestamp counter enable" "0,1"
rgroup.long 0x270++0x03
line.long 0x00 "TX_DPATH_TSCR,Transmit Datapath Timestamp Counter Register"
hexmask.long 0x00 0.--31. 1. "CVAL,Timestamp counter value"
rgroup.long 0x274++0x03
line.long 0x00 "TX_DPATH_BCR,Transmit Datapath Bit counter register"
hexmask.long 0x00 0.--31. 1. "CVAL,Bit count value"
rgroup.long 0x278++0x03
line.long 0x00 "TX_DPATH_BCTR,Transmit datapath Bit count timestamp register"
hexmask.long 0x00 0.--31. 1. "BCT_VAL,Bit count timestamp value"
rgroup.long 0x27C++0x03
line.long 0x00 "TX_DPATH_BCRR,Transmmit datapath Bit read timestamp register"
hexmask.long 0x00 0.--31. 1. "BCT_VAL,Bit count timestamp value"
group.long 0x2A0++0x03
line.long 0x00 "HPD_DBNC_CTRL,HPD Debounce Control Register"
hexmask.long 0x00 0.--31. 1. "VAL,HDP pin debounce interval"
group.long 0x2A4++0x03
line.long 0x00 "HPD_DBNC_CTRL_SET,HPD Debounce Control Register"
hexmask.long 0x00 0.--31. 1. "VAL,HDP pin debounce interval"
group.long 0x2A8++0x03
line.long 0x00 "HPD_DBNC_CTRL_CLR,HPD Debounce Control Register"
hexmask.long 0x00 0.--31. 1. "VAL,HDP pin debounce interval"
group.long 0x2AC++0x03
line.long 0x00 "HPD_DBNC_CTRL_TOG,HPD Debounce Control Register"
hexmask.long 0x00 0.--31. 1. "VAL,HDP pin debounce interval"
group.long 0x2D0++0x03
line.long 0x00 "TEMPERATURE,Chip Temperature for eARC PHY"
hexmask.long 0x00 0.--31. 1. "VAL,Temperature"
tree.end
tree "ECSPI (Enhanced Configurable SPI)"
repeat 3. (list 1. 2. 3.) (list ad:0x30820000 ad:0x30830000 ad:0x30840000)
tree "ECSPI$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "RXDATA,Receive Data Register"
hexmask.long 0x00 0.--31. 1. "ECSPI_RXDATA,Receive Data"
wgroup.long 0x04++0x03
line.long 0x00 "TXDATA,Transmit Data Register"
hexmask.long 0x00 0.--31. 1. "ECSPI_TXDATA,Transmit Data"
group.long 0x08++0x03
line.long 0x00 "CONREG,Control Register"
hexmask.long.word 0x00 20.--31. 1. "BURST_LENGTH,Burst Length"
bitfld.long 0x00 18.--19. "CHANNEL_SELECT,SPI CHANNEL SELECT bits" "0: Channel 0 is selected,?..."
newline
bitfld.long 0x00 16.--17. "DRCTL,SPI Data Ready Control" "0: The SPI_RDY signal is a don't care,1: Burst will be triggered by the falling edge..,2: Burst will be triggered by a low level of the..,?..."
bitfld.long 0x00 12.--15. "PRE_DIVIDER,SPI Pre Divider" "0: PRE_DIVIDER_0,1: PRE_DIVIDER_1,2: PRE_DIVIDER_2,?,?,?,?,?,?,?,?,?,?,13: PRE_DIVIDER_13,14: PRE_DIVIDER_14,15: PRE_DIVIDER_15"
newline
bitfld.long 0x00 8.--11. "POST_DIVIDER,SPI Post Divider" "0: POST_DIVIDER_0,1: POST_DIVIDER_1,2: POST_DIVIDER_2,?,?,?,?,?,?,?,?,?,?,?,14: Divide by 2 14,15: Divide by 2 15"
bitfld.long 0x00 4.--7. "CHANNEL_MODE,SPI CHANNEL MODE selects the mode for each SPI channel" "0: CHANNEL_MODE_0,1: CHANNEL_MODE_1,?..."
newline
bitfld.long 0x00 3. "SMC,Start Mode Control" "0: SPI Exchange Bit (XCH) controls when a SPI..,1: Immediately starts a SPI burst when data is.."
bitfld.long 0x00 2. "XCH,SPI Exchange Bit" "0: XCH_0,1: Initiates exchange (write) or busy (read)"
newline
bitfld.long 0x00 1. "HT,Hardware Trigger Enable" "0: Disable HT mode,1: Enable HT mode"
bitfld.long 0x00 0. "EN,SPI Block Enable Control" "0: Disable the block,1: Enable the block"
group.long 0x0C++0x03
line.long 0x00 "CONFIGREG,Config Register"
bitfld.long 0x00 24.--28. "HT_LENGTH,HT LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--23. "SCLK_CTL,SCLK CTL" "0: SCLK_CTL_0,1: SCLK_CTL_1,?..."
newline
bitfld.long 0x00 16.--19. "DATA_CTL,DATA CTL" "0: DATA_CTL_0,1: DATA_CTL_1,?..."
bitfld.long 0x00 12.--15. "SS_POL,SPI SS Polarity Select" "0: Active low,1: Active high,?..."
newline
bitfld.long 0x00 8.--11. "SS_CTL,SPI SS Wave Form Select" "0: In master mode - only one SPI burst will be..,1: In master mode - Negate Chip Select (SS)..,?..."
bitfld.long 0x00 4.--7. "SCLK_POL,SPI Clock Polarity Control" "0: Active high polarity (0 = Idle),1: Active low polarity (1 = Idle),?..."
newline
bitfld.long 0x00 0.--3. "SCLK_PHA,SPI Clock/Data Phase Control" "0: Phase 0 operation,1: Phase 1 operation,?..."
group.long 0x10++0x03
line.long 0x00 "INTREG,Interrupt Control Register"
bitfld.long 0x00 7. "TCEN,Transfer Completed Interrupt enable" "0: Disable,1: TCEN_1"
bitfld.long 0x00 6. "ROEN,RXFIFO Overflow Interrupt enable" "0: Disable,1: ROEN_1"
newline
bitfld.long 0x00 5. "RFEN,RXFIFO Full Interrupt enable" "0: Disable,1: RFEN_1"
bitfld.long 0x00 4. "RDREN,RXFIFO Data Request Interrupt enable" "0: RDREN_0,1: RDREN_1"
newline
bitfld.long 0x00 3. "RREN,RXFIFO Ready Interrupt enable" "0: Disable,1: RREN_1"
bitfld.long 0x00 2. "TFEN,TXFIFO Full Interrupt enable" "0: Disable,1: TFEN_1"
newline
bitfld.long 0x00 1. "TDREN,TXFIFO Data Request Interrupt enable" "0: TDREN_0,1: TDREN_1"
bitfld.long 0x00 0. "TEEN,TXFIFO Empty Interrupt enable" "0: Disable,1: TEEN_1"
group.long 0x14++0x03
line.long 0x00 "DMAREG,DMA Control Register"
bitfld.long 0x00 31. "RXTDEN,RXFIFO TAIL DMA Request/Interrupt Enable" "0: RXTDEN_0,1: RXTDEN_1"
bitfld.long 0x00 24.--29. "RX_DMA_LENGTH,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 23. "RXDEN,RXFIFO DMA Request Enable" "0: RXDEN_0,1: RXDEN_1"
bitfld.long 0x00 16.--21. "RX_THRESHOLD,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 7. "TEDEN,TXFIFO Empty DMA Request Enable" "0: TEDEN_0,1: TEDEN_1"
bitfld.long 0x00 0.--5. "TX_THRESHOLD,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18++0x03
line.long 0x00 "STATREG,Status Register"
eventfld.long 0x00 7. "TC,Transfer Completed Status bit" "0: Transfer in progress,1: Transfer completed"
eventfld.long 0x00 6. "RO,RXFIFO Overflow" "0: RXFIFO has no overflow,1: RXFIFO has overflowed"
newline
rbitfld.long 0x00 5. "RF,RXFIFO Full" "0: Not Full,1: Full"
rbitfld.long 0x00 4. "RDR,RXFIFO Data Request" "0: When RXTDE is set - Number of data entries in..,1: When RXTDE is set - Number of data entries in.."
newline
rbitfld.long 0x00 3. "RR,RXFIFO Ready" "0: No valid data in RXFIFO,1: More than 1 word in RXFIFO"
rbitfld.long 0x00 2. "TF,TXFIFO Full" "0: TXFIFO is not Full,1: TXFIFO is Full"
newline
rbitfld.long 0x00 1. "TDR,TXFIFO Data Request" "0: Number of valid data slots in TXFIFO is..,1: Number of valid data slots in TXFIFO is not.."
rbitfld.long 0x00 0. "TE,TXFIFO Empty" "0: TXFIFO contains one or more words,1: TXFIFO is empty"
group.long 0x1C++0x03
line.long 0x00 "PERIODREG,Sample Period Control Register"
bitfld.long 0x00 16.--21. "CSD_CTL,Chip Select Delay Control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "CSRC,Clock Source Control" "0: SPI Clock (SCLK),1: Low-Frequency Reference Clock (32.768 KHz)"
newline
hexmask.long.word 0x00 0.--14. 1. "SAMPLE_PERIOD,Sample Period Control"
group.long 0x20++0x03
line.long 0x00 "TESTREG,Test Control Register"
bitfld.long 0x00 31. "LBC,Loop Back Control" "0: Not connected,1: Transmitter and receiver sections internally.."
hexmask.long.byte 0x00 8.--14. 1. "RXCNT,RXFIFO Counter"
newline
hexmask.long.byte 0x00 0.--6. 1. "TXCNT,TXFIFO Counter"
wgroup.long 0x40++0x03
line.long 0x00 "MSGDATA,Message Data Register"
hexmask.long 0x00 0.--31. 1. "ECSPI_MSGDATA,ECSPI_MSGDATA holds the top word of MSG Data FIFO"
tree.end
repeat.end
tree.end
tree "EDDC"
base ad:0x32FDFE00
group.byte 0x00++0x00
line.byte 0x00 "i2cm_slave,I2C DDC Slave address Configuration Register"
hexmask.byte 0x00 0.--6. 1. "slaveaddr,Slave address to be sent during read and write normal operations"
group.byte 0x01++0x00
line.byte 0x00 "i2cm_address,I2C DDC Address Configuration Register"
hexmask.byte 0x00 0.--7. 1. "address,Register address for read and write operations"
group.byte 0x02++0x00
line.byte 0x00 "i2cm_datao,I2C DDC Data Write Register"
hexmask.byte 0x00 0.--7. 1. "datao,Data to be written on register pointed by address[7:0]"
rgroup.byte 0x03++0x00
line.byte 0x00 "i2cm_datai,I2C DDC Data read Register"
hexmask.byte 0x00 0.--7. 1. "datai,Data read from register pointed by address[7:0]"
wgroup.byte 0x04++0x00
line.byte 0x00 "i2cm_operation,I2C DDC RD/RD_EXT/WR Operation Register Read and write operation request"
bitfld.byte 0x00 5. "busclear,bus clear operation request" "0,1"
bitfld.byte 0x00 4. "wr,Single byte write operation request" "0,1"
newline
bitfld.byte 0x00 3. "rd8_ext,Extended sequential read operation request" "0,1"
bitfld.byte 0x00 2. "rd8,Sequential read operation request" "0,1"
newline
bitfld.byte 0x00 1. "rd_ext,After writing 1'b1 to rd_ext bit a extended data read operation is started (E-DDC read operation)" "0,1"
bitfld.byte 0x00 0. "rd,Single byte read operation request" "0,1"
group.byte 0x05++0x00
line.byte 0x00 "i2cm_int,I2C DDC Done Interrupt Register This register configures the I2C master interrupts"
bitfld.byte 0x00 6. "read_req_mask,Read request interruption mask signal" "0,1"
bitfld.byte 0x00 2. "done_mask,Done interrupt mask signal" "0,1"
group.byte 0x06++0x00
line.byte 0x00 "i2cm_ctlint,I2C DDC error Interrupt Register This register configures the I2C master arbitration lost and not acknowledge error interrupts"
bitfld.byte 0x00 6. "nack_mask,Not acknowledge error interrupt mask signal" "0,1"
bitfld.byte 0x00 2. "arbitration_mask,Arbitration error interrupt mask signal" "0,1"
group.byte 0x07++0x00
line.byte 0x00 "i2cm_div,I2C DDC Speed Control Register This register configures the division relation between master and scl clock"
bitfld.byte 0x00 3. "fast_std_mode,Sets the I2C Master to work in Fast Mode or Standard Mode" "0: Standard Mode,1: Fast Mode"
bitfld.byte 0x00 0.--2. "spare,Reserved as spare bit with no associated functionality" "0,1,2,3,4,5,6,7"
group.byte 0x08++0x00
line.byte 0x00 "i2cm_segaddr,I2C DDC Segment Address Configuration Register This register configures the segment address for extended R/W destination and is used for EDID reading operations particularly for the Extended Data Read Operation for Enhanced DDC"
hexmask.byte 0x00 0.--6. 1. "seg_addr,I2C DDC Segment Address Configuration Register"
group.byte 0x09++0x00
line.byte 0x00 "i2cm_softrstz,I2C DDC Software Reset Control Register This register resets the I2C master"
bitfld.byte 0x00 0. "i2c_softrstz,I2C Master Software Reset" "0,1"
group.byte 0x0A++0x00
line.byte 0x00 "i2cm_segptr,I2C DDC Segment Pointer Register This register configures the segment pointer for extended RD/WR request"
hexmask.byte 0x00 0.--7. 1. "segptr,I2C DDC Segment Pointer Register"
group.byte 0x0B++0x00
line.byte 0x00 "i2cm_ss_scl_hcnt_1_addr,I2C DDC Slow Speed SCL High Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_hcnt1,I2C DDC Slow Speed SCL High Level Control Register 1"
group.byte 0x0C++0x00
line.byte 0x00 "i2cm_ss_scl_hcnt_0_addr,I2C DDC Slow Speed SCL High Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_hcnt0,I2C DDC Slow Speed SCL High Level Control Register 0"
group.byte 0x0D++0x00
line.byte 0x00 "i2cm_ss_scl_lcnt_1_addr,I2C DDC Slow Speed SCL Low Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_lcnt1,I2C DDC Slow Speed SCL Low Level Control Register 1"
group.byte 0x0E++0x00
line.byte 0x00 "i2cm_ss_scl_lcnt_0_addr,I2C DDC Slow Speed SCL Low Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_lcnt0,I2C DDC Slow Speed SCL Low Level Control Register 0"
group.byte 0x0F++0x00
line.byte 0x00 "i2cm_fs_scl_hcnt_1_addr,I2C DDC Fast Speed SCL High Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_hcnt1,I2C DDC Fast Speed SCL High Level Control Register 1"
group.byte 0x10++0x00
line.byte 0x00 "i2cm_fs_scl_hcnt_0_addr,I2C DDC Fast Speed SCL High Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_hcnt0,I2C DDC Fast Speed SCL High Level Control Register 0"
group.byte 0x11++0x00
line.byte 0x00 "i2cm_fs_scl_lcnt_1_addr,I2C DDC Fast Speed SCL Low Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_lcnt1,I2C DDC Fast Speed SCL Low Level Control Register 1"
group.byte 0x12++0x00
line.byte 0x00 "i2cm_fs_scl_lcnt_0_addr,I2C DDC Fast Speed SCL Low Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_lcnt0,I2C DDC Fast Speed SCL Low Level Control Register 0"
group.byte 0x13++0x00
line.byte 0x00 "i2cm_sda_hold,I2C DDC SDA Hold Register"
hexmask.byte 0x00 0.--7. 1. "osda_hold,Defines the number of SFR clock cycles to meet tHD DAT (300 ns) osda_hold = round_to_high_integer (300 ns / (1 / isfrclk_frequency))"
group.byte 0x14++0x00
line.byte 0x00 "i2cm_scdc_read_update,SCDC Control Register This register configures the SCDC update status read through the I2C master interface"
bitfld.byte 0x00 5. "updtrd_vsyncpoll_en,Update read polling enabled" "0,1"
bitfld.byte 0x00 4. "read_request_en,Read request enabled" "0,1"
newline
bitfld.byte 0x00 0. "read_update,When set to 1'b1 a SCDC Update Read is performed and the read data loaded into registers i2cm_scdc_update0 and i2cm_scdc_update1" "0,1"
rgroup.byte 0x20++0x00
line.byte 0x00 "i2cm_read_buff0,I2C Master Sequential Read Buffer Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff0,Byte 0 of a I2C read buffer sequential read (from address i2cm_address)"
rgroup.byte 0x21++0x00
line.byte 0x00 "i2cm_read_buff1,I2C Master Sequential Read Buffer Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff1,Byte 1 of a I2C read buffer sequential read (from address i2cm_address+1)"
rgroup.byte 0x22++0x00
line.byte 0x00 "i2cm_read_buff2,I2C Master Sequential Read Buffer Register 2"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff2,Byte 2 of a I2C read buffer sequential read (from address i2cm_address+2)"
rgroup.byte 0x23++0x00
line.byte 0x00 "i2cm_read_buff3,I2C Master Sequential Read Buffer Register 3"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff3,Byte 3 of a I2C read buffer sequential read (from address i2cm_address+3)"
rgroup.byte 0x24++0x00
line.byte 0x00 "i2cm_read_buff4,I2C Master Sequential Read Buffer Register 4"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff4,Byte 4 of a I2C read buffer sequential read (from address i2cm_address+4)"
rgroup.byte 0x25++0x00
line.byte 0x00 "i2cm_read_buff5,I2C Master Sequential Read Buffer Register 5"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff5,Byte 5 of a I2C read buffer sequential read (from address i2cm_address+5)"
rgroup.byte 0x26++0x00
line.byte 0x00 "i2cm_read_buff6,I2C Master Sequential Read Buffer Register 6"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff6,Byte 6 of a I2C read buffer sequential read (from address i2cm_address+6)"
rgroup.byte 0x27++0x00
line.byte 0x00 "i2cm_read_buff7,I2C Master Sequential Read Buffer Register 7"
hexmask.byte 0x00 0.--7. 1. "i2cm_read_buff7,Byte 7 of a I2C read buffer sequential read (from address i2cm_address+7)"
rgroup.byte 0x30++0x00
line.byte 0x00 "i2cm_scdc_update0,I2C SCDC Read Update Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cm_scdc_update0,Byte 0 of a SCDC I2C update sequential"
rgroup.byte 0x31++0x00
line.byte 0x00 "i2cm_scdc_update1,I2C SCDC Read Update Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cm_scdc_update1,Byte 1 of a SCDC I2C update sequential"
tree.end
tree "ENET (Ethernet MAC)"
base ad:0x30BE0000
group.long 0x04++0x03
line.long 0x00 "EIR,Interrupt Event Register"
eventfld.long 0x00 30. "BABR,Babbling Receive Error" "0,1"
eventfld.long 0x00 29. "BABT,Babbling Transmit Error" "0,1"
newline
eventfld.long 0x00 28. "GRA,Graceful Stop Complete" "0,1"
eventfld.long 0x00 27. "TXF,Transmit Frame Interrupt" "0,1"
newline
eventfld.long 0x00 26. "TXB,Transmit Buffer Interrupt" "0,1"
eventfld.long 0x00 25. "RXF,Receive Frame Interrupt" "0,1"
newline
eventfld.long 0x00 24. "RXB,Receive Buffer Interrupt" "0,1"
eventfld.long 0x00 23. "MII,MII Interrupt" "0,1"
newline
eventfld.long 0x00 22. "EBERR,Ethernet Bus Error" "0,1"
eventfld.long 0x00 21. "LC,Late Collision" "0,1"
newline
eventfld.long 0x00 20. "RL,Collision Retry Limit" "0,1"
eventfld.long 0x00 19. "UN,Transmit FIFO Underrun" "0,1"
newline
eventfld.long 0x00 18. "PLR,Payload Receive Error" "0,1"
eventfld.long 0x00 17. "WAKEUP,Node Wakeup Request Indication" "0,1"
newline
eventfld.long 0x00 16. "TS_AVAIL,Transmit Timestamp Available" "0,1"
eventfld.long 0x00 15. "TS_TIMER,Timestamp Timer" "0,1"
newline
eventfld.long 0x00 14. "RXFLUSH_2,RX DMA Ring 2 flush indication" "0,1"
eventfld.long 0x00 13. "RXFLUSH_1,RX DMA Ring 1 flush indication" "0,1"
newline
eventfld.long 0x00 12. "RXFLUSH_0,RX DMA Ring 0 flush indication" "0,1"
eventfld.long 0x00 7. "TXF2,Transmit frame interrupt class 2" "0,1"
newline
eventfld.long 0x00 6. "TXB2,Transmit buffer interrupt class 2" "0,1"
eventfld.long 0x00 5. "RXF2,Receive frame interrupt class 2" "0,1"
newline
eventfld.long 0x00 4. "RXB2,Receive buffer interrupt class 2" "0,1"
eventfld.long 0x00 3. "TXF1,Transmit frame interrupt class 1" "0,1"
newline
eventfld.long 0x00 2. "TXB1,Transmit buffer interrupt class 1" "0,1"
eventfld.long 0x00 1. "RXF1,Receive frame interrupt class 1" "0,1"
newline
eventfld.long 0x00 0. "RXB1,Receive buffer interrupt class 1" "0,1"
group.long 0x08++0x03
line.long 0x00 "EIMR,Interrupt Mask Register"
bitfld.long 0x00 30. "BABR,BABR Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
bitfld.long 0x00 29. "BABT,BABT Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
newline
bitfld.long 0x00 28. "GRA,GRA Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
bitfld.long 0x00 27. "TXF,TXF Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
newline
bitfld.long 0x00 26. "TXB,TXB Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
bitfld.long 0x00 25. "RXF,RXF Interrupt Mask" "0,1"
newline
bitfld.long 0x00 24. "RXB,RXB Interrupt Mask" "0,1"
bitfld.long 0x00 23. "MII,MII Interrupt Mask" "0,1"
newline
bitfld.long 0x00 22. "EBERR,EBERR Interrupt Mask" "0,1"
bitfld.long 0x00 21. "LC,LC Interrupt Mask" "0,1"
newline
bitfld.long 0x00 20. "RL,RL Interrupt Mask" "0,1"
bitfld.long 0x00 19. "UN,UN Interrupt Mask" "0,1"
newline
bitfld.long 0x00 18. "PLR,PLR Interrupt Mask" "0,1"
bitfld.long 0x00 17. "WAKEUP,WAKEUP Interrupt Mask" "0,1"
newline
bitfld.long 0x00 16. "TS_AVAIL,TS_AVAIL Interrupt Mask" "0,1"
bitfld.long 0x00 15. "TS_TIMER,TS_TIMER Interrupt Mask" "0,1"
newline
bitfld.long 0x00 14. "RXFLUSH_2,Corresponds to interrupt source EIR[RXFLUSH_2] and determines whether an interrupt condition can generate an interrupt" "0,1"
bitfld.long 0x00 13. "RXFLUSH_1,Corresponds to interrupt source EIR[RXFLUSH_1] and determines whether an interrupt condition can generate an interrupt" "0,1"
newline
bitfld.long 0x00 12. "RXFLUSH_0,Corresponds to interrupt source EIR[RXFLUSH_0] and determines whether an interrupt condition can generate an interrupt" "0,1"
bitfld.long 0x00 7. "TXF2,Transmit frame interrupt class 2" "0,1"
newline
bitfld.long 0x00 6. "TXB2,Transmit buffer interrupt class 2" "0,1"
bitfld.long 0x00 5. "RXF2,Receive frame interrupt class 2" "0,1"
newline
bitfld.long 0x00 4. "RXB2,Receive buffer interrupt class 2" "0,1"
bitfld.long 0x00 3. "TXF1,Transmit frame interrupt class 1" "0,1"
newline
bitfld.long 0x00 2. "TXB1,Transmit buffer interrupt class 1" "0,1"
bitfld.long 0x00 1. "RXF1,Receive frame interrupt class 1" "0,1"
newline
bitfld.long 0x00 0. "RXB1,Receive buffer interrupt class 1" "0,1"
group.long 0x10++0x03
line.long 0x00 "RDAR,Receive Descriptor Active Register - Ring 0"
bitfld.long 0x00 24. "RDAR,Receive Descriptor Active" "0,1"
group.long 0x14++0x03
line.long 0x00 "TDAR,Transmit Descriptor Active Register - Ring 0"
bitfld.long 0x00 24. "TDAR,Transmit Descriptor Active" "0,1"
group.long 0x24++0x03
line.long 0x00 "ECR,Ethernet Control Register"
bitfld.long 0x00 17. "RXC_DLY,Receive clock delay" "0: Use non-delayed version of RGMII_RXC,1: Use delayed version of RGMII_RXC"
bitfld.long 0x00 16. "TXC_DLY,Transmit clock delay" "0: RGMII_TXC is not delayed,1: Generate delayed version of RGMII_TXC"
newline
bitfld.long 0x00 11. "SVLANDBL,S-VLAN double tag" "0,1"
bitfld.long 0x00 10. "VLANUSE2ND,VLAN use second tag" "0: Always extract data from the first VLAN tag..,1: When a double-tagged frame is detected the.."
newline
bitfld.long 0x00 9. "SVLANEN,S-VLAN enable" "0: Only the EtherType 0x8100 will be considered..,1: The EtherType 0x88a8 will be considered in.."
bitfld.long 0x00 8. "DBSWP,Descriptor Byte Swapping Enable" "0: The buffer descriptor bytes are not swapped..,1: The buffer descriptor bytes are swapped to.."
newline
bitfld.long 0x00 6. "DBGEN,Debug Enable" "0: MAC continues operation in debug mode,1: MAC enters hardware freeze mode when the.."
bitfld.long 0x00 5. "SPEED,Selects between 10/100-Mbit/s and 1000-Mbit/s modes of operation" "0: 10/100-Mbit/s mode,1: 1000-Mbit/s mode"
newline
bitfld.long 0x00 4. "EN1588,EN1588 Enable" "0: Legacy FEC buffer descriptors and functions..,1: Enhanced frame time-stamping functions enabled"
bitfld.long 0x00 3. "SLEEP,Sleep Mode Enable" "0: Normal operating mode,1: Sleep mode"
newline
bitfld.long 0x00 2. "MAGICEN,Magic Packet Detection Enable" "0: Magic detection logic disabled,1: The MAC core detects magic packets and.."
bitfld.long 0x00 1. "ETHEREN,Ethernet Enable" "0: Reception immediately stops and transmission..,1: MAC is enabled and reception and transmission.."
newline
bitfld.long 0x00 0. "RESET,Ethernet MAC Reset" "0,1"
group.long 0x40++0x03
line.long 0x00 "MMFR,MII Management Frame Register"
bitfld.long 0x00 30.--31. "ST,Start Of Frame Delimiter" "0,1,2,3"
bitfld.long 0x00 28.--29. "OP,Operation Code" "0,1,2,3"
newline
bitfld.long 0x00 23.--27. "PA,PHY Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18.--22. "RA,Register Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--17. "TA,Turn Around" "0,1,2,3"
hexmask.long.word 0x00 0.--15. 1. "DATA,Management Frame Data"
group.long 0x44++0x03
line.long 0x00 "MSCR,MII Speed Control Register"
bitfld.long 0x00 8.--10. "HOLDTIME,Hold time On MDIO Output" "0: 1 internal module clock cycle,1: 2 internal module clock cycles,2: 3 internal module clock cycles,?,?,?,?,7: 8 internal module clock cycles"
bitfld.long 0x00 7. "DIS_PRE,Disable Preamble" "0: Preamble enabled,1: Preamble (32 ones) is not prepended to the.."
newline
bitfld.long 0x00 1.--6. "MII_SPEED,MII Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x64++0x03
line.long 0x00 "MIBC,MIB Control Register"
bitfld.long 0x00 31. "MIB_DIS,Disable MIB Logic" "0: MIB logic is enabled,1: MIB logic is disabled"
rbitfld.long 0x00 30. "MIB_IDLE,MIB Idle" "0: The MIB block is updating MIB counters,1: The MIB block is not currently updating any.."
newline
bitfld.long 0x00 29. "MIB_CLEAR,MIB Clear" "0: See note above,1: All statistics counters are reset to 0"
group.long 0x84++0x03
line.long 0x00 "RCR,Receive Control Register"
rbitfld.long 0x00 31. "GRS,Graceful Receive Stopped" "0,1"
bitfld.long 0x00 30. "NLC,Payload Length Check Disable" "0: The payload length check is disabled,1: The core checks the frame's payload length.."
newline
hexmask.long.word 0x00 16.--29. 1. "MAX_FL,Maximum Frame Length"
bitfld.long 0x00 15. "CFEN,MAC Control Frame Enable" "0: MAC control frames with any opcode other than..,1: MAC control frames with any opcode other than.."
newline
bitfld.long 0x00 14. "CRCFWD,Terminate/Forward Received CRC" "0: The CRC field of received frames is..,1: The CRC field is stripped from the frame"
bitfld.long 0x00 13. "PAUFWD,Terminate/Forward Pause Frames" "0: Pause frames are terminated and discarded in..,1: Pause frames are forwarded to the user.."
newline
bitfld.long 0x00 12. "PADEN,Enable Frame Padding Remove On Receive" "0: No padding is removed on receive by the MAC,1: Padding is removed from received frames"
bitfld.long 0x00 9. "RMII_10T,Enables 10-Mbit/s mode of the RMII or RGMII" "0: 100-Mbit/s operation,1: 10-Mbit/s operation"
newline
bitfld.long 0x00 8. "RMII_MODE,RMII Mode Enable" "0: MAC configured for MII mode,1: MAC configured for RMII operation"
bitfld.long 0x00 6. "RGMII_EN,RGMII Mode Enable" "0: MAC configured for non-RGMII operation,1: MAC configured for RGMII operation"
newline
bitfld.long 0x00 5. "FCE,Flow Control Enable" "0,1"
bitfld.long 0x00 4. "BC_REJ,Broadcast Frame Reject" "0,1"
newline
bitfld.long 0x00 3. "PROM,Promiscuous Mode" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "MII_MODE,Media Independent Interface Mode" "?,1: RMII mode as indicated by the RMII_MODE field"
newline
bitfld.long 0x00 1. "DRT,Disable Receive On Transmit" "0: Receive path operates independently of..,1: Disable reception of frames while transmitting"
bitfld.long 0x00 0. "LOOP,Internal Loopback" "0: Loopback disabled,1: Transmitted frames are looped back internal.."
group.long 0xC4++0x03
line.long 0x00 "TCR,Transmit Control Register"
bitfld.long 0x00 9. "CRCFWD,Forward Frame From Application With CRC" "0: TxBD[TC] controls whether the frame has a CRC..,1: The transmitter does not append any CRC to.."
bitfld.long 0x00 8. "ADDINS,Set MAC Address On Transmit" "0: The source MAC address is not modified by the..,1: The MAC overwrites the source MAC address.."
newline
bitfld.long 0x00 5.--7. "ADDSEL,Source MAC Address Select On Transmit" "0: Node MAC address programmed on PADDR1/2..,?..."
rbitfld.long 0x00 4. "RFC_PAUSE,Receive Frame Control Pause" "0,1"
newline
bitfld.long 0x00 3. "TFC_PAUSE,Transmit Frame Control Pause" "0: No PAUSE frame transmitted,1: The MAC stops transmission of data frames.."
bitfld.long 0x00 2. "FDEN,Full-Duplex Enable" "0,1"
newline
bitfld.long 0x00 0. "GTS,Graceful Transmit Stop" "0,1"
group.long 0xE4++0x03
line.long 0x00 "PALR,Physical Address Lower Register"
hexmask.long 0x00 0.--31. 1. "PADDR1,Pause Address"
group.long 0xE8++0x03
line.long 0x00 "PAUR,Physical Address Upper Register"
hexmask.long.word 0x00 16.--31. 1. "PADDR2,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match and the source address field in PAUSE frames"
hexmask.long.word 0x00 0.--15. 1. "TYPE,Type Field In PAUSE Frames"
group.long 0xEC++0x03
line.long 0x00 "OPD,Opcode/Pause Duration Register"
hexmask.long.word 0x00 16.--31. 1. "OPCODE,Opcode Field In PAUSE Frames"
hexmask.long.word 0x00 0.--15. 1. "PAUSE_DUR,Pause Duration"
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
group.long ($2+0xF0)++0x03
line.long 0x00 "TXIC$1,Transmit Interrupt Coalescing Register"
bitfld.long 0x00 31. "ICEN,Interrupt Coalescing Enable" "0: Disable Interrupt coalescing,1: Enable Interrupt coalescing"
bitfld.long 0x00 30. "ICCS,Interrupt Coalescing Timer Clock Source Select" "0: Use GMII TX clocks,1: Use ENET system clock"
newline
hexmask.long.byte 0x00 20.--27. 1. "ICFT,Interrupt coalescing frame count threshold"
hexmask.long.word 0x00 0.--15. 1. "ICTT,Interrupt coalescing timer threshold"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
group.long ($2+0x100)++0x03
line.long 0x00 "RXIC$1,Receive Interrupt Coalescing Register"
bitfld.long 0x00 31. "ICEN,Interrupt Coalescing Enable" "0: Disable Interrupt coalescing,1: Enable Interrupt coalescing"
bitfld.long 0x00 30. "ICCS,Interrupt Coalescing Timer Clock Source Select" "0: Use MII/GMII TX clocks,1: Use ENET system clock"
newline
hexmask.long.byte 0x00 20.--27. 1. "ICFT,Interrupt coalescing frame count threshold"
hexmask.long.word 0x00 0.--15. 1. "ICTT,Interrupt coalescing timer threshold"
repeat.end
group.long 0x118++0x03
line.long 0x00 "IAUR,Descriptor Individual Upper Address Register"
hexmask.long 0x00 0.--31. 1. "IADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
group.long 0x11C++0x03
line.long 0x00 "IALR,Descriptor Individual Lower Address Register"
hexmask.long 0x00 0.--31. 1. "IADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
group.long 0x120++0x03
line.long 0x00 "GAUR,Descriptor Group Upper Address Register"
hexmask.long 0x00 0.--31. 1. "GADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
group.long 0x124++0x03
line.long 0x00 "GALR,Descriptor Group Lower Address Register"
hexmask.long 0x00 0.--31. 1. "GADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
group.long 0x144++0x03
line.long 0x00 "TFWR,Transmit FIFO Watermark Register"
bitfld.long 0x00 8. "STRFWD,Store And Forward Enable" "0: Reset,1: STRFWD_1"
bitfld.long 0x00 0.--5. "TFWR,Transmit FIFO" "0: 64 bytes written,1: 64 bytes written,2: 128 bytes written,3: 192 bytes written,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: 4032 bytes written"
group.long 0x160++0x03
line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register"
hexmask.long 0x00 3.--31. 1. "R_DES_START,Pointer to the beginning of the receive buffer descriptor queue 1"
group.long 0x164++0x03
line.long 0x00 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register"
hexmask.long 0x00 3.--31. 1. "X_DES_START,Pointer to the beginning of transmit buffer descriptor queue 1"
group.long 0x168++0x03
line.long 0x00 "MRBR1,Maximum Receive Buffer Size Register - Ring 1"
hexmask.long.byte 0x00 4.--10. 1. "R_BUF_SIZE,Receive buffer size in bytes"
group.long 0x16C++0x03
line.long 0x00 "RDSR2,Receive Descriptor Ring 2 Start Register"
hexmask.long 0x00 3.--31. 1. "R_DES_START,Pointer to the beginning of receive buffer descriptor queue 2"
group.long 0x170++0x03
line.long 0x00 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register"
hexmask.long 0x00 3.--31. 1. "X_DES_START,Pointer to the beginning of transmit buffer descriptor queue 2"
group.long 0x174++0x03
line.long 0x00 "MRBR2,Maximum Receive Buffer Size Register - Ring 2"
hexmask.long.byte 0x00 4.--10. 1. "R_BUF_SIZE,Receive buffer size in bytes"
group.long 0x180++0x03
line.long 0x00 "RDSR,Receive Descriptor Ring 0 Start Register"
hexmask.long 0x00 3.--31. 1. "R_DES_START,Pointer to the beginning of the receive buffer descriptor queue"
group.long 0x184++0x03
line.long 0x00 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register"
hexmask.long 0x00 3.--31. 1. "X_DES_START,Pointer to the beginning of the transmit buffer descriptor queue"
group.long 0x188++0x03
line.long 0x00 "MRBR,Maximum Receive Buffer Size Register - Ring 0"
hexmask.long.byte 0x00 4.--10. 1. "R_BUF_SIZE,Receive buffer size in bytes"
group.long 0x190++0x03
line.long 0x00 "RSFL,Receive FIFO Section Full Threshold"
hexmask.long.word 0x00 0.--9. 1. "RX_SECTION_FULL,Value Of Receive FIFO Section Full Threshold"
group.long 0x194++0x03
line.long 0x00 "RSEM,Receive FIFO Section Empty Threshold"
bitfld.long 0x00 16.--20. "STAT_SECTION_EMPTY,RX Status FIFO Section Empty Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--9. 1. "RX_SECTION_EMPTY,Value Of The Receive FIFO Section Empty Threshold"
group.long 0x198++0x03
line.long 0x00 "RAEM,Receive FIFO Almost Empty Threshold"
hexmask.long.word 0x00 0.--9. 1. "RX_ALMOST_EMPTY,Value Of The Receive FIFO Almost Empty Threshold"
group.long 0x19C++0x03
line.long 0x00 "RAFL,Receive FIFO Almost Full Threshold"
hexmask.long.word 0x00 0.--9. 1. "RX_ALMOST_FULL,Value Of The Receive FIFO Almost Full Threshold"
group.long 0x1A0++0x03
line.long 0x00 "TSEM,Transmit FIFO Section Empty Threshold"
hexmask.long.word 0x00 0.--9. 1. "TX_SECTION_EMPTY,Value Of The Transmit FIFO Section Empty Threshold"
group.long 0x1A4++0x03
line.long 0x00 "TAEM,Transmit FIFO Almost Empty Threshold"
hexmask.long.word 0x00 0.--9. 1. "TX_ALMOST_EMPTY,Value of Transmit FIFO Almost Empty Threshold"
group.long 0x1A8++0x03
line.long 0x00 "TAFL,Transmit FIFO Almost Full Threshold"
hexmask.long.word 0x00 0.--9. 1. "TX_ALMOST_FULL,Value Of The Transmit FIFO Almost Full Threshold"
group.long 0x1AC++0x03
line.long 0x00 "TIPG,Transmit Inter-Packet Gap"
bitfld.long 0x00 0.--4. "IPG,Transmit Inter-Packet Gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1B0++0x03
line.long 0x00 "FTRL,Frame Truncation Length"
hexmask.long.word 0x00 0.--13. 1. "TRUNC_FL,Frame Truncation Length"
group.long 0x1C0++0x03
line.long 0x00 "TACC,Transmit Accelerator Function Configuration"
bitfld.long 0x00 4. "PROCHK,Enables insertion of protocol checksum" "0: Checksum not inserted,1: If an IP frame with a known protocol is.."
bitfld.long 0x00 3. "IPCHK,Enables insertion of IP header checksum" "0: Checksum is not inserted,1: If an IP frame is transmitted the checksum is.."
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bitfld.long 0x00 0. "SHIFT16,TX FIFO Shift-16" "0: SHIFT16_0,1: Indicates to the transmit data FIFO that the.."
group.long 0x1C4++0x03
line.long 0x00 "RACC,Receive Accelerator Function Configuration"
bitfld.long 0x00 7. "SHIFT16,RX FIFO Shift-16" "0: SHIFT16_0,1: Instructs the MAC to write two additional.."
bitfld.long 0x00 6. "LINEDIS,Enable Discard Of Frames With MAC Layer Errors" "0: Frames with errors are not discarded,1: Any frame received with a CRC length or PHY.."
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bitfld.long 0x00 2. "PRODIS,Enable Discard Of Frames With Wrong Protocol Checksum" "0: Frames with wrong checksum are not discarded,1: If a TCP/IP UDP/IP or ICMP/IP frame is.."
bitfld.long 0x00 1. "IPDIS,Enable Discard Of Frames With Wrong IPv4 Header Checksum" "0: Frames with wrong IPv4 header checksum are..,1: If an IPv4 frame is received with a.."
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bitfld.long 0x00 0. "PADREM,Enable Padding Removal For Short IP Frames" "0: Padding not removed,1: Any bytes following the IP payload section of.."
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
group.long ($2+0x1C8)++0x03
line.long 0x00 "RCMR$1,Receive Classification Match Register for Class n"
bitfld.long 0x00 16. "MATCHEN,Match Enable" "0: Disabled (default),1: The register contents are valid and a.."
bitfld.long 0x00 12.--14. "CMP3,Compare 3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "CMP2,Compare 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "CMP1,Compare 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "CMP0,Compare 0" "0,1,2,3,4,5,6,7"
repeat.end
group.long 0x1D8++0x03
line.long 0x00 "DMA1CFG,DMA Class Based Configuration"
bitfld.long 0x00 17. "CALC_NOIPG,Calculate no IPG" "0: The traffic shaper function should consider..,1: Addition of 12 bytes for the IPG should be.."
bitfld.long 0x00 16. "DMA_CLASS_EN,DMA class enable" "0: The DMA controller's channel for the class is..,1: Enable the DMA controller to support the.."
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hexmask.long.word 0x00 0.--15. 1. "IDLE_SLOPE,Idle slope"
group.long 0x1DC++0x03
line.long 0x00 "DMA2CFG,DMA Class Based Configuration"
bitfld.long 0x00 17. "CALC_NOIPG,Calculate no IPG" "0: The traffic shaper function should consider..,1: Addition of 12 bytes for the IPG should be.."
bitfld.long 0x00 16. "DMA_CLASS_EN,DMA class enable" "0: The DMA controller's channel for the class is..,1: Enable the DMA controller to support the.."
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hexmask.long.word 0x00 0.--15. 1. "IDLE_SLOPE,Idle slope"
group.long 0x1E0++0x03
line.long 0x00 "RDAR1,Receive Descriptor Active Register - Ring 1"
bitfld.long 0x00 24. "RDAR,Receive Descriptor Active" "0,1"
group.long 0x1E4++0x03
line.long 0x00 "TDAR1,Transmit Descriptor Active Register - Ring 1"
bitfld.long 0x00 24. "TDAR,Transmit Descriptor Active" "0,1"
group.long 0x1E8++0x03
line.long 0x00 "RDAR2,Receive Descriptor Active Register - Ring 2"
bitfld.long 0x00 24. "RDAR,Receive Descriptor Active" "0,1"
group.long 0x1EC++0x03
line.long 0x00 "TDAR2,Transmit Descriptor Active Register - Ring 2"
bitfld.long 0x00 24. "TDAR,Transmit Descriptor Active" "0,1"
group.long 0x1F0++0x03
line.long 0x00 "QOS,QOS Scheme"
bitfld.long 0x00 5. "RX_FLUSH2,RX Flush Ring 2" "0: RX_FLUSH2_0,1: RX_FLUSH2_1"
bitfld.long 0x00 4. "RX_FLUSH1,RX Flush Ring 1" "0: RX_FLUSH1_0,1: RX_FLUSH1_1"
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bitfld.long 0x00 3. "RX_FLUSH0,RX Flush Ring 0" "0: RX_FLUSH0_0,1: RX_FLUSH0_1"
bitfld.long 0x00 0.--2. "TX_SCHEME,TX scheme configuration" "0: Credit-based scheme,1: Round-robin scheme,?..."
rgroup.long 0x200++0x03
line.long 0x00 "RMON_T_DROP,Reserved Statistic Register"
rgroup.long 0x204++0x03
line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Packet count"
rgroup.long 0x208++0x03
line.long 0x00 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Broadcast packets"
rgroup.long 0x20C++0x03
line.long 0x00 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Multicast packets"
rgroup.long 0x210++0x03
line.long 0x00 "RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Packets with CRC/align error"
rgroup.long 0x214++0x03
line.long 0x00 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets less than 64 bytes with good CRC"
rgroup.long 0x218++0x03
line.long 0x00 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes with good CRC"
rgroup.long 0x21C++0x03
line.long 0x00 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of packets less than 64 bytes with bad CRC"
rgroup.long 0x220++0x03
line.long 0x00 "RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes and bad CRC"
rgroup.long 0x224++0x03
line.long 0x00 "RMON_T_COL,Tx Collision Count Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit collisions"
rgroup.long 0x228++0x03
line.long 0x00 "RMON_T_P64,Tx 64-Byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 64-byte transmit packets"
rgroup.long 0x22C++0x03
line.long 0x00 "RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 65- to 127-byte transmit packets"
rgroup.long 0x230++0x03
line.long 0x00 "RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 128- to 255-byte transmit packets"
rgroup.long 0x234++0x03
line.long 0x00 "RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 256- to 511-byte transmit packets"
rgroup.long 0x238++0x03
line.long 0x00 "RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 512- to 1023-byte transmit packets"
rgroup.long 0x23C++0x03
line.long 0x00 "RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 1024- to 2047-byte transmit packets"
rgroup.long 0x240++0x03
line.long 0x00 "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than 2048 bytes"
rgroup.long 0x244++0x03
line.long 0x00 "RMON_T_OCTETS,Tx Octets Statistic Register"
hexmask.long 0x00 0.--31. 1. "TXOCTS,Number of transmit octets"
rgroup.long 0x248++0x03
line.long 0x00 "IEEE_T_DROP,Reserved Statistic Register"
rgroup.long 0x24C++0x03
line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted OK"
rgroup.long 0x250++0x03
line.long 0x00 "IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with one collision"
rgroup.long 0x254++0x03
line.long 0x00 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with multiple collisions"
rgroup.long 0x258++0x03
line.long 0x00 "IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with deferral delay"
rgroup.long 0x25C++0x03
line.long 0x00 "IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with late collision"
rgroup.long 0x260++0x03
line.long 0x00 "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with excessive collisions"
rgroup.long 0x264++0x03
line.long 0x00 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with transmit FIFO underrun"
rgroup.long 0x268++0x03
line.long 0x00 "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with carrier sense error"
rgroup.long 0x26C++0x03
line.long 0x00 "IEEE_T_SQE,Reserved Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,This read-only field is reserved and always has the value 0"
rgroup.long 0x270++0x03
line.long 0x00 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of flow-control pause frames transmitted"
rgroup.long 0x274++0x03
line.long 0x00 "IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register"
hexmask.long 0x00 0.--31. 1. "COUNT,Octet count for frames transmitted without error Counts total octets (includes header and FCS fields)"
rgroup.long 0x284++0x03
line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of packets received"
rgroup.long 0x288++0x03
line.long 0x00 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive broadcast packets"
rgroup.long 0x28C++0x03
line.long 0x00 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive multicast packets"
rgroup.long 0x290++0x03
line.long 0x00 "RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with CRC or align error"
rgroup.long 0x294++0x03
line.long 0x00 "RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and good CRC"
rgroup.long 0x298++0x03
line.long 0x00 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and good CRC"
rgroup.long 0x29C++0x03
line.long 0x00 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and bad CRC"
rgroup.long 0x2A0++0x03
line.long 0x00 "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and bad CRC"
rgroup.long 0x2A4++0x03
line.long 0x00 "RMON_R_RESVD_0,Reserved Statistic Register"
rgroup.long 0x2A8++0x03
line.long 0x00 "RMON_R_P64,Rx 64-Byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 64-byte receive packets"
rgroup.long 0x2AC++0x03
line.long 0x00 "RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 65- to 127-byte recieve packets"
rgroup.long 0x2B0++0x03
line.long 0x00 "RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 128- to 255-byte recieve packets"
rgroup.long 0x2B4++0x03
line.long 0x00 "RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 256- to 511-byte recieve packets"
rgroup.long 0x2B8++0x03
line.long 0x00 "RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 512- to 1023-byte recieve packets"
rgroup.long 0x2BC++0x03
line.long 0x00 "RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 1024- to 2047-byte recieve packets"
rgroup.long 0x2C0++0x03
line.long 0x00 "RMON_R_P_GTE2048,Rx Packets Greater than 2048 Bytes Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of greater-than-2048-byte recieve packets"
rgroup.long 0x2C4++0x03
line.long 0x00 "RMON_R_OCTETS,Rx Octets Statistic Register"
hexmask.long 0x00 0.--31. 1. "COUNT,Number of receive octets"
rgroup.long 0x2C8++0x03
line.long 0x00 "IEEE_R_DROP,Frames not Counted Correctly Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Frame count"
rgroup.long 0x2CC++0x03
line.long 0x00 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received OK"
rgroup.long 0x2D0++0x03
line.long 0x00 "IEEE_R_CRC,Frames Received with CRC Error Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received with CRC error"
rgroup.long 0x2D4++0x03
line.long 0x00 "IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received with alignment error"
rgroup.long 0x2D8++0x03
line.long 0x00 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Receive FIFO overflow count"
rgroup.long 0x2DC++0x03
line.long 0x00 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of flow-control pause frames received"
rgroup.long 0x2E0++0x03
line.long 0x00 "IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic Register"
hexmask.long 0x00 0.--31. 1. "COUNT,Number of octets for frames received without error"
group.long 0x400++0x03
line.long 0x00 "ATCR,Adjustable Timer Control Register"
bitfld.long 0x00 13. "SLAVE,Enable Timer Slave Mode" "0: The timer is active and all configuration..,1: The internal timer is disabled and the.."
bitfld.long 0x00 11. "CAPTURE,Capture Timer Value" "0: No effect,1: The current time is captured and can be read.."
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bitfld.long 0x00 9. "RESTART,Reset Timer" "0,1"
bitfld.long 0x00 7. "PINPER,Enables event signal output assertion on period event" "0: PINPER_0,1: PINPER_1"
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bitfld.long 0x00 4. "PEREN,Enable Periodical Event" "0: Disable,1: A period event interrupt can be generated.."
bitfld.long 0x00 3. "OFFRST,Reset Timer On Offset Event" "0: The timer is not affected and no action..,1: If OFFEN is set the timer resets to zero when.."
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bitfld.long 0x00 2. "OFFEN,Enable One-Shot Offset Event" "0: Disable,1: The timer can be reset to zero when the given.."
bitfld.long 0x00 0. "EN,Enable Timer" "0: The timer stops at the current value,1: The timer starts incrementing"
group.long 0x404++0x03
line.long 0x00 "ATVR,Timer Value Register"
hexmask.long 0x00 0.--31. 1. "ATIME,A write sets the timer"
group.long 0x408++0x03
line.long 0x00 "ATOFF,Timer Offset Register"
hexmask.long 0x00 0.--31. 1. "OFFSET,Offset value for one-shot event generation"
group.long 0x40C++0x03
line.long 0x00 "ATPER,Timer Period Register"
hexmask.long 0x00 0.--31. 1. "PERIOD,Value for generating periodic events"
group.long 0x410++0x03
line.long 0x00 "ATCOR,Timer Correction Register"
hexmask.long 0x00 0.--30. 1. "COR,Correction Counter Wrap-Around Value"
group.long 0x414++0x03
line.long 0x00 "ATINC,Time-Stamping Clock Period Register"
hexmask.long.byte 0x00 8.--14. 1. "INC_CORR,Correction Increment Value"
hexmask.long.byte 0x00 0.--6. 1. "INC,Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds"
rgroup.long 0x418++0x03
line.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame"
hexmask.long 0x00 0.--31. 1. "TIMESTAMP,Timestamp of the last frame transmitted by the core that had TxBD[TS] set"
group.long 0x604++0x03
line.long 0x00 "TGSR,Timer Global Status Register"
eventfld.long 0x00 3. "TF3,Copy Of Timer Flag For Channel 3" "0: Timer Flag for Channel 3 is clear,1: Timer Flag for Channel 3 is set"
eventfld.long 0x00 2. "TF2,Copy Of Timer Flag For Channel 2" "0: Timer Flag for Channel 2 is clear,1: Timer Flag for Channel 2 is set"
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eventfld.long 0x00 1. "TF1,Copy Of Timer Flag For Channel 1" "0: Timer Flag for Channel 1 is clear,1: Timer Flag for Channel 1 is set"
eventfld.long 0x00 0. "TF0,Copy Of Timer Flag For Channel 0" "0: Timer Flag for Channel 0 is clear,1: Timer Flag for Channel 0 is set"
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x608)++0x03
line.long 0x00 "TCSR$1,Timer Control Status Register"
eventfld.long 0x00 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not..,1: Input Capture or Output Compare has occurred"
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
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bitfld.long 0x00 2.--5. "TMODE,Timer Mode" "0: Timer Channel is disabled,1: Timer Channel is configured for Input Capture..,2: Timer Channel is configured for Input Capture..,3: Timer Channel is configured for Input Capture..,4: Timer Channel is configured for Output..,5: Timer Channel is configured for Output..,6: Timer Channel is configured for Output..,7: Timer Channel is configured for Output..,?,9: Timer Channel is configured for Output..,10: Timer Channel is configured for Output..,11: Timer Channel is configured for Output..,?,?,14: Timer Channel is configured for Output..,15: Timer Channel is configured for Output.."
bitfld.long 0x00 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x60C)++0x03
line.long 0x00 "TCCR$1,Timer Compare Capture Register"
hexmask.long 0x00 0.--31. 1. "TCC,Timer Capture Compare"
repeat.end
tree.end
tree "ENET_QOS"
base ad:0x30BF0000
group.long 0x00++0x03
line.long 0x00 "MAC_CONFIGURATION,MAC Configuration Register"
bitfld.long 0x00 28.--30. "SARC,Source Address Insertion or Replacement Control" "0: mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,2: Contents of MAC Addr-0 inserted in SA field,3: Contents of MAC Addr-0 replaces SA field,?,?,6: Contents of MAC Addr-1 inserted in SA field,7: Contents of MAC Addr-1 replaces SA field"
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bitfld.long 0x00 27. "IPC,Checksum Offload" "0: IP header/payload checksum checking is disabled,1: IP header/payload checksum checking is enabled"
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bitfld.long 0x00 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times IPG,1: 88 bit times IPG,2: 80 bit times IPG,3: 72 bit times IPG,4: 64 bit times IPG,5: 56 bit times IPG,6: 48 bit times IPG,7: 40 bit times IPG"
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bitfld.long 0x00 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0: Giant Packet Size Limit Control is disabled,1: Giant Packet Size Limit Control is enabled"
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bitfld.long 0x00 22. "S2KP,IEEE 802" "0: Support upto 2K packet is disabled,1: Support upto 2K packet is Enabled"
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bitfld.long 0x00 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0: CRC stripping for Type packets is disabled,1: CRC stripping for Type packets is enabled"
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bitfld.long 0x00 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0: Automatic Pad or CRC Stripping is disabled,1: Automatic Pad or CRC Stripping is enabled"
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bitfld.long 0x00 19. "WD,Watchdog Disable" "0: Watchdog is enabled,1: Watchdog is disabled"
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bitfld.long 0x00 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0: Packet Burst is disabled,1: Packet Burst is enabled"
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bitfld.long 0x00 17. "JD,Jabber Disable" "0: Jabber is enabled,1: Jabber is disabled"
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bitfld.long 0x00 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0: Jumbo packet is disabled,1: Jumbo packet is enabled"
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bitfld.long 0x00 15. "PS,Port Select" "0: For 1000 or 2500 Mbps operations,1: For 10 or 100 Mbps operations"
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bitfld.long 0x00 14. "FES,Speed" "0: 10 Mbps when PS bit is 1 and 1 Gbps when PS..,1: 100 Mbps when PS bit is 1 and 2.5 Gbps when.."
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bitfld.long 0x00 13. "DM,Duplex Mode" "0: Half-duplex mode,1: Full-duplex mode"
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bitfld.long 0x00 12. "LM,Loopback Mode" "0: Loopback is disabled,1: Loopback is enabled"
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bitfld.long 0x00 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0: ECRSFD is disabled,1: ECRSFD is enabled"
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bitfld.long 0x00 10. "DO,Disable Receive Own" "0: Enable Receive Own,1: Disable Receive Own"
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bitfld.long 0x00 9. "DCRS,Disable Carrier Sense During Transmission" "0: Enable Carrier Sense During Transmission,1: Disable Carrier Sense During Transmission"
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bitfld.long 0x00 8. "DR,Disable Retry" "0: Enable Retry,1: Disable Retry"
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bitfld.long 0x00 5.--6. "BL,Back-Off Limit" "0: k = min(n 10),1: k = min(n 8),2: k = min(n 4),3: k = min(n 1)"
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bitfld.long 0x00 4. "DC,Deferral Check" "0: Deferral check function is disabled,1: Deferral check function is enabled"
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bitfld.long 0x00 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?..."
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bitfld.long 0x00 1. "TE,Transmitter Enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x00 0. "RE,Receiver Enable" "0: Receiver is disabled,1: Receiver is enabled"
group.long 0x04++0x03
line.long 0x00 "MAC_EXT_CONFIGURATION,MAC Extended Configuration Register"
bitfld.long 0x00 25.--29. "EIPG,Extended Inter-Packet Gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0: Extended Inter-Packet Gap is disabled,1: Extended Inter-Packet Gap is enabled"
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bitfld.long 0x00 19. "PDC,Packet Duplication Control" "0: Packet Duplication Control is disabled,1: Packet Duplication Control is enabled"
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bitfld.long 0x00 18. "USP,Unicast Slow Protocol Packet Detect" "0: Unicast Slow Protocol Packet Detection is..,1: Unicast Slow Protocol Packet Detection is.."
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bitfld.long 0x00 17. "SPEN,Slow Protocol Detection Enable" "0: Slow Protocol Detection is disabled,1: Slow Protocol Detection is enabled"
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bitfld.long 0x00 16. "DCRCC,Disable CRC Checking for Received Packets" "0: CRC Checking is enabled,1: CRC Checking is disabled"
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hexmask.long.word 0x00 0.--13. 1. "GPSL,Giant Packet Size Limit"
group.long 0x08++0x03
line.long 0x00 "MAC_PACKET_FILTER,MAC Packet Filter"
bitfld.long 0x00 31. "RA,Receive All" "0: Receive All is disabled,1: Receive All is enabled"
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bitfld.long 0x00 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0: Forward Non-TCP/UDP over IP Packets,1: Drop Non-TCP/UDP over IP Packets"
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bitfld.long 0x00 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0: Layer 3 and Layer 4 Filters are disabled,1: Layer 3 and Layer 4 Filters are enabled"
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bitfld.long 0x00 16. "VTFE,VLAN Tag Filter Enable" "0: VLAN Tag Filter is disabled,1: VLAN Tag Filter is enabled"
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bitfld.long 0x00 10. "HPF,Hash or Perfect Filter" "0: Hash or Perfect Filter is disabled,1: Hash or Perfect Filter is enabled"
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bitfld.long 0x00 9. "SAF,Source Address Filter Enable" "0: SA Filtering is disabled,1: SA Filtering is enabled"
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bitfld.long 0x00 8. "SAIF,SA Inverse Filtering" "0: SA Inverse Filtering is disabled,1: SA Inverse Filtering is enabled"
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bitfld.long 0x00 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: MAC filters all control packets from reaching..,1: MAC forwards all control packets except Pause..,2: MAC forwards all control packets to the..,3: MAC forwards the control packets that pass.."
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bitfld.long 0x00 5. "DBF,Disable Broadcast Packets" "0: Enable Broadcast Packets,1: Disable Broadcast Packets"
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bitfld.long 0x00 4. "PM,Pass All Multicast" "0: Pass All Multicast is disabled,1: Pass All Multicast is enabled"
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bitfld.long 0x00 3. "DAIF,DA Inverse Filtering" "0: DA Inverse Filtering is disabled,1: DA Inverse Filtering is enabled"
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bitfld.long 0x00 2. "HMC,Hash Multicast" "0: Hash Multicast is disabled,1: Hash Multicast is enabled"
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bitfld.long 0x00 1. "HUC,Hash Unicast" "0: Hash Unicast is disabled,1: Hash Unicast is enabled"
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bitfld.long 0x00 0. "PR,Promiscuous Mode" "0: Promiscuous Mode is disabled,1: Promiscuous Mode is enabled"
group.long 0x0C++0x03
line.long 0x00 "MAC_WATCHDOG_TIMEOUT,Watchdog Timeout"
bitfld.long 0x00 8. "PWE,Programmable Watchdog Enable" "0: Programmable Watchdog is disabled,1: Programmable Watchdog is enabled"
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bitfld.long 0x00 0.--3. "WTO,Watchdog Timeout" "0: bf_2KBYTES,1: bf_3KBYTES,2: bf_4KBYTES,3: bf_5KBYTES,4: bf_6KBYTES,5: bf_7KBYTES,6: bf_8KBYTES,7: bf_9KBYTES,8: bf_10KBYTES,9: bf_11KBYTES,10: bf_12KBYTES,11: bf_13KBYTES,12: bf_14KBYTES,13: bf_15KBYTES,14: bf_16383BYTES,?..."
group.long 0x10++0x03
line.long 0x00 "MAC_HASH_TABLE_REG0,MAC Hash Table Register 0"
hexmask.long 0x00 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table"
group.long 0x14++0x03
line.long 0x00 "MAC_HASH_TABLE_REG1,MAC Hash Table Register 1"
hexmask.long 0x00 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table"
group.long 0x50++0x03
line.long 0x00 "MAC_VLAN_TAG_CTRL,MAC VLAN Tag Control"
bitfld.long 0x00 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0: Inner VLAN Tag in Rx status is disabled,1: Inner VLAN Tag in Rx status is enabled"
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bitfld.long 0x00 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 27. "ERIVLT,ERIVLT" "0: Inner VLAN tag is disabled,1: Inner VLAN tag is enabled"
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bitfld.long 0x00 26. "EDVLP,Enable Double VLAN Processing" "0: Double VLAN Processing is disabled,1: Double VLAN Processing is enabled"
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bitfld.long 0x00 25. "VTHM,VLAN Tag Hash Table Match Enable" "0: VLAN Tag Hash Table Match is disabled,1: VLAN Tag Hash Table Match is enabled"
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bitfld.long 0x00 24. "EVLRXS,Enable VLAN Tag in Rx status" "0: VLAN Tag in Rx status is disabled,1: VLAN Tag in Rx status is enabled"
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bitfld.long 0x00 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0: S-VLAN is disabled,1: S-VLAN is enabled"
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bitfld.long 0x00 17. "VTIM,VLAN Tag Inverse Match Enable" "0: VLAN Tag Inverse Match is disabled,1: VLAN Tag Inverse Match is enabled"
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bitfld.long 0x00 2.--6. "OFS,Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 1. "CT,Command Type" "0: Write operation,1: Read operation"
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bitfld.long 0x00 0. "OB,Operation Busy" "0: Operation Busy is disabled,1: Operation Busy is enabled"
group.long 0x54++0x03
line.long 0x00 "MAC_VLAN_TAG_DATA,MAC VLAN Tag Data"
bitfld.long 0x00 25.--27. "DMACHN,DMA Channel Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24. "DMACHEN,DMA Channel Number Enable" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled"
newline
bitfld.long 0x00 20. "ERIVLT,Enable Inner VLAN Tag Comparison" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled"
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bitfld.long 0x00 19. "ERSVLM,Enable S-VLAN Match for received Frames" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled"
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bitfld.long 0x00 18. "DOVLTC,Disable VLAN Type Comparison" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled"
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bitfld.long 0x00 17. "ETV,12bits or 16bits VLAN comparison" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison"
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bitfld.long 0x00 16. "VEN,VLAN Tag Enable" "0: VLAN Tag is disabled,1: VLAN Tag is enabled"
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hexmask.long.word 0x00 0.--15. 1. "VID,VLAN Tag ID"
group.long 0x58++0x03
line.long 0x00 "MAC_VLAN_HASH_TABLE,MAC VLAN Hash Table"
hexmask.long.word 0x00 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table"
group.long 0x60++0x03
line.long 0x00 "MAC_VLAN_INCL,VLAN Tag Inclusion or Replacement"
rbitfld.long 0x00 31. "BUSY,Busy" "0: Busy status not detected,1: Busy status detected"
newline
bitfld.long 0x00 30. "RDWR,Read write control" "0: Read operation of indirect access,1: Write operation of indirect access"
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bitfld.long 0x00 24.--26. "ADDR,Address" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 21. "CBTI,Channel based tag insertion" "0: Channel based tag insertion is disabled,1: Channel based tag insertion is enabled"
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bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
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bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN" "0: C-VLAN type (0x8100) is inserted or replaced,1: S-VLAN type (0x88A8) is inserted or replaced"
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bitfld.long 0x00 18. "VLP,VLAN Priority Control" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
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bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets"
group.long 0x64++0x03
line.long 0x00 "MAC_INNER_VLAN_INCL,MAC Inner VLAN Tag Inclusion or Replacement"
bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
newline
bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted"
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bitfld.long 0x00 18. "VLP,VLAN Priority Control" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
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bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets"
group.long 0x70++0x03
line.long 0x00 "MAC_Q0_TX_FLOW_CTRL,MAC Q0 Tx Flow Control"
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time"
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bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause" "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
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bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
newline
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
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bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
group.long 0x74++0x03
line.long 0x00 "MAC_Q1_TX_FLOW_CTRL,MAC Q1 Tx Flow Control"
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time"
newline
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause" "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
newline
bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
newline
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
newline
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
group.long 0x78++0x03
line.long 0x00 "MAC_Q2_TX_FLOW_CTRL,MAC Q2 Tx Flow Control"
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time"
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bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause" "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
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bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
newline
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
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bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
group.long 0x7C++0x03
line.long 0x00 "MAC_Q3_TX_FLOW_CTRL,MAC Q3 Tx Flow Control"
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time"
newline
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause" "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
newline
bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
newline
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
newline
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
group.long 0x80++0x03
line.long 0x00 "MAC_Q4_TX_FLOW_CTRL,MAC Q4 Tx Flow Control"
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time"
newline
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause" "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
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bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
newline
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
newline
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
group.long 0x90++0x03
line.long 0x00 "MAC_RX_FLOW_CTRL,MAC Rx Flow Control"
bitfld.long 0x00 8. "PFCE,Priority Based Flow Control Enable" "0: Priority Based Flow Control is disabled,1: Priority Based Flow Control is enabled"
newline
bitfld.long 0x00 1. "UP,Unicast Pause Packet Detect" "0: Unicast Pause Packet Detect disabled,1: Unicast Pause Packet Detect enabled"
newline
bitfld.long 0x00 0. "RFE,Receive Flow Control Enable" "0: Receive Flow Control is disabled,1: Receive Flow Control is enabled"
group.long 0x94++0x03
line.long 0x00 "MAC_RXQ_CTRL4,Receive Queue Control 4"
bitfld.long 0x00 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable" "0: VLAN tag Filter Fail Packets Queuing is..,1: VLAN tag Filter Fail Packets Queuing is enabled"
newline
bitfld.long 0x00 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0: Multicast Address Filter Fail Packets Queuing..,1: Multicast Address Filter Fail Packets Queuing.."
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bitfld.long 0x00 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0: Unicast Address Filter Fail Packets Queuing..,1: Unicast Address Filter Fail Packets Queuing.."
group.long 0x98++0x03
line.long 0x00 "MAC_TXQ_PRTY_MAP0,Transmit Queue Priority Mapping 0"
hexmask.long.byte 0x00 24.--31. 1. "PSTQ3,Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit"
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hexmask.long.byte 0x00 16.--23. 1. "PSTQ2,Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit"
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hexmask.long.byte 0x00 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit"
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hexmask.long.byte 0x00 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0"
group.long 0x9C++0x03
line.long 0x00 "MAC_TXQ_PRTY_MAP1,Transmit Queue Priority Mapping 1"
hexmask.long.byte 0x00 0.--7. 1. "PSTQ4,Priorities Selected in Transmit Queue 4"
group.long 0xA0++0x03
line.long 0x00 "MAC_RXQ_CTRL0,Receive Queue Control 0"
bitfld.long 0x00 8.--9. "RXQ4EN,Receive Queue 4 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
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bitfld.long 0x00 6.--7. "RXQ3EN,Receive Queue 3 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
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bitfld.long 0x00 4.--5. "RXQ2EN,Receive Queue 2 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
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bitfld.long 0x00 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
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bitfld.long 0x00 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
group.long 0xA4++0x03
line.long 0x00 "MAC_RXQ_CTRL1,Receive Queue Control 1"
bitfld.long 0x00 24.--26. "FPRQ,Frame Preemption Residue Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0,1,2,3"
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bitfld.long 0x00 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0: Tagged AV Control Packets Queuing is disabled,1: Tagged AV Control Packets Queuing is enabled"
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bitfld.long 0x00 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field" "0: Multicast and Broadcast Queue is disabled,1: Multicast and Broadcast Queue is enabled"
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bitfld.long 0x00 16.--18. "MCBCQ,Multicast and Broadcast Queue" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,?..."
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bitfld.long 0x00 12.--14. "UPQ,Untagged Packet Queue" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,?..."
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bitfld.long 0x00 8.--10. "DCBCPQ,DCB Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,?..."
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bitfld.long 0x00 4.--6. "PTPQ,PTP Packets Queue" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,?..."
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bitfld.long 0x00 0.--2. "AVCPQ,AV Untagged Control Packets Queue" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,?..."
group.long 0xA8++0x03
line.long 0x00 "MAC_RXQ_CTRL2,Receive Queue Control 2"
hexmask.long.byte 0x00 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3"
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hexmask.long.byte 0x00 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2"
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hexmask.long.byte 0x00 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1"
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hexmask.long.byte 0x00 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0"
group.long 0xAC++0x03
line.long 0x00 "MAC_RXQ_CTRL3,Receive Queue Control 3"
hexmask.long.byte 0x00 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4"
rgroup.long 0xB0++0x03
line.long 0x00 "MAC_INTERRUPT_STATUS,Interrupt Status"
bitfld.long 0x00 20. "MFRIS,MMC FPE Receive Interrupt Status" "0: MMC FPE Receive Interrupt status not active,1: MMC FPE Receive Interrupt status active"
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bitfld.long 0x00 19. "MFTIS,MMC FPE Transmit Interrupt Status" "0: MMC FPE Transmit Interrupt status not active,1: MMC FPE Transmit Interrupt status active"
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bitfld.long 0x00 18. "MDIOIS,MDIO Interrupt Status" "0: MDIO Interrupt status not active,1: MDIO Interrupt status active"
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bitfld.long 0x00 17. "FPEIS,Frame Preemption Interrupt Status" "0: Frame Preemption Interrupt status not active,1: Frame Preemption Interrupt status active"
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bitfld.long 0x00 14. "RXSTSIS,Receive Status Interrupt" "0: Receive Interrupt status not active,1: Receive Interrupt status active"
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bitfld.long 0x00 13. "TXSTSIS,Transmit Status Interrupt" "0: Transmit Interrupt status not active,1: Transmit Interrupt status active"
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bitfld.long 0x00 12. "TSIS,Timestamp Interrupt Status" "0: Timestamp Interrupt status not active,1: Timestamp Interrupt status active"
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bitfld.long 0x00 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status" "0: MMC Receive Checksum Offload Interrupt status..,1: MMC Receive Checksum Offload Interrupt status.."
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bitfld.long 0x00 10. "MMCTXIS,MMC Transmit Interrupt Status" "0: MMC Transmit Interrupt status not active,1: MMC Transmit Interrupt status active"
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bitfld.long 0x00 9. "MMCRXIS,MMC Receive Interrupt Status" "0: MMC Receive Interrupt status not active,1: MMC Receive Interrupt status active"
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bitfld.long 0x00 8. "MMCIS,MMC Interrupt Status" "0: MMC Interrupt status not active,1: MMC Interrupt status active"
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bitfld.long 0x00 5. "LPIIS,LPI Interrupt Status" "0: LPI Interrupt status not active,1: LPI Interrupt status active"
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bitfld.long 0x00 4. "PMTIS,PMT Interrupt Status" "0: PMT Interrupt status not active,1: PMT Interrupt status active"
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bitfld.long 0x00 3. "PHYIS,PHY Interrupt" "0: PHY Interrupt not detected,1: PHY Interrupt detected"
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bitfld.long 0x00 0. "RGSMIIIS,RGMII or SMII Interrupt Status" "0: RGMII or SMII Interrupt Status is not active,1: RGMII or SMII Interrupt Status is active"
group.long 0xB4++0x03
line.long 0x00 "MAC_INTERRUPT_ENABLE,Interrupt Enable"
bitfld.long 0x00 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_INTERRUPT_STATUS register" "0: MDIO Interrupt is disabled,1: MDIO Interrupt is enabled"
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bitfld.long 0x00 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS" "0: Frame Preemption Interrupt is disabled,1: Frame Preemption Interrupt is enabled"
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bitfld.long 0x00 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS]" "0: Receive Status Interrupt is disabled,1: Receive Status Interrupt is enabled"
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bitfld.long 0x00 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS]" "0: Timestamp Status Interrupt is disabled,1: Timestamp Status Interrupt is enabled"
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bitfld.long 0x00 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS]" "0: Timestamp Interrupt is disabled,1: Timestamp Interrupt is enabled"
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bitfld.long 0x00 5. "LPIIE,LPI Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS]" "0: LPI Interrupt is disabled,1: LPI Interrupt is enabled"
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bitfld.long 0x00 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS]" "0: PMT Interrupt is disabled,1: PMT Interrupt is enabled"
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bitfld.long 0x00 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS]" "0: PHY Interrupt is disabled,1: PHY Interrupt is enabled"
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bitfld.long 0x00 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register" "0: RGMII or SMII Interrupt is disabled,1: RGMII or SMII Interrupt is enabled"
rgroup.long 0xB8++0x03
line.long 0x00 "MAC_RX_TX_STATUS,Receive Transmit Status"
bitfld.long 0x00 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_CONFIGURATION register" "0: No receive watchdog timeout,1: Receive watchdog timed out"
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bitfld.long 0x00 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0: No collision,1: Excessive collision is sensed"
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bitfld.long 0x00 4. "LCOL,Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode 512 bytes.." "0: No collision,1: Late collision is sensed"
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bitfld.long 0x00 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the DC bit is set in the MAC_CONFIGURATION register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0: No Excessive deferral,1: Excessive deferral"
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bitfld.long 0x00 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0: Carrier is present,1: Loss of carrier"
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bitfld.long 0x00 1. "NCARR,No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0: Carrier is present,1: No carrier"
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bitfld.long 0x00 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_CONFIGURATION register" "0: No Transmit Jabber Timeout,1: Transmit Jabber Timeout occurred"
group.long 0xC0++0x03
line.long 0x00 "MAC_PMT_CONTROL_STATUS,PMT Control and Status"
bitfld.long 0x00 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set the remote wake-up packet filter register pointer is reset to 3'b000" "0: Remote Wake-Up Packet Filter Register Pointer..,1: Remote Wake-Up Packet Filter Register Pointer.."
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rbitfld.long 0x00 24.--28. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7 15 or 31 when 4 8 or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN the MAC receiver drops all received frames until it receives the expected Wake-up frame" "0: Remote Wake-up Packet Forwarding is disabled,1: Remote Wake-up Packet Forwarding is enabled"
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bitfld.long 0x00 9. "GLBLUCAST,Global Unicast When this bit set any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet" "0: Global unicast is disabled,1: Global unicast is enabled"
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rbitfld.long 0x00 6. "RWKPRCVD,Remote Wake-Up Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a remote wake-up packet" "0: Remote wake-up packet is received,1: Remote wake-up packet is received"
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rbitfld.long 0x00 5. "MGKPRCVD,Magic Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a magic packet" "0: No Magic packet is received,1: Magic packet is received"
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bitfld.long 0x00 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set a power management event is generated when the MAC receives a remote wake-up packet" "0: Remote wake-up packet is disabled,1: Remote wake-up packet is enabled"
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bitfld.long 0x00 1. "MGKPKTEN,Magic Packet Enable When this bit is set a power management event is generated when the MAC receives a magic packet" "0: Magic Packet is disabled,1: Magic Packet is enabled"
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bitfld.long 0x00 0. "PWRDWN,Power Down When this bit is set the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet" "0: Power down is disabled,1: Power down is enabled"
group.long 0xC4++0x03
line.long 0x00 "MAC_RWK_PACKET_FILTER,Remote Wakeup Filter"
hexmask.long 0x00 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter This field contains the various controls of RWK Packet filter"
group.long 0xD0++0x03
line.long 0x00 "MAC_LPI_CONTROL_STATUS,LPI Control and Status"
bitfld.long 0x00 21. "LPITCSE,LPI Tx Clock Stop Enable When this bit is set the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped" "0: LPI Tx Clock Stop is disabled,1: LPI Tx Clock Stop is enabled"
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bitfld.long 0x00 20. "LPIATE,LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state" "0: LPI Timer is disabled,1: LPI Timer is enabled"
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bitfld.long 0x00 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side" "0: LPI Tx Automate is disabled,1: LPI Tx Automate is enabled"
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bitfld.long 0x00 18. "PLSEN,PHY Link Status Enable This bit enables the link status received on the RGMII SGMII or SMII Receive paths to be used for activating the LPI LS TIMER" "0: PHY Link Status is disabled,1: PHY Link Status is enabled"
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bitfld.long 0x00 17. "PLS,PHY Link Status This bit indicates the link status of the PHY" "0: link is down,1: link is okay (UP)"
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bitfld.long 0x00 16. "LPIEN,LPI Enable When this bit is set it instructs the MAC Transmitter to enter the LPI state" "0: LPI state is disabled,1: LPI state is enabled"
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rbitfld.long 0x00 9. "RLPIST,Receive LPI State When this bit is set it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface" "0: Receive LPI state not detected,1: Receive LPI state detected"
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rbitfld.long 0x00 8. "TLPIST,Transmit LPI State When this bit is set it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface" "0: Transmit LPI state not detected,1: Transmit LPI state detected"
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rbitfld.long 0x00 3. "RLPIEX,Receive LPI Exit When this bit is set it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface exited the LPI state and resumed the normal reception" "0: Receive LPI exit not detected,1: Receive LPI exit detected"
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rbitfld.long 0x00 2. "RLPIEN,Receive LPI Entry When this bit is set it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state" "0: Receive LPI entry not detected,1: Receive LPI entry detected"
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rbitfld.long 0x00 1. "TLPIEX,Transmit LPI Exit When this bit is set it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired" "0: Transmit LPI exit not detected,1: Transmit LPI exit detected"
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rbitfld.long 0x00 0. "TLPIEN,Transmit LPI Entry When this bit is set it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit" "0: Transmit LPI entry not detected,1: Transmit LPI entry detected"
group.long 0xD4++0x03
line.long 0x00 "MAC_LPI_TIMERS_CONTROL,LPI Timers Control"
hexmask.long.word 0x00 16.--25. 1. "LST,LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY"
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hexmask.long.word 0x00 0.--15. 1. "TWT,LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission"
group.long 0xD8++0x03
line.long 0x00 "MAC_LPI_ENTRY_TIMER,Tx LPI Entry Timer Control"
hexmask.long.tbyte 0x00 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode after it has transmitted all the frames"
group.long 0xDC++0x03
line.long 0x00 "MAC_ONEUS_TIC_COUNTER,One-microsecond Reference Timer"
hexmask.long.word 0x00 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us"
group.long 0xF8++0x03
line.long 0x00 "MAC_PHYIF_CONTROL_STATUS,PHY Interface Control and Status"
rbitfld.long 0x00 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0)" "0: Link down,1: Link up"
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rbitfld.long 0x00 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link" "0: bf_2500K,1: bf_25M,2: bf_125M,?..."
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rbitfld.long 0x00 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link" "0: Half-duplex mode,1: Full-duplex mode"
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bitfld.long 0x00 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII SGMII or SMII interface" "0: Link down,1: Link up"
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bitfld.long 0x00 0. "TC,Transmit Configuration in RGMII SGMII or SMII When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII SMII or SGMII port" "0: Disable Transmit Configuration in RGMII SGMII..,1: Enable Transmit Configuration in RGMII SGMII.."
rgroup.long 0x110++0x03
line.long 0x00 "MAC_VERSION,MAC Version"
hexmask.long.byte 0x00 8.--15. 1. "USERVER,User-defined Version (8'h10)"
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hexmask.long.byte 0x00 0.--7. 1. "SNPSVER,Synopsys-defined Version"
rgroup.long 0x114++0x03
line.long 0x00 "MAC_DEBUG,MAC Debug"
bitfld.long 0x00 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission"
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bitfld.long 0x00 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0: MAC GMII or MII Transmit Protocol Engine..,1: MAC GMII or MII Transmit Protocol Engine.."
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bitfld.long 0x00 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3"
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bitfld.long 0x00 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0: MAC GMII or MII Receive Protocol Engine..,1: MAC GMII or MII Receive Protocol Engine.."
rgroup.long 0x11C++0x03
line.long 0x00 "MAC_HW_FEATURE0,Optional Features or Functions 0"
bitfld.long 0x00 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: REVMIII"
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bitfld.long 0x00 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected" "0: Source Address or VLAN Insertion Enable..,1: Source Address or VLAN Insertion Enable.."
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bitfld.long 0x00 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: Internal,1: External,2: BOTH,?..."
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bitfld.long 0x00 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected" "0: MAC Addresses 64-127 Select option is not..,1: MAC Addresses 64-127 Select option is selected"
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bitfld.long 0x00 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected" "0: MAC Addresses 32-63 Select option is not..,1: MAC Addresses 32-63 Select option is selected"
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bitfld.long 0x00 18.--22. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected" "0: Receive Checksum Offload Enable option is not..,1: Receive Checksum Offload Enable option is.."
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bitfld.long 0x00 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected" "0: Transmit Checksum Offload Enable option is..,1: Transmit Checksum Offload Enable option is.."
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bitfld.long 0x00 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected" "0: Energy Efficient Ethernet Enable option is..,1: Energy Efficient Ethernet Enable option is.."
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bitfld.long 0x00 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: IEEE 1588-2008 Timestamp Enable option is not..,1: IEEE 1588-2008 Timestamp Enable option is.."
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bitfld.long 0x00 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected" "0: ARP Offload Enable option is not selected,1: ARP Offload Enable option is selected"
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bitfld.long 0x00 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected" "0: RMON Module Enable option is not selected,1: RMON Module Enable option is selected"
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bitfld.long 0x00 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected" "0: PMT Magic Packet Enable option is not selected,1: PMT Magic Packet Enable option is selected"
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bitfld.long 0x00 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected" "0: PMT Remote Wake-up Packet Enable option is..,1: PMT Remote Wake-up Packet Enable option is.."
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bitfld.long 0x00 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected" "0: SMA (MDIO) Interface not selected,1: SMA (MDIO) Interface selected"
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bitfld.long 0x00 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected" "0: VLAN Hash Filter not selected,1: VLAN Hash Filter selected"
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bitfld.long 0x00 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is selected" "0: No PCS Registers (TBI SGMII or RTBI PHY..,1: PCS Registers (TBI SGMII or RTBI PHY interface)"
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bitfld.long 0x00 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected" "0: No Half-duplex support,1: Half-duplex support"
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bitfld.long 0x00 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation" "0: No 1000 Mbps support,1: 1000 Mbps support"
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bitfld.long 0x00 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation" "0: No 10 or 100 Mbps support,1: 10 or 100 Mbps support"
rgroup.long 0x120++0x03
line.long 0x00 "MAC_HW_FEATURE1,Optional Features or Functions 1"
bitfld.long 0x00 27.--30. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters" "0: No L3 or L4 Filter,1: 1 L3 or L4 Filter,2: 2 L3 or L4 Filters,3: 3 L3 or L4 Filters,4: 4 L3 or L4 Filters,5: 5 L3 or L4 Filters,6: 6 L3 or L4 Filters,7: 7 L3 or L4 Filters,8: 8 L3 or L4 Filters,?..."
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bitfld.long 0x00 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table" "0: No hash table,1: bf_64,2: bf_128,3: bf_256"
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bitfld.long 0x00 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected" "0: One Step for PTP over UDP/IP Feature is not..,1: One Step for PTP over UDP/IP Feature is.."
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bitfld.long 0x00 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected" "0: Rx Side Only AV Feature is not selected,1: Rx Side Only AV Feature is selected"
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bitfld.long 0x00 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected" "0: AV Feature is not selected,1: AV Feature is selected"
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bitfld.long 0x00 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected" "0: DMA Debug Registers option is not selected,1: DMA Debug Registers option is selected"
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bitfld.long 0x00 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected" "0: TCP Segmentation Offload Feature is not..,1: TCP Segmentation Offload Feature is selected"
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bitfld.long 0x00 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected" "0: Split Header Feature is not selected,1: Split Header Feature is selected"
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bitfld.long 0x00 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected" "0: DCB Feature is not selected,1: DCB Feature is selected"
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bitfld.long 0x00 14.--15. "ADDR64,Address Width" "0: bf_32,1: bf_40,2: bf_48,?..."
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bitfld.long 0x00 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected" "0: IEEE 1588 High Word Register option is not..,1: IEEE 1588 High Word Register option is selected"
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bitfld.long 0x00 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected" "0: PTP Offload feature is not selected,1: PTP Offload feature is selected"
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bitfld.long 0x00 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected" "0: One-Step Timestamping feature is not selected,1: One-Step Timestamping feature is selected"
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bitfld.long 0x00 6.--10. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: bf_32KB,9: bf_64KB,10: bf_128KB,?..."
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bitfld.long 0x00 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected" "0: Single Port RAM feature is not selected,1: Single Port RAM feature is selected"
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bitfld.long 0x00 0.--4. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: bf_32KB,9: bf_64KB,10: bf_128KB,11: bf_256KB,?..."
rgroup.long 0x124++0x03
line.long 0x00 "MAC_HW_FEATURE2,Optional Features or Functions 2"
bitfld.long 0x00 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary input,3: 3 auxiliary input,4: 4 auxiliary input,?..."
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bitfld.long 0x00 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS output,3: 3 PPS output,4: 4 PPS output,?..."
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bitfld.long 0x00 18.--21. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels" "0: 1 MTL Tx Channel,1: 2 MTL Tx Channels,2: 3 MTL Tx Channels,3: 4 MTL Tx Channels,4: 5 MTL Tx Channels,?..."
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bitfld.long 0x00 12.--15. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels" "0: 1 MTL Rx Channel,1: 2 MTL Rx Channels,2: 3 MTL Rx Channels,3: 4 MTL Rx Channels,4: 5 MTL Rx Channels,?..."
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bitfld.long 0x00 6.--9. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues" "0: 1 MTL Tx Queue,1: 2 MTL Tx Queues,2: 3 MTL Tx Queues,3: 4 MTL Tx Queues,4: 5 MTL Tx Queues,?..."
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bitfld.long 0x00 0.--3. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues" "0: 1 MTL Rx Queue,1: 2 MTL Rx Queues,2: 3 MTL Rx Queues,3: 4 MTL Rx Queues,4: 5 MTL Rx Queues,?..."
rgroup.long 0x128++0x03
line.long 0x00 "MAC_HW_FEATURE3,Optional Features or Functions 3"
bitfld.long 0x00 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features" "0: No Safety features selected,1: Only ECC protection for external memory..,2: All the Automotive Safety features are..,3: All the Automotive Safety features are.."
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bitfld.long 0x00 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is.."
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bitfld.long 0x00 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected" "0: Frame Preemption Enable feature is not selected,1: Frame Preemption Enable feature is selected"
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bitfld.long 0x00 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field" "0: Width not configured,1: WIDTH16,2: WIDTH20,3: WIDTH24"
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bitfld.long 0x00 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5" "0: No Depth configured,1: DEPTH64,2: DEPTH128,3: DEPTH256,4: DEPTH512,5: DEPTH1024,?..."
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bitfld.long 0x00 16. "ESTSEL,Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.."
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bitfld.long 0x00 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser" "0: 64 Entries,1: 128 Entries,2: 256 Entries,?..."
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bitfld.long 0x00 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser" "0: bf_64BYTES,1: bf_128BYTES,2: bf_256BYTES,?..."
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bitfld.long 0x00 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected" "0: Flexible Receive Parser feature is not selected,1: Flexible Receive Parser feature is selected"
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bitfld.long 0x00 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected" "0: Broadcast/Multicast Packet Duplication..,1: Broadcast/Multicast Packet Duplication.."
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bitfld.long 0x00 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected" "0: Double VLAN option is not selected,1: Double VLAN option is selected"
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bitfld.long 0x00 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected" "0: Enable Queue/Channel based VLAN tag insertion..,1: Enable Queue/Channel based VLAN tag insertion.."
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bitfld.long 0x00 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?..."
group.long 0x200++0x03
line.long 0x00 "MAC_MDIO_ADDRESS,MDIO Address"
bitfld.long 0x00 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit" "0: Preamble Suppression disabled,1: Preamble Suppression enabled"
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bitfld.long 0x00 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)" "0: Back to Back transactions disabled,1: Back to Back transactions enabled"
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bitfld.long 0x00 21.--25. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design" "0: CSR clock = 60-100 MHz MDC clock = CSR clock/42,1: CSR clock = 100-150 MHz MDC clock = CSR..,2: CSR clock = 20-35 MHz MDC clock = CSR clock/16,3: CSR clock = 35-60 MHz MDC clock = CSR clock/26,4: CSR clock = 150-250 MHz MDC clock = CSR..,5: CSR clock = 250-300 MHz MDC clock = CSR..,6: CSR clock = 300-500 MHz MDC clock = CSR..,7: CSR clock = 500-800 MHz MDC clock = CSR,?,?,?,11: 0) ensures that the MDC clock is approximately,?..."
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bitfld.long 0x00 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0: Skip Address Packet is disabled,1: Skip Address Packet is enabled"
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bitfld.long 0x00 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII GOC_1 and GOC_O is encoded as follows" "0: GMII Operation Command 1 is disabled,1: GMII Operation Command 1 is enabled"
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bitfld.long 0x00 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII" "0: GMII Operation Command 0 is disabled,1: GMII Operation Command 0 is enabled"
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bitfld.long 0x00 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0: Clause 45 PHY is disabled,1: Clause 45 PHY is enabled"
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bitfld.long 0x00 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave" "0: GMII Busy is disabled,1: GMII Busy is enabled"
group.long 0x204++0x03
line.long 0x00 "MAC_MDIO_DATA,MAC MDIO Data"
hexmask.long.word 0x00 16.--31. 1. "RA,Register Address This field is valid only when C45E is set"
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hexmask.long.word 0x00 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation"
group.long 0x230++0x03
line.long 0x00 "MAC_CSR_SW_CTRL,CSR Software Control"
bitfld.long 0x00 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it" "0: Register Clear on Write 1 is disabled,1: Register Clear on Write 1 is enabled"
group.long 0x234++0x03
line.long 0x00 "MAC_FPE_CTRL_STS,Frame Preemption Control"
bitfld.long 0x00 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field)" "0: Not transmitted Respond Frame,1: transmitted Respond Frame"
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bitfld.long 0x00 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field)" "0: Not transmitted Verify Frame,1: transmitted Verify Frame"
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bitfld.long 0x00 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received" "0: Not received Respond Frame,1: Received Respond Frame"
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bitfld.long 0x00 16. "RVER,Received Verify Frame Set when a Verify mPacket is received" "0: Not received Verify Frame,1: Received Verify Frame"
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bitfld.long 0x00 3. "S1_SET_0,Synopsys Reserved Must be set to 0" "0,1"
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bitfld.long 0x00 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket" "0: Send Respond mPacket is disabled,1: Send Respond mPacket is enabled"
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bitfld.long 0x00 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket" "0: Send Verify mPacket is disabled,1: Send Verify mPacket is enabled"
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bitfld.long 0x00 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled" "0: Tx Frame Preemption is disabled,1: Tx Frame Preemption is enabled"
rgroup.long 0x240++0x03
line.long 0x00 "MAC_PRESN_TIME_NS,32-bit Binary Rollover Equivalent Time"
hexmask.long 0x00 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns"
group.long 0x244++0x03
line.long 0x00 "MAC_PRESN_TIME_UPDT,MAC 1722 Presentation Time"
hexmask.long 0x00 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time"
group.long 0x300++0x03
line.long 0x00 "MAC_ADDRESS0_HIGH,MAC Address0 High"
rbitfld.long 0x00 31. "AE,Address Enable This bit is always set to 1" "0: INVALID,1: This bit is always set to 1"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address"
group.long 0x304++0x03
line.long 0x00 "MAC_ADDRESS0_LOW,MAC Address0 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address"
group.long 0x308++0x03
line.long 0x00 "MAC_ADDRESS1_HIGH,MAC Address1 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x30C++0x03
line.long 0x00 "MAC_ADDRESS1_LOW,MAC Address1 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x310++0x03
line.long 0x00 "MAC_ADDRESS2_HIGH,MAC Address2 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x314++0x03
line.long 0x00 "MAC_ADDRESS2_LOW,MAC Address2 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x318++0x03
line.long 0x00 "MAC_ADDRESS3_HIGH,MAC Address3 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x31C++0x03
line.long 0x00 "MAC_ADDRESS3_LOW,MAC Address3 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x320++0x03
line.long 0x00 "MAC_ADDRESS4_HIGH,MAC Address4 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x324++0x03
line.long 0x00 "MAC_ADDRESS4_LOW,MAC Address4 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x328++0x03
line.long 0x00 "MAC_ADDRESS5_HIGH,MAC Address5 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x32C++0x03
line.long 0x00 "MAC_ADDRESS5_LOW,MAC Address5 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x330++0x03
line.long 0x00 "MAC_ADDRESS6_HIGH,MAC Address6 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x334++0x03
line.long 0x00 "MAC_ADDRESS6_LOW,MAC Address6 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x338++0x03
line.long 0x00 "MAC_ADDRESS7_HIGH,MAC Address7 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x33C++0x03
line.long 0x00 "MAC_ADDRESS7_LOW,MAC Address7 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x340++0x03
line.long 0x00 "MAC_ADDRESS8_HIGH,MAC Address8 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x344++0x03
line.long 0x00 "MAC_ADDRESS8_LOW,MAC Address8 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x348++0x03
line.long 0x00 "MAC_ADDRESS9_HIGH,MAC Address9 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x34C++0x03
line.long 0x00 "MAC_ADDRESS9_LOW,MAC Address9 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x350++0x03
line.long 0x00 "MAC_ADDRESS10_HIGH,MAC Address10 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x354++0x03
line.long 0x00 "MAC_ADDRESS10_LOW,MAC Address10 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x358++0x03
line.long 0x00 "MAC_ADDRESS11_HIGH,MAC Address11 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x35C++0x03
line.long 0x00 "MAC_ADDRESS11_LOW,MAC Address11 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x360++0x03
line.long 0x00 "MAC_ADDRESS12_HIGH,MAC Address12 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x364++0x03
line.long 0x00 "MAC_ADDRESS12_LOW,MAC Address12 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x368++0x03
line.long 0x00 "MAC_ADDRESS13_HIGH,MAC Address13 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x36C++0x03
line.long 0x00 "MAC_ADDRESS13_LOW,MAC Address13 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x370++0x03
line.long 0x00 "MAC_ADDRESS14_HIGH,MAC Address14 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x374++0x03
line.long 0x00 "MAC_ADDRESS14_LOW,MAC Address14 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x378++0x03
line.long 0x00 "MAC_ADDRESS15_HIGH,MAC Address15 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x37C++0x03
line.long 0x00 "MAC_ADDRESS15_LOW,MAC Address15 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x380++0x03
line.long 0x00 "MAC_ADDRESS16_HIGH,MAC Address16 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x384++0x03
line.long 0x00 "MAC_ADDRESS16_LOW,MAC Address16 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x388++0x03
line.long 0x00 "MAC_ADDRESS17_HIGH,MAC Address17 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x38C++0x03
line.long 0x00 "MAC_ADDRESS17_LOW,MAC Address17 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x390++0x03
line.long 0x00 "MAC_ADDRESS18_HIGH,MAC Address18 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x394++0x03
line.long 0x00 "MAC_ADDRESS18_LOW,MAC Address18 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x398++0x03
line.long 0x00 "MAC_ADDRESS19_HIGH,MAC Address19 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x39C++0x03
line.long 0x00 "MAC_ADDRESS19_LOW,MAC Address19 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3A0++0x03
line.long 0x00 "MAC_ADDRESS20_HIGH,MAC Address20 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3A4++0x03
line.long 0x00 "MAC_ADDRESS20_LOW,MAC Address20 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3A8++0x03
line.long 0x00 "MAC_ADDRESS21_HIGH,MAC Address21 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3AC++0x03
line.long 0x00 "MAC_ADDRESS21_LOW,MAC Address21 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3B0++0x03
line.long 0x00 "MAC_ADDRESS22_HIGH,MAC Address22 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3B4++0x03
line.long 0x00 "MAC_ADDRESS22_LOW,MAC Address22 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3B8++0x03
line.long 0x00 "MAC_ADDRESS23_HIGH,MAC Address23 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3BC++0x03
line.long 0x00 "MAC_ADDRESS23_LOW,MAC Address23 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3C0++0x03
line.long 0x00 "MAC_ADDRESS24_HIGH,MAC Address24 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3C4++0x03
line.long 0x00 "MAC_ADDRESS24_LOW,MAC Address24 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3C8++0x03
line.long 0x00 "MAC_ADDRESS25_HIGH,MAC Address25 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3CC++0x03
line.long 0x00 "MAC_ADDRESS25_LOW,MAC Address25 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3D0++0x03
line.long 0x00 "MAC_ADDRESS26_HIGH,MAC Address26 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3D4++0x03
line.long 0x00 "MAC_ADDRESS26_LOW,MAC Address26 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3D8++0x03
line.long 0x00 "MAC_ADDRESS27_HIGH,MAC Address27 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3DC++0x03
line.long 0x00 "MAC_ADDRESS27_LOW,MAC Address27 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3E0++0x03
line.long 0x00 "MAC_ADDRESS28_HIGH,MAC Address28 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3E4++0x03
line.long 0x00 "MAC_ADDRESS28_LOW,MAC Address28 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3E8++0x03
line.long 0x00 "MAC_ADDRESS29_HIGH,MAC Address29 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3EC++0x03
line.long 0x00 "MAC_ADDRESS29_LOW,MAC Address29 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3F0++0x03
line.long 0x00 "MAC_ADDRESS30_HIGH,MAC Address30 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3F4++0x03
line.long 0x00 "MAC_ADDRESS30_LOW,MAC Address30 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x3F8++0x03
line.long 0x00 "MAC_ADDRESS31_HIGH,MAC Address31 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x3FC++0x03
line.long 0x00 "MAC_ADDRESS31_LOW,MAC Address31 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x400++0x03
line.long 0x00 "MAC_ADDRESS32_HIGH,MAC Address32 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x404++0x03
line.long 0x00 "MAC_ADDRESS32_LOW,MAC Address32 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x408++0x03
line.long 0x00 "MAC_ADDRESS33_HIGH,MAC Address33 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x40C++0x03
line.long 0x00 "MAC_ADDRESS33_LOW,MAC Address33 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x410++0x03
line.long 0x00 "MAC_ADDRESS34_HIGH,MAC Address34 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x414++0x03
line.long 0x00 "MAC_ADDRESS34_LOW,MAC Address34 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x418++0x03
line.long 0x00 "MAC_ADDRESS35_HIGH,MAC Address35 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x41C++0x03
line.long 0x00 "MAC_ADDRESS35_LOW,MAC Address35 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x420++0x03
line.long 0x00 "MAC_ADDRESS36_HIGH,MAC Address36 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x424++0x03
line.long 0x00 "MAC_ADDRESS36_LOW,MAC Address36 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x428++0x03
line.long 0x00 "MAC_ADDRESS37_HIGH,MAC Address37 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x42C++0x03
line.long 0x00 "MAC_ADDRESS37_LOW,MAC Address37 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x430++0x03
line.long 0x00 "MAC_ADDRESS38_HIGH,MAC Address38 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x434++0x03
line.long 0x00 "MAC_ADDRESS38_LOW,MAC Address38 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x438++0x03
line.long 0x00 "MAC_ADDRESS39_HIGH,MAC Address39 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x43C++0x03
line.long 0x00 "MAC_ADDRESS39_LOW,MAC Address39 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x440++0x03
line.long 0x00 "MAC_ADDRESS40_HIGH,MAC Address40 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x444++0x03
line.long 0x00 "MAC_ADDRESS40_LOW,MAC Address40 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x448++0x03
line.long 0x00 "MAC_ADDRESS41_HIGH,MAC Address41 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x44C++0x03
line.long 0x00 "MAC_ADDRESS41_LOW,MAC Address41 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x450++0x03
line.long 0x00 "MAC_ADDRESS42_HIGH,MAC Address42 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x454++0x03
line.long 0x00 "MAC_ADDRESS42_LOW,MAC Address42 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x458++0x03
line.long 0x00 "MAC_ADDRESS43_HIGH,MAC Address43 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x45C++0x03
line.long 0x00 "MAC_ADDRESS43_LOW,MAC Address43 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x460++0x03
line.long 0x00 "MAC_ADDRESS44_HIGH,MAC Address44 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x464++0x03
line.long 0x00 "MAC_ADDRESS44_LOW,MAC Address44 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x468++0x03
line.long 0x00 "MAC_ADDRESS45_HIGH,MAC Address45 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x46C++0x03
line.long 0x00 "MAC_ADDRESS45_LOW,MAC Address45 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x470++0x03
line.long 0x00 "MAC_ADDRESS46_HIGH,MAC Address46 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x474++0x03
line.long 0x00 "MAC_ADDRESS46_LOW,MAC Address46 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x478++0x03
line.long 0x00 "MAC_ADDRESS47_HIGH,MAC Address47 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x47C++0x03
line.long 0x00 "MAC_ADDRESS47_LOW,MAC Address47 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x480++0x03
line.long 0x00 "MAC_ADDRESS48_HIGH,MAC Address48 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x484++0x03
line.long 0x00 "MAC_ADDRESS48_LOW,MAC Address48 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x488++0x03
line.long 0x00 "MAC_ADDRESS49_HIGH,MAC Address49 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x48C++0x03
line.long 0x00 "MAC_ADDRESS49_LOW,MAC Address49 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x490++0x03
line.long 0x00 "MAC_ADDRESS50_HIGH,MAC Address50 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x494++0x03
line.long 0x00 "MAC_ADDRESS50_LOW,MAC Address50 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x498++0x03
line.long 0x00 "MAC_ADDRESS51_HIGH,MAC Address51 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x49C++0x03
line.long 0x00 "MAC_ADDRESS51_LOW,MAC Address51 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4A0++0x03
line.long 0x00 "MAC_ADDRESS52_HIGH,MAC Address52 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4A4++0x03
line.long 0x00 "MAC_ADDRESS52_LOW,MAC Address52 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4A8++0x03
line.long 0x00 "MAC_ADDRESS53_HIGH,MAC Address53 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4AC++0x03
line.long 0x00 "MAC_ADDRESS53_LOW,MAC Address53 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4B0++0x03
line.long 0x00 "MAC_ADDRESS54_HIGH,MAC Address54 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4B4++0x03
line.long 0x00 "MAC_ADDRESS54_LOW,MAC Address54 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4B8++0x03
line.long 0x00 "MAC_ADDRESS55_HIGH,MAC Address55 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4BC++0x03
line.long 0x00 "MAC_ADDRESS55_LOW,MAC Address55 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4C0++0x03
line.long 0x00 "MAC_ADDRESS56_HIGH,MAC Address56 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4C4++0x03
line.long 0x00 "MAC_ADDRESS56_LOW,MAC Address56 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4C8++0x03
line.long 0x00 "MAC_ADDRESS57_HIGH,MAC Address57 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4CC++0x03
line.long 0x00 "MAC_ADDRESS57_LOW,MAC Address57 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4D0++0x03
line.long 0x00 "MAC_ADDRESS58_HIGH,MAC Address58 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4D4++0x03
line.long 0x00 "MAC_ADDRESS58_LOW,MAC Address58 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4D8++0x03
line.long 0x00 "MAC_ADDRESS59_HIGH,MAC Address59 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4DC++0x03
line.long 0x00 "MAC_ADDRESS59_LOW,MAC Address59 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4E0++0x03
line.long 0x00 "MAC_ADDRESS60_HIGH,MAC Address60 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4E4++0x03
line.long 0x00 "MAC_ADDRESS60_LOW,MAC Address60 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4E8++0x03
line.long 0x00 "MAC_ADDRESS61_HIGH,MAC Address61 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4EC++0x03
line.long 0x00 "MAC_ADDRESS61_LOW,MAC Address61 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4F0++0x03
line.long 0x00 "MAC_ADDRESS62_HIGH,MAC Address62 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4F4++0x03
line.long 0x00 "MAC_ADDRESS62_LOW,MAC Address62 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x4F8++0x03
line.long 0x00 "MAC_ADDRESS63_HIGH,MAC Address63 High"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
newline
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
group.long 0x4FC++0x03
line.long 0x00 "MAC_ADDRESS63_LOW,MAC Address63 Low"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
group.long 0x700++0x03
line.long 0x00 "MAC_MMC_CONTROL,MMC Control"
bitfld.long 0x00 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit" "0: Update MMC Counters for Dropped Broadcast..,1: Update MMC Counters for Dropped Broadcast.."
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bitfld.long 0x00 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0: Full-Half Preset is disabled,1: Full-Half Preset is enabled"
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bitfld.long 0x00 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0: Counters Preset is disabled,1: Counters Preset is enabled"
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bitfld.long 0x00 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0: MMC Counter Freeze is disabled,1: MMC Counter Freeze is enabled"
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bitfld.long 0x00 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0: Reset on Read is disabled,1: Reset on Read is enabled"
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bitfld.long 0x00 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0: Counter Stop Rollover is disabled,1: Counter Stop Rollover is enabled"
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bitfld.long 0x00 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
rgroup.long 0x704++0x03
line.long 0x00 "MAC_MMC_RX_INTERRUPT,MMC Rx Interrupt"
bitfld.long 0x00 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition Counter Interrupt..,1: MMC Receive LPI transition Counter Interrupt.."
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bitfld.long 0x00 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond Counter Interrupt..,1: MMC Receive LPI microsecond Counter Interrupt.."
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bitfld.long 0x00 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
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bitfld.long 0x00 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
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bitfld.long 0x00 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
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bitfld.long 0x00 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
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bitfld.long 0x00 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
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bitfld.long 0x00 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
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bitfld.long 0x00 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
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bitfld.long 0x00 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
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bitfld.long 0x00 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
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bitfld.long 0x00 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
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bitfld.long 0x00 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
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bitfld.long 0x00 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
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bitfld.long 0x00 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
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bitfld.long 0x00 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
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bitfld.long 0x00 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
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bitfld.long 0x00 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
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bitfld.long 0x00 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
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bitfld.long 0x00 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt..,1: MMC Receive Good Octet Counter Interrupt.."
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bitfld.long 0x00 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
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bitfld.long 0x00 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
rgroup.long 0x708++0x03
line.long 0x00 "MAC_MMC_TX_INTERRUPT,MMC Tx Interrupt"
bitfld.long 0x00 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition Counter Interrupt..,1: MMC Transmit LPI transition Counter Interrupt.."
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bitfld.long 0x00 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond Counter..,1: MMC Transmit LPI microsecond Counter.."
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bitfld.long 0x00 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
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bitfld.long 0x00 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
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bitfld.long 0x00 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
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bitfld.long 0x00 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
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bitfld.long 0x00 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
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bitfld.long 0x00 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
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bitfld.long 0x00 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
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bitfld.long 0x00 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
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bitfld.long 0x00 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
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bitfld.long 0x00 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
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bitfld.long 0x00 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
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bitfld.long 0x00 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
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bitfld.long 0x00 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
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bitfld.long 0x00 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
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bitfld.long 0x00 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
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bitfld.long 0x00 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
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bitfld.long 0x00 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
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bitfld.long 0x00 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
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bitfld.long 0x00 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
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bitfld.long 0x00 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
group.long 0x70C++0x03
line.long 0x00 "MAC_MMC_RX_INTERRUPT_MASK,MMC Rx Interrupt Mask"
bitfld.long 0x00 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition counter interrupt..,1: MMC Receive LPI transition counter interrupt.."
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bitfld.long 0x00 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond counter interrupt..,1: MMC Receive LPI microsecond counter interrupt.."
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bitfld.long 0x00 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
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bitfld.long 0x00 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
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bitfld.long 0x00 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
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bitfld.long 0x00 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
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bitfld.long 0x00 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
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bitfld.long 0x00 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
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bitfld.long 0x00 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
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bitfld.long 0x00 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
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bitfld.long 0x00 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
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bitfld.long 0x00 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
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bitfld.long 0x00 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
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bitfld.long 0x00 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
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bitfld.long 0x00 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
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bitfld.long 0x00 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
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bitfld.long 0x00 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
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bitfld.long 0x00 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
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bitfld.long 0x00 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
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bitfld.long 0x00 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Mask..,1: MMC Receive Good Octet Counter Interrupt Mask.."
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bitfld.long 0x00 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
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bitfld.long 0x00 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
group.long 0x710++0x03
line.long 0x00 "MAC_MMC_TX_INTERRUPT_MASK,MMC Tx Interrupt Mask"
bitfld.long 0x00 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition counter interrupt..,1: MMC Transmit LPI transition counter interrupt.."
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bitfld.long 0x00 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond counter..,1: MMC Transmit LPI microsecond counter.."
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bitfld.long 0x00 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
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bitfld.long 0x00 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
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bitfld.long 0x00 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
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bitfld.long 0x00 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
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bitfld.long 0x00 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
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bitfld.long 0x00 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
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bitfld.long 0x00 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
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bitfld.long 0x00 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
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bitfld.long 0x00 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
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bitfld.long 0x00 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
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bitfld.long 0x00 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
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bitfld.long 0x00 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
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bitfld.long 0x00 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
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bitfld.long 0x00 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
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bitfld.long 0x00 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
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bitfld.long 0x00 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
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bitfld.long 0x00 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
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bitfld.long 0x00 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
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bitfld.long 0x00 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
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bitfld.long 0x00 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
rgroup.long 0x714++0x03
line.long 0x00 "MAC_TX_OCTET_COUNT_GOOD_BAD,Tx Octet Count Good and Bad"
hexmask.long 0x00 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets"
rgroup.long 0x718++0x03
line.long 0x00 "MAC_TX_PACKET_COUNT_GOOD_BAD,Tx Packet Count Good and Bad"
hexmask.long 0x00 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets"
rgroup.long 0x71C++0x03
line.long 0x00 "MAC_TX_BROADCAST_PACKETS_GOOD,Tx Broadcast Packets Good"
hexmask.long 0x00 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted"
rgroup.long 0x720++0x03
line.long 0x00 "MAC_TX_MULTICAST_PACKETS_GOOD,Tx Multicast Packets Good"
hexmask.long 0x00 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted"
rgroup.long 0x724++0x03
line.long 0x00 "MAC_TX_64OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 64-Byte Packets"
hexmask.long 0x00 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets"
rgroup.long 0x728++0x03
line.long 0x00 "MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 65 to 127-Byte Packets"
hexmask.long 0x00 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x72C++0x03
line.long 0x00 "MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 128 to 255-Byte Packets"
hexmask.long 0x00 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x730++0x03
line.long 0x00 "MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 256 to 511-Byte Packets"
hexmask.long 0x00 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x734++0x03
line.long 0x00 "MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 512 to 1023-Byte Packets"
hexmask.long 0x00 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x738++0x03
line.long 0x00 "MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 1024 to Max-Byte Packets"
hexmask.long 0x00 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x73C++0x03
line.long 0x00 "MAC_TX_UNICAST_PACKETS_GOOD_BAD,Good and Bad Unicast Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted"
rgroup.long 0x740++0x03
line.long 0x00 "MAC_TX_MULTICAST_PACKETS_GOOD_BAD,Good and Bad Multicast Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted"
rgroup.long 0x744++0x03
line.long 0x00 "MAC_TX_BROADCAST_PACKETS_GOOD_BAD,Good and Bad Broadcast Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted"
rgroup.long 0x748++0x03
line.long 0x00 "MAC_TX_UNDERFLOW_ERROR_PACKETS,Tx Packets Aborted By Underflow Error"
hexmask.long 0x00 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error"
rgroup.long 0x74C++0x03
line.long 0x00 "MAC_TX_SINGLE_COLLISION_GOOD_PACKETS,Single Collision Good Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode"
rgroup.long 0x750++0x03
line.long 0x00 "MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Multiple Collision Good Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode"
rgroup.long 0x754++0x03
line.long 0x00 "MAC_TX_DEFERRED_PACKETS,Deferred Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode"
rgroup.long 0x758++0x03
line.long 0x00 "MAC_TX_LATE_COLLISION_PACKETS,Late Collision Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error"
rgroup.long 0x75C++0x03
line.long 0x00 "MAC_TX_EXCESSIVE_COLLISION_PACKETS,Excessive Collision Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors"
rgroup.long 0x760++0x03
line.long 0x00 "MAC_TX_CARRIER_ERROR_PACKETS,Carrier Error Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)"
rgroup.long 0x764++0x03
line.long 0x00 "MAC_TX_OCTET_COUNT_GOOD,Bytes Transmitted in Good Packets"
hexmask.long 0x00 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets"
rgroup.long 0x768++0x03
line.long 0x00 "MAC_TX_PACKET_COUNT_GOOD,Good Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted"
rgroup.long 0x76C++0x03
line.long 0x00 "MAC_TX_EXCESSIVE_DEFERRAL_ERROR,Packets Aborted By Excessive Deferral Error"
hexmask.long 0x00 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)"
rgroup.long 0x770++0x03
line.long 0x00 "MAC_TX_PAUSE_PACKETS,Pause Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted"
rgroup.long 0x774++0x03
line.long 0x00 "MAC_TX_VLAN_PACKETS_GOOD,Good VLAN Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted"
rgroup.long 0x778++0x03
line.long 0x00 "MAC_TX_OSIZE_PACKETS_GOOD,Good Oversize Packets Transmitted"
hexmask.long 0x00 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in S2KP bit of the CONFIGURATION register)"
rgroup.long 0x780++0x03
line.long 0x00 "MAC_RX_PACKETS_COUNT_GOOD_BAD,Good and Bad Packets Received"
hexmask.long 0x00 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received"
rgroup.long 0x784++0x03
line.long 0x00 "MAC_RX_OCTET_COUNT_GOOD_BAD,Bytes in Good and Bad Packets Received"
hexmask.long 0x00 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets"
rgroup.long 0x788++0x03
line.long 0x00 "MAC_RX_OCTET_COUNT_GOOD,Bytes in Good Packets Received"
hexmask.long 0x00 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets"
rgroup.long 0x78C++0x03
line.long 0x00 "MAC_RX_BROADCAST_PACKETS_GOOD,Good Broadcast Packets Received"
hexmask.long 0x00 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received"
rgroup.long 0x790++0x03
line.long 0x00 "MAC_RX_MULTICAST_PACKETS_GOOD,Good Multicast Packets Received"
hexmask.long 0x00 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received"
rgroup.long 0x794++0x03
line.long 0x00 "MAC_RX_CRC_ERROR_PACKETS,CRC Error Packets Received"
hexmask.long 0x00 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error"
rgroup.long 0x798++0x03
line.long 0x00 "MAC_RX_ALIGNMENT_ERROR_PACKETS,Alignment Error Packets Received"
hexmask.long 0x00 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error"
rgroup.long 0x79C++0x03
line.long 0x00 "MAC_RX_RUNT_ERROR_PACKETS,Runt Error Packets Received"
hexmask.long 0x00 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error"
rgroup.long 0x7A0++0x03
line.long 0x00 "MAC_RX_JABBER_ERROR_PACKETS,Jabber Error Packets Received"
hexmask.long 0x00 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error"
rgroup.long 0x7A4++0x03
line.long 0x00 "MAC_RX_UNDERSIZE_PACKETS_GOOD,Good Undersize Packets Received"
hexmask.long 0x00 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors"
rgroup.long 0x7A8++0x03
line.long 0x00 "MAC_RX_OVERSIZE_PACKETS_GOOD,Good Oversize Packets Received"
hexmask.long 0x00 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION.."
rgroup.long 0x7AC++0x03
line.long 0x00 "MAC_RX_64OCTETS_PACKETS_GOOD_BAD,Good and Bad 64-Byte Packets Received"
hexmask.long 0x00 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble"
rgroup.long 0x7B0++0x03
line.long 0x00 "MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD,Good and Bad 64-to-127 Byte Packets Received"
hexmask.long 0x00 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7B4++0x03
line.long 0x00 "MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD,Good and Bad 128-to-255 Byte Packets Received"
hexmask.long 0x00 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7B8++0x03
line.long 0x00 "MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD,Good and Bad 256-to-511 Byte Packets Received"
hexmask.long 0x00 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7BC++0x03
line.long 0x00 "MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD,Good and Bad 512-to-1023 Byte Packets Received"
hexmask.long 0x00 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7C0++0x03
line.long 0x00 "MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Good and Bad 1024-to-Max Byte Packets Received"
hexmask.long 0x00 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7C4++0x03
line.long 0x00 "MAC_RX_UNICAST_PACKETS_GOOD,Good Unicast Packets Received"
hexmask.long 0x00 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received"
rgroup.long 0x7C8++0x03
line.long 0x00 "MAC_RX_LENGTH_ERROR_PACKETS,Length Error Packets Received"
hexmask.long 0x00 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field"
rgroup.long 0x7CC++0x03
line.long 0x00 "MAC_RX_OUT_OF_RANGE_TYPE_PACKETS,Out-of-range Type Packets Received"
hexmask.long 0x00 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)"
rgroup.long 0x7D0++0x03
line.long 0x00 "MAC_RX_PAUSE_PACKETS,Pause Packets Received"
hexmask.long 0x00 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received"
rgroup.long 0x7D4++0x03
line.long 0x00 "MAC_RX_FIFO_OVERFLOW_PACKETS,Missed Packets Due to FIFO Overflow"
hexmask.long 0x00 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow"
rgroup.long 0x7D8++0x03
line.long 0x00 "MAC_RX_VLAN_PACKETS_GOOD_BAD,Good and Bad VLAN Packets Received"
hexmask.long 0x00 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received"
rgroup.long 0x7DC++0x03
line.long 0x00 "MAC_RX_WATCHDOG_ERROR_PACKETS,Watchdog Error Packets Received"
hexmask.long 0x00 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_CONFIGURATION register) 10 240.."
rgroup.long 0x7E0++0x03
line.long 0x00 "MAC_RX_RECEIVE_ERROR_PACKETS,Receive Error Packets Received"
hexmask.long 0x00 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface"
rgroup.long 0x7E4++0x03
line.long 0x00 "MAC_RX_CONTROL_PACKETS_GOOD,Good Control Packets Received"
hexmask.long 0x00 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received"
rgroup.long 0x7EC++0x03
line.long 0x00 "MAC_TX_LPI_USEC_CNTR,Microseconds Tx LPI Asserted"
hexmask.long 0x00 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted"
rgroup.long 0x7F0++0x03
line.long 0x00 "MAC_TX_LPI_TRAN_CNTR,Number of Times Tx LPI Asserted"
hexmask.long 0x00 0.--31. 1. "TXLPITRC,Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred"
rgroup.long 0x7F4++0x03
line.long 0x00 "MAC_RX_LPI_USEC_CNTR,Microseconds Rx LPI Sampled"
hexmask.long 0x00 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted"
rgroup.long 0x7F8++0x03
line.long 0x00 "MAC_RX_LPI_TRAN_CNTR,Number of Times Rx LPI Entered"
hexmask.long 0x00 0.--31. 1. "RXLPITRC,Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred"
group.long 0x800++0x03
line.long 0x00 "MAC_MMC_IPC_RX_INTERRUPT_MASK,MMC IPC Receive Interrupt Mask"
bitfld.long 0x00 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Octet Counter..,1: MMC Receive ICMP Error Octet Counter.."
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bitfld.long 0x00 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Octet Counter Interrupt..,1: MMC Receive ICMP Good Octet Counter Interrupt.."
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bitfld.long 0x00 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Octet Counter Interrupt..,1: MMC Receive TCP Error Octet Counter Interrupt.."
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bitfld.long 0x00 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Octet Counter Interrupt..,1: MMC Receive TCP Good Octet Counter Interrupt.."
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bitfld.long 0x00 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Octet Counter Interrupt..,1: MMC Receive UDP Good Octet Counter Interrupt.."
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bitfld.long 0x00 24. "RXUDPGOIM,MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Octet Counter..,1: MMC Receive IPV6 No Payload Octet Counter.."
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bitfld.long 0x00 23. "RXIPV6NOPAYOIM,MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Octet Counter..,1: MMC Receive IPV6 Header Error Octet Counter.."
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bitfld.long 0x00 22. "RXIPV6HEROIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Octet Counter Interrupt..,1: MMC Receive IPV6 Good Octet Counter Interrupt.."
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bitfld.long 0x00 21. "RXIPV6GOIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Octet Counter Interrupt..,1: MMC Receive IPV6 Good Octet Counter Interrupt.."
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bitfld.long 0x00 20. "RXIPV4UDSBLOIM,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Octet..,1: MMC Receive IPV4 UDP Checksum Disabled Octet.."
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bitfld.long 0x00 19. "RXIPV4FRAGOIM,MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Octet Counter..,1: MMC Receive IPV4 Fragmented Octet Counter.."
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bitfld.long 0x00 18. "RXIPV4NOPAYOIM,MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Octet Counter..,1: MMC Receive IPV4 No Payload Octet Counter.."
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bitfld.long 0x00 17. "RXIPV4HEROIM,MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Octet Counter..,1: MMC Receive IPV4 Header Error Octet Counter.."
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bitfld.long 0x00 16. "RXIPV4GOIM,MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Octet Counter Interrupt..,1: MMC Receive IPV4 Good Octet Counter Interrupt.."
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bitfld.long 0x00 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Packet Counter..,1: MMC Receive ICMP Error Packet Counter.."
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bitfld.long 0x00 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Packet Counter..,1: MMC Receive ICMP Good Packet Counter.."
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bitfld.long 0x00 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Packet Counter..,1: MMC Receive TCP Error Packet Counter.."
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bitfld.long 0x00 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Packet Counter Interrupt..,1: MMC Receive TCP Good Packet Counter Interrupt.."
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bitfld.long 0x00 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Error Packet Counter..,1: MMC Receive UDP Error Packet Counter.."
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bitfld.long 0x00 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Packet Counter Interrupt..,1: MMC Receive UDP Good Packet Counter Interrupt.."
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bitfld.long 0x00 7. "RXIPV6NOPAYPIM,MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Packet Counter..,1: MMC Receive IPV6 No Payload Packet Counter.."
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bitfld.long 0x00 6. "RXIPV6HERPIM,MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Packet Counter..,1: MMC Receive IPV6 Header Error Packet Counter.."
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bitfld.long 0x00 5. "RXIPV6GPIM,MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Packet Counter..,1: MMC Receive IPV6 Good Packet Counter.."
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bitfld.long 0x00 4. "RXIPV4UDSBLPIM,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Packet..,1: MMC Receive IPV4 UDP Checksum Disabled Packet.."
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bitfld.long 0x00 3. "RXIPV4FRAGPIM,MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Packet Counter..,1: MMC Receive IPV4 Fragmented Packet Counter.."
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bitfld.long 0x00 2. "RXIPV4NOPAYPIM,MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Packet Counter..,1: MMC Receive IPV4 No Payload Packet Counter.."
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bitfld.long 0x00 1. "RXIPV4HERPIM,MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Packet Counter..,1: MMC Receive IPV4 Header Error Packet Counter.."
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bitfld.long 0x00 0. "RXIPV4GPIM,MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Packet Counter..,1: MMC Receive IPV4 Good Packet Counter.."
rgroup.long 0x808++0x03
line.long 0x00 "MAC_MMC_IPC_RX_INTERRUPT,MMC IPC Receive Interrupt"
bitfld.long 0x00 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Octet Counter..,1: MMC Receive ICMP Error Octet Counter.."
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bitfld.long 0x00 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Octet Counter Interrupt..,1: MMC Receive ICMP Good Octet Counter Interrupt.."
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bitfld.long 0x00 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Octet Counter Interrupt..,1: MMC Receive TCP Error Octet Counter Interrupt.."
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bitfld.long 0x00 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Octet Counter Interrupt..,1: MMC Receive TCP Good Octet Counter Interrupt.."
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bitfld.long 0x00 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Error Octet Counter Interrupt..,1: MMC Receive UDP Error Octet Counter Interrupt.."
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bitfld.long 0x00 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Octet Counter Interrupt..,1: MMC Receive UDP Good Octet Counter Interrupt.."
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bitfld.long 0x00 23. "RXIPV6NOPAYOIS,MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Octet Counter..,1: MMC Receive IPV6 No Payload Octet Counter.."
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bitfld.long 0x00 22. "RXIPV6HEROIS,MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Octet Counter..,1: MMC Receive IPV6 Header Error Octet Counter.."
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bitfld.long 0x00 21. "RXIPV6GOIS,MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Octet Counter Interrupt..,1: MMC Receive IPV6 Good Octet Counter Interrupt.."
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bitfld.long 0x00 20. "RXIPV4UDSBLOIS,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Octet..,1: MMC Receive IPV4 UDP Checksum Disabled Octet.."
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bitfld.long 0x00 19. "RXIPV4FRAGOIS,MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Octet Counter..,1: MMC Receive IPV4 Fragmented Octet Counter.."
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bitfld.long 0x00 18. "RXIPV4NOPAYOIS,MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Octet Counter..,1: MMC Receive IPV4 No Payload Octet Counter.."
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bitfld.long 0x00 17. "RXIPV4HEROIS,MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Octet Counter..,1: MMC Receive IPV4 Header Error Octet Counter.."
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bitfld.long 0x00 16. "RXIPV4GOIS,MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Octet Counter Interrupt..,1: MMC Receive IPV4 Good Octet Counter Interrupt.."
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bitfld.long 0x00 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Packet Counter..,1: MMC Receive ICMP Error Packet Counter.."
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bitfld.long 0x00 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Packet Counter..,1: MMC Receive ICMP Good Packet Counter.."
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bitfld.long 0x00 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Packet Counter..,1: MMC Receive TCP Error Packet Counter.."
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bitfld.long 0x00 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Packet Counter Interrupt..,1: MMC Receive TCP Good Packet Counter Interrupt.."
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bitfld.long 0x00 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Error Packet Counter..,1: MMC Receive UDP Error Packet Counter.."
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bitfld.long 0x00 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Packet Counter Interrupt..,1: MMC Receive UDP Good Packet Counter Interrupt.."
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bitfld.long 0x00 7. "RXIPV6NOPAYPIS,MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Packet Counter..,1: MMC Receive IPV6 No Payload Packet Counter.."
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bitfld.long 0x00 6. "RXIPV6HERPIS,MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Packet Counter..,1: MMC Receive IPV6 Header Error Packet Counter.."
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bitfld.long 0x00 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Packet Counter..,1: MMC Receive IPV6 Good Packet Counter.."
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bitfld.long 0x00 4. "RXIPV4UDSBLPIS,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Packet..,1: MMC Receive IPV4 UDP Checksum Disabled Packet.."
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bitfld.long 0x00 3. "RXIPV4FRAGPIS,MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Packet Counter..,1: MMC Receive IPV4 Fragmented Packet Counter.."
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bitfld.long 0x00 2. "RXIPV4NOPAYPIS,MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Packet Counter..,1: MMC Receive IPV4 No Payload Packet Counter.."
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bitfld.long 0x00 1. "RXIPV4HERPIS,MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Packet Counter..,1: MMC Receive IPV4 Header Error Packet Counter.."
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bitfld.long 0x00 0. "RXIPV4GPIS,MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Packet Counter..,1: MMC Receive IPV4 Good Packet Counter.."
rgroup.long 0x810++0x03
line.long 0x00 "MAC_RXIPV4_GOOD_PACKETS,Good IPv4 Datagrams Received"
hexmask.long 0x00 0.--31. 1. "RXIPV4GDPKT,RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP UDP or ICMP payload"
rgroup.long 0x814++0x03
line.long 0x00 "MAC_RXIPV4_HEADER_ERROR_PACKETS,IPv4 Datagrams Received with Header Errors"
hexmask.long 0x00 0.--31. 1. "RXIPV4HDRERRPKT,RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams received with header (checksum length or version mismatch) errors"
rgroup.long 0x818++0x03
line.long 0x00 "MAC_RXIPV4_NO_PAYLOAD_PACKETS,IPv4 Datagrams Received with No Payload"
hexmask.long 0x00 0.--31. 1. "RXIPV4NOPAYPKT,RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets received that did not have a TCP UDP or ICMP payload"
rgroup.long 0x81C++0x03
line.long 0x00 "MAC_RXIPV4_FRAGMENTED_PACKETS,IPv4 Datagrams Received with Fragmentation"
hexmask.long 0x00 0.--31. 1. "RXIPV4FRAGPKT,RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation"
rgroup.long 0x820++0x03
line.long 0x00 "MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS,IPv4 Datagrams Received with UDP Checksum Disabled"
hexmask.long 0x00 0.--31. 1. "RXIPV4UDSBLPKT,RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
rgroup.long 0x824++0x03
line.long 0x00 "MAC_RXIPV6_GOOD_PACKETS,Good IPv6 Datagrams Received"
hexmask.long 0x00 0.--31. 1. "RXIPV6GDPKT,RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP UDP or ICMP payload"
rgroup.long 0x828++0x03
line.long 0x00 "MAC_RXIPV6_HEADER_ERROR_PACKETS,IPv6 Datagrams Received with Header Errors"
hexmask.long 0x00 0.--31. 1. "RXIPV6HDRERRPKT,RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors"
rgroup.long 0x82C++0x03
line.long 0x00 "MAC_RXIPV6_NO_PAYLOAD_PACKETS,IPv6 Datagrams Received with No Payload"
hexmask.long 0x00 0.--31. 1. "RXIPV6NOPAYPKT,RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets received that did not have a TCP UDP or ICMP payload"
rgroup.long 0x830++0x03
line.long 0x00 "MAC_RXUDP_GOOD_PACKETS,IPv6 Datagrams Received with Good UDP"
hexmask.long 0x00 0.--31. 1. "RXUDPGDPKT,RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload"
rgroup.long 0x834++0x03
line.long 0x00 "MAC_RXUDP_ERROR_PACKETS,IPv6 Datagrams Received with UDP Checksum Error"
hexmask.long 0x00 0.--31. 1. "RXUDPERRPKT,RxUDP Error Packets This field indicates the number of good IP datagrams received whose UDP payload has a checksum error"
rgroup.long 0x838++0x03
line.long 0x00 "MAC_RXTCP_GOOD_PACKETS,IPv6 Datagrams Received with Good TCP Payload"
hexmask.long 0x00 0.--31. 1. "RXTCPGDPKT,RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload"
rgroup.long 0x83C++0x03
line.long 0x00 "MAC_RXTCP_ERROR_PACKETS,IPv6 Datagrams Received with TCP Checksum Error"
hexmask.long 0x00 0.--31. 1. "RXTCPERRPKT,RxTCP Error Packets This field indicates the number of good IP datagrams received whose TCP payload has a checksum error"
rgroup.long 0x840++0x03
line.long 0x00 "MAC_RXICMP_GOOD_PACKETS,IPv6 Datagrams Received with Good ICMP Payload"
hexmask.long 0x00 0.--31. 1. "RXICMPGDPKT,RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload"
rgroup.long 0x844++0x03
line.long 0x00 "MAC_RXICMP_ERROR_PACKETS,IPv6 Datagrams Received with ICMP Checksum Error"
hexmask.long 0x00 0.--31. 1. "RXICMPERRPKT,RxICMP Error Packets This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error"
rgroup.long 0x850++0x03
line.long 0x00 "MAC_RXIPV4_GOOD_OCTETS,Good Bytes Received in IPv4 Datagrams"
hexmask.long 0x00 0.--31. 1. "RXIPV4GDOCT,RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP UDP or ICMP data"
rgroup.long 0x854++0x03
line.long 0x00 "MAC_RXIPV4_HEADER_ERROR_OCTETS,Bytes Received in IPv4 Datagrams with Header Errors"
hexmask.long 0x00 0.--31. 1. "RXIPV4HDRERROCT,RxIPv4 Header Error Octets This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum length version mismatch)"
rgroup.long 0x858++0x03
line.long 0x00 "MAC_RXIPV4_NO_PAYLOAD_OCTETS,Bytes Received in IPv4 Datagrams with No Payload"
hexmask.long 0x00 0.--31. 1. "RXIPV4NOPAYOCT,RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP UDP or ICMP payload"
rgroup.long 0x85C++0x03
line.long 0x00 "MAC_RXIPV4_FRAGMENTED_OCTETS,Bytes Received in Fragmented IPv4 Datagrams"
hexmask.long 0x00 0.--31. 1. "RXIPV4FRAGOCT,RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams"
rgroup.long 0x860++0x03
line.long 0x00 "MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS,Bytes Received with UDP Checksum Disabled"
hexmask.long 0x00 0.--31. 1. "RXIPV4UDSBLOCT,RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled"
rgroup.long 0x864++0x03
line.long 0x00 "MAC_RXIPV6_GOOD_OCTETS,Bytes Received in Good IPv6 Datagrams"
hexmask.long 0x00 0.--31. 1. "RXIPV6GDOCT,RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP UDP or ICMP data"
rgroup.long 0x868++0x03
line.long 0x00 "MAC_RXIPV6_HEADER_ERROR_OCTETS,Bytes Received in IPv6 Datagrams with Data Errors"
hexmask.long 0x00 0.--31. 1. "RXIPV6HDRERROCT,RxIPv6 Header Error Octets This field indicates the number of bytes received in IPv6 datagrams with header errors (length version mismatch)"
rgroup.long 0x86C++0x03
line.long 0x00 "MAC_RXIPV6_NO_PAYLOAD_OCTETS,Bytes Received in IPv6 Datagrams with No Payload"
hexmask.long 0x00 0.--31. 1. "RXIPV6NOPAYOCT,RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP UDP or ICMP payload"
rgroup.long 0x870++0x03
line.long 0x00 "MAC_RXUDP_GOOD_OCTETS,Bytes Received in Good UDP Segment"
hexmask.long 0x00 0.--31. 1. "RXUDPGDOCT,RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment"
rgroup.long 0x874++0x03
line.long 0x00 "MAC_RXUDP_ERROR_OCTETS,Bytes Received in UDP Segment with Checksum Errors"
hexmask.long 0x00 0.--31. 1. "RXUDPERROCT,RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors"
rgroup.long 0x878++0x03
line.long 0x00 "MAC_RXTCP_GOOD_OCTETS,Bytes Received in Good TCP Segment"
hexmask.long 0x00 0.--31. 1. "RXTCPGDOCT,RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment"
rgroup.long 0x87C++0x03
line.long 0x00 "MAC_RXTCP_ERROR_OCTETS,Bytes Received in TCP Segment with Checksum Errors"
hexmask.long 0x00 0.--31. 1. "RXTCPERROCT,RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors"
rgroup.long 0x880++0x03
line.long 0x00 "MAC_RXICMP_GOOD_OCTETS,Bytes Received in Good ICMP Segment"
hexmask.long 0x00 0.--31. 1. "RXICMPGDOCT,RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment"
rgroup.long 0x884++0x03
line.long 0x00 "MAC_RXICMP_ERROR_OCTETS,Bytes Received in ICMP Segment with Checksum Errors"
hexmask.long 0x00 0.--31. 1. "RXICMPERROCT,RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors"
rgroup.long 0x8A0++0x03
line.long 0x00 "MAC_MMC_FPE_TX_INTERRUPT,MMC FPE Transmit Interrupt"
bitfld.long 0x00 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx Hold Request Counter Interrupt Status..,1: MMC Tx Hold Request Counter Interrupt Status.."
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bitfld.long 0x00 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx FPE Fragment Counter Interrupt status..,1: MMC Tx FPE Fragment Counter Interrupt status.."
group.long 0x8A4++0x03
line.long 0x00 "MAC_MMC_FPE_TX_INTERRUPT_MASK,MMC FPE Transmit Mask Interrupt"
bitfld.long 0x00 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Hold Request Counter Interrupt..,1: MMC Transmit Hold Request Counter Interrupt.."
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bitfld.long 0x00 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Fragment Counter Interrupt Mask..,1: MMC Transmit Fragment Counter Interrupt Mask.."
rgroup.long 0x8A8++0x03
line.long 0x00 "MAC_MMC_TX_FPE_FRAGMENT_CNTR,MMC FPE Transmitted Fragment Counter"
hexmask.long 0x00 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
rgroup.long 0x8AC++0x03
line.long 0x00 "MAC_MMC_TX_HOLD_REQ_CNTR,MMC FPE Transmitted Hold Request Counter"
hexmask.long 0x00 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC"
rgroup.long 0x8C0++0x03
line.long 0x00 "MAC_MMC_FPE_RX_INTERRUPT,MMC FPE Receive Interrupt"
bitfld.long 0x00 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Status..,1: MMC Rx FPE Fragment Counter Interrupt Status.."
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bitfld.long 0x00 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
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bitfld.long 0x00 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
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bitfld.long 0x00 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
group.long 0x8C4++0x03
line.long 0x00 "MAC_MMC_FPE_RX_INTERRUPT_MASK,MMC FPE Receive Interrupt Mask"
bitfld.long 0x00 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Mask is..,1: MMC Rx FPE Fragment Counter Interrupt Mask is.."
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bitfld.long 0x00 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
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bitfld.long 0x00 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
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bitfld.long 0x00 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
rgroup.long 0x8C8++0x03
line.long 0x00 "MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR,MMC Receive Packet Reassembly Error Counter"
hexmask.long 0x00 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value"
rgroup.long 0x8CC++0x03
line.long 0x00 "MAC_MMC_RX_PACKET_SMD_ERR_CNTR,MMC Receive Packet SMD Error Counter"
hexmask.long 0x00 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame"
rgroup.long 0x8D0++0x03
line.long 0x00 "MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR,MMC Receive Packet Successful Reassembly Counter"
hexmask.long 0x00 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC"
rgroup.long 0x8D4++0x03
line.long 0x00 "MAC_MMC_RX_FPE_FRAGMENT_CNTR,MMC FPE Received Fragment Counter"
hexmask.long 0x00 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
group.long 0x900++0x03
line.long 0x00 "MAC_L3_L4_CONTROL0,Layer 3 and Layer 4 Control of Filter 0"
bitfld.long 0x00 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24.--26. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x904++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS0,Layer 4 Address 0"
hexmask.long.word 0x00 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x910++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG0,Layer 3 Address 0 Register 0"
hexmask.long 0x00 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x914++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG0,Layer 3 Address 1 Register 0"
hexmask.long 0x00 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x918++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG0,Layer 3 Address 2 Register 0"
hexmask.long 0x00 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x91C++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG0,Layer 3 Address 3 Register 0"
hexmask.long 0x00 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x930++0x03
line.long 0x00 "MAC_L3_L4_CONTROL1,Layer 3 and Layer 4 Control of Filter 1"
bitfld.long 0x00 28. "DMCHEN1,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24.--26. "DMCHN1,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM1,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM1,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN1,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM1,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM1,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM1,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM1,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN1,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x934++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS1,Layer 4 Address 0"
hexmask.long.word 0x00 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x940++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG1,Layer 3 Address 0 Register 1"
hexmask.long 0x00 0.--31. 1. "L3A01,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x944++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG1,Layer 3 Address 1 Register 1"
hexmask.long 0x00 0.--31. 1. "L3A11,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x948++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG1,Layer 3 Address 2 Register 1"
hexmask.long 0x00 0.--31. 1. "L3A21,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x94C++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG1,Layer 3 Address 3 Register 1"
hexmask.long 0x00 0.--31. 1. "L3A31,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x960++0x03
line.long 0x00 "MAC_L3_L4_CONTROL2,Layer 3 and Layer 4 Control of Filter 2"
bitfld.long 0x00 28. "DMCHEN2,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24.--26. "DMCHN2,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM2,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM2,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN2,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM2,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM2,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM2,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
newline
bitfld.long 0x00 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM2,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN2,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x964++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS2,Layer 4 Address 2"
hexmask.long.word 0x00 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x970++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG2,Layer 3 Address 0 Register 2"
hexmask.long 0x00 0.--31. 1. "L3A02,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x974++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG2,Layer 3 Address 0 Register 2"
hexmask.long 0x00 0.--31. 1. "L3A12,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x978++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG2,Layer 3 Address 2 Register 2"
hexmask.long 0x00 0.--31. 1. "L3A22,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x97C++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG2,Layer 3 Address 3 Register 2"
hexmask.long 0x00 0.--31. 1. "L3A32,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x990++0x03
line.long 0x00 "MAC_L3_L4_CONTROL3,Layer 3 and Layer 4 Control of Filter 3"
bitfld.long 0x00 28. "DMCHEN3,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24.--26. "DMCHN3,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM3,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM3,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
newline
bitfld.long 0x00 16. "L4PEN3,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM3,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM3,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM3,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM3,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
newline
bitfld.long 0x00 0. "L3PEN3,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x994++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS3,Layer 4 Address 3"
hexmask.long.word 0x00 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
newline
hexmask.long.word 0x00 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x9A0++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG3,Layer 3 Address 0 Register 3"
hexmask.long 0x00 0.--31. 1. "L3A03,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x9A4++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG3,Layer 3 Address 1 Register 3"
hexmask.long 0x00 0.--31. 1. "L3A13,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x9A8++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG3,Layer 3 Address 2 Register 3"
hexmask.long 0x00 0.--31. 1. "L3A23,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x9AC++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG3,Layer 3 Address 3 Register 3"
hexmask.long 0x00 0.--31. 1. "L3A33,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x9C0++0x03
line.long 0x00 "MAC_L3_L4_CONTROL4,Layer 3 and Layer 4 Control of Filter 4"
bitfld.long 0x00 28. "DMCHEN4,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
newline
bitfld.long 0x00 24.--26. "DMCHN4,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
newline
bitfld.long 0x00 20. "L4DPM4,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
newline
bitfld.long 0x00 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
newline
bitfld.long 0x00 18. "L4SPM4,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
newline
bitfld.long 0x00 16. "L4PEN4,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
newline
bitfld.long 0x00 11.--15. "L3HDBM4,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "L3HSBM4,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
newline
bitfld.long 0x00 4. "L3DAM4,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
newline
bitfld.long 0x00 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
newline
bitfld.long 0x00 2. "L3SAM4,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
newline
bitfld.long 0x00 0. "L3PEN4,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x9C4++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS4,Layer 4 Address 4"
hexmask.long.word 0x00 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
newline
hexmask.long.word 0x00 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x9D0++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG4,Layer 3 Address 0 Register 4"
hexmask.long 0x00 0.--31. 1. "L3A04,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x9D4++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG4,Layer 3 Address 1 Register 4"
hexmask.long 0x00 0.--31. 1. "L3A14,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x9D8++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG4,Layer 3 Address 2 Register 4"
hexmask.long 0x00 0.--31. 1. "L3A24,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x9DC++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG4,Layer 3 Address 3 Register 4"
hexmask.long 0x00 0.--31. 1. "L3A34,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x9F0++0x03
line.long 0x00 "MAC_L3_L4_CONTROL5,Layer 3 and Layer 4 Control of Filter 5"
bitfld.long 0x00 28. "DMCHEN5,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
newline
bitfld.long 0x00 24.--26. "DMCHN5,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
newline
bitfld.long 0x00 20. "L4DPM5,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
newline
bitfld.long 0x00 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
newline
bitfld.long 0x00 18. "L4SPM5,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
newline
bitfld.long 0x00 16. "L4PEN5,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
newline
bitfld.long 0x00 11.--15. "L3HDBM5,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "L3HSBM5,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
newline
bitfld.long 0x00 4. "L3DAM5,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
newline
bitfld.long 0x00 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
newline
bitfld.long 0x00 2. "L3SAM5,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
newline
bitfld.long 0x00 0. "L3PEN5,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x9F4++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS5,Layer 4 Address 5"
hexmask.long.word 0x00 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
newline
hexmask.long.word 0x00 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0xA00++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG5,Layer 3 Address 0 Register 5"
hexmask.long 0x00 0.--31. 1. "L3A05,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0xA04++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG5,Layer 3 Address 1 Register 5"
hexmask.long 0x00 0.--31. 1. "L3A15,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0xA08++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG5,Layer 3 Address 2 Register 5"
hexmask.long 0x00 0.--31. 1. "L3A25,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0xA0C++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG5,Layer 3 Address 3 Register 5"
hexmask.long 0x00 0.--31. 1. "L3A35,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0xA20++0x03
line.long 0x00 "MAC_L3_L4_CONTROL6,Layer 3 and Layer 4 Control of Filter 6"
bitfld.long 0x00 28. "DMCHEN6,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
newline
bitfld.long 0x00 24.--26. "DMCHN6,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
newline
bitfld.long 0x00 20. "L4DPM6,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
newline
bitfld.long 0x00 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
newline
bitfld.long 0x00 18. "L4SPM6,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
newline
bitfld.long 0x00 16. "L4PEN6,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
newline
bitfld.long 0x00 11.--15. "L3HDBM6,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "L3HSBM6,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
newline
bitfld.long 0x00 4. "L3DAM6,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
newline
bitfld.long 0x00 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
newline
bitfld.long 0x00 2. "L3SAM6,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
newline
bitfld.long 0x00 0. "L3PEN6,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0xA24++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS6,Layer 4 Address 6"
hexmask.long.word 0x00 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
newline
hexmask.long.word 0x00 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0xA30++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG6,Layer 3 Address 0 Register 6"
hexmask.long 0x00 0.--31. 1. "L3A06,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0xA34++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG6,Layer 3 Address 1 Register 6"
hexmask.long 0x00 0.--31. 1. "L3A16,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0xA38++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG6,Layer 3 Address 2 Register 6"
hexmask.long 0x00 0.--31. 1. "L3A26,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0xA3C++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG6,Layer 3 Address 3 Register 6"
hexmask.long 0x00 0.--31. 1. "L3A36,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0xA50++0x03
line.long 0x00 "MAC_L3_L4_CONTROL7,Layer 3 and Layer 4 Control of Filter 0"
bitfld.long 0x00 28. "DMCHEN7,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
newline
bitfld.long 0x00 24.--26. "DMCHN7,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
newline
bitfld.long 0x00 20. "L4DPM7,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
newline
bitfld.long 0x00 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
newline
bitfld.long 0x00 18. "L4SPM7,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
newline
bitfld.long 0x00 16. "L4PEN7,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
newline
bitfld.long 0x00 11.--15. "L3HDBM7,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "L3HSBM7,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
newline
bitfld.long 0x00 4. "L3DAM7,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
newline
bitfld.long 0x00 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
newline
bitfld.long 0x00 2. "L3SAM7,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
newline
bitfld.long 0x00 0. "L3PEN7,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0xA54++0x03
line.long 0x00 "MAC_LAYER4_ADDRESS7,Layer 4 Address 7"
hexmask.long.word 0x00 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
newline
hexmask.long.word 0x00 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0xA60++0x03
line.long 0x00 "MAC_LAYER3_ADDR0_REG7,Layer 3 Address 0 Register 7"
hexmask.long 0x00 0.--31. 1. "L3A07,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0xA64++0x03
line.long 0x00 "MAC_LAYER3_ADDR1_REG7,Layer 3 Address 1 Register 7"
hexmask.long 0x00 0.--31. 1. "L3A17,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0xA68++0x03
line.long 0x00 "MAC_LAYER3_ADDR2_REG7,Layer 3 Address 2 Register 7"
hexmask.long 0x00 0.--31. 1. "L3A27,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0xA6C++0x03
line.long 0x00 "MAC_LAYER3_ADDR3_REG7,Layer 3 Address 3 Register 7"
hexmask.long 0x00 0.--31. 1. "L3A37,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0xB00++0x03
line.long 0x00 "MAC_TIMESTAMP_CONTROL,Timestamp Control"
bitfld.long 0x00 28. "AV8021ASMEN,AV 802" "0: AV 802.1AS Mode is disabled,1: AV 802.1AS Mode is enabled"
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bitfld.long 0x00 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0: Transmit Timestamp Status Mode is disabled,1: Transmit Timestamp Status Mode is enabled"
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bitfld.long 0x00 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0: External System Time Input is disabled,1: External System Time Input is enabled"
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bitfld.long 0x00 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct for changes made to origin timestamp and/or correction field as.." "0: checksum correction during OST for PTP over..,1: checksum correction during OST for PTP over.."
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bitfld.long 0x00 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0: MAC Address for PTP Packet Filtering is..,1: MAC Address for PTP Packet Filtering is enabled"
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bitfld.long 0x00 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3"
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bitfld.long 0x00 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0: Snapshot for Messages Relevant to Master is..,1: Snapshot for Messages Relevant to Master is.."
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bitfld.long 0x00 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0: Timestamp Snapshot for Event Messages is..,1: Timestamp Snapshot for Event Messages is.."
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bitfld.long 0x00 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0: Processing of PTP Packets Sent over IPv4-UDP..,1: Processing of PTP Packets Sent over IPv4-UDP.."
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bitfld.long 0x00 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0: Processing of PTP Packets Sent over IPv6-UDP..,1: Processing of PTP Packets Sent over IPv6-UDP.."
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bitfld.long 0x00 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0: Processing of PTP over Ethernet Packets is..,1: Processing of PTP over Ethernet Packets is.."
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bitfld.long 0x00 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0: PTP Packet Processing for Version 2 Format is..,1: PTP Packet Processing for Version 2 Format is.."
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bitfld.long 0x00 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0: Timestamp Digital or Binary Rollover Control..,1: Timestamp Digital or Binary Rollover Control.."
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bitfld.long 0x00 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0: Timestamp for All Packets disabled,1: Timestamp for All Packets enabled"
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bitfld.long 0x00 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled" "0: Presentation Time Generation is disabled,1: Presentation Time Generation is enabled"
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bitfld.long 0x00 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0: Addend Register is not updated,1: Addend Register is updated"
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bitfld.long 0x00 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not updated,1: Timestamp is updated"
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bitfld.long 0x00 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not initialized,1: Timestamp is initialized"
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bitfld.long 0x00 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0: Coarse method is used to update system..,1: Fine method is used to update system timestamp"
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bitfld.long 0x00 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0: Timestamp is disabled,1: Timestamp is enabled"
group.long 0xB04++0x03
line.long 0x00 "MAC_SUB_SECOND_INCREMENT,Subsecond Increment"
hexmask.long.byte 0x00 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register"
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hexmask.long.byte 0x00 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8"
rgroup.long 0xB08++0x03
line.long 0x00 "MAC_SYSTEM_TIME_SECONDS,System Time Seconds"
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC"
rgroup.long 0xB0C++0x03
line.long 0x00 "MAC_SYSTEM_TIME_NANOSECONDS,System Time Nanoseconds"
hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0"
group.long 0xB10++0x03
line.long 0x00 "MAC_SYSTEM_TIME_SECONDS_UPDATE,System Time Seconds Update"
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update"
group.long 0xB14++0x03
line.long 0x00 "MAC_SYSTEM_TIME_NANOSECONDS_UPDATE,System Time Nanoseconds Update"
bitfld.long 0x00 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0: Add time,1: Subtract time"
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hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update"
group.long 0xB18++0x03
line.long 0x00 "MAC_TIMESTAMP_ADDEND,Timestamp Addend"
hexmask.long 0x00 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization"
group.long 0xB1C++0x03
line.long 0x00 "MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS,System Time - Higher Word Seconds"
hexmask.long.word 0x00 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value"
rgroup.long 0xB20++0x03
line.long 0x00 "MAC_TIMESTAMP_STATUS,Timestamp Status"
bitfld.long 0x00 25.--29. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set" "0: Auxiliary Timestamp Snapshot Trigger Missed..,1: Auxiliary Timestamp Snapshot Trigger Missed.."
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bitfld.long 0x00 16.--19. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and.." "0: Tx Timestamp Status Interrupt status not..,1: Tx Timestamp Status Interrupt status detected"
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bitfld.long 0x00 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO" "0: Auxiliary Timestamp Trigger Snapshot status..,1: Auxiliary Timestamp Trigger Snapshot status.."
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bitfld.long 0x00 1. "TSTARGT0,Timestamp Target Time Reached When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers" "0: Timestamp Target Time Reached status not..,1: Timestamp Target Time Reached status detected"
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bitfld.long 0x00 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0: Timestamp Seconds Overflow status not detected,1: Timestamp Seconds Overflow status detected"
rgroup.long 0xB30++0x03
line.long 0x00 "MAC_TX_TIMESTAMP_STATUS_NANOSECONDS,Transmit Timestamp Status Nanoseconds"
bitfld.long 0x00 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL register is reset - The timestamp of the previous packet is.." "0: Transmit Timestamp Status Missed status not..,1: Transmit Timestamp Status Missed status.."
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hexmask.long 0x00 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp"
rgroup.long 0xB34++0x03
line.long 0x00 "MAC_TX_TIMESTAMP_STATUS_SECONDS,Transmit Timestamp Status Seconds"
hexmask.long 0x00 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp"
group.long 0xB40++0x03
line.long 0x00 "MAC_AUXILIARY_CONTROL,Auxiliary Timestamp Control"
bitfld.long 0x00 7. "ATSEN3,Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 6. "ATSEN2,Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 5. "ATSEN1,Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 4. "ATSEN0,Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 0. "ATSFC,Auxiliary Snapshot FIFO Clear When set this bit resets the pointers of the Auxiliary Snapshot FIFO" "0: Auxiliary Snapshot FIFO Clear is disabled,1: Auxiliary Snapshot FIFO Clear is enabled"
rgroup.long 0xB48++0x03
line.long 0x00 "MAC_AUXILIARY_TIMESTAMP_NANOSECONDS,Auxiliary Timestamp Nanoseconds"
hexmask.long 0x00 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp"
rgroup.long 0xB4C++0x03
line.long 0x00 "MAC_AUXILIARY_TIMESTAMP_SECONDS,Auxiliary Timestamp Seconds"
hexmask.long 0x00 0.--31. 1. "AUXTSHI,Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp"
group.long 0xB50++0x03
line.long 0x00 "MAC_TIMESTAMP_INGRESS_ASYM_CORR,Timestamp Ingress Asymmetry Correction"
hexmask.long 0x00 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet"
group.long 0xB54++0x03
line.long 0x00 "MAC_TIMESTAMP_EGRESS_ASYM_CORR,imestamp Egress Asymmetry Correction"
hexmask.long 0x00 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet"
group.long 0xB58++0x03
line.long 0x00 "MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND,Timestamp Ingress Correction Nanosecond"
hexmask.long 0x00 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression"
group.long 0xB5C++0x03
line.long 0x00 "MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND,Timestamp Egress Correction Nanosecond"
hexmask.long 0x00 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
group.long 0xB60++0x03
line.long 0x00 "MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC,Timestamp Ingress Correction Subnanosecond"
hexmask.long.byte 0x00 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the Ingress Correction expression"
group.long 0xB64++0x03
line.long 0x00 "MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC,Timestamp Egress Correction Subnanosecond"
hexmask.long.byte 0x00 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
rgroup.long 0xB68++0x03
line.long 0x00 "MAC_TIMESTAMP_INGRESS_LATENCY,Timestamp Ingress Latency"
hexmask.long.word 0x00 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
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hexmask.long.byte 0x00 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
rgroup.long 0xB6C++0x03
line.long 0x00 "MAC_TIMESTAMP_EGRESS_LATENCY,Timestamp Egress Latency"
hexmask.long.word 0x00 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
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hexmask.long.byte 0x00 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
group.long 0xB70++0x03
line.long 0x00 "MAC_PPS_CONTROL,PPS Control"
bitfld.long 0x00 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode" "0,1"
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bitfld.long 0x00 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 24.--27. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode" "0: 2nd PPS instance is disabled to operate in..,1: 2nd PPS instance is enabled to operate in PPS.."
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bitfld.long 0x00 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 16.--19. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode" "0: 1st PPS instance is disabled to operate in..,1: 1st PPS instance is enabled to operate in PPS.."
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bitfld.long 0x00 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 8.--11. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode" "0: 0th PPS instance is enabled to operate in PPS..,1: 0th PPS instance is enabled to operate in.."
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bitfld.long 0x00 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is set Bits[3:0] function as PPSCMD" "0: Flexible PPS Output Mode is disabled,1: Flexible PPS Output Mode is enabled"
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bitfld.long 0x00 0.--3. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB80++0x03
line.long 0x00 "MAC_PPS0_TARGET_TIME_SECONDS,PPS0 Target Time Seconds"
hexmask.long 0x00 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xB84++0x03
line.long 0x00 "MAC_PPS0_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds"
bitfld.long 0x00 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xB88++0x03
line.long 0x00 "MAC_PPS0_INTERVAL,PPS0 Interval"
hexmask.long 0x00 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xB8C++0x03
line.long 0x00 "MAC_PPS0_WIDTH,PPS0 Width"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xB90++0x03
line.long 0x00 "MAC_PPS1_TARGET_TIME_SECONDS,PPS1 Target Time Seconds"
hexmask.long 0x00 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xB94++0x03
line.long 0x00 "MAC_PPS1_TARGET_TIME_NANOSECONDS,PPS1 Target Time Nanoseconds"
bitfld.long 0x00 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xB98++0x03
line.long 0x00 "MAC_PPS1_INTERVAL,PPS1 Interval"
hexmask.long 0x00 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xB9C++0x03
line.long 0x00 "MAC_PPS1_WIDTH,PPS1 Width"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xBA0++0x03
line.long 0x00 "MAC_PPS2_TARGET_TIME_SECONDS,PPS2 Target Time Seconds"
hexmask.long 0x00 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xBA4++0x03
line.long 0x00 "MAC_PPS2_TARGET_TIME_NANOSECONDS,PPS2 Target Time Nanoseconds"
bitfld.long 0x00 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xBA8++0x03
line.long 0x00 "MAC_PPS2_INTERVAL,PPS2 Interval"
hexmask.long 0x00 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xBAC++0x03
line.long 0x00 "MAC_PPS2_WIDTH,PPS2 Width"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xBB0++0x03
line.long 0x00 "MAC_PPS3_TARGET_TIME_SECONDS,PPS3 Target Time Seconds"
hexmask.long 0x00 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xBB4++0x03
line.long 0x00 "MAC_PPS3_TARGET_TIME_NANOSECONDS,PPS3 Target Time Nanoseconds"
bitfld.long 0x00 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xBB8++0x03
line.long 0x00 "MAC_PPS3_INTERVAL,PPS3 Interval"
hexmask.long 0x00 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xBBC++0x03
line.long 0x00 "MAC_PPS3_WIDTH,PPS3 Width"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xBC0++0x03
line.long 0x00 "MAC_PTO_CONTROL,PTP Offload Engine Control"
hexmask.long.byte 0x00 8.--15. 1. "DN,Domain Number This field indicates the domain Number in which the PTP node is operating"
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bitfld.long 0x00 7. "PDRDIS,Disable Peer Delay Response response generation When this bit is set the Peer Delay Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) request packet as required by the programmed mode" "0: Peer Delay Response response generation is..,1: Peer Delay Response response generation is.."
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bitfld.long 0x00 6. "DRRDIS,Disable PTO Delay Request/Response response generation When this bit is set the Delay Request and Delay response is not generated for received SYNC and Delay request packet respectively as required by the programmed mode" "0: PTO Delay Request/Response response..,1: PTO Delay Request/Response response.."
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bitfld.long 0x00 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger When this bit is set one PTP Pdelay_Req message is transmitted" "0: Automatic PTP Pdelay_Req message Trigger is..,1: Automatic PTP Pdelay_Req message Trigger is.."
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bitfld.long 0x00 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger When this bit is set one PTP SYNC message is transmitted" "0: Automatic PTP SYNC message Trigger is disabled,1: Automatic PTP SYNC message Trigger is enabled"
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bitfld.long 0x00 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable When this bit is set PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Peer-to-Peer Transparent mode" "0: Automatic PTP Pdelay_Req message is disabled,1: Automatic PTP Pdelay_Req message is enabled"
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bitfld.long 0x00 1. "ASYNCEN,Automatic PTP SYNC message Enable When this bit is set PTP SYNC message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Clock Master mode" "0: Automatic PTP SYNC message is disabled,1: Automatic PTP SYNC message is enabled"
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bitfld.long 0x00 0. "PTOEN,PTP Offload Enable When this bit is set the PTP Offload feature is enabled" "0: PTP Offload feature is disabled,1: PTP Offload feature is enabled"
group.long 0xBC4++0x03
line.long 0x00 "MAC_SOURCE_PORT_IDENTITY0,Source Port Identity 0"
hexmask.long 0x00 0.--31. 1. "SPI0,Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node"
group.long 0xBC8++0x03
line.long 0x00 "MAC_SOURCE_PORT_IDENTITY1,Source Port Identity 1"
hexmask.long 0x00 0.--31. 1. "SPI1,Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node"
group.long 0xBCC++0x03
line.long 0x00 "MAC_SOURCE_PORT_IDENTITY2,Source Port Identity 2"
hexmask.long.word 0x00 0.--15. 1. "SPI2,Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node"
group.long 0xBD0++0x03
line.long 0x00 "MAC_LOG_MESSAGE_INTERVAL,Log Message Interval"
hexmask.long.byte 0x00 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node"
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bitfld.long 0x00 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio In Slave mode it is used for controlling frequency of Delay_Req messages transmitted" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception..,2: for every 4 SYNC messages,3: for every 8 SYNC messages,4: for every 16 SYNC messages,5: for every 32 SYNC messages,?..."
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hexmask.long.byte 0x00 0.--7. 1. "LSI,Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master"
group.long 0xC00++0x03
line.long 0x00 "MTL_OPERATION_MODE,MTL Operation Mode"
bitfld.long 0x00 15. "FRPE,Flexible Rx parser Enable When this bit is set to 1 the Programmable Rx Parser functionality is enabled" "0: Flexible Rx parser is disabled,1: Flexible Rx parser is enabled"
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bitfld.long 0x00 9. "CNTCLR,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
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bitfld.long 0x00 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0" "0: Counters Preset is disabled,1: Counters Preset is enabled"
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bitfld.long 0x00 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling" "0: WRR algorithm,1: WFQ algorithm when DCB feature is..,2: DWRR algorithm when DCB feature is..,3: Strict priority algorithm"
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bitfld.long 0x00 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)"
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bitfld.long 0x00 1. "DTXSTS,Drop Transmit Status When this bit is set the Tx packet status received from the MAC is dropped in the MTL" "0: Drop Transmit Status is disabled,1: Drop Transmit Status is enabled"
group.long 0xC08++0x03
line.long 0x00 "MTL_DBG_CTL,FIFO Debug Access Control and Status"
bitfld.long 0x00 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode" "0: Transmit Packet Available Interrupt Status is..,1: Transmit Packet Available Interrupt Status is.."
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bitfld.long 0x00 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.."
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bitfld.long 0x00 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access" "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD..,2: TSO FIFO (cannot be accessed when SLVMOD is..,3: Rx FIFO"
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bitfld.long 0x00 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Write is disabled,1: FIFO Write is enabled"
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bitfld.long 0x00 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Read is disabled,1: FIFO Read is enabled"
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bitfld.long 0x00 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled"
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bitfld.long 0x00 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled"
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bitfld.long 0x00 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
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bitfld.long 0x00 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
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bitfld.long 0x00 1. "DBGMOD,Debug Mode Access to FIFO When this bit is set it indicates that the current access to the FIFO is read write and debug access" "0: Debug Mode Access to FIFO is disabled,1: Debug Mode Access to FIFO is enabled"
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bitfld.long 0x00 0. "FDBGEN,FIFO Debug Access Enable When this bit is set it indicates that the debug mode access to the FIFO is enabled" "0: FIFO Debug Access is disabled,1: FIFO Debug Access is enabled"
group.long 0xC0C++0x03
line.long 0x00 "MTL_DBG_STS,FIFO Debug Status"
hexmask.long.tbyte 0x00 15.--31. 1. "LOCR,Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO"
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bitfld.long 0x00 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO" "0: Transmit Status Available Interrupt Status..,1: Transmit Status Available Interrupt Status.."
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bitfld.long 0x00 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO" "0: Receive Packet Available Interrupt Status not..,1: Receive Packet Available Interrupt Status.."
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rbitfld.long 0x00 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
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rbitfld.long 0x00 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
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rbitfld.long 0x00 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_DEBUG_DATA register" "0: FIFO Busy not detected,1: FIFO Busy detected"
group.long 0xC10++0x03
line.long 0x00 "MTL_FIFO_DEBUG_DATA,FIFO Debug Data"
hexmask.long 0x00 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO"
rgroup.long 0xC20++0x03
line.long 0x00 "MTL_INTERRUPT_STATUS,MTL Interrupt Status"
bitfld.long 0x00 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected"
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bitfld.long 0x00 18. "ESTIS,EST (TAS- 802" "0: EST (TAS- 802.1Qbv) Interrupt status not..,1: EST (TAS- 802.1Qbv) Interrupt status detected"
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bitfld.long 0x00 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected"
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bitfld.long 0x00 4. "Q4IS,Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4" "0: Queue 4 Interrupt status not detected,1: Queue 4 Interrupt status detected"
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bitfld.long 0x00 3. "Q3IS,Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3" "0: Queue 3 Interrupt status not detected,1: Queue 3 Interrupt status detected"
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bitfld.long 0x00 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2" "0: Queue 2 Interrupt status not detected,1: Queue 2 Interrupt status detected"
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bitfld.long 0x00 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected"
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bitfld.long 0x00 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected"
group.long 0xC30++0x03
line.long 0x00 "MTL_RXQ_DMA_MAP0,Receive Queue and DMA Channel Mapping 0"
bitfld.long 0x00 28. "Q3DDMACH,Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set this bit indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in.." "0: Queue 3 disabled for DA-based DMA Channel..,1: Queue 3 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 24.--26. "Q3MDMACH,Queue 3 Mapped to DMA Channel This field controls the routing of the received packet in Queue 3 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: Reserved,6: Reserved,7: Reserved This field is valid when the"
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bitfld.long 0x00 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 2 disabled for DA-based DMA Channel..,1: Queue 2 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 16.--18. "Q2MDMACH,Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: Reserved,6: Reserved,7: Reserved This field is valid when the"
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bitfld.long 0x00 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 1 disabled for DA-based DMA Channel..,1: Queue 1 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 8.--10. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: Reserved,6: Reserved,7: Reserved This field is valid when the"
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bitfld.long 0x00 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 0 disabled for DA-based DMA Channel..,1: Queue 0 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 0.--2. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: Reserved,6: Reserved,7: Reserved This field is valid when the"
group.long 0xC34++0x03
line.long 0x00 "MTL_RXQ_DMA_MAP1,Receive Queue and DMA Channel Mapping 1"
bitfld.long 0x00 4. "Q4DDMACH,Queue 4 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 4 disabled for DA-based DMA Channel..,1: Queue 4 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 0.--2. "Q4MDMACH,Queue 4 Mapped to DMA Channel This field controls the routing of the packet received in Queue 4 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: Reserved,6: Reserved,7: Reserved This field is valid when the"
group.long 0xC40++0x03
line.long 0x00 "MTL_TBS_CTRL,Time Based Scheduling Control"
hexmask.long.tbyte 0x00 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time"
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bitfld.long 0x00 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid" "0: LEOS field is invalid,1: LEOS field is valid"
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bitfld.long 0x00 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list" "0: EST offset Mode is disabled,1: EST offset Mode is enabled"
group.long 0xC50++0x03
line.long 0x00 "MTL_EST_CONTROL,Enhancements to Scheduled Transmission Control"
hexmask.long.byte 0x00 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds"
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hexmask.long.word 0x00 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays etc"
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bitfld.long 0x00 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_STATUS register" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations"
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bitfld.long 0x00 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_STATUS register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped" "0: Do not Drop Frames causing Scheduling Error,1: Drop Frames causing Scheduling Error"
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bitfld.long 0x00 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register)" "0: Drop frames during Frame Size Error,1: Do not Drop frames during Frame Size Error"
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bitfld.long 0x00 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR" "0: Switch to S/W owned list is disabled,1: Switch to S/W owned list is enabled"
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bitfld.long 0x00 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state" "0: EST is disabled,1: EST is enabled"
group.long 0xC58++0x03
line.long 0x00 "MTL_EST_STATUS,Enhancements to Scheduled Transmission Status"
rbitfld.long 0x00 16.--19. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 8.--11. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 7. "SWOL,S/W owned list When '0' indicates Gate control list number 0 is owned by software and when 1 indicates the Gate Control list 1 is owned by the software" "0: Gate control list number 0 is owned by software,1: Gate control list number 1 is owned by software"
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bitfld.long 0x00 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the Cycle Time (CTR)" "0: Constant Gate Control Error not detected,1: Constant Gate Control Error detected"
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rbitfld.long 0x00 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL" "0: Head-Of-Line Blocking due to Scheduling not..,1: Head-Of-Line Blocking due to Scheduling.."
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rbitfld.long 0x00 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "0: Head-Of-Line Blocking due to Frame Size not..,1: Head-Of-Line Blocking due to Frame Size.."
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bitfld.long 0x00 1. "BTRE,BTR Error When 1 indicates a programming error in the BTR of SWOL where the programmed value is less than current time" "0: BTR Error not detected,1: BTR Error detected"
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bitfld.long 0x00 0. "SWLC,Switch to S/W owned list Complete When 1 indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect" "0: Switch to S/W owned list Complete not detected,1: Switch to S/W owned list Complete detected"
group.long 0xC60++0x03
line.long 0x00 "MTL_EST_SCH_ERROR,EST Scheduling Error"
bitfld.long 0x00 0.--4. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC64++0x03
line.long 0x00 "MTL_EST_FRM_SIZE_ERROR,EST Frame Size Error"
bitfld.long 0x00 0.--4. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xC68++0x03
line.long 0x00 "MTL_EST_FRM_SIZE_CAPTURE,EST Frame Size Capture"
bitfld.long 0x00 16.--18. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register)" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register"
group.long 0xC70++0x03
line.long 0x00 "MTL_EST_INTR_ENABLE,EST Interrupt Enable"
bitfld.long 0x00 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status" "0: Interrupt for CGCE is disabled,1: Interrupt for CGCE is enabled"
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bitfld.long 0x00 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status" "0: Interrupt for HLBS is disabled,1: Interrupt for HLBS is enabled"
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bitfld.long 0x00 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status" "0: Interrupt for HLBF is disabled,1: Interrupt for HLBF is enabled"
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bitfld.long 0x00 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status" "0: Interrupt for BTR Error is disabled,1: Interrupt for BTR Error is enabled"
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bitfld.long 0x00 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list" "0: Interrupt for Switch List is disabled,1: Interrupt for Switch List is enabled"
group.long 0xC80++0x03
line.long 0x00 "MTL_EST_GCL_CONTROL,EST GCL Control"
rbitfld.long 0x00 22.--23. "ESTEIEC,ECC Inject Error Control for EST Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field"
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rbitfld.long 0x00 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register enables the ECC error injection feature" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled"
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bitfld.long 0x00 20. "ERR0,When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set" "0: ERR0 is disabled,1: ERR1 is enabled"
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hexmask.long.word 0x00 8.--16. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is 0 )"
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bitfld.long 0x00 5. "DBGB,Debug Mode Bank Select When set to 0 indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers)" "0: R/W in debug mode should be directed to Bank 0,1: R/W in debug mode should be directed to Bank 1"
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bitfld.long 0x00 4. "DBGM,Debug Mode When set to 1 indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to 0 SWOL bit is used to determine which bank to use" "0: Debug Mode is disabled,1: Debug Mode is enabled"
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bitfld.long 0x00 2. "GCRR,Gate Control Related Registers When set to 1 indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA" "0: Gate Control Related Registers are disabled,1: Gate Control Related Registers are enabled"
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bitfld.long 0x00 1. "R1W0,Read '1' Write '0': When set to '1': Read Operation When set to '0': Write Operation" "0: Write Operation,1: Read Operation"
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bitfld.long 0x00 0. "SRWO,Start Read/Write Op When set indicates a Read/Write Op has started and is in progress" "0: Start Read/Write Op disabled,1: Start Read/Write Op enabled"
group.long 0xC84++0x03
line.long 0x00 "MTL_EST_GCL_DATA,EST GCL Data"
hexmask.long 0x00 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register"
group.long 0xC90++0x03
line.long 0x00 "MTL_FPE_CTRL_STS,Frame Preemption Control and Status"
rbitfld.long 0x00 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was.."
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bitfld.long 0x00 8.--12. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames" "0,1,2,3"
group.long 0xC94++0x03
line.long 0x00 "MTL_FPE_ADVANCE,Frame Preemption Hold and Release Advance"
hexmask.long.word 0x00 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission"
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hexmask.long.word 0x00 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission"
group.long 0xCA0++0x03
line.long 0x00 "MTL_RXP_CONTROL_STATUS,RXP Control Status"
rbitfld.long 0x00 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing" "0: RX Parser not in Idle state,1: RX Parser in Idle state"
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hexmask.long.byte 0x00 16.--23. 1. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory"
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hexmask.long.byte 0x00 0.--7. 1. "NVE,Number of valid entries in the Instruction table This control indicates the number of valid entries in the Instruction Memory"
group.long 0xCA4++0x03
line.long 0x00 "MTL_RXP_INTERRUPT_CONTROL_STATUS,RXP Interrupt Control Status"
bitfld.long 0x00 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled"
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bitfld.long 0x00 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled"
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bitfld.long 0x00 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable When this bit is set the NPEOVIS interrupt is enabled" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
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bitfld.long 0x00 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.."
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bitfld.long 0x00 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status.."
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bitfld.long 0x00 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected"
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bitfld.long 0x00 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_CONTROL register) then this bit is set to 1" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
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bitfld.long 0x00 0. "NVEOVIS,Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register) then this bit is set to 1" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.."
rgroup.long 0xCA8++0x03
line.long 0x00 "MTL_RXP_DROP_CNT,RXP Drop Count"
bitfld.long 0x00 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1"
rgroup.long 0xCAC++0x03
line.long 0x00 "MTL_RXP_ERROR_CNT,RXP Error Count"
bitfld.long 0x00 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.."
group.long 0xCB0++0x03
line.long 0x00 "MTL_RXP_INDIRECT_ACC_CONTROL_STATUS,RXP Indirect Access Control and Status"
bitfld.long 0x00 31. "STARTBUSY,FRP Instruction Table Access Busy When this bit is set to 1 by the software then it indicates to start the Read/Write operation from/to the Rx Parser Memory" "0: hardware not busy,1: hardware is busy (Read/Write operation.."
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bitfld.long 0x00 16. "WRRDN,Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory" "0: Read operation to the Rx Parser Memory,1: Write operation to the Rx Parser Memory"
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hexmask.long.word 0x00 0.--9. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table"
group.long 0xCB4++0x03
line.long 0x00 "MTL_RXP_INDIRECT_ACC_DATA,RXP Indirect Access Data"
hexmask.long 0x00 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command"
group.long 0xD00++0x03
line.long 0x00 "MTL_TXQ0_OPERATION_MODE,Queue 0 Transmit Operation Mode"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xD04++0x03
line.long 0x00 "MTL_TXQ0_UNDERFLOW,Queue 0 Underflow Counter"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xD08++0x03
line.long 0x00 "MTL_TXQ0_DEBUG,Queue 0 Transmit Debug"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
rgroup.long 0xD14++0x03
line.long 0x00 "MTL_TXQ0_ETS_STATUS,Queue 0 ETS Status"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xD18++0x03
line.long 0x00 "MTL_TXQ0_QUANTUM_WEIGHT,Queue 0 Quantum or Weights"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle"
group.long 0xD2C++0x03
line.long 0x00 "MTL_Q0_INTERRUPT_CONTROL_STATUS,Queue 0 Interrupt Control Status"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xD30++0x03
line.long 0x00 "MTL_RXQ0_OPERATION_MODE,Queue 0 Receive Operation Mode"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
rgroup.long 0xD34++0x03
line.long 0x00 "MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT,Queue 0 Missed Packet and Overflow Counter"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xD38++0x03
line.long 0x00 "MTL_RXQ0_DEBUG,Queue 0 Receive Debug"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xD3C++0x03
line.long 0x00 "MTL_RXQ0_CONTROL,Queue 0 Receive Control"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0xD40++0x03
line.long 0x00 "MTL_TXQ1_OPERATION_MODE,Queue 1 Transmit Operation Mode"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xD44++0x03
line.long 0x00 "MTL_TXQ1_UNDERFLOW,Queue 1 Underflow Counter"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xD48++0x03
line.long 0x00 "MTL_TXQ1_DEBUG,Queue 1 Transmit Debug"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
group.long 0xD50++0x03
line.long 0x00 "MTL_TXQ1_ETS_CONTROL,Queue 1 ETS Control"
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
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bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
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bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
rgroup.long 0xD54++0x03
line.long 0x00 "MTL_TXQ1_ETS_STATUS,Queue 1 ETS Status"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xD58++0x03
line.long 0x00 "MTL_TXQ1_QUANTUM_WEIGHT,Queue 1 idleSlopeCredit Quantum or Weights"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
group.long 0xD5C++0x03
line.long 0x00 "MTL_TXQ1_SENDSLOPECREDIT,Queue 1 sendSlopeCredit"
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
group.long 0xD60++0x03
line.long 0x00 "MTL_TXQ1_HICREDIT,Queue 1 hiCredit"
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
group.long 0xD64++0x03
line.long 0x00 "MTL_TXQ1_LOCREDIT,Queue 1 loCredit"
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
group.long 0xD6C++0x03
line.long 0x00 "MTL_Q1_INTERRUPT_CONTROL_STATUS,Queue 1 Interrupt Control Status"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xD70++0x03
line.long 0x00 "MTL_RXQ1_OPERATION_MODE,Queue 1 Receive Operation Mode"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
rgroup.long 0xD74++0x03
line.long 0x00 "MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT,Queue 1 Missed Packet and Overflow Counter"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xD78++0x03
line.long 0x00 "MTL_RXQ1_DEBUG,Queue 1 Receive Debug"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xD7C++0x03
line.long 0x00 "MTL_RXQ1_CONTROL,Queue 1 Receive Control"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0xD80++0x03
line.long 0x00 "MTL_TXQ2_OPERATION_MODE,Queue 2 Transmit Operation Mode"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xD84++0x03
line.long 0x00 "MTL_TXQ2_UNDERFLOW,Queue 2 Underflow Counter"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xD88++0x03
line.long 0x00 "MTL_TXQ2_DEBUG,Queue 2 Transmit Debug"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
group.long 0xD90++0x03
line.long 0x00 "MTL_TXQ2_ETS_CONTROL,Queue 2 ETS Control"
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
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bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
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bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
rgroup.long 0xD94++0x03
line.long 0x00 "MTL_TXQ2_ETS_STATUS,Queue 2 ETS Status"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xD98++0x03
line.long 0x00 "MTL_TXQ2_QUANTUM_WEIGHT,Queue 2 idleSlopeCredit Quantum or Weights"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
group.long 0xD9C++0x03
line.long 0x00 "MTL_TXQ2_SENDSLOPECREDIT,Queue 2 sendSlopeCredit"
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
group.long 0xDA0++0x03
line.long 0x00 "MTL_TXQ2_HICREDIT,Queue 2 hiCredit"
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
group.long 0xDA4++0x03
line.long 0x00 "MTL_TXQ2_LOCREDIT,Queue 2 loCredit"
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
group.long 0xDAC++0x03
line.long 0x00 "MTL_Q2_INTERRUPT_CONTROL_STATUS,Queue 2 Interrupt Control Status"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xDB0++0x03
line.long 0x00 "MTL_RXQ2_OPERATION_MODE,Queue 2 Receive Operation Mode"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
rgroup.long 0xDB4++0x03
line.long 0x00 "MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT,Queue 2 Missed Packet and Overflow Counter"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xDB8++0x03
line.long 0x00 "MTL_RXQ2_DEBUG,Queue 2 Receive Debug"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xDBC++0x03
line.long 0x00 "MTL_RXQ2_CONTROL,Queue 2 Receive Control"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0xDC0++0x03
line.long 0x00 "MTL_TXQ3_OPERATION_MODE,Queue 3 Transmit Operation Mode"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xDC4++0x03
line.long 0x00 "MTL_TXQ3_UNDERFLOW,Queue 3 Underflow Counter"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xDC8++0x03
line.long 0x00 "MTL_TXQ3_DEBUG,Queue 3 Transmit Debug"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
group.long 0xDD0++0x03
line.long 0x00 "MTL_TXQ3_ETS_CONTROL,Queue 3 ETS Control"
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
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bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
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bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "MTL_TXQ3_ETS_STATUS,Queue 3 ETS Status"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xDD8++0x03
line.long 0x00 "MTL_TXQ3_QUANTUM_WEIGHT,Queue 3 idleSlopeCredit Quantum or Weights"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
group.long 0xDDC++0x03
line.long 0x00 "MTL_TXQ3_SENDSLOPECREDIT,Queue 3 sendSlopeCredit"
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
group.long 0xDE0++0x03
line.long 0x00 "MTL_TXQ3_HICREDIT,Queue 3 hiCredit"
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
group.long 0xDE4++0x03
line.long 0x00 "MTL_TXQ3_LOCREDIT,Queue 3 loCredit"
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
group.long 0xDEC++0x03
line.long 0x00 "MTL_Q3_INTERRUPT_CONTROL_STATUS,Queue 3 Interrupt Control Status"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xDF0++0x03
line.long 0x00 "MTL_RXQ3_OPERATION_MODE,Queue 3 Receive Operation Mode"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
rgroup.long 0xDF4++0x03
line.long 0x00 "MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT,Queue 3 Missed Packet and Overflow Counter"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xDF8++0x03
line.long 0x00 "MTL_RXQ3_DEBUG,Queue 3 Receive Debug"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xDFC++0x03
line.long 0x00 "MTL_RXQ3_CONTROL,Queue 3 Receive Control"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0xE00++0x03
line.long 0x00 "MTL_TXQ4_OPERATION_MODE,Queue 4 Transmit Operation Mode"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xE04++0x03
line.long 0x00 "MTL_TXQ4_UNDERFLOW,Queue 4 Underflow Counter"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xE08++0x03
line.long 0x00 "MTL_TXQ4_DEBUG,Queue 4 Transmit Debug"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
group.long 0xE10++0x03
line.long 0x00 "MTL_TXQ4_ETS_CONTROL,Queue 4 ETS Control"
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
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bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
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bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
rgroup.long 0xE14++0x03
line.long 0x00 "MTL_TXQ4_ETS_STATUS,Queue 4 ETS Status"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xE18++0x03
line.long 0x00 "MTL_TXQ4_QUANTUM_WEIGHT,Queue 4 idleSlopeCredit Quantum or Weights"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
group.long 0xE1C++0x03
line.long 0x00 "MTL_TXQ4_SENDSLOPECREDIT,Queue 4 sendSlopeCredit"
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
group.long 0xE20++0x03
line.long 0x00 "MTL_TXQ4_HICREDIT,Queue 4 hiCredit"
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
group.long 0xE24++0x03
line.long 0x00 "MTL_TXQ4_LOCREDIT,Queue 4 loCredit"
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
group.long 0xE2C++0x03
line.long 0x00 "MTL_Q4_INTERRUPT_CONTROL_STATUS,Queue 4 Interrupt Control Status"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xE30++0x03
line.long 0x00 "MTL_RXQ4_OPERATION_MODE,Queue 4 Receive Operation Mode"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
rgroup.long 0xE34++0x03
line.long 0x00 "MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT,Queue 4 Missed Packet and Overflow Counter"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xE38++0x03
line.long 0x00 "MTL_RXQ4_DEBUG,Queue 4 Receive Debug"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xE3C++0x03
line.long 0x00 "MTL_RXQ4_CONTROL,Queue 4 Receive Control"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0x1000++0x03
line.long 0x00 "DMA_MODE,DMA Bus Mode"
bitfld.long 0x00 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos" "0: See above description,1: See above description,2: See above description,?..."
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bitfld.long 0x00 8. "DSPW,Descriptor Posted Write When this bit is set to 0 the descriptor writes are always non-posted" "0: Descriptor Posted Write is disabled,1: Descriptor Posted Write is enabled"
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bitfld.long 0x00 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0: Software Reset is disabled,1: Software Reset is enabled"
group.long 0x1004++0x03
line.long 0x00 "DMA_SYSBUS_MODE,DMA System Bus Mode"
bitfld.long 0x00 31. "EN_LPI,Enable Low Power Interface (LPI) When set to 1 this bit enables the LPI mode supported by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller" "0: Low Power Interface (LPI) is disabled,1: Low Power Interface (LPI) is enabled"
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bitfld.long 0x00 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet When set to 1 this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received" "0: Unlock on Magic Packet or Remote Wake-Up..,1: Unlock on Magic Packet or Remote Wake-Up.."
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bitfld.long 0x00 24.--27. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 13. "ONEKBBE,1 KB Boundary Crossing Enable for the EQOS-AXI Master When set the burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary" "0: 1 KB Boundary Crossing for the EQOS-AXI..,1: 1 KB Boundary Crossing for the EQOS-AXI.."
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bitfld.long 0x00 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0: Address-Aligned Beats is disabled,1: Address-Aligned Beats is enabled"
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bitfld.long 0x00 10. "AALE,Automatic AXI LPI enable When set to 1 enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register" "0: Automatic AXI LPI is disabled,1: Automatic AXI LPI is enabled"
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bitfld.long 0x00 3. "BLEN16,AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 16 on the AXI interface" "0: No effect,1: AXI Burst Length 16"
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bitfld.long 0x00 2. "BLEN8,AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 8 on the AXI interface" "0: No effect,1: AXI Burst Length 8"
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bitfld.long 0x00 1. "BLEN4,AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 4 on the AXI interface" "0: No effect,1: AXI Burst Length 4"
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bitfld.long 0x00 0. "FB,Fixed Burst Length When this bit is set to 1 the EQOS-AXI master initiates burst transfers of specified lengths as given below" "0: Fixed Burst Length is disabled,1: Fixed Burst Length is enabled"
rgroup.long 0x1008++0x03
line.long 0x00 "DMA_INTERRUPT_STATUS,DMA Interrupt Status"
bitfld.long 0x00 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0: MAC Interrupt Status not detected,1: MAC Interrupt Status detected"
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bitfld.long 0x00 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0: MTL Interrupt Status not detected,1: MTL Interrupt Status detected"
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bitfld.long 0x00 4. "DC4IS,DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4" "0: DMA Channel 4 Interrupt Status not detected,1: DMA Channel 4 Interrupt Status detected"
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bitfld.long 0x00 3. "DC3IS,DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3" "0: DMA Channel 3 Interrupt Status not detected,1: DMA Channel 3 Interrupt Status detected"
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bitfld.long 0x00 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2" "0: DMA Channel 2 Interrupt Status not detected,1: DMA Channel 2 Interrupt Status detected"
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bitfld.long 0x00 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0: DMA Channel 1 Interrupt Status not detected,1: DMA Channel 1 Interrupt Status detected"
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bitfld.long 0x00 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0: DMA Channel 0 Interrupt Status not detected,1: DMA Channel 0 Interrupt Status detected"
rgroup.long 0x100C++0x03
line.long 0x00 "DMA_DEBUG_STATUS0,DMA Debug Status 0"
bitfld.long 0x00 28.--31. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 24.--27. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 20.--23. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 16.--19. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 12.--15. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 8.--11. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 1. "AXRHSTS,AXI Master Read Channel Status When high this bit indicates that the read channel of the AXI master is active and it is transferring the data" "0: AXI Master Read Channel Status not detected,1: AXI Master Read Channel Status detected"
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bitfld.long 0x00 0. "AXWHSTS,AXI Master Write Channel When high this bit indicates that the write channel of the AXI master is active and it is transferring data" "0: AXI Master Write Channel or AHB Master Status..,1: AXI Master Write Channel or AHB Master Status.."
rgroup.long 0x1010++0x03
line.long 0x00 "DMA_DEBUG_STATUS1,DMA Debug Status 1"
bitfld.long 0x00 12.--15. "TPS4,DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 8.--11. "RPS4,DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 4.--7. "TPS3,DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 0.--3. "RPS3,DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
group.long 0x1040++0x03
line.long 0x00 "DMA_AXI_LPI_ENTRY_INTERVAL,AXI LPI Entry Interval Control"
bitfld.long 0x00 0.--3. "LPIEI,LPI Entry Interval Contains the number of system clock cycles multiplied by 64 to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1050++0x03
line.long 0x00 "DMA_TBS_CTRL,TBS Control"
hexmask.long.tbyte 0x00 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time"
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bitfld.long 0x00 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid"
group.long 0x1100++0x03
line.long 0x00 "DMA_CH0_CONTROL,DMA Channel 0 Control"
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_TX_CONTROL and Bits[21:16] in DMA_CH0_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1104++0x03
line.long 0x00 "DMA_CH0_TX_CONTROL,DMA Channel 0 Transmit Control"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1108++0x03
line.long 0x00 "DMA_CH0_RX_CONTROL,DMA Channel 0 Receive Control"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1114++0x03
line.long 0x00 "DMA_CH0_TXDESC_LIST_ADDRESS,Channel 0 Tx Descriptor List Address register"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x111C++0x03
line.long 0x00 "DMA_CH0_RXDESC_LIST_ADDRESS,Channel 0 Rx Descriptor List Address register"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x1120++0x03
line.long 0x00 "DMA_CH0_TXDESC_TAIL_POINTER,Channel 0 Tx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x1128++0x03
line.long 0x00 "DMA_CH0_RXDESC_TAIL_POINTER,Channel 0 Rx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x112C++0x03
line.long 0x00 "DMA_CH0_TXDESC_RING_LENGTH,Channel 0 Tx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x1130++0x03
line.long 0x00 "DMA_CH0_RXDESC_RING_LENGTH,Channel 0 Rx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x1134++0x03
line.long 0x00 "DMA_CH0_INTERRUPT_ENABLE,Channel 0 Interrupt Enable"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x1138++0x03
line.long 0x00 "DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER,Channel 0 Receive Interrupt Watchdog Timer"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x113C++0x03
line.long 0x00 "DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS,Channel 0 Slot Function Control and Status"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x1144++0x03
line.long 0x00 "DMA_CH0_CURRENT_APP_TXDESC,Channel 0 Current Application Transmit Descriptor"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x114C++0x03
line.long 0x00 "DMA_CH0_CURRENT_APP_RXDESC,Channel 0 Current Application Receive Descriptor"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x1154++0x03
line.long 0x00 "DMA_CH0_CURRENT_APP_TXBUFFER,Channel 0 Current Application Transmit Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x115C++0x03
line.long 0x00 "DMA_CH0_CURRENT_APP_RXBUFFER,Channel 0 Current Application Receive Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x1160++0x03
line.long 0x00 "DMA_CH0_STATUS,DMA Channel 0 Status"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow (intermediate descriptor) or all ones descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x1164++0x03
line.long 0x00 "DMA_CH0_MISS_FRAME_CNT,Channel 0 Missed Frame Counter"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in DMA_CH0_RX_CONTROL register"
rgroup.long 0x1168++0x03
line.long 0x00 "DMA_CH0_RXP_ACCEPT_CNT,Channel 0 RXP Frames Accepted Counter"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
rgroup.long 0x116C++0x03
line.long 0x00 "DMA_CH0_RX_ERI_CNT,Channel 0 Receive ERI Counter"
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
group.long 0x1180++0x03
line.long 0x00 "DMA_CH1_CONTROL,DMA Channel 1 Control"
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in TX_CONTROL and Bits[21:16] in DMA_CH1_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1184++0x03
line.long 0x00 "DMA_CH1_TX_CONTROL,DMA Channel 1 Transmit Control"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1188++0x03
line.long 0x00 "DMA_CH1_RX_CONTROL,DMA Channel 1 Receive Control"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1194++0x03
line.long 0x00 "DMA_CH1_TXDESC_LIST_ADDRESS,Channel 1 Tx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x119C++0x03
line.long 0x00 "DMA_CH1_RXDESC_LIST_ADDRESS,Channel 1 Rx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x11A0++0x03
line.long 0x00 "DMA_CH1_TXDESC_TAIL_POINTER,Channel 1 Tx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x11A8++0x03
line.long 0x00 "DMA_CH1_RXDESC_TAIL_POINTER,Channel 1 Rx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x11AC++0x03
line.long 0x00 "DMA_CH1_TXDESC_RING_LENGTH,Channel 1 Tx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x11B0++0x03
line.long 0x00 "DMA_CH1_RXDESC_RING_LENGTH,Channel 1 Rx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x11B4++0x03
line.long 0x00 "DMA_CH1_INTERRUPT_ENABLE,Channel 1 Interrupt Enable"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x11B8++0x03
line.long 0x00 "DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER,Channel 1 Receive Interrupt Watchdog Timer"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x11BC++0x03
line.long 0x00 "DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS,Channel 1 Slot Function Control and Status"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x11C4++0x03
line.long 0x00 "DMA_CH1_CURRENT_APP_TXDESC,Channel 1 Current Application Transmit Descriptor"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x11CC++0x03
line.long 0x00 "DMA_CH1_CURRENT_APP_RXDESC,Channel 1 Current Application Receive Descriptor"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x11D4++0x03
line.long 0x00 "DMA_CH1_CURRENT_APP_TXBUFFER,Channel 1 Current Application Transmit Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x11DC++0x03
line.long 0x00 "DMA_CH1_CURRENT_APP_RXBUFFER,Channel 1 Current Application Receive Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x11E0++0x03
line.long 0x00 "DMA_CH1_STATUS,DMA Channel 1 Status"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x11E4++0x03
line.long 0x00 "DMA_CH1_MISS_FRAME_CNT,Channel 1 Missed Frame Counter"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register"
rgroup.long 0x11E8++0x03
line.long 0x00 "DMA_CH1_RXP_ACCEPT_CNT,Channel 1 RXP Frames Accepted Counter"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
rgroup.long 0x11EC++0x03
line.long 0x00 "DMA_CH1_RX_ERI_CNT,Channel 1 Receive ERI Counter"
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
group.long 0x1200++0x03
line.long 0x00 "DMA_CH2_CONTROL,DMA Channel 2 Control"
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH2_TX_CONTROL and Bits[21:16] in DMA_CH2_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1204++0x03
line.long 0x00 "DMA_CH2_TX_CONTROL,DMA Channel 2 Transmit Control"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1208++0x03
line.long 0x00 "DMA_CH2_RX_CONTROL,DMA Channel 2 Receive Control"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1214++0x03
line.long 0x00 "DMA_CH2_TXDESC_LIST_ADDRESS,Channel 2 Tx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x121C++0x03
line.long 0x00 "DMA_CH2_RXDESC_LIST_ADDRESS,Channel 2 Rx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x1220++0x03
line.long 0x00 "DMA_CH2_TXDESC_TAIL_POINTER,Channel 2 Tx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x1228++0x03
line.long 0x00 "DMA_CH2_RXDESC_TAIL_POINTER,Channel 2 Rx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x122C++0x03
line.long 0x00 "DMA_CH2_TXDESC_RING_LENGTH,Channel 2 Tx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x1230++0x03
line.long 0x00 "DMA_CH2_RXDESC_RING_LENGTH,Channel 2 Rx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x1234++0x03
line.long 0x00 "DMA_CH2_INTERRUPT_ENABLE,Channel 2 Interrupt Enable"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x1238++0x03
line.long 0x00 "DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER,Channel 2 Receive Interrupt Watchdog Timer"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x123C++0x03
line.long 0x00 "DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS,Channel 2 Slot Function Control and Status"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x1244++0x03
line.long 0x00 "DMA_CH2_CURRENT_APP_TXDESC,Channel 2 Current Application Transmit Descriptor"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x124C++0x03
line.long 0x00 "DMA_CH2_CURRENT_APP_RXDESC,Channel 2 Current Application Receive Descriptor"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x1254++0x03
line.long 0x00 "DMA_CH2_CURRENT_APP_TXBUFFER,Channel 2 Current Application Transmit Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x125C++0x03
line.long 0x00 "DMA_CH2_CURRENT_APP_RXBUFFER,Channel 2 Current Application Receive Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x1260++0x03
line.long 0x00 "DMA_CH2_STATUS,DMA Channel 2 Status"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH2_INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x1264++0x03
line.long 0x00 "DMA_CH2_MISS_FRAME_CNT,Channel 2 Missed Frame Counter"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in DMA_CH2_RX_CONTROL register"
rgroup.long 0x1268++0x03
line.long 0x00 "DMA_CH2_RXP_ACCEPT_CNT,Channel 2 RXP Frames Accepted Counter"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
rgroup.long 0x126C++0x03
line.long 0x00 "DMA_CH2_RX_ERI_CNT,Channel 2 Receive ERI Counter"
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH2_RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
group.long 0x1280++0x03
line.long 0x00 "DMA_CH3_CONTROL,DMA Channel 3 Control"
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH3_TX_CONTROL and Bits[21:16] in DMA_CH3_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1284++0x03
line.long 0x00 "DMA_CH3_TX_CONTROL,DMA Channel 3 Transmit Control"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1288++0x03
line.long 0x00 "DMA_CH3_RX_CONTROL,DMA Channel 3 Receive Control"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1294++0x03
line.long 0x00 "DMA_CH3_TXDESC_LIST_ADDRESS,Channel 3 Tx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x129C++0x03
line.long 0x00 "DMA_CH3_RXDESC_LIST_ADDRESS,Channel 3 Rx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x12A0++0x03
line.long 0x00 "DMA_CH3_TXDESC_TAIL_POINTER,Channel 3 Tx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x12A8++0x03
line.long 0x00 "DMA_CH3_RXDESC_TAIL_POINTER,Channel 3 Rx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x12AC++0x03
line.long 0x00 "DMA_CH3_TXDESC_RING_LENGTH,Channel 3 Tx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x12B0++0x03
line.long 0x00 "DMA_CH3_RXDESC_RING_LENGTH,Channel 3 Rx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x12B4++0x03
line.long 0x00 "DMA_CH3_INTERRUPT_ENABLE,Channel 3 Interrupt Enable"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x12B8++0x03
line.long 0x00 "DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER,Channel 3 Receive Interrupt Watchdog Time"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x12BC++0x03
line.long 0x00 "DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS,Channel 3 Slot Function Control and Status"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x12C4++0x03
line.long 0x00 "DMA_CH3_CURRENT_APP_TXDESC,Channel 3 Current Application Transmit Descriptor"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x12CC++0x03
line.long 0x00 "DMA_CH3_CURRENT_APP_RXDESC,Channel 3 Current Application Receive Descriptor"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x12D4++0x03
line.long 0x00 "DMA_CH3_CURRENT_APP_TXBUFFER,Channel 3 Current Application Transmit Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x12DC++0x03
line.long 0x00 "DMA_CH3_CURRENT_APP_RXBUFFER,Channel 3 Current Application Receive Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x12E0++0x03
line.long 0x00 "DMA_CH3_STATUS,DMA Channel 3 Status"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x12E4++0x03
line.long 0x00 "DMA_CH3_MISS_FRAME_CNT,Channel 3 Missed Frame Counter"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register"
rgroup.long 0x12E8++0x03
line.long 0x00 "DMA_CH3_RXP_ACCEPT_CNT,Channel 3 RXP Frames Accepted Counter"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
rgroup.long 0x12EC++0x03
line.long 0x00 "DMA_CH3_RX_ERI_CNT,Channel 3 Receive ERI Counter"
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH3_RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
group.long 0x1300++0x03
line.long 0x00 "DMA_CH4_CONTROL,DMA Channel 4 Control"
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1304++0x03
line.long 0x00 "DMA_CH4_TX_CONTROL,DMA Channel 4 Transmit Control"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1308++0x03
line.long 0x00 "DMA_CH4_RX_CONTROL,DMA Channel 4 Receive Control"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1314++0x03
line.long 0x00 "DMA_CH4_TXDESC_LIST_ADDRESS,Channel 4 Tx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x131C++0x03
line.long 0x00 "DMA_CH4_RXDESC_LIST_ADDRESS,Channel 4 Rx Descriptor List Address"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x1320++0x03
line.long 0x00 "DMA_CH4_TXDESC_TAIL_POINTER,Channel 4 Tx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x1328++0x03
line.long 0x00 "DMA_CH4_RXDESC_TAIL_POINTER,Channel 4 Rx Descriptor Tail Pointer"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x132C++0x03
line.long 0x00 "DMA_CH4_TXDESC_RING_LENGTH,Channel 4 Tx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x1330++0x03
line.long 0x00 "DMA_CH4_RXDESC_RING_LENGTH,Channel 4 Rx Descriptor Ring Length"
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x1334++0x03
line.long 0x00 "DMA_CH4_INTERRUPT_ENABLE,Channel 4 Interrupt Enable"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x1338++0x03
line.long 0x00 "DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER,Channel 4 Receive Interrupt Watchdog Timer"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x133C++0x03
line.long 0x00 "DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS,Channel 4 Slot Function Control and Status"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x1344++0x03
line.long 0x00 "DMA_CH4_CURRENT_APP_TXDESC,Channel 4 Current Application Transmit Descriptor"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x134C++0x03
line.long 0x00 "DMA_CH4_CURRENT_APP_RXDESC,Channel 4 Current Application Receive Descriptor"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x1354++0x03
line.long 0x00 "DMA_CH4_CURRENT_APP_TXBUFFER,Channel 4 Current Application Transmit Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x135C++0x03
line.long 0x00 "DMA_CH4_CURRENT_APP_RXBUFFER,Channel 4 Current Application Receive Buffer Address"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x1360++0x03
line.long 0x00 "DMA_CH4_STATUS,DMA Channel 4 Status"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
newline
bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
newline
bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x1364++0x03
line.long 0x00 "DMA_CH4_MISS_FRAME_CNT,Channel 4 Missed Frame Counter"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
newline
hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register"
rgroup.long 0x1368++0x03
line.long 0x00 "DMA_CH4_RXP_ACCEPT_CNT,Channel 4 RXP Frames Accepted Counter"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
newline
hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
rgroup.long 0x136C++0x03
line.long 0x00 "DMA_CH4_RX_ERI_CNT,Channel 4 Receive ERI Counter"
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
tree.end
tree "FLEXSPI (FlexSPI)"
base ad:0x30BB0000
group.long 0x00++0x03
line.long 0x00 "MCR0,Module Control Register 0"
hexmask.long.byte 0x00 24.--31. 1. "AHBGRANTWAIT,Timeout wait cycle for AHB command grant"
hexmask.long.byte 0x00 16.--23. 1. "IPGRANTWAIT,Time out wait cycle for IP command grant"
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bitfld.long 0x00 15. "LEARNEN,This bit is used to enable/disable data learning feature" "0: LEARNEN_0,1: LEARNEN_1"
bitfld.long 0x00 14. "SCKFREERUNEN,This bit is used to force SCLK output free-running" "0: SCKFREERUNEN_0,1: SCKFREERUNEN_1"
newline
bitfld.long 0x00 13. "COMBINATIONEN,This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0])" "0: COMBINATIONEN_0,1: COMBINATIONEN_1"
bitfld.long 0x00 12. "DOZEEN,Doze mode enable bit" "0: Doze mode support disabled,1: Doze mode support enabled"
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bitfld.long 0x00 11. "HSEN,Half Speed Serial Flash access Enable" "0: Disable divide by 2 of serial flash clock for..,1: Enable divide by 2 of serial flash clock for.."
bitfld.long 0x00 8.--10. "SERCLKDIV,The serial root clock could be divided inside FlexSPI" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8"
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bitfld.long 0x00 7. "ATDFEN,Enable AHB bus Write Access to IP TX FIFO" "0: IP TX FIFO should be written by IP Bus,1: IP TX FIFO should be written by AHB Bus"
bitfld.long 0x00 6. "ARDFEN,Enable AHB bus Read Access to IP RX FIFO" "0: IP RX FIFO should be read by IP Bus,1: IP RX FIFO should be read by AHB Bus"
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bitfld.long 0x00 4.--5. "RXCLKSRC,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,?,3: Flash provided Read strobe and input from DQS.."
bitfld.long 0x00 1. "MDIS,Module Disable" "0,1"
newline
bitfld.long 0x00 0. "SWRESET,Software Reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "MCR1,Module Control Register 1"
hexmask.long.word 0x00 16.--31. 1. "SEQWAIT,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"
hexmask.long.word 0x00 0.--15. 1. "AHBBUSWAIT,AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles AHB Bus will get an error response"
group.long 0x08++0x03
line.long 0x00 "MCR2,Module Control Register 2"
hexmask.long.byte 0x00 24.--31. 1. "RESUMEWAIT,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed"
bitfld.long 0x00 19. "SCKBDIFFOPT,B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK)" "0: B_SCLK pad is used as port B SCLK clock output,1: B_SCLK pad is used as port A SCLK inverted.."
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bitfld.long 0x00 15. "SAMEDEVICEEN,All external devices are same devices (both in types and size) for A1/A2/B1/B2" "0: In Individual mode..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register.."
bitfld.long 0x00 14. "CLRLEARNPHASE,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1" "0,1"
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bitfld.long 0x00 11. "CLRAHBBUFOPT,This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK" "0: AHB RX/TX Buffer will not be cleaned..,1: AHB RX/TX Buffer will be cleaned.."
group.long 0x0C++0x03
line.long 0x00 "AHBCR,AHB Bus Control Register"
bitfld.long 0x00 6. "READADDROPT,AHB Read Address option bit" "0: There is AHB read burst start address..,1: There is no AHB read burst start address.."
bitfld.long 0x00 5. "PREFETCHEN,AHB Read Prefetch Enable" "0,1"
newline
bitfld.long 0x00 4. "BUFFERABLEEN,Enable AHB bus bufferable write access support" "0: Disabled,1: Enabled"
bitfld.long 0x00 3. "CACHABLEEN,Enable AHB bus cachable read access support" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "APAREN,Parallel mode enabled for AHB triggered Command (both read and write)" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
group.long 0x10++0x03
line.long 0x00 "INTEN,Interrupt Enable Register"
bitfld.long 0x00 11. "SEQTIMEOUTEN,Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details" "0,1"
bitfld.long 0x00 10. "AHBBUSTIMEOUTEN,AHB Bus timeout interrupt.Refer Interrupts chapter for more details" "0,1"
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bitfld.long 0x00 9. "SCKSTOPBYWREN,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable" "0,1"
bitfld.long 0x00 8. "SCKSTOPBYRDEN,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable" "0,1"
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bitfld.long 0x00 7. "DATALEARNFAILEN,Data Learning failed interrupt enable" "0,1"
bitfld.long 0x00 6. "IPTXWEEN,IP TX FIFO WaterMark empty interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "IPRXWAEN,IP RX FIFO WaterMark available interrupt enable" "0,1"
bitfld.long 0x00 4. "AHBCMDERREN,AHB triggered Command Sequences Error Detected interrupt enable" "0,1"
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bitfld.long 0x00 3. "IPCMDERREN,IP triggered Command Sequences Error Detected interrupt enable" "0,1"
bitfld.long 0x00 2. "AHBCMDGEEN,AHB triggered Command Sequences Grant Timeout interrupt enable" "0,1"
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bitfld.long 0x00 1. "IPCMDGEEN,IP triggered Command Sequences Grant Timeout interrupt enable" "0,1"
bitfld.long 0x00 0. "IPCMDDONEEN,IP triggered Command Sequences Execution finished interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "INTR,Interrupt Register"
eventfld.long 0x00 11. "SEQTIMEOUT,Sequence execution timeout interrupt" "0,1"
eventfld.long 0x00 10. "AHBBUSTIMEOUT,AHB Bus timeout interrupt.Refer Interrupts chapter for more details" "0,1"
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eventfld.long 0x00 9. "SCKSTOPBYWR,SCLK is stopped during command sequence because Async TX FIFO empty interrupt" "0,1"
eventfld.long 0x00 8. "SCKSTOPBYRD,SCLK is stopped during command sequence because Async RX FIFO full interrupt" "0,1"
newline
eventfld.long 0x00 7. "DATALEARNFAIL,Data Learning failed interrupt" "0,1"
eventfld.long 0x00 6. "IPTXWE,IP TX FIFO watermark empty interrupt" "0,1"
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eventfld.long 0x00 5. "IPRXWA,IP RX FIFO watermark available interrupt" "0,1"
eventfld.long 0x00 4. "AHBCMDERR,AHB triggered Command Sequences Error Detected interrupt" "0,1"
newline
eventfld.long 0x00 3. "IPCMDERR,IP triggered Command Sequences Error Detected interrupt" "0,1"
eventfld.long 0x00 2. "AHBCMDGE,AHB triggered Command Sequences Grant Timeout interrupt" "0,1"
newline
eventfld.long 0x00 1. "IPCMDGE,IP triggered Command Sequences Grant Timeout interrupt" "0,1"
eventfld.long 0x00 0. "IPCMDDONE,IP triggered Command Sequences Execution finished interrupt" "0,1"
group.long 0x18++0x03
line.long 0x00 "LUTKEY,LUT Key Register"
hexmask.long 0x00 0.--31. 1. "KEY,The Key to lock or unlock LUT"
group.long 0x1C++0x03
line.long 0x00 "LUTCR,LUT Control Register"
bitfld.long 0x00 1. "UNLOCK,Unlock LUT" "0,1"
bitfld.long 0x00 0. "LOCK,Lock LUT" "0,1"
group.long 0x20++0x03
line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x24++0x03
line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x28++0x03
line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x2C++0x03
line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x30++0x03
line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x34++0x03
line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x38++0x03
line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x3C++0x03
line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0"
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
group.long 0x60++0x03
line.long 0x00 "FLSHA1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x64++0x03
line.long 0x00 "FLSHA2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x68++0x03
line.long 0x00 "FLSHB1CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
group.long 0x6C++0x03
line.long 0x00 "FLSHB2CR0,Flash Control Register 0"
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x70)++0x03
line.long 0x00 "FLSHCR1A$1,Flash Control Register $1"
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
newline
bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
newline
bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x78)++0x03
line.long 0x00 "FLSHCR1B$1,Flash Control Register $1"
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
newline
bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
newline
bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x80)++0x03
line.long 0x00 "FLSHCR2A$1,Flash Control Register 2"
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
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hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--12. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x88)++0x03
line.long 0x00 "FLSHCR2B$1,Flash Control Register 2"
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
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hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--12. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
group.long 0x94++0x03
line.long 0x00 "FLSHCR4,Flash Control Register 4"
bitfld.long 0x00 3. "WMENB,Write mask enable bit for flash device on port B" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
bitfld.long 0x00 2. "WMENA,Write mask enable bit for flash device on port A" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
newline
bitfld.long 0x00 0. "WMOPT1,Write mask option bit 1" "0: DQS pin will be used as Write Mask when..,1: DQS pin will not be used as Write Mask when.."
group.long 0xA0++0x03
line.long 0x00 "IPCR0,IP Control Register 0"
hexmask.long 0x00 0.--31. 1. "SFAR,Serial Flash Address for IP command"
group.long 0xA4++0x03
line.long 0x00 "IPCR1,IP Control Register 1"
bitfld.long 0x00 31. "IPAREN,Parallel mode Enabled for IP command" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
bitfld.long 0x00 24.--26. "ISEQNUM,Sequence Number for IP command: ISEQNUM+1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--20. "ISEQID,Sequence Index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "IDATSZ,Flash Read/Program Data Size (in Bytes) for IP command"
group.long 0xB0++0x03
line.long 0x00 "IPCMD,IP Command Register"
bitfld.long 0x00 0. "TRG,Setting this bit will trigger an IP Command" "0,1"
group.long 0xB4++0x03
line.long 0x00 "DLPR,Data Learn Pattern Register"
hexmask.long 0x00 0.--31. 1. "DLP,Data Learning Pattern"
group.long 0xB8++0x03
line.long 0x00 "IPRXFCR,IP RX FIFO Control Register"
bitfld.long 0x00 2.--7. "RXWMRK,Watermark level is (RXWMRK+1)*64 Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "RXDMAEN,IP RX FIFO reading by DMA enabled" "0: IP RX FIFO would be read by processor,1: IP RX FIFO would be read by DMA"
newline
bitfld.long 0x00 0. "CLRIPRXF,Clear all valid data entries in IP RX FIFO" "0,1"
group.long 0xBC++0x03
line.long 0x00 "IPTXFCR,IP TX FIFO Control Register"
hexmask.long.byte 0x00 2.--8. 1. "TXWMRK,Watermark level is (TXWMRK+1)*64 Bits"
bitfld.long 0x00 1. "TXDMAEN,IP TX FIFO filling by DMA enabled" "0: IP TX FIFO would be filled by processor,1: IP TX FIFO would be filled by DMA"
newline
bitfld.long 0x00 0. "CLRIPTXF,Clear all valid data entries in IP TX FIFO" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DLLCRA,DLL Control Register 0"
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
newline
bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
newline
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
group.long 0xC4++0x03
line.long 0x00 "DLLCRB,DLL Control Register 0"
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
newline
bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
newline
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
rgroup.long 0xE0++0x03
line.long 0x00 "STS0,Status Register 0"
bitfld.long 0x00 8.--11. "DATALEARNPHASEB,Indicate the sampling clock phase selection on Port B after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DATALEARNPHASEA,Indicate the sampling clock phase selection on Port A after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "ARBCMDSRC,This status field indicates the trigger source of current command sequence granted by arbitrator" "0: Triggered by AHB read command (triggered by..,1: Triggered by AHB write command (triggered by..,2: Triggered by IP command (triggered by setting..,3: Triggered by suspended command (resumed)"
bitfld.long 0x00 1. "ARBIDLE,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface" "0,1"
newline
bitfld.long 0x00 0. "SEQIDLE,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface" "0,1"
rgroup.long 0xE4++0x03
line.long 0x00 "STS1,Status Register 1"
bitfld.long 0x00 24.--27. "IPCMDERRCODE,Indicates the Error Code when IP command Error detected" "0: IPCMDERRCODE_0,?,2: IP command with JMP_ON_CS instruction used in..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,6: Flash access start address exceed the whole..,?,?,?,?,?,?,?,14: Sequence execution timeout,15: Flash boundary crossed"
bitfld.long 0x00 16.--20. "IPCMDERRID,Indicates the sequence Index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--11. "AHBCMDERRCODE,Indicates the Error Code when AHB command Error detected" "0: AHBCMDERRCODE_0,?,2: AHB Write command with JMP_ON_CS instruction..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,?,?,?,?,?,?,?,?,14: Sequence execution timeout,?..."
bitfld.long 0x00 0.--4. "AHBCMDERRID,Indicates the sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xE8++0x03
line.long 0x00 "STS2,Status Register 2"
bitfld.long 0x00 24.--29. "BREFSEL,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. "BSLVSEL,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 17. "BREFLOCK,Flash B sample clock reference delay line locked" "0,1"
bitfld.long 0x00 16. "BSLVLOCK,Flash B sample clock slave delay line locked" "0,1"
newline
bitfld.long 0x00 8.--13. "AREFSEL,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 2.--7. "ASLVSEL,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "AREFLOCK,Flash A sample clock reference delay line locked" "0,1"
bitfld.long 0x00 0. "ASLVLOCK,Flash A sample clock slave delay line locked" "0,1"
rgroup.long 0xEC++0x03
line.long 0x00 "AHBSPNDSTS,AHB Suspend Status Register"
hexmask.long.word 0x00 16.--31. 1. "DATLFT,Left Data size for suspended command sequence (in byte)"
bitfld.long 0x00 1.--3. "BUFID,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "ACTIVE,Indicates if an AHB read prefetch command sequence has been suspended" "0,1"
rgroup.long 0xF0++0x03
line.long 0x00 "IPRXFSTS,IP RX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. "RDCNTR,Total Read Data Counter: RDCNTR * 64 Bits"
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP RX FIFO"
rgroup.long 0xF4++0x03
line.long 0x00 "IPTXFSTS,IP TX FIFO Status Register"
hexmask.long.word 0x00 16.--31. 1. "WRCNTR,Total Write Data Counter: WRCNTR * 64 Bits"
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP TX FIFO"
repeat 32. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x100)++0x03
line.long 0x00 "RFDR[$1],IP RX FIFO Data Register x $1"
hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data"
repeat.end
repeat 32. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x180)++0x03
line.long 0x00 "TFDR[$1],IP TX FIFO Data Register x $1"
hexmask.long 0x00 0.--31. 1. "TXDATA,TX Data"
repeat.end
repeat 128. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "LUT[$1],LUT x $1"
bitfld.long 0x00 26.--31. "OPCODE1,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "NUM_PADS1,NUM_PADS1" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "OPERAND1,OPERAND1"
bitfld.long 0x00 10.--15. "OPCODE0,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "NUM_PADS0,NUM_PADS0" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "OPERAND0,OPERAND0"
repeat.end
tree.end
tree "FRAMECOMPOSER (FrameComposer)"
base ad:0x32FD9000
group.byte 0x00++0x00
line.byte 0x00 "fc_invidconf,Frame Composer Input Video Configuration and HDCP Keepout Register"
bitfld.byte 0x00 7. "HDCP_keepout,Start/stop HDCP keepout window generation" "0,1"
bitfld.byte 0x00 6. "vsync_in_polarity,Vsync input polarity" "0: Active low,1: Active high"
newline
bitfld.byte 0x00 5. "hsync_in_polarity,Hsync input polarity" "0: Active low,1: Active high"
bitfld.byte 0x00 4. "de_in_polarity,Data enable input polarity" "0: Active low,1: Active high"
newline
bitfld.byte 0x00 3. "DVI_modez,Active low" "0: DVI mode selected,1: HDMI mode selected"
bitfld.byte 0x00 1. "r_v_blank_in_osc,Used for CEA861-D modes with fractional Vblank (for example modes 5 6 7 10 11 20 21 and 22)" "0,1"
newline
bitfld.byte 0x00 0. "in_I_P,Input video mode" "0: Progressive,1: Interlaced"
group.byte 0x01++0x00
line.byte 0x00 "fc_inhactiv0,Frame Composer Input Video HActive Pixels Register 0"
hexmask.byte 0x00 0.--7. 1. "H_in_activ,Input video Horizontal active pixel region width"
group.byte 0x02++0x00
line.byte 0x00 "fc_inhactiv1,Frame Composer Input Video HActive Pixels Register 1"
bitfld.byte 0x00 5. "H_in_activ_13,Input video Horizontal active pixel region width (0" "0,1"
bitfld.byte 0x00 4. "H_in_activ_12,Input video Horizontal active pixel region width (0" "0,1"
newline
bitfld.byte 0x00 0.--3. "H_in_activ,Input video Horizontal active pixel region width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x03++0x00
line.byte 0x00 "fc_inhblank0,Frame Composer Input Video HBlank Pixels Register 0"
hexmask.byte 0x00 0.--7. 1. "H_in_blank,Input video Horizontal blanking pixel region width"
group.byte 0x04++0x00
line.byte 0x00 "fc_inhblank1,Frame Composer Input Video HBlank Pixels Register 1"
bitfld.byte 0x00 2.--4. "H_in_blank_12,Input video Horizontal blanking pixel region width If configuration parameter DWC_HDMI_TX_14 = True (1) this bit field holds bit 12:10 of number of horizontal blanking pixels" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--1. "H_in_blank,Input video Horizontal blanking pixel region width this bit field holds bits 9:8 of number of Horizontal blanking pixels" "0,1,2,3"
group.byte 0x05++0x00
line.byte 0x00 "fc_invactiv0,Frame Composer Input Video VActive Pixels Register 0"
hexmask.byte 0x00 0.--7. 1. "V_in_activ,Input video Vertical active pixel region width"
group.byte 0x06++0x00
line.byte 0x00 "fc_invactiv1,Frame Composer Input Video VActive Pixels Register 1"
bitfld.byte 0x00 3.--4. "V_in_activ_12_11,Input video Vertical active pixel region width" "0,1,2,3"
bitfld.byte 0x00 0.--2. "V_in_activ,Input video Vertical active pixel region width" "0,1,2,3,4,5,6,7"
group.byte 0x07++0x00
line.byte 0x00 "fc_invblank,Frame Composer Input Video VBlank Pixels Register"
hexmask.byte 0x00 0.--7. 1. "V_in_blank,Input video Vertical blanking pixel region width"
group.byte 0x08++0x00
line.byte 0x00 "fc_hsyncindelay0,Frame Composer Input Video HSync Front Porch Register 0"
hexmask.byte 0x00 0.--7. 1. "H_in_delay,Input video Hsync active edge delay"
group.byte 0x09++0x00
line.byte 0x00 "fc_hsyncindelay1,Frame Composer Input Video HSync Front Porch Register 1"
bitfld.byte 0x00 3.--4. "H_in_delay_12,Input video Horizontal active edge delay" "0,1,2,3"
bitfld.byte 0x00 0.--2. "H_in_delay,Input video Horizontal active edge delay" "0,1,2,3,4,5,6,7"
group.byte 0x0A++0x00
line.byte 0x00 "fc_hsyncinwidth0,Frame Composer Input Video HSync Width Register 0"
hexmask.byte 0x00 0.--7. 1. "H_in_width,Input video Hsync active pulse width"
group.byte 0x0B++0x00
line.byte 0x00 "fc_hsyncinwidth1,Frame Composer Input Video HSync Width Register 1"
bitfld.byte 0x00 1. "H_in_width_9,Input video Hsync active pulse width" "0,1"
bitfld.byte 0x00 0. "H_in_width,Input video Hsync active pulse width" "0,1"
group.byte 0x0C++0x00
line.byte 0x00 "fc_vsyncindelay,Frame Composer Input Video VSync Front Porch Register"
hexmask.byte 0x00 0.--7. 1. "V_in_delay,Input video Vsync active edge delay"
group.byte 0x0D++0x00
line.byte 0x00 "fc_vsyncinwidth,Frame Composer Input Video VSync Width Register"
bitfld.byte 0x00 0.--5. "V_in_width,Input video Vsync active pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 2. (strings "0" "1" )(list 0x0 0x1 )
group.byte ($2+0x0E)++0x00
line.byte 0x00 "fc_infreq$1,Frame Composer Input Video Refresh Rate Register $1"
hexmask.byte 0x00 0.--7. 1. "infreq,Video refresh rate in Hz*1E3 format"
repeat.end
group.byte 0x10++0x00
line.byte 0x00 "fc_infreq2,Frame Composer Input Video Refresh Rate Register 2"
bitfld.byte 0x00 0.--3. "infreq,Video refresh rate in Hz*1E3 format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x11++0x00
line.byte 0x00 "fc_ctrldur,Frame Composer Control Period Duration Register"
hexmask.byte 0x00 0.--7. 1. "ctrlperiodduration,Configuration of the control period minimum duration (minimum of 12 pixel clock cycles refer to HDMI 1"
group.byte 0x12++0x00
line.byte 0x00 "fc_exctrldur,Frame Composer Extended Control Period Duration Register"
hexmask.byte 0x00 0.--7. 1. "exctrlperiodduration,Configuration of the extended control period minimum duration (minimum of 32 pixel clock cycles refer to HDMI 1"
group.byte 0x13++0x00
line.byte 0x00 "fc_exctrlspac,Frame Composer Extended Control Period Maximum Spacing Register"
hexmask.byte 0x00 0.--7. 1. "exctrlperiodspacing,Configuration of the maximum spacing between consecutive extended control periods (maximum of 50ms refer to the applicable HDMI specification)"
group.byte 0x14++0x00
line.byte 0x00 "fc_ch0pream,Frame Composer Channel 0 Non-Preamble Data Register"
hexmask.byte 0x00 0.--7. 1. "ch0_preamble_filter,When in control mode configures 8 bits that fill the channel 0 data lines not used to transmit the preamble (for more clarification refer to the HDMI 1"
group.byte 0x15++0x00
line.byte 0x00 "fc_ch1pream,Frame Composer Channel 1 Non-Preamble Data Register"
bitfld.byte 0x00 0.--5. "ch1_preamble_filter,When in control mode configures 6 bits that fill the channel 1 data lines not used to transmit the preamble (for more clarification refer to the HDMI 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x16++0x00
line.byte 0x00 "fc_ch2pream,Frame Composer Channel 2 Non-Preamble Data Register"
bitfld.byte 0x00 0.--5. "ch2_preamble_filter,When in control mode configures 6 bits that fill the channel 2 data lines not used to transmit the preamble (for more clarification refer to the HDMI 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x17++0x00
line.byte 0x00 "fc_aviconf3,Frame Composer AVI Packet Configuration Register 3"
bitfld.byte 0x00 2.--3. "YQ,YCbCr Quantization range according to the CEA specification" "0,1,2,3"
bitfld.byte 0x00 0.--1. "CN,IT content type according to CEA the specification" "0,1,2,3"
group.byte 0x18++0x00
line.byte 0x00 "fc_gcp,Frame Composer GCP Packet Configuration Register"
bitfld.byte 0x00 2. "default_phase,Value of default_phase in the GCP packet" "0,1"
bitfld.byte 0x00 1. "set_avmute,Value of set_avmute in the GCP packet Once the AVmute is set the frame composer schedules the GCP packet with AVmute set in the packet scheduler to be sent once (may only be transmitted between the active edge of VSYNC and 384 pixels.." "0,1"
newline
bitfld.byte 0x00 0. "clear_avmute,Value of clear_avmute in the GCP packet" "0,1"
group.byte 0x19++0x00
line.byte 0x00 "fc_aviconf0,Frame Composer AVI Packet Configuration Register 0"
bitfld.byte 0x00 7. "rgc_ycc_indication_2,Y2 Bit 2 of rgc_ycc_indication" "0,1"
bitfld.byte 0x00 6. "active_format_present,Active format present" "0,1"
newline
bitfld.byte 0x00 4.--5. "scan_information,Scan information" "0,1,2,3"
bitfld.byte 0x00 2.--3. "bar_information,Bar information data valid" "0,1,2,3"
newline
bitfld.byte 0x00 0.--1. "rgc_ycc_indication,Y1 Y0 RGB or YCbCr indicator" "0,1,2,3"
group.byte 0x1A++0x00
line.byte 0x00 "fc_aviconf1,Frame Composer AVI Packet Configuration Register 1"
bitfld.byte 0x00 6.--7. "Colorimetry,Colorimetry" "0,1,2,3"
bitfld.byte 0x00 4.--5. "picture_aspect_ratio,Picture aspect ratio" "0,1,2,3"
newline
bitfld.byte 0x00 0.--3. "active_aspect_ratio,Active aspect ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1B++0x00
line.byte 0x00 "fc_aviconf2,Frame Composer AVI Packet Configuration Register 2"
bitfld.byte 0x00 7. "it_content,IT content" "0,1"
bitfld.byte 0x00 4.--6. "extended_colorimetry,Extended colorimetry" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 2.--3. "quantization_range,Quantization range" "0,1,2,3"
bitfld.byte 0x00 0.--1. "non_uniform_picture_scaling,Non-uniform picture scaling" "0,1,2,3"
group.byte 0x1C++0x00
line.byte 0x00 "fc_avivid,Frame Composer AVI Packet VIC Register"
bitfld.byte 0x00 7. "fc_avivid_7,Bit 7 of fc_avivid register" "0,1"
hexmask.byte 0x00 0.--6. 1. "fc_avivid,Configures the AVI InfoFrame Video Identification code"
group.byte 0x25++0x00
line.byte 0x00 "fc_audiconf0,Frame Composer AUD Packet Configuration Register 0"
bitfld.byte 0x00 4.--6. "CC,Channel count" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--3. "CT,Coding Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x26++0x00
line.byte 0x00 "fc_audiconf1,Frame Composer AUD Packet Configuration Register 1"
bitfld.byte 0x00 4.--5. "SS,Sampling size" "0,1,2,3"
bitfld.byte 0x00 0.--2. "SF,Sampling frequency" "0,1,2,3,4,5,6,7"
group.byte 0x27++0x00
line.byte 0x00 "fc_audiconf2,Frame Composer AUD Packet Configuration Register 2"
hexmask.byte 0x00 0.--7. 1. "CA,Channel allocation"
group.byte 0x28++0x00
line.byte 0x00 "fc_audiconf3,Frame Composer AUD Packet Configuration Register 3"
bitfld.byte 0x00 5.--6. "LFEPBL,LFE playback information LFEPBL1 LFEPBL0 LFE playback level as compared to the other channels" "0,1,2,3"
bitfld.byte 0x00 4. "DM_INH,Down mix enable" "0,1"
newline
bitfld.byte 0x00 0.--3. "LSV,Level shift value (for down mixing)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x29++0x00
line.byte 0x00 "fc_vsdieeeid0,Frame Composer VSI Packet Data IEEE Register 0"
hexmask.byte 0x00 0.--7. 1. "IEEE,This register configures the Vendor Specific InfoFrame IEEE registration identifier"
group.byte 0x2A++0x00
line.byte 0x00 "fc_vsdsize,Frame Composer VSI Packet Data Size Register"
bitfld.byte 0x00 0.--4. "VSDSIZE,Packet size as described in the HDMI Vendor Specific InfoFrame (from the HDMI specification)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 2. (strings "1" "2" )(list 0x0 0x1 )
group.byte ($2+0x30)++0x00
line.byte 0x00 "fc_vsdieeeid$1,Frame Composer VSI Packet Data IEEE Register $1"
hexmask.byte 0x00 0.--7. 1. "IEEE,This register configures the Vendor Specific InfoFrame IEEE registration identifier"
repeat.end
group.byte 0x62++0x00
line.byte 0x00 "fc_spddeviceinf,Frame Composer SPD Packet Data Source Product Descriptor Register"
hexmask.byte 0x00 0.--7. 1. "fc_spddeviceinf,Frame Composer SPD Packet Data Source Product Descriptor Register"
group.byte 0x63++0x00
line.byte 0x00 "fc_audsconf,Frame Composer Audio Sample Flat and Layout Configuration Register"
bitfld.byte 0x00 4.--7. "aud_packet_sampflt,Set the audio packet sample flat value to be sent on the packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "aud_packet_layout,Set the audio packet layout to be sent in the packet" "0: layout 0 If,1: layout 1"
rgroup.byte 0x64++0x00
line.byte 0x00 "fc_audsstat,Frame Composer Audio Sample Flat and Layout Status Register"
bitfld.byte 0x00 0.--3. "packet_sampprs,Shows the data sample present indication of the last Audio sample packet sent by the HDMI TX Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x65++0x00
line.byte 0x00 "fc_audsv,Frame Composer Audio Sample Validity Flag Register"
bitfld.byte 0x00 7. "V3r,Set validity bit V for Channel 3 Right" "0,1"
bitfld.byte 0x00 6. "V2r,Set validity bit V for Channel 2 Right" "0,1"
newline
bitfld.byte 0x00 5. "V1r,Set validity bit V for Channel 1 Right" "0,1"
bitfld.byte 0x00 4. "V0r,Set validity bit V for Channel 0 Right" "0,1"
newline
bitfld.byte 0x00 3. "V3l,Set validity bit V for Channel 3 Left" "0,1"
bitfld.byte 0x00 2. "V2l,Set validity bit V for Channel 2 Left" "0,1"
newline
bitfld.byte 0x00 1. "V1l,Set validity bit V for Channel 1 Left" "0,1"
bitfld.byte 0x00 0. "V0l,Set validity bit V for Channel 0 Left" "0,1"
group.byte 0x66++0x00
line.byte 0x00 "fc_audsu,Frame Composer Audio Sample User Flag Register"
bitfld.byte 0x00 7. "U3r,Set user bit U for Channel 3 Right" "0,1"
bitfld.byte 0x00 6. "U2r,Set user bit U for Channel 2 Right" "0,1"
newline
bitfld.byte 0x00 5. "U1r,Set user bit U for Channel 1 Right" "0,1"
bitfld.byte 0x00 4. "U0r,Set user bit U for Channel 0 Right" "0,1"
newline
bitfld.byte 0x00 3. "U3l,Set user bit U for Channel 3 Left" "0,1"
bitfld.byte 0x00 2. "U2l,Set user bit U for Channel 2 Left" "0,1"
newline
bitfld.byte 0x00 1. "U1l,Set user bit U for Channel 1 Left" "0,1"
bitfld.byte 0x00 0. "U0l,Set user bit U for Channel 0 Left" "0,1"
group.byte 0x67++0x00
line.byte 0x00 "fc_audschnl0,Frame Composer Audio Sample Channel Status Configuration Register 0"
bitfld.byte 0x00 4.--5. "oiec_cgmsa,CGMS-A" "0,1,2,3"
bitfld.byte 0x00 0. "oiec_copyright,IEC Copyright indication" "0,1"
group.byte 0x68++0x00
line.byte 0x00 "fc_audschnl1,Frame Composer Audio Sample Channel Status Configuration Register 1"
hexmask.byte 0x00 0.--7. 1. "oiec_categorycode,Category code"
group.byte 0x69++0x00
line.byte 0x00 "fc_audschnl2,Frame Composer Audio Sample Channel Status Configuration Register 2"
bitfld.byte 0x00 4.--6. "oiec_pcmaudiomode,PCM audio mode" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--3. "oiec_sourcenumber,Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6A++0x00
line.byte 0x00 "fc_audschnl3,Frame Composer Audio Sample Channel Status Configuration Register 3"
bitfld.byte 0x00 4.--7. "oiec_channelnumcr1,Channel number for second right sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "oiec_channelnumcr0,Channel number for first right sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6B++0x00
line.byte 0x00 "fc_audschnl4,Frame Composer Audio Sample Channel Status Configuration Register 4"
bitfld.byte 0x00 4.--7. "oiec_channelnumcr3,Channel number for fourth right sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "oiec_channelnumcr2,Channel number for third right sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6C++0x00
line.byte 0x00 "fc_audschnl5,Frame Composer Audio Sample Channel Status Configuration Register 5"
bitfld.byte 0x00 4.--7. "oiec_channelnumcl1,Channel number for second left sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "oiec_channelnumcl0,Channel number for first left sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6D++0x00
line.byte 0x00 "fc_audschnl6,Frame Composer Audio Sample Channel Status Configuration Register 6"
bitfld.byte 0x00 4.--7. "oiec_channelnumcl3,Channel number for fourth left sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "oiec_channelnumcl2,Channel number for third left sample" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6E++0x00
line.byte 0x00 "fc_audschnl7,Frame Composer Audio Sample Channel Status Configuration Register 7"
bitfld.byte 0x00 6.--7. "oiec_sampfreq_ext,Sampling frequency (channel status bits 31 and 30)" "0,1,2,3"
bitfld.byte 0x00 4.--5. "oiec_clkaccuracy,Clock accuracy" "0,1,2,3"
newline
bitfld.byte 0x00 0.--3. "oiec_sampfreq,Sampling frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6F++0x00
line.byte 0x00 "fc_audschnl8,Frame Composer Audio Sample Channel Status Configuration Register 8"
bitfld.byte 0x00 4.--7. "oiec_origsampfreq,Original sampling frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "oiec_wordlength,Word length configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x73++0x00
line.byte 0x00 "fc_ctrlqhigh,Frame Composer Number of High Priority Packets Attended Configuration Register"
bitfld.byte 0x00 0.--4. "onhighattended,Configures the number of high priority packets or audio sample packets consecutively attended before checking low priority queue status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x74++0x00
line.byte 0x00 "fc_ctrlqlow,Frame Composer Number of Low Priority Packets Attended Configuration Register"
bitfld.byte 0x00 0.--4. "onlowattended,Configures the number of low priority packets or null packets consecutively attended before checking high priority queue status or audio samples availability" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x75++0x00
line.byte 0x00 "fc_acp0,Frame Composer ACP Packet Type Configuration Register 0"
hexmask.byte 0x00 0.--7. 1. "acptype,Configures the ACP packet type"
group.byte 0x82++0x00
line.byte 0x00 "fc_acp16,Frame Composer ACP Packet Body Configuration Register 16"
hexmask.byte 0x00 0.--7. 1. "fc_acp16,Frame Composer ACP Packet Body Configuration Register 16"
group.byte 0x83++0x00
line.byte 0x00 "fc_acp15,Frame Composer ACP Packet Body Configuration Register 15"
hexmask.byte 0x00 0.--7. 1. "fc_acp15,Frame Composer ACP Packet Body Configuration Register 15"
group.byte 0x84++0x00
line.byte 0x00 "fc_acp14,Frame Composer ACP Packet Body Configuration Register 14"
hexmask.byte 0x00 0.--7. 1. "fc_acp14,Frame Composer ACP Packet Body Configuration Register 14"
group.byte 0x85++0x00
line.byte 0x00 "fc_acp13,Frame Composer ACP Packet Body Configuration Register 13"
hexmask.byte 0x00 0.--7. 1. "fc_acp13,Frame Composer ACP Packet Body Configuration Register 13"
group.byte 0x86++0x00
line.byte 0x00 "fc_acp12,Frame Composer ACP Packet Body Configuration Register 12"
hexmask.byte 0x00 0.--7. 1. "fc_acp12,Frame Composer ACP Packet Body Configuration Register 12"
group.byte 0x87++0x00
line.byte 0x00 "fc_acp11,Frame Composer ACP Packet Body Configuration Register 11"
hexmask.byte 0x00 0.--7. 1. "fc_acp11,Frame Composer ACP Packet Body Configuration Register 11"
group.byte 0x88++0x00
line.byte 0x00 "fc_acp10,Frame Composer ACP Packet Body Configuration Register 10"
hexmask.byte 0x00 0.--7. 1. "fc_acp10,Frame Composer ACP Packet Body Configuration Register 10"
group.byte 0x89++0x00
line.byte 0x00 "fc_acp9,Frame Composer ACP Packet Body Configuration Register 9"
hexmask.byte 0x00 0.--7. 1. "fc_acp9,Frame Composer ACP Packet Body Configuration Register 9"
group.byte 0x8A++0x00
line.byte 0x00 "fc_acp8,Frame Composer ACP Packet Body Configuration Register 8"
hexmask.byte 0x00 0.--7. 1. "fc_acp8,Frame Composer ACP Packet Body Configuration Register 8"
group.byte 0x8B++0x00
line.byte 0x00 "fc_acp7,Frame Composer ACP Packet Body Configuration Register 7"
hexmask.byte 0x00 0.--7. 1. "fc_acp7,Frame Composer ACP Packet Body Configuration Register 7"
group.byte 0x8C++0x00
line.byte 0x00 "fc_acp6,Frame Composer ACP Packet Body Configuration Register 6"
hexmask.byte 0x00 0.--7. 1. "fc_acp6,Frame Composer ACP Packet Body Configuration Register 6"
group.byte 0x8D++0x00
line.byte 0x00 "fc_acp5,Frame Composer ACP Packet Body Configuration Register 5"
hexmask.byte 0x00 0.--7. 1. "fc_acp5,Frame Composer ACP Packet Body Configuration Register 5"
group.byte 0x8E++0x00
line.byte 0x00 "fc_acp4,Frame Composer ACP Packet Body Configuration Register 4"
hexmask.byte 0x00 0.--7. 1. "fc_acp4,Frame Composer ACP Packet Body Configuration Register 4"
group.byte 0x8F++0x00
line.byte 0x00 "fc_acp3,Frame Composer ACP Packet Body Configuration Register 3"
hexmask.byte 0x00 0.--7. 1. "fc_acp3,Frame Composer ACP Packet Body Configuration Register 3"
group.byte 0x90++0x00
line.byte 0x00 "fc_acp2,Frame Composer ACP Packet Body Configuration Register 2"
hexmask.byte 0x00 0.--7. 1. "fc_acp2,Frame Composer ACP Packet Body Configuration Register 2"
group.byte 0x91++0x00
line.byte 0x00 "fc_acp1,Frame Composer ACP Packet Body Configuration Register 1"
hexmask.byte 0x00 0.--7. 1. "fc_acp1,Frame Composer ACP Packet Body Configuration Register 1"
group.byte 0x92++0x00
line.byte 0x00 "fc_iscr1_0,Frame Composer ISRC1 Packet Status Valid and Continue Configuration Register"
bitfld.byte 0x00 2.--4. "isrc_status,ISRC1 Status signal" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 1. "isrc_valid,ISRC1 Valid control signal" "0,1"
newline
bitfld.byte 0x00 0. "isrc_cont,ISRC1 Indication of packet continuation (ISRC2 will be transmitted)" "0,1"
group.byte 0x93++0x00
line.byte 0x00 "fc_iscr1_16,Frame Composer ISRC1 Packet Body Register 16"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_16,Frame Composer ISRC1 Packet Body Register 16 configures ISRC1 packet body of the ISRC1 packet"
group.byte 0x94++0x00
line.byte 0x00 "fc_iscr1_15,Frame Composer ISRC1 Packet Body Register 15"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_15,Frame Composer ISRC1 Packet Body Register 15"
group.byte 0x95++0x00
line.byte 0x00 "fc_iscr1_14,Frame Composer ISRC1 Packet Body Register 14"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_14,Frame Composer ISRC1 Packet Body Register 14"
group.byte 0x96++0x00
line.byte 0x00 "fc_iscr1_13,Frame Composer ISRC1 Packet Body Register 13"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_13,Frame Composer ISRC1 Packet Body Register 13"
group.byte 0x97++0x00
line.byte 0x00 "fc_iscr1_12,Frame Composer ISRC1 Packet Body Register 12"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_12,Frame Composer ISRC1 Packet Body Register 12"
group.byte 0x98++0x00
line.byte 0x00 "fc_iscr1_11,Frame Composer ISRC1 Packet Body Register 11"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_11,Frame Composer ISRC1 Packet Body Register 11"
group.byte 0x99++0x00
line.byte 0x00 "fc_iscr1_10,Frame Composer ISRC1 Packet Body Register 10"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_10,Frame Composer ISRC1 Packet Body Register 10"
group.byte 0x9A++0x00
line.byte 0x00 "fc_iscr1_9,Frame Composer ISRC1 Packet Body Register 9"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_9,Frame Composer ISRC1 Packet Body Register 9"
group.byte 0x9B++0x00
line.byte 0x00 "fc_iscr1_8,Frame Composer ISRC1 Packet Body Register 8"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_8,Frame Composer ISRC1 Packet Body Register 8"
group.byte 0x9C++0x00
line.byte 0x00 "fc_iscr1_7,Frame Composer ISRC1 Packet Body Register 7"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_7,Frame Composer ISRC1 Packet Body Register 7"
group.byte 0x9D++0x00
line.byte 0x00 "fc_iscr1_6,Frame Composer ISRC1 Packet Body Register 6"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_6,Frame Composer ISRC1 Packet Body Register 6"
group.byte 0x9E++0x00
line.byte 0x00 "fc_iscr1_5,Frame Composer ISRC1 Packet Body Register 5"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_5,Frame Composer ISRC1 Packet Body Register 5"
group.byte 0x9F++0x00
line.byte 0x00 "fc_iscr1_4,Frame Composer ISRC1 Packet Body Register 4"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_4,Frame Composer ISRC1 Packet Body Register 4"
group.byte 0xA0++0x00
line.byte 0x00 "fc_iscr1_3,Frame Composer ISRC1 Packet Body Register 3"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_3,Frame Composer ISRC1 Packet Body Register 3"
group.byte 0xA1++0x00
line.byte 0x00 "fc_iscr1_2,Frame Composer ISRC1 Packet Body Register 2"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_2,Frame Composer ISRC1 Packet Body Register 2"
group.byte 0xA2++0x00
line.byte 0x00 "fc_iscr1_1,Frame Composer ISRC1 Packet Body Register 1"
hexmask.byte 0x00 0.--7. 1. "fc_iscr1_1,Frame Composer ISRC1 Packet Body Register 1"
group.byte 0xA3++0x00
line.byte 0x00 "fc_iscr2_15,Frame Composer ISRC2 Packet Body Register 15"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_15,Frame Composer ISRC2 Packet Body Register 15 configures the ISRC2 packet body of the ISRC2 packet"
group.byte 0xA4++0x00
line.byte 0x00 "fc_iscr2_14,Frame Composer ISRC2 Packet Body Register 14"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_14,Frame Composer ISRC2 Packet Body Register 14"
group.byte 0xA5++0x00
line.byte 0x00 "fc_iscr2_13,Frame Composer ISRC2 Packet Body Register 13"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_13,Frame Composer ISRC2 Packet Body Register 13"
group.byte 0xA6++0x00
line.byte 0x00 "fc_iscr2_12,Frame Composer ISRC2 Packet Body Register 12"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_12,Frame Composer ISRC2 Packet Body Register 12"
group.byte 0xA7++0x00
line.byte 0x00 "fc_iscr2_11,Frame Composer ISRC2 Packet Body Register 11"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_11,Frame Composer ISRC2 Packet Body Register 11"
group.byte 0xA8++0x00
line.byte 0x00 "fc_iscr2_10,Frame Composer ISRC2 Packet Body Register 10"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_10,Frame Composer ISRC2 Packet Body Register 10"
group.byte 0xA9++0x00
line.byte 0x00 "fc_iscr2_9,Frame Composer ISRC2 Packet Body Register 9"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_9,Frame Composer ISRC2 Packet Body Register 9"
group.byte 0xAA++0x00
line.byte 0x00 "fc_iscr2_8,Frame Composer ISRC2 Packet Body Register 8"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_8,Frame Composer ISRC2 Packet Body Register 8"
group.byte 0xAB++0x00
line.byte 0x00 "fc_iscr2_7,Frame Composer ISRC2 Packet Body Register 7"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_7,Frame Composer ISRC2 Packet Body Register 7"
group.byte 0xAC++0x00
line.byte 0x00 "fc_iscr2_6,Frame Composer ISRC2 Packet Body Register 6"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_6,Frame Composer ISRC2 Packet Body Register 6"
group.byte 0xAD++0x00
line.byte 0x00 "fc_iscr2_5,Frame Composer ISRC2 Packet Body Register 5"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_5,Frame Composer ISRC2 Packet Body Register 5"
group.byte 0xAE++0x00
line.byte 0x00 "fc_iscr2_4,Frame Composer ISRC2 Packet Body Register 4"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_4,Frame Composer ISRC2 Packet Body Register 4"
group.byte 0xAF++0x00
line.byte 0x00 "fc_iscr2_3,Frame Composer ISRC2 Packet Body Register 3"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_3,Frame Composer ISRC2 Packet Body Register 3"
group.byte 0xB0++0x00
line.byte 0x00 "fc_iscr2_2,Frame Composer ISRC2 Packet Body Register 2"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_2,Frame Composer ISRC2 Packet Body Register 2"
group.byte 0xB1++0x00
line.byte 0x00 "fc_iscr2_1,Frame Composer ISRC2 Packet Body Register 1"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_1,Frame Composer ISRC2 Packet Body Register 1"
group.byte 0xB2++0x00
line.byte 0x00 "fc_iscr2_0,Frame Composer ISRC2 Packet Body Register 0"
hexmask.byte 0x00 0.--7. 1. "fc_iscr2_0,Frame Composer ISRC2 Packet Body Register 0"
group.byte 0xB3++0x00
line.byte 0x00 "fc_datauto0,Frame Composer Data Island Auto Packet Scheduling Register 0 Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for SPD VSD ISRC2 ISRC1 and ACP packets"
bitfld.byte 0x00 4. "spd_auto,Enables SPD automatic packet scheduling" "0,1"
bitfld.byte 0x00 3. "vsd_auto,Enables VSD automatic packet scheduling" "0,1"
newline
bitfld.byte 0x00 2. "iscr2_auto,Enables ISRC2 automatic packet scheduling" "0,1"
bitfld.byte 0x00 1. "iscr1_auto,Enables ISRC1 automatic packet scheduling" "0,1"
newline
bitfld.byte 0x00 0. "acp_auto,Enables ACP automatic packet scheduling" "0,1"
group.byte 0xB4++0x00
line.byte 0x00 "fc_datauto1,Frame Composer Data Island Auto Packet Scheduling Register 1 Configures the Frame Composer (FC) RDRB frame interpolation for SPD VSD ISRC2 ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets"
bitfld.byte 0x00 0.--3. "auto_frame_interpolation,Packet frame interpolation for automatic packet scheduling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xB5++0x00
line.byte 0x00 "fc_datauto2,Frame Composer Data Island Auto packet scheduling Register 2 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for SPD VSD ISRC2 ISRC1 and ACP packet insertion on data island when FC is on RDRB mode.."
bitfld.byte 0x00 4.--7. "auto_frame_packets,Packets per frame for automatic packet scheduling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "auto_line_spacing,Packets line spacing for automatic packet scheduling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.byte 0xB6++0x00
line.byte 0x00 "fc_datman,Frame Composer Data Island Manual Packet Request Register Requests to the Frame Composer the data island packet insertion for NULL SPD VSD ISRC2 ISRC1 and ACP packets when FC_DATAUTO0 bit is in manual mode for the packet requested"
bitfld.byte 0x00 5. "null_tx,Null packet" "0,1"
bitfld.byte 0x00 4. "spd_tx,SPD packet" "0,1"
newline
bitfld.byte 0x00 3. "vsd_tx,VSD packet" "0,1"
bitfld.byte 0x00 2. "iscr2_tx,ISRC2 packet" "0,1"
newline
bitfld.byte 0x00 1. "iscr1_tx,ISRC1 packet" "0,1"
bitfld.byte 0x00 0. "acp_tx,ACP packet" "0,1"
group.byte 0xB7++0x00
line.byte 0x00 "fc_datauto3,Frame Composer Data Island Auto Packet Scheduling Register 3 Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for AVI GCP AUDI and ACR packets"
bitfld.byte 0x00 6. "drm_auto,Enables DRM packet insertion" "0,1"
bitfld.byte 0x00 5. "nvbi_auto,Enables NTSC VBI packet insertion" "0,1"
newline
bitfld.byte 0x00 4. "amp_auto,Enables AMP packet insertion" "0,1"
bitfld.byte 0x00 3. "avi_auto,Enables AVI packet insertion" "0,1"
newline
bitfld.byte 0x00 2. "gcp_auto,Enables GCP packet insertion" "0,1"
bitfld.byte 0x00 1. "audi_auto,Enables AUDI packet insertion" "0,1"
newline
bitfld.byte 0x00 0. "acr_auto,Enables ACR packet insertion" "0,1"
group.byte 0xB8++0x00
line.byte 0x00 "fc_rdrb0,Frame Composer Round Robin ACR Packet Insertion Register 0 Configures the Frame Composer (FC) RDRB frame interpolation for ACR packet insertion on data island when FC is on RDRB mode for this packet"
bitfld.byte 0x00 0.--3. "ACRframeinterpolation,ACR Frame interpolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xB9++0x00
line.byte 0x00 "fc_rdrb1,Frame Composer Round Robin ACR Packet Insertion Register 1 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the ACR packet insertion on data island when FC is on RDRB mode this packet"
bitfld.byte 0x00 4.--7. "ACRpacketsinframe,ACR packets in frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "ACRpacketlinespacing,ACR packet line spacing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xBA++0x00
line.byte 0x00 "fc_rdrb2,Frame Composer Round Robin AUDI Packet Insertion Register 2 Configures the Frame Composer (FC) RDRB frame interpolation for AUDI packet insertion on data island when FC is on RDRB mode for this packet"
bitfld.byte 0x00 0.--3. "AUDIframeinterpolation,Audio frame interpolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xBB++0x00
line.byte 0x00 "fc_rdrb3,Frame Composer Round Robin AUDI Packet Insertion Register 3 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AUDI packet insertion on data island when FC is on RDRB mode this packet"
bitfld.byte 0x00 4.--7. "AUDIpacketsinframe,Audio packets per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "AUDIpacketlinespacing,Audio packets line spacing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xBC++0x00
line.byte 0x00 "fc_rdrb4,Frame Composer Round Robin GCP Packet Insertion Register 4 Configures the Frame Composer (FC) RDRB frame interpolation for GCP packet insertion on data island when FC is on RDRB mode for this packet"
bitfld.byte 0x00 0.--3. "GCPframeinterpolation,Frames interpolated between GCP packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xBD++0x00
line.byte 0x00 "fc_rdrb5,Frame Composer Round Robin GCP Packet Insertion Register 5 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the GCP packet insertion on data island when FC is on RDRB mode this packet"
bitfld.byte 0x00 4.--7. "GCPpacketsinframe,GCP packets per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "GCPpacketlinespacing,GCP packets line spacing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xBE++0x00
line.byte 0x00 "fc_rdrb6,Frame Composer Round Robin AVI Packet Insertion Register 6 Configures the Frame Composer (FC) RDRB frame interpolation for AVI packet insertion on data island when FC is on RDRB mode for this packet"
bitfld.byte 0x00 0.--3. "AVIframeinterpolation,Frames interpolated between AVI packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xBF++0x00
line.byte 0x00 "fc_rdrb7,Frame Composer Round Robin AVI Packet Insertion Register 7 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AVI packet insertion on data island when FC is on RDRB mode this packet"
bitfld.byte 0x00 4.--7. "AVIpacketsinframe,AVI packets per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "AVIpacketlinespacing,AVI packets line spacing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC0++0x00
line.byte 0x00 "fc_rdrb8,Frame Composer Round Robin AMP Packet Insertion Register 8"
bitfld.byte 0x00 0.--3. "AMPframeinterpolation,AMP frame interpolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC1++0x00
line.byte 0x00 "fc_rdrb9,Frame Composer Round Robin AMP Packet Insertion Register 9"
bitfld.byte 0x00 4.--7. "AMPpacketsinframe,AMP packets per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "AMPpacketlinespacing,AMP packets line spacing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC2++0x00
line.byte 0x00 "fc_rdrb10,Frame Composer Round Robin NTSC VBI Packet Insertion Register 10"
bitfld.byte 0x00 0.--3. "NVBIframeinterpolation,NTSC VBI frame interpolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC3++0x00
line.byte 0x00 "fc_rdrb11,Frame Composer Round Robin NTSC VBI Packet Insertion Register 11"
bitfld.byte 0x00 4.--7. "NVBIpacketsinframe,NTSC VBI packets per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "NVBIpacketlinespacing,NTSC VBI packets line spacing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC4++0x00
line.byte 0x00 "fc_rdrb12,Frame Composer Round Robin DRM Packet Insertion Register 12"
bitfld.byte 0x00 0.--3. "DRMframeinterpolation,DRM frame interpolation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC5++0x00
line.byte 0x00 "fc_rdrb13,Frame Composer Round Robin DRM Packet Insertion Register 13"
bitfld.byte 0x00 4.--7. "DRMpacketsinframe,DRM packets per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "DRMpacketlinespacing,DRM packets line spacing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD2++0x00
line.byte 0x00 "fc_mask0,Frame Composer Packet Interrupt Mask Register 0"
bitfld.byte 0x00 7. "AUDI,Mask bit for FC_INT0" "0,1"
bitfld.byte 0x00 6. "ACP,Mask bit for FC_INT0" "0,1"
newline
bitfld.byte 0x00 5. "HBR,Mask bit for FC_INT0" "0,1"
bitfld.byte 0x00 4. "MAS,Mask bit for FC_INT0" "0,1"
newline
bitfld.byte 0x00 3. "NVBI,Mask bit for FC_INT0" "0,1"
bitfld.byte 0x00 2. "AUDS,Mask bit for FC_INT0" "0,1"
newline
bitfld.byte 0x00 1. "ACR,Mask bit for FC_INT0" "0,1"
bitfld.byte 0x00 0. "NULL,Mask bit for FC_INT0" "0,1"
group.byte 0xD6++0x00
line.byte 0x00 "fc_mask1,Frame Composer Packet Interrupt Mask Register 1"
bitfld.byte 0x00 7. "GMD,Mask bit for FC_INT1" "0,1"
bitfld.byte 0x00 6. "ISCR1,Mask bit for FC_INT1" "0,1"
newline
bitfld.byte 0x00 5. "ISCR2,Mask bit for FC_INT1" "0,1"
bitfld.byte 0x00 4. "VSD,Mask bit for FC_INT1" "0,1"
newline
bitfld.byte 0x00 3. "SPD,Mask bit for FC_INT1" "0,1"
bitfld.byte 0x00 2. "AMP,Mask bit for FC_INT1" "0,1"
newline
bitfld.byte 0x00 1. "AVI,Mask bit for FC_INT1" "0,1"
bitfld.byte 0x00 0. "GCP,Mask bit for FC_INT1" "0,1"
group.byte 0xDA++0x00
line.byte 0x00 "fc_mask2,Frame Composer High/Low Priority Overflow and DRM Interrupt Mask Register 2"
bitfld.byte 0x00 4. "DRM,Mask bit for FC_INT2" "0,1"
bitfld.byte 0x00 1. "LowPriority_overflow,Mask bit for FC_INT2" "0,1"
newline
bitfld.byte 0x00 0. "HighPriority_overflow,Mask bit for FC_INT2" "0,1"
group.byte 0xE0++0x00
line.byte 0x00 "fc_prconf,Frame Composer Pixel Repetition Configuration Register"
bitfld.byte 0x00 4.--7. "incoming_pr_factor,Configures the input video pixel repetition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "output_pr_factor,Configures the video pixel repetition ratio to be sent on the AVI InfoFrame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xE1++0x00
line.byte 0x00 "fc_scrambler_ctrl,Frame Composer Scrambler Control"
bitfld.byte 0x00 4. "scrambler_ucp_line,Debug register" "0,1"
bitfld.byte 0x00 0. "scrambler_on,When set (1'b1) this field activates the HDMI 2" "0,1"
group.byte 0xE2++0x00
line.byte 0x00 "fc_multistream_ctrl,Frame Composer Multi-Stream Audio Control"
bitfld.byte 0x00 0. "fc_mas_packet_en,This field when set (1'b1) activates the HDMI 2" "0,1"
group.byte 0xE3++0x00
line.byte 0x00 "fc_packet_tx_en,Frame Composer Packet Transmission Control"
bitfld.byte 0x00 7. "drm_tx_en,DRM transmission control" "0: Transmission disabled,1: Transmission enabled"
bitfld.byte 0x00 6. "nvbi_tx_en,NTSC VBI transmission control" "0: Transmission disabled,1: Transmission enabled"
newline
bitfld.byte 0x00 5. "amp_tx_en,AMP transmission control" "0: Transmission disabled,1: Transmission enabled"
bitfld.byte 0x00 4. "aut_tx_en,ACP SPD VSIF ISRC1 and SRC2 packet transmission control" "0: Transmission disabled,1: Transmission enabled"
newline
bitfld.byte 0x00 3. "audi_tx_en,AUDI packet transmission control" "0: Transmission disabled,1: Transmission enabled"
bitfld.byte 0x00 2. "avi_tx_en,AVI packet transmission control" "0: Transmission disabled,1: Transmission enabled"
newline
bitfld.byte 0x00 1. "gcp_tx_en,GCP transmission control" "0: Transmission disabled,1: Transmission enabled"
bitfld.byte 0x00 0. "acr_tx_en,ACR packet transmission control" "0: Transmission disabled,1: Transmission enabled"
group.byte 0xE8++0x00
line.byte 0x00 "fc_actspc_hdlr_cfg,Frame Composer Active Space Control"
bitfld.byte 0x00 1. "actspc_hdlr_tgl,Active Space handler control" "0,1"
bitfld.byte 0x00 0. "actspc_hdlr_en,Active Space Handler Control" "0,1"
group.byte 0xE9++0x00
line.byte 0x00 "fc_invact_2d_0,Frame Composer Input Video 2D VActive Pixels Register 0"
hexmask.byte 0x00 0.--7. 1. "fc_invact_2d_0,2D Input video vertical active pixel region width"
group.byte 0xEA++0x00
line.byte 0x00 "fc_invact_2d_1,Frame Composer Input Video VActive pixels Register 1"
bitfld.byte 0x00 0.--3. "fc_invact_2d_1,2D Input video vertical active pixel region width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x100++0x00
line.byte 0x00 "fc_gmd_stat,Frame Composer GMD Packet Status Register Gamut metadata packet status bit information for no_current_gmd next_gmd_field gmd_packet_sequence and current_gamut_seq_num"
bitfld.byte 0x00 7. "igmdno_crnt_gbd,Gamut scheduling: No current gamut data" "0,1"
bitfld.byte 0x00 6. "igmddnext_field,Gamut scheduling: Gamut Next field" "0,1"
newline
bitfld.byte 0x00 4.--5. "igmdpacket_seq,Gamut scheduling: Gamut packet sequence" "0,1,2,3"
bitfld.byte 0x00 0.--3. "igmdcurrent_gamut_seq_num,Gamut scheduling: Current Gamut packet sequence number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x101++0x00
line.byte 0x00 "fc_gmd_en,Frame Composer GMD Packet Enable Register This register enables Gamut metadata (GMD) packet transmission"
bitfld.byte 0x00 0. "gmdenabletx,Gamut Metadata packet transmission enable (1b)" "0,1"
wgroup.byte 0x102++0x00
line.byte 0x00 "fc_gmd_up,Frame Composer GMD Packet Update Register This register performs an GMD packet content update according to the configured packet body (FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB)"
bitfld.byte 0x00 0. "gmdupdatepacket,Gamut Metadata packet update" "0,1"
group.byte 0x103++0x00
line.byte 0x00 "fc_gmd_conf,Frame Composer GMD Packet Schedule Configuration Register This register configures the number of GMD packets to be inserted per frame (starting always in the line where the active Vsync appears) and the line spacing between the transmitted.."
bitfld.byte 0x00 4.--7. "gmdpacketsinframe,Number of GMD packets per frame or video field (profile P0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "gmdpacketlinespacing,Number of line spacing between the transmitted GMD packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x104++0x00
line.byte 0x00 "fc_gmd_hb,Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register This register configures the GMD packet header affected_gamut_seq_num and gmd_profile bits"
bitfld.byte 0x00 4.--6. "gmdgbd_profile,GMD profile bits" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--3. "gmdaffected_gamut_seq_num,Affected gamut sequence number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x128++0x00
line.byte 0x00 "fc_amp_hb1,Frame Composer AMP Packet Header Register 1"
hexmask.byte 0x00 0.--7. 1. "fc_amp_hb0,Frame Composer AMP Packet Header Register 1"
group.byte 0x129++0x00
line.byte 0x00 "fc_amp_hb2,Frame Composer AMP Packet Header Register 2"
hexmask.byte 0x00 0.--7. 1. "fc_amp_hb1,Frame Composer AMP Packet Header Register 2"
group.byte 0x148++0x00
line.byte 0x00 "fc_nvbi_hb1,Frame Composer NTSC VBI Packet Header Register 1"
hexmask.byte 0x00 0.--7. 1. "fc_nvbi_hb0,Frame Composer NTSC VBI Packet Header Register 1"
group.byte 0x149++0x00
line.byte 0x00 "fc_nvbi_hb2,Frame Composer NTSC VBI Packet Header Register 2"
hexmask.byte 0x00 0.--7. 1. "fc_nvbi_hb1,Frame Composer NTSC VBI Packet Header Register 2"
wgroup.byte 0x167++0x00
line.byte 0x00 "fc_drm_up,Frame Composer DRM Packet Update Register This register performs an DRM packet content update according to the configured packet body (FC_DRM_PB0 to FC_DRM_PB27) and packet header (FC_DRM_HB)"
bitfld.byte 0x00 0. "drmpacketupdate,DRM packet update" "0,1"
group.byte 0x200++0x00
line.byte 0x00 "fc_dbgforce,Frame Composer video/audio Force Enable Register This register allows to force the controller to output audio and video data the values configured in the FC_DBGAUD and FC_DBGTMDS registers"
bitfld.byte 0x00 4. "forceaudio,Force fixed audio output with FC_DBGAUDxCHx register contents" "0,1"
bitfld.byte 0x00 0. "forcevideo,Force fixed video output with FC_DBGTMDSx register contents" "0,1"
group.byte 0x201++0x00
line.byte 0x00 "fc_dbgaud0ch0,Frame Composer Audio Data Channel 0 Register 0 Configures the audio fixed data to be used in channel 0 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch0,Frame Composer Audio Data Channel 0 Register 0"
group.byte 0x202++0x00
line.byte 0x00 "fc_dbgaud1ch0,Frame Composer Audio Data Channel 0 Register 1 Configures the audio fixed data to be used in channel 0 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch0,Frame Composer Audio Data Channel 0 Register 1"
group.byte 0x203++0x00
line.byte 0x00 "fc_dbgaud2ch0,Frame Composer Audio Data Channel 0 Register 2 Configures the audio fixed data to be used in channel 0 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch0,Frame Composer Audio Data Channel 0 Register 2"
group.byte 0x204++0x00
line.byte 0x00 "fc_dbgaud0ch1,Frame Composer Audio Data Channel 1 Register 0 Configures the audio fixed data to be used in channel 1 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch1,Frame Composer Audio Data Channel 1 Register 0"
group.byte 0x205++0x00
line.byte 0x00 "fc_dbgaud1ch1,Frame Composer Audio Data Channel 1 Register 1 Configures the audio fixed data to be used in channel 1 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch1,Frame Composer Audio Data Channel 1 Register 1"
group.byte 0x206++0x00
line.byte 0x00 "fc_dbgaud2ch1,Frame Composer Audio Data Channel 1 Register 2 Configures the audio fixed data to be used in channel 1 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch1,Frame Composer Audio Data Channel 1 Register 2"
group.byte 0x207++0x00
line.byte 0x00 "fc_dbgaud0ch2,Frame Composer Audio Data Channel 2 Register 0 Configures the audio fixed data to be used in channel 2 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch2,Frame Composer Audio Data Channel 2 Register 0"
group.byte 0x208++0x00
line.byte 0x00 "fc_dbgaud1ch2,Frame Composer Audio Data Channel 2 Register 1 Configures the audio fixed data to be used in channel 2 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch2,Frame Composer Audio Data Channel 2 Register 1"
group.byte 0x209++0x00
line.byte 0x00 "fc_dbgaud2ch2,Frame Composer Audio Data Channel 2 Register 2 Configures the audio fixed data to be used in channel 2 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch2,Frame Composer Audio Data Channel 2 Register 2"
group.byte 0x20A++0x00
line.byte 0x00 "fc_dbgaud0ch3,Frame Composer Audio Data Channel 3 Register 0 Configures the audio fixed data to be used in channel 3 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch3,Frame Composer Audio Data Channel 3 Register 0"
group.byte 0x20B++0x00
line.byte 0x00 "fc_dbgaud1ch3,Frame Composer Audio Data Channel 3 Register 1 Configures the audio fixed data to be used in channel 3 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch3,Frame Composer Audio Data Channel 3 Register 1"
group.byte 0x20C++0x00
line.byte 0x00 "fc_dbgaud2ch3,Frame Composer Audio Data Channel 3 Register 2 Configures the audio fixed data to be used in channel 3 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch3,Frame Composer Audio Data Channel 3 Register 2"
group.byte 0x20D++0x00
line.byte 0x00 "fc_dbgaud0ch4,Frame Composer Audio Data Channel 4 Register 0 Configures the audio fixed data to be used in channel 4 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch4,Frame Composer Audio Data Channel 4 Register 0"
group.byte 0x20E++0x00
line.byte 0x00 "fc_dbgaud1ch4,Frame Composer Audio Data Channel 4 Register 1 Configures the audio fixed data to be used in channel 4 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch4,Frame Composer Audio Data Channel 4 Register 1"
group.byte 0x20F++0x00
line.byte 0x00 "fc_dbgaud2ch4,Frame Composer Audio Data Channel 4 Register 2 Configures the audio fixed data to be used in channel 4 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch4,Frame Composer Audio Data Channel 4 Register 2"
group.byte 0x210++0x00
line.byte 0x00 "fc_dbgaud0ch5,Frame Composer Audio Data Channel 5 Register 0 Configures the audio fixed data to be used in channel 5 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch5,Frame Composer Audio Data Channel 5 Register 0"
group.byte 0x211++0x00
line.byte 0x00 "fc_dbgaud1ch5,Frame Composer Audio Data Channel 5 Register 1 Configures the audio fixed data to be used in channel 5 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch5,Frame Composer Audio Data Channel 5 Register 1"
group.byte 0x212++0x00
line.byte 0x00 "fc_dbgaud2ch5,Frame Composer Audio Data Channel 5 Register 2 Configures the audio fixed data to be used in channel 5 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch5,Frame Composer Audio Data Channel 5 Register 2"
group.byte 0x213++0x00
line.byte 0x00 "fc_dbgaud0ch6,Frame Composer Audio Data Channel 6 Register 0 Configures the audio fixed data to be used in channel 6 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch6,Frame Composer Audio Data Channel 6 Register 0"
group.byte 0x214++0x00
line.byte 0x00 "fc_dbgaud1ch6,Frame Composer Audio Data Channel 6 Register 1 Configures the audio fixed data to be used in channel 6 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch6,Frame Composer Audio Data Channel 6 Register 1"
group.byte 0x215++0x00
line.byte 0x00 "fc_dbgaud2ch6,Frame Composer Audio Data Channel 6 Register 2 Configures the audio fixed data to be used in channel 6 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch6,Frame Composer Audio Data Channel 6 Register 2"
group.byte 0x216++0x00
line.byte 0x00 "fc_dbgaud0ch7,Frame Composer Audio Data Channel 7 Register 0 Configures the audio fixed data to be used in channel 7 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud0ch7,Frame Composer Audio Data Channel 7 Register 0"
group.byte 0x217++0x00
line.byte 0x00 "fc_dbgaud1ch7,Frame Composer Audio Data Channel 7 Register 1 Configures the audio fixed data to be used in channel 7 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud1ch7,Frame Composer Audio Data Channel 7 Register 1"
group.byte 0x218++0x00
line.byte 0x00 "fc_dbgaud2ch7,Frame Composer Audio Data Channel 7 Register 2 Configures the audio fixed data to be used in channel 7 when in fixed audio selection"
hexmask.byte 0x00 0.--7. 1. "fc_dbgaud2ch7,Frame Composer Audio Data Channel 7 Register 2"
tree.end
tree "GLUE_USB (USB3_GLUE)"
tree "USB1_GLUE"
base ad:0x381F0000
group.long 0x00++0x03
line.long 0x00 "USB_CTL0_ADDR,USB_CTL0_ADDR"
bitfld.long 0x00 26. "DisRxDetU3RxDet,DisRxDetU3RxDet of USB 3.0 SS Ports" "0,1"
bitfld.long 0x00 25. "StartRxDetU3RxDet,StartRxdetU3RxDet of USB 3.0 SS Ports" "0,1"
newline
bitfld.long 0x00 24. "utmi_iddig_sel,iddig source select signal" "0: utmi_iddig_sel_0,1: utmi_iddig_sel_1"
bitfld.long 0x00 22.--23. "hub_port_perm_attach,Indicates if the device attached to a downstream port is permanently attached or not" "0: Not permanently attached,1: hub_port_perm_attach_1,?..."
newline
bitfld.long 0x00 16.--21. "fladj_30mhz_reg,HS Jitter Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 14. "xhc_bme,Disable the bus mastering capability of the xHC" "0: Bus mastering capability is disabled,1: Bus mastering capability is enabled"
newline
bitfld.long 0x00 12. "host_port_power_control_present,This port defines the bit [3] of Capability Parameters (HCCPARAMS)" "0: Indicates that the port does not have port..,1: Indicates that the port has port power switches"
bitfld.long 0x00 8.--11. "bus_filter_bypass,Bus Filter Bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "host_u3_port_disable,USB 3.0 SS Port Disable control" "0: host_u3_port_disable_0,1: host_u3_port_disable_1"
bitfld.long 0x00 6. "host_u2_port_disable,USB 2.0 Port Disable control" "0: host_u2_port_disable_0,1: Port Disabled"
group.long 0x04++0x03
line.long 0x00 "USB_CTL1_ADDR,USB_CTL1_ADDR"
bitfld.long 0x00 17. "power_polarity,Power polarity" "0: power_polarity_0,1: power_polarity_1"
bitfld.long 0x00 16. "oc_polarity,Overcurrent polarity" "0: oc_polarity_0,1: oc_polarity_1"
rgroup.long 0x20++0x03
line.long 0x00 "USB_STS0_ADDR,USB_STS0_ADDR"
bitfld.long 0x00 16. "DisRxDetU3RxDet_ack,DisRxDetU3RxDet_ack of USB 3.0 SS Ports" "0,1"
bitfld.long 0x00 15. "IDDIG,This controller signal indicates whether the connected plug is a mini-A or mini-B plug" "0: Connected plug is a mini-A plug,1: Connected plug is a mini-B plug"
newline
bitfld.long 0x00 14. "pme_generation,PME# Generation" "0,1"
bitfld.long 0x00 13. "bc_chirp_on,When asserted indicates an imminent chirp signal" "0,1"
newline
bitfld.long 0x00 12. "host_system_err,Host System Error" "0,1"
hexmask.long.word 0x00 0.--11. 1. "host_current_belt,Current BELT Value"
group.long 0x40++0x03
line.long 0x00 "PHY_CTL0_ADDR,PHY_CTL0_ADDR"
bitfld.long 0x00 21.--23. "ssc_range,Spread Spectrum Clock Range" "0: ssc_range_0,1: ssc_range_1,2: ssc_range_2,?..."
hexmask.long.word 0x00 12.--20. 1. "ssc_ref_clk_sel,Spread Spectrum Reference Clock Shifting"
newline
bitfld.long 0x00 11. "ssc_en,Spread Spectrum Enable" "0,1"
bitfld.long 0x00 5.--10. "fsel,fsel" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,39: 100MHz ref clock,?,?,42: 24MHz ref clock,?..."
newline
bitfld.long 0x00 2. "ref_ssp_en,Reference Clock Enable for SS function" "0,1"
group.long 0x44++0x03
line.long 0x00 "PHY_CTL1_ADDR,PHY_CTL1_ADDR"
bitfld.long 0x00 20. "VDATDETENB0,Battery Charging Attach/Connect Detection Enable" "0,1"
bitfld.long 0x00 19. "VDATSRCENB0,Battery Charging Sourcing Select" "0,1"
newline
bitfld.long 0x00 18. "CHRGSEL0,Battery Charging Source Select" "0,1"
bitfld.long 0x00 17. "DCDENB0,Data Contact Detection Enable" "0,1"
newline
bitfld.long 0x00 16. "ACAENB0,Battery Charging Source Select" "0,1"
bitfld.long 0x00 15. "rtune_req,Resistor Tune Request" "0,1"
newline
bitfld.long 0x00 1. "COMMONONN,Common Block Power-Down Control" "0,1"
bitfld.long 0x00 0. "phy_reset,USB3.0 PHY Signal" "0,1"
group.long 0x48++0x03
line.long 0x00 "PHY_CTL2_ADDR,PHY_CTL2_ADDR"
bitfld.long 0x00 16. "rx0loslfpsen,RX LOS LFPS Filter Enable" "0,1"
bitfld.long 0x00 14. "utmi_idpullup,Analog ID Input Sample Enable" "0,1"
newline
bitfld.long 0x00 11. "VBUSVLDEXTSEL0,Selects the VBUSVLDEXTn input or the internal Session Valid comparator to indicate when the VBUSn signal on the USB cable is valid" "0,1"
bitfld.long 0x00 10. "VBUSVLDEXT0,External VBUS Valid Indicator" "0,1"
newline
bitfld.long 0x00 8. "TXENABLEN0,USB 1.1 Data Enable" "0,1"
bitfld.long 0x00 7. "FSXCVROWNER0,UTMI+/Serial Interface Select" "0,1"
newline
bitfld.long 0x00 6. "FSSE0EXT0,USB 1.1 Transmit Data" "0,1"
bitfld.long 0x00 5. "FSDATAEXT0,USB 1.1 SE0 Generation" "0,1"
group.long 0x4C++0x03
line.long 0x00 "PHY_CTL3_ADDR,PHY_CTL3_ADDR"
bitfld.long 0x00 29.--31. "tx_vboost_lvl,TX Voltage Boost Level" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "ios_bias,Loss-of-Signal Detector Threshold Level Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22.--25. "TXREFTUNE0,HS DC Voltage Level Adjustment" "0: TXREFTUNE0_0,1: TXREFTUNE0_1,2: TXREFTUNE0_2,3: TXREFTUNE0_3,4: TXREFTUNE0_4,5: TXREFTUNE0_5,6: TXREFTUNE0_6,7: TXREFTUNE0_7,8: TXREFTUNE0_8,9: TXREFTUNE0_9,10: TXREFTUNE0_10,11: TXREFTUNE0_11,12: TXREFTUNE0_12,13: TXREFTUNE0_13,14: TXREFTUNE0_14,15: TXREFTUNE0_15"
bitfld.long 0x00 20.--21. "TXRISETUNE0,HS Transmitter Rise/Fall Time Adjustment" "0: TXRISETUNE0_0,1: TXRISETUNE0_1,2: TXRISETUNE0_2,3: TXRISETUNE0_3"
newline
bitfld.long 0x00 18.--19. "TXRESTUNE0,USB Source Impedance Adjustment Some applications require additional devices to be added on the USB such as a series switch which can add significant series resistance" "0,1,2,3"
bitfld.long 0x00 17. "TXPREEMPULSETUNE0,HS Transmitter Pre-Emphasis Duration Control This signal controls the duration for which the HS pre-emphasis current is sourced onto DP or DM" "0,1"
newline
bitfld.long 0x00 15.--16. "TXPREEMPMPTUNE0,HS Transmitter Pre-Emphasis Current Control" "0: Disabled (default),1: 1x pre-emphasis current,2: 2x pre-emphasis current,3: 3x pre-emphasis current"
bitfld.long 0x00 13.--14. "TXSHXSTUNE0,Transmitter High-Speed Crossover Adjustment" "?,1: TXSHXSTUNE0_1,2: TXSHXSTUNE0_2,3: TXSHXSTUNE0_3"
newline
bitfld.long 0x00 9.--12. "TXFSLSTUNE0,FS/LS Source Impedance Adjustment" "0: TXFSLSTUNE0_0,1: TXFSLSTUNE0_1,?,3: TXFSLSTUNE0_3,?,?,?,7: TXFSLSTUNE0_7,?,?,?,?,?,?,?,15: TXFSLSTUNE0_15"
bitfld.long 0x00 6.--8. "SQRXTUNE0,Squelch Threshold Adjustment" "0: SQRXTUNE0_0,1: SQRXTUNE0_1,2: SQRXTUNE0_2,3: SQRXTUNE0_3,4: SQRXTUNE0_4,5: SQRXTUNE0_5,6: SQRXTUNE0_6,7: SQRXTUNE0_7"
newline
bitfld.long 0x00 3.--5. "TUNE0,VBUS Valid Threshold Adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "COMPIDISTUNE,Disconnect Threshold Adjustment" "0: COMPIDISTUNE_0,1: COMPIDISTUNE_1,2: COMPIDISTUNE_2,3: COMPIDISTUNE_3,4: COMPIDISTUNE_4,5: COMPIDISTUNE_5,6: COMPIDISTUNE_6,7: COMPIDISTUNE_7"
group.long 0x50++0x03
line.long 0x00 "PHY_CTL4_ADDR,PHY_CTL4_ADDR"
bitfld.long 0x00 21.--26. "pcs_tx_deemph_6db,TX De-Emphasis at 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15.--20. "pcs_tx_deemph_3b5db,TX De-Emphasis at 3.5 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 5.--14. 1. "pcs_rx_los_msk_val,Configurable Loss-of-Signal Mask Width"
group.long 0x54++0x03
line.long 0x00 "PHY_CTL5_ADDR,PHY_CTL5_ADDR"
hexmask.long.byte 0x00 0.--6. 1. "pcs_tx_swing_full,TX Amplitude (Full Swing Mode)"
group.long 0x58++0x03
line.long 0x00 "PHY_CTL6_ADDR,PHY_CTL6_ADDR"
bitfld.long 0x00 3. "lane0_ext_pclk_req,External PIPE Clock Enable Request" "0,1"
bitfld.long 0x00 2. "lane0_tx2rx_loopbk,Loopback" "0,1"
group.long 0x80++0x03
line.long 0x00 "PHY_STS0_ADDR,PHY_STS0_ADDR"
eventfld.long 0x00 31. "utmi_clk_vld,USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set" "0,1"
eventfld.long 0x00 30. "pipe_clk_vld,USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set" "0,1"
newline
rbitfld.long 0x00 6. "rtune_ack,Resistor Tune Acknowledge" "0,1"
rbitfld.long 0x00 4. "CHGDET0,Battery Charger Detection Output" "0,1"
tree.end
tree "USB2_GLUE"
base ad:0x382F0000
group.long 0x00++0x03
line.long 0x00 "USB_CTL0_ADDR,USB_CTL0_ADDR"
bitfld.long 0x00 26. "DisRxDetU3RxDet,DisRxDetU3RxDet of USB 3.0 SS Ports" "0,1"
bitfld.long 0x00 25. "StartRxDetU3RxDet,StartRxdetU3RxDet of USB 3.0 SS Ports" "0,1"
newline
bitfld.long 0x00 24. "utmi_iddig_sel,iddig source select signal" "0: utmi_iddig_sel_0,1: utmi_iddig_sel_1"
bitfld.long 0x00 22.--23. "hub_port_perm_attach,Indicates if the device attached to a downstream port is permanently attached or not" "0: Not permanently attached,1: hub_port_perm_attach_1,?..."
newline
bitfld.long 0x00 16.--21. "fladj_30mhz_reg,HS Jitter Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 14. "xhc_bme,Disable the bus mastering capability of the xHC" "0: Bus mastering capability is disabled,1: Bus mastering capability is enabled"
newline
bitfld.long 0x00 12. "host_port_power_control_present,This port defines the bit [3] of Capability Parameters (HCCPARAMS)" "0: Indicates that the port does not have port..,1: Indicates that the port has port power switches"
bitfld.long 0x00 8.--11. "bus_filter_bypass,Bus Filter Bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "host_u3_port_disable,USB 3.0 SS Port Disable control" "0: host_u3_port_disable_0,1: host_u3_port_disable_1"
bitfld.long 0x00 6. "host_u2_port_disable,USB 2.0 Port Disable control" "0: host_u2_port_disable_0,1: Port Disabled"
group.long 0x04++0x03
line.long 0x00 "USB_CTL1_ADDR,USB_CTL1_ADDR"
bitfld.long 0x00 17. "power_polarity,Power polarity" "0: power_polarity_0,1: power_polarity_1"
bitfld.long 0x00 16. "oc_polarity,Overcurrent polarity" "0: oc_polarity_0,1: oc_polarity_1"
rgroup.long 0x20++0x03
line.long 0x00 "USB_STS0_ADDR,USB_STS0_ADDR"
bitfld.long 0x00 16. "DisRxDetU3RxDet_ack,DisRxDetU3RxDet_ack of USB 3.0 SS Ports" "0,1"
bitfld.long 0x00 15. "IDDIG,This controller signal indicates whether the connected plug is a mini-A or mini-B plug" "0: Connected plug is a mini-A plug,1: Connected plug is a mini-B plug"
newline
bitfld.long 0x00 14. "pme_generation,PME# Generation" "0,1"
bitfld.long 0x00 13. "bc_chirp_on,When asserted indicates an imminent chirp signal" "0,1"
newline
bitfld.long 0x00 12. "host_system_err,Host System Error" "0,1"
hexmask.long.word 0x00 0.--11. 1. "host_current_belt,Current BELT Value"
group.long 0x40++0x03
line.long 0x00 "PHY_CTL0_ADDR,PHY_CTL0_ADDR"
bitfld.long 0x00 21.--23. "ssc_range,Spread Spectrum Clock Range" "0: ssc_range_0,1: ssc_range_1,2: ssc_range_2,?..."
hexmask.long.word 0x00 12.--20. 1. "ssc_ref_clk_sel,Spread Spectrum Reference Clock Shifting"
newline
bitfld.long 0x00 11. "ssc_en,Spread Spectrum Enable" "0,1"
bitfld.long 0x00 5.--10. "fsel,fsel" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,39: 100MHz ref clock,?,?,42: 24MHz ref clock,?..."
newline
bitfld.long 0x00 2. "ref_ssp_en,Reference Clock Enable for SS function" "0,1"
group.long 0x44++0x03
line.long 0x00 "PHY_CTL1_ADDR,PHY_CTL1_ADDR"
bitfld.long 0x00 20. "VDATDETENB0,Battery Charging Attach/Connect Detection Enable" "0,1"
bitfld.long 0x00 19. "VDATSRCENB0,Battery Charging Sourcing Select" "0,1"
newline
bitfld.long 0x00 18. "CHRGSEL0,Battery Charging Source Select" "0,1"
bitfld.long 0x00 17. "DCDENB0,Data Contact Detection Enable" "0,1"
newline
bitfld.long 0x00 16. "ACAENB0,Battery Charging Source Select" "0,1"
bitfld.long 0x00 15. "rtune_req,Resistor Tune Request" "0,1"
newline
bitfld.long 0x00 1. "COMMONONN,Common Block Power-Down Control" "0,1"
bitfld.long 0x00 0. "phy_reset,USB3.0 PHY Signal" "0,1"
group.long 0x48++0x03
line.long 0x00 "PHY_CTL2_ADDR,PHY_CTL2_ADDR"
bitfld.long 0x00 16. "rx0loslfpsen,RX LOS LFPS Filter Enable" "0,1"
bitfld.long 0x00 14. "utmi_idpullup,Analog ID Input Sample Enable" "0,1"
newline
bitfld.long 0x00 11. "VBUSVLDEXTSEL0,Selects the VBUSVLDEXTn input or the internal Session Valid comparator to indicate when the VBUSn signal on the USB cable is valid" "0,1"
bitfld.long 0x00 10. "VBUSVLDEXT0,External VBUS Valid Indicator" "0,1"
newline
bitfld.long 0x00 8. "TXENABLEN0,USB 1.1 Data Enable" "0,1"
bitfld.long 0x00 7. "FSXCVROWNER0,UTMI+/Serial Interface Select" "0,1"
newline
bitfld.long 0x00 6. "FSSE0EXT0,USB 1.1 Transmit Data" "0,1"
bitfld.long 0x00 5. "FSDATAEXT0,USB 1.1 SE0 Generation" "0,1"
group.long 0x4C++0x03
line.long 0x00 "PHY_CTL3_ADDR,PHY_CTL3_ADDR"
bitfld.long 0x00 29.--31. "tx_vboost_lvl,TX Voltage Boost Level" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "ios_bias,Loss-of-Signal Detector Threshold Level Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22.--25. "TXREFTUNE0,HS DC Voltage Level Adjustment" "0: TXREFTUNE0_0,1: TXREFTUNE0_1,2: TXREFTUNE0_2,3: TXREFTUNE0_3,4: TXREFTUNE0_4,5: TXREFTUNE0_5,6: TXREFTUNE0_6,7: TXREFTUNE0_7,8: TXREFTUNE0_8,9: TXREFTUNE0_9,10: TXREFTUNE0_10,11: TXREFTUNE0_11,12: TXREFTUNE0_12,13: TXREFTUNE0_13,14: TXREFTUNE0_14,15: TXREFTUNE0_15"
bitfld.long 0x00 20.--21. "TXRISETUNE0,HS Transmitter Rise/Fall Time Adjustment" "0: TXRISETUNE0_0,1: TXRISETUNE0_1,2: TXRISETUNE0_2,3: TXRISETUNE0_3"
newline
bitfld.long 0x00 18.--19. "TXRESTUNE0,USB Source Impedance Adjustment Some applications require additional devices to be added on the USB such as a series switch which can add significant series resistance" "0,1,2,3"
bitfld.long 0x00 17. "TXPREEMPULSETUNE0,HS Transmitter Pre-Emphasis Duration Control This signal controls the duration for which the HS pre-emphasis current is sourced onto DP or DM" "0,1"
newline
bitfld.long 0x00 15.--16. "TXPREEMPMPTUNE0,HS Transmitter Pre-Emphasis Current Control" "0: Disabled (default),1: 1x pre-emphasis current,2: 2x pre-emphasis current,3: 3x pre-emphasis current"
bitfld.long 0x00 13.--14. "TXSHXSTUNE0,Transmitter High-Speed Crossover Adjustment" "?,1: TXSHXSTUNE0_1,2: TXSHXSTUNE0_2,3: TXSHXSTUNE0_3"
newline
bitfld.long 0x00 9.--12. "TXFSLSTUNE0,FS/LS Source Impedance Adjustment" "0: TXFSLSTUNE0_0,1: TXFSLSTUNE0_1,?,3: TXFSLSTUNE0_3,?,?,?,7: TXFSLSTUNE0_7,?,?,?,?,?,?,?,15: TXFSLSTUNE0_15"
bitfld.long 0x00 6.--8. "SQRXTUNE0,Squelch Threshold Adjustment" "0: SQRXTUNE0_0,1: SQRXTUNE0_1,2: SQRXTUNE0_2,3: SQRXTUNE0_3,4: SQRXTUNE0_4,5: SQRXTUNE0_5,6: SQRXTUNE0_6,7: SQRXTUNE0_7"
newline
bitfld.long 0x00 3.--5. "TUNE0,VBUS Valid Threshold Adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "COMPIDISTUNE,Disconnect Threshold Adjustment" "0: COMPIDISTUNE_0,1: COMPIDISTUNE_1,2: COMPIDISTUNE_2,3: COMPIDISTUNE_3,4: COMPIDISTUNE_4,5: COMPIDISTUNE_5,6: COMPIDISTUNE_6,7: COMPIDISTUNE_7"
group.long 0x50++0x03
line.long 0x00 "PHY_CTL4_ADDR,PHY_CTL4_ADDR"
bitfld.long 0x00 21.--26. "pcs_tx_deemph_6db,TX De-Emphasis at 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15.--20. "pcs_tx_deemph_3b5db,TX De-Emphasis at 3.5 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 5.--14. 1. "pcs_rx_los_msk_val,Configurable Loss-of-Signal Mask Width"
group.long 0x54++0x03
line.long 0x00 "PHY_CTL5_ADDR,PHY_CTL5_ADDR"
hexmask.long.byte 0x00 0.--6. 1. "pcs_tx_swing_full,TX Amplitude (Full Swing Mode)"
group.long 0x58++0x03
line.long 0x00 "PHY_CTL6_ADDR,PHY_CTL6_ADDR"
bitfld.long 0x00 3. "lane0_ext_pclk_req,External PIPE Clock Enable Request" "0,1"
bitfld.long 0x00 2. "lane0_tx2rx_loopbk,Loopback" "0,1"
group.long 0x80++0x03
line.long 0x00 "PHY_STS0_ADDR,PHY_STS0_ADDR"
eventfld.long 0x00 31. "utmi_clk_vld,USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set" "0,1"
eventfld.long 0x00 30. "pipe_clk_vld,USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set" "0,1"
newline
rbitfld.long 0x00 6. "rtune_ack,Resistor Tune Acknowledge" "0,1"
rbitfld.long 0x00 4. "CHGDET0,Battery Charger Detection Output" "0,1"
tree.end
tree.end
tree "GPC"
base ad:0x303A0000
group.long 0x00++0x03
line.long 0x00 "LPCR_A53_BSC,Basic Low power control register of A53 platform"
bitfld.long 0x00 31. "MASK_DSM_TRIGGER,DSM Trigger Mask" "0: DSM trigger of A53 platform will not be masked,1: DSM trigger of A53 platform will be masked"
newline
bitfld.long 0x00 30. "IRQ_SRC_A53_WUP,LPCR_A53_BSC[IRQ_SRC_C0] LPCR_A53_BSC[IRQ_SRC_C1] LPCR_A53_BSC[IRQ_SRC_C2] LPCR_A53_BSC[IRQ_SRC_C3] and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power" "0: LPM wakeup source be OR result of..,1: LPM wakeup source from external INT[127:0].."
newline
bitfld.long 0x00 29. "IRQ_SRC_C1,LPCR_A53_BSC[IRQ_SRC_C0] LPCR_A53_BSC[IRQ_SRC_C1] LPCR_A53_BSC[IRQ_SRC_C2] LPCR_A53_BSC[IRQ_SRC_C3] and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power" "0: core1 wakeup source from external INT[127:0]..,1: core1 wakeup source from GIC(nFIQ[1]/nIRQ[1].."
newline
bitfld.long 0x00 28. "IRQ_SRC_C0,LPCR_A53_BSC[IRQ_SRC_C0] LPCR_A53_BSC[IRQ_SRC_C1] LPCR_A53_BSC[IRQ_SRC_C2] LPCR_A53_BSC[IRQ_SRC_C3] and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power" "0: core0 wakeup source from external INT[127:0]..,1: core0 wakeup source from GIC(nFIQ[0]/nIRQ[0].."
newline
bitfld.long 0x00 26. "MASK_L2CC_WFI,L2 cache controller Wait For Interrupt Mask Register" "0: WFI for L2 cache controller is not masked,1: WFI for L2 cache controller is masked"
newline
bitfld.long 0x00 24. "MASK_SCU_WFI,SCU Wait For Interrupt Mask Register" "0: WFI for SCU is not masked,1: WFI for SCU is masked"
newline
bitfld.long 0x00 23. "IRQ_SRC_C3,LPCR_A53_BSC[IRQ_SRC_C0] LPCR_A53_BSC[IRQ_SRC_C1] LPCR_A53_BSC[IRQ_SRC_C2] LPCR_A53_BSC[IRQ_SRC_C3] and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power" "0: core3 wakeup source from external INT[127:0]..,1: core3 wakeup source from external.."
newline
bitfld.long 0x00 22. "IRQ_SRC_C2,LPCR_A53_BSC[IRQ_SRC_C0] LPCR_A53_BSC[IRQ_SRC_C1] LPCR_A53_BSC[IRQ_SRC_C2] LPCR_A53_BSC[IRQ_SRC_C3] and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide the wake up source for A53 LPM and core0/core1/core2/core3 power" "0: core2 wakeup source from external INT[127:0]..,1: core2 wakeup source from external.."
newline
bitfld.long 0x00 19. "MASK_CORE3_WFI,CORE3 Wait For Interrupt Mask" "0: WFI for CORE3 is not masked,1: WFI for CORE3 is masked"
newline
bitfld.long 0x00 18. "MASK_CORE2_WFI,CORE2 Wait For Interrupt Mask" "0: WFI for CORE2 is not masked,1: WFI for CORE2 is masked"
newline
bitfld.long 0x00 17. "MASK_CORE1_WFI,CORE1 Wait For Interrupt Mask" "0: WFI for CORE1 is not masked,1: WFI for CORE1 is masked"
newline
bitfld.long 0x00 16. "MASK_CORE0_WFI,CORE0 Wait For Interrupt Mask" "0: WFI for CORE0 is not masked,1: WFI for CORE0 is masked"
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bitfld.long 0x00 14. "CPU_CLK_ON_LPM,Define if A53 clocks will be disabled on wait/stop mode" "0: A53 clock disabled on wait/stop mode,1: A53 clock enabled on wait/stop mode"
newline
bitfld.long 0x00 8. "MST2_LPM_HSK_MASK,MASTER2 LPM handshake mask" "0: enable MASTER2 LPM handshake wait ACK from..,1: disable MASTER2 LPM handshake mask ACK from.."
newline
bitfld.long 0x00 7. "MST1_LPM_HSK_MASK,MASTER1 LPM handshake mask" "0: enable MASTER1 LPM handshake wait ACK from..,1: disable MASTER1 LPM handshake mask ACK from.."
newline
bitfld.long 0x00 6. "MST0_LPM_HSK_MASK,MASTER0 LPM handshake mask" "0: enable MASTER0 LPM handshake wait ACK from..,1: disable MASTER0 LPM handshake mask ACK from.."
newline
bitfld.long 0x00 2.--3. "LPM1,CORE1 Setting the low power mode that system will enter on next assertion of dsm_request signal" "0: Remain in RUN mode,1: Transfer to WAIT mode,2: Transfer to STOP mode,?..."
newline
bitfld.long 0x00 0.--1. "LPM0,CORE0 Setting the low power mode that system will enter on next assertion of dsm_request signal" "0: Remain in RUN mode,1: Transfer to WAIT mode,2: Transfer to STOP mode,?..."
group.long 0x04++0x03
line.long 0x00 "LPCR_A53_AD,Advanced Low power control register of A53 platform"
bitfld.long 0x00 31. "L2PGE,no description available" "0: L2 cache RAM will power down with SCU power..,1: L2 cache RAM will not power down with SCU.."
newline
bitfld.long 0x00 27. "EN_C3_PUP,no description available" "0: CORE3 will not power up with lower power mode..,1: CORE3 will power up with low power mode.."
newline
bitfld.long 0x00 26. "EN_C3_IRQ_PUP,no description available" "0: CORE3 will not power up with IRQ request,1: CORE3 will power up with IRQ request"
newline
bitfld.long 0x00 25. "EN_C2_PUP,no description available" "0: CORE2 will not power up with lower power mode..,1: CORE2 will power up with low power mode.."
newline
bitfld.long 0x00 24. "EN_C2_IRQ_PUP,no description available" "0: CORE2 will not power up with IRQ request,1: CORE2 will power up with IRQ request"
newline
bitfld.long 0x00 19. "EN_C3_PDN,no description available" "0: CORE3 will not be power down with low power..,1: CORE3 will be power down with low power mode.."
newline
bitfld.long 0x00 18. "EN_C3_WFI_PDN,no description available" "0: CORE3 will not be power down with WFI request,1: CORE3 will be power down with WFI request"
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bitfld.long 0x00 17. "EN_C2_PDN,no description available" "0: CORE2 will not be power down with low power..,1: CORE2 will be power down with low power mode.."
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bitfld.long 0x00 16. "EN_C2_WFI_PDN,no description available" "0: CORE2 will not be power down with WFI request,1: CORE2 will be power down with WFI request"
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bitfld.long 0x00 11. "EN_C1_PUP,no description available" "0: CORE1 will not power up with low power mode..,1: CORE1 will power up with low power mode request"
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bitfld.long 0x00 10. "EN_C1_IRQ_PUP,no description available" "0: CORE1 will not power up with IRQ request,1: CORE1 will power up with IRQ request"
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bitfld.long 0x00 9. "EN_C0_PUP,(only used wake up from CPU01_OFF mode)" "0: CORE0 will not power up with low power mode..,1: CORE0 will power up with low power mode request"
newline
bitfld.long 0x00 8. "EN_C0_IRQ_PUP,no description available" "0: CORE0 will not power up with IRQ request,1: CORE0 will power up with IRQ request"
newline
bitfld.long 0x00 5. "EN_L2_WFI_PDN,Before reset L2 WFI is 1 and make GPC generate an error DSM request" "0: SCU and L2 will not be power down with WFI..,1: SCU and L2 will be power down with WFI.."
newline
bitfld.long 0x00 4. "EN_PLAT_PDN,no description available" "0: SCU and L2 cache RAM will not be power down..,1: SCU and L2 cache RAM will be power down with.."
newline
bitfld.long 0x00 3. "EN_C1_PDN,no description available" "0: CORE1 will not be power down with low power..,1: CORE1 will be power down with low power mode.."
newline
bitfld.long 0x00 2. "EN_C1_WFI_PDN,no description available" "0: CORE1 will not be power down with WFI request,1: CORE1 will be power down with WFI request"
newline
bitfld.long 0x00 1. "EN_C0_PDN,no description available" "0: CORE0 will not be power down with low power..,1: CORE0 will be power down with low power mode.."
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bitfld.long 0x00 0. "EN_C0_WFI_PDN,no description available" "0: CORE0 will not be power down with WFI request,1: CORE0 will be power down with WFI request"
group.long 0x08++0x03
line.long 0x00 "LPCR_M7,Low power control register of CPU1"
bitfld.long 0x00 31. "MASK_DSM_TRIGGER,M7 WFI Mask" "0: DSM trigger of M7 platform will not be masked,1: DSM trigger of M7 platform will be masked"
newline
bitfld.long 0x00 16. "MASK_M7_WFI,M7 WFI Mask" "0: WFI for M7 is not masked,1: WFI for M7 is masked"
newline
bitfld.long 0x00 14. "CPU_CLK_ON_LPM,Define if M7 clocks will be disabled on wait/stop mode" "0: M7 clock disabled on wait/stop mode,1: M7 clock enabled on wait/stop mode"
newline
bitfld.long 0x00 3. "EN_M7_PUP,Enable M7 virtual PGC power up with LPM enter" "0,1"
newline
bitfld.long 0x00 2. "EN_M7_PDN,Enable M7 virtual PGC power down with LPM enter" "0,1"
newline
bitfld.long 0x00 0.--1. "LPM0,Setting the low power mode that system will enter on next assertion of dsm_request signal" "0: Remain in RUN mode,1: Transfer to WAIT mode,2: Transfer to STOP mode,?..."
group.long 0x14++0x03
line.long 0x00 "SLPCR,System low power control register"
bitfld.long 0x00 31. "EN_DSM,DSM enable" "0: DSM disabled,1: DSM enabled"
newline
bitfld.long 0x00 30. "RBC_EN,Enable for REG_BYPASS_COUNTER" "0: REG_BYPASS_COUNTER disabled,1: REG_BYPASS_COUNTER enabled"
newline
bitfld.long 0x00 24.--29. "REG_BYPASS_COUNT,Counter for REG_BYPASS signal assertion after standby voltage request by PMIC_STBY_REQ" "0: REG_BYPASS_COUNT_0,1: 1 CKIL clock period delay,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: 63 CKIL clock period delay"
newline
bitfld.long 0x00 23. "DISABLE_A53_IS_DSM,no description available" "0: Enable A53 isolation signal in DSM,1: Disable A53 isolation signal in DSM"
newline
bitfld.long 0x00 19. "EN_M7_FASTWUP_STOP_MODE,Enable M7 fast wake up stop mode relevant PLLs will not be closed in this mode" "0,1"
newline
bitfld.long 0x00 18. "EN_M7_FASTWUP_WAIT_MODE,Enable M7 fast wake up wait mode relevant PLLs will not be closed in this mode" "0,1"
newline
bitfld.long 0x00 17. "EN_A53_FASTWUP_STOP_MODE,Enable A53 fast wake up stop mode relevant PLLs will not be closed in this mode" "0,1"
newline
bitfld.long 0x00 16. "EN_A53_FASTWUP_WAIT_MODE,Enable A53 fast wake up wait mode relevant PLLs will not be closed in this mode" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "OSCCNT,Oscillator ready counter value"
newline
bitfld.long 0x00 7. "COSC_EN,On-chip oscillator enable bit - this bit value is reflected on the output cosc_en" "0: Disable on-chip oscillator,1: Enable on-chip oscillator"
newline
bitfld.long 0x00 6. "COSC_PWRDOWN,In run mode software can manually control powering down of on chip oscillator i" "0: On-chip oscillator will not be powered down i.e,1: On-chip oscillator will be powered down i.e"
newline
bitfld.long 0x00 3.--5. "STBY_COUNT,Standby counter definition" "0: GPC will wait 4 ckil clock cycles,1: GPC will wait 8 ckil clock cycles,2: GPC will wait 16 ckil clock cycles,3: GPC will wait 32 ckil clock cycles,4: GPC will wait 64 ckil clock cycles,5: GPC will wait 128 ckil clock cycles,6: GPC will wait 256 ckil clock cycles,7: GPC will wait 512 ckil clock cycles"
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bitfld.long 0x00 2. "VSTBY,Voltage standby request bit" "0: Voltage will not be changed to standby..,1: Voltage will be changed to standby voltage.."
newline
bitfld.long 0x00 1. "SBYOS,Standby clock oscillator bit" "0: On chip oscillator will not be powered down..,1: On chip oscillator will be powered down after.."
newline
bitfld.long 0x00 0. "BYPASS_PMIC_READY,By asserting this bit GPC will bypass waiting for PMIC_READY signal when coming out of DSM" "0: Don't bypass the PMIC_READY signal - GPC will..,1: Bypass the PMIC_READY signal - GPC will not.."
group.long 0x18++0x03
line.long 0x00 "MST_CPU_MAPPING,MASTER LPM Handshake"
bitfld.long 0x00 2. "MST2_CPU_MAPPING,MASTER2 CPU Mapping" "0: GPC will not send out power off requirement,1: GPC will send out power off requirement"
newline
bitfld.long 0x00 1. "MST1_CPU_MAPPING,MASTER1 CPU Mapping" "0: GPC will not send out power off requirement,1: GPC will send out power off requirement"
newline
bitfld.long 0x00 0. "MST0_CPU_MAPPING,MASTER0 CPU Mapping" "0: GPC will not send out power off requirement,1: GPC will send out power off requirement"
group.long 0x20++0x03
line.long 0x00 "MLPCR,Memory low power control register"
hexmask.long.byte 0x00 24.--31. 1. "MEMLP_RET_PGEN,Delay counter for retnx and pgen"
newline
hexmask.long.byte 0x00 16.--23. 1. "MEM_EXT_CNT,Delay counter to start existing from memory low power"
newline
hexmask.long.byte 0x00 8.--15. 1. "MEMLP_ENT_CNT,Delay counter to make sure all clock off after pll_dis_req is issued by smc"
newline
bitfld.long 0x00 2. "ROMLP_PDN_DIS,ROM shut down control" "0: Enable ROM shut down control(should also..,1: Disable ROM shut down control"
newline
bitfld.long 0x00 1. "MEMLP_RET_SEL,Retention select" "0: retention mode 2,1: retention mode 1"
newline
bitfld.long 0x00 0. "MEMLP_CTL_DIS,RAM low-power control" "0: Enable RAM low power control,1: Disable RAM low power control"
group.long 0x24++0x03
line.long 0x00 "PGC_ACK_SEL_A53,PGC acknowledge signal selection of A53 platform"
bitfld.long 0x00 31. "A53_PGC_PUP_ACK,Select power up acknowledge signal of A53 (dummy) PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 30. "A53_PGC_PDN_ACK,Select power down acknowledge signal of A53 (dummy) PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 13. "NOC_PGC_PUP_ACK,Select power down acknowledge signal of NOC PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 12. "NOC_PGC_PDN_ACK,Select power down acknowledge signal of NOC PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 9. "A53_PLAT_PGC_PUP_ACK,Select power down acknowledge signal of A53 PLATFORM PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 8. "A53_PLAT_PGC_PDN_ACK,Select power down acknowledge signal of A53 PLATFORM PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 7. "A53_C3_PGC_PUP_ACK,Select power down acknowledge signal of A53 CORE3 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 6. "A53_C3_PGC_PDN_ACK,Select power down acknowledge signal of A53 CORE3 PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 5. "A53_C2_PGC_PUP_ACK,Select power down acknowledge signal of A53 CORE2 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 4. "A53_C2_PGC_PDN_ACK,Select power down acknowledge signal of A53 CORE2 PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 3. "A53_C1_PGC_PUP_ACK,Select power down acknowledge signal of A53 CORE1 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 2. "A53_C1_PGC_PDN_ACK,Select power down acknowledge signal of A53 CORE1 PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 1. "A53_C0_PGC_PUP_ACK,Select power down acknowledge signal of A53 CORE0 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 0. "A53_C0_PGC_PDN_ACK,Select power down acknowledge signal of A53 CORE0 PGC as the power down acknowledge for A53 LPM" "0,1"
group.long 0x28++0x03
line.long 0x00 "PGC_ACK_SEL_M7,PGC acknowledge signal selection of M7 platform"
bitfld.long 0x00 31. "M7_DUMMY_PGC_PUP_ACK,Select power up acknowledge signal of M7 (dummy) PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 30. "M7_DUMMY_PGC_PDN_ACK,Select power down acknowledge signal of M7 (dummy) PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 13. "NOC_PGC_PUP_ACK,Select power down acknowledge signal of NOC PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 12. "NOC_PGC_PDN_ACK,Select power down acknowledge signal of NOC PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 1. "M7_VIRTUAL_PGC_PUP_ACK,Select power up acknowledge signal of M7 virtual PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 0. "M7_VIRTUAL_PGC_PDN_ACK,Select power down acknowledge signal of M7 virtual PGC as the power down acknowledge for M7 LPM" "0,1"
group.long 0x2C++0x03
line.long 0x00 "MISC,GPC Miscellaneous register"
bitfld.long 0x00 31. "MIPI_LDO_EN_CTRL,MIPI LDO enable control" "0,1"
newline
bitfld.long 0x00 25. "M7_BYPASS_PUP_MASK,no description available" "0,1"
newline
bitfld.long 0x00 24. "A53_BYPASS_PUP_MASK,no description available" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_REQ_MASK,M7 power-down mask" "0: M7 power down request to virtual M7 PGC will..,1: M7 power down request to virtual M7 PGC will.."
newline
bitfld.long 0x00 5. "GPC_IRQ_MASK,GPC interrupt/event masking" "0: GPC_IRQ_MASK_0,1: Interrupt / event is masked"
newline
bitfld.long 0x00 1. "A53_SLEEP_HOLD_REQ_B,A53 sleep hold" "0: Hold A53 platform in sleep mode,1: Don't hold A53 platform in sleep mode"
newline
bitfld.long 0x00 0. "M7_SLEEP_HOLD_REQ_B,M7 sleep hold" "0: Hold M7 platform in sleep mode,1: Don't hold M7 platform in sleep mode"
group.long 0x30++0x03
line.long 0x00 "IMR1_CORE0_A53,IRQ masking register 1 of A53 core0"
hexmask.long 0x00 0.--31. 1. "IMR1_CORE0_A53,A53 core0 IRQ[31:0] masking bits"
group.long 0x34++0x03
line.long 0x00 "IMR2_CORE0_A53,IRQ masking register 2 of A53 core0"
hexmask.long 0x00 0.--31. 1. "IMR2_CORE0_A53,A53 core0 IRQ[63:32] masking bits"
group.long 0x38++0x03
line.long 0x00 "IMR3_CORE0_A53,IRQ masking register 3 of A53 core0"
hexmask.long 0x00 0.--31. 1. "IMR3_CORE0_A53,A53 core0 IRQ[95:64] masking bits"
group.long 0x3C++0x03
line.long 0x00 "IMR4_CORE0_A53,IRQ masking register 4 of A53 core0"
hexmask.long 0x00 0.--31. 1. "IMR4_CORE0_A53,A53 core0 IRQ[127:96] masking bits"
group.long 0x40++0x03
line.long 0x00 "IMR5_CORE0_A53,IRQ masking register 5 of A53 core0"
hexmask.long 0x00 0.--31. 1. "IMR5_CORE0_A53,A53 core0 IRQ[159:128] masking bits"
group.long 0x44++0x03
line.long 0x00 "IMR1_CORE1_A53,IRQ masking register 1 of A53 core1"
hexmask.long 0x00 0.--31. 1. "IMR1_CORE1_A53,A53 core1 IRQ[31:0] masking bits"
group.long 0x48++0x03
line.long 0x00 "IMR2_CORE1_A53,IRQ masking register 2 of A53 core1"
hexmask.long 0x00 0.--31. 1. "IMR2_CORE1_A53,A53 core1 IRQ[63:32] masking bits"
group.long 0x4C++0x03
line.long 0x00 "IMR3_CORE1_A53,IRQ masking register 3 of A53 core1"
hexmask.long 0x00 0.--31. 1. "IMR3_CORE1_A53,A53 core1 IRQ[95:64] masking bits"
group.long 0x50++0x03
line.long 0x00 "IMR4_CORE1_A53,IRQ masking register 4 of A53 core1"
hexmask.long 0x00 0.--31. 1. "IMR4_CORE1_A53,A53 core1 IRQ[127:96] masking bits"
group.long 0x54++0x03
line.long 0x00 "IMR5_CORE1_A53,IRQ masking register 5 of A53 core1"
hexmask.long 0x00 0.--31. 1. "IMR5_CORE1_A53,A53 core1 IRQ[159:128] masking bits"
group.long 0x58++0x03
line.long 0x00 "IMR1_M7,IRQ masking register 1 of M7"
hexmask.long 0x00 0.--31. 1. "IMR1_M7,M7 IRQ[31:0] masking bits"
group.long 0x5C++0x03
line.long 0x00 "IMR2_M7,IRQ masking register 2 of M7"
hexmask.long 0x00 0.--31. 1. "IMR2_M7,M7 IRQ[63:32] masking bits"
group.long 0x60++0x03
line.long 0x00 "IMR3_M7,IRQ masking register 3 of M7"
hexmask.long 0x00 0.--31. 1. "IMR3_M7,M7 IRQ[95:64] masking bits"
group.long 0x64++0x03
line.long 0x00 "IMR4_M7,IRQ masking register 4 of M7"
hexmask.long 0x00 0.--31. 1. "IMR4_M7,M7 IRQ[127:96] masking bits"
group.long 0x68++0x03
line.long 0x00 "IMR5_M7,IRQ masking register 5 of M7"
hexmask.long 0x00 0.--31. 1. "IMR5_M7,M7 IRQ[159:128] masking bits"
rgroup.long 0x80++0x03
line.long 0x00 "ISR1_A53,IRQ status register 1 of A53"
hexmask.long 0x00 0.--31. 1. "ISR1_A53,A53 IRQ[31:0] status"
rgroup.long 0x84++0x03
line.long 0x00 "ISR2_A53,IRQ status register 2 of A53"
hexmask.long 0x00 0.--31. 1. "ISR2_A53,A53 IRQ[63:32] status"
rgroup.long 0x88++0x03
line.long 0x00 "ISR3_A53,IRQ status register 3 of A53"
hexmask.long 0x00 0.--31. 1. "ISR3_A53,A53 IRQ[95:64] status"
rgroup.long 0x8C++0x03
line.long 0x00 "ISR4_A53,IRQ status register 4 of A53"
hexmask.long 0x00 0.--31. 1. "ISR4_A53,A53 IRQ[127:96] status"
rgroup.long 0x90++0x03
line.long 0x00 "ISR5_A53,IRQ status register 5 of A53"
hexmask.long 0x00 0.--31. 1. "ISR5_A53,A53 IRQ[159:128] status"
rgroup.long 0x94++0x03
line.long 0x00 "ISR1_M7,IRQ status register 1 of M7"
hexmask.long 0x00 0.--31. 1. "ISR1_M7,M7 IRQ[31:0] status"
rgroup.long 0x98++0x03
line.long 0x00 "ISR2_M7,IRQ status register 2 of M7"
hexmask.long 0x00 0.--31. 1. "ISR2_M7,M7 IRQ[63:32] status"
rgroup.long 0x9C++0x03
line.long 0x00 "ISR3_M7,IRQ status register 3 of M7"
hexmask.long 0x00 0.--31. 1. "ISR3_M7,M7 IRQ[95:64] status"
rgroup.long 0xA0++0x03
line.long 0x00 "ISR4_M7,IRQ status register 4 of M7"
hexmask.long 0x00 0.--31. 1. "ISR4_M7,M7 IRQ[127:96] status"
rgroup.long 0xA4++0x03
line.long 0x00 "ISR5_M7,IRQ status register 5 of M7"
hexmask.long 0x00 0.--31. 1. "ISR5_M7,M7 IRQ[159:128] status"
group.long 0xD0++0x03
line.long 0x00 "CPU_PGC_SW_PUP_REQ,CPU PGC software power up trigger"
bitfld.long 0x00 4. "SCU_A53_SW_PUP_REQ,Software power up trigger for SCU A53 PGC" "0,1"
newline
bitfld.long 0x00 3. "CORE3_A53_SW_PUP_REQ,Software power up trigger for Core3 A53 PGC" "0,1"
newline
bitfld.long 0x00 2. "CORE2_A53_SW_PUP_REQ,Software power up trigger for Core2 A53" "0,1"
newline
bitfld.long 0x00 1. "CORE1_A53_SW_PUP_REQ,Software power up trigger for Core1 A53 PGC" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_SW_PUP_REQ,Software power up trigger for Core0 A53 PGC" "0,1"
group.long 0xD4++0x03
line.long 0x00 "MIX_PGC_SW_PUP_REQ,MIX PGC software power up trigger"
bitfld.long 0x00 1. "NOC_SW_PUP_REQ,Software power up trigger for NOC PGC" "0,1"
newline
bitfld.long 0x00 0. "MF_SW_PUP_REQ,Software power up trigger for MIX PGC" "0,1"
group.long 0xD8++0x03
line.long 0x00 "PU_PGC_SW_PUP_REQ,PU PGC software up trigger"
bitfld.long 0x00 19. "DDRMIX_SW_PUP_REQ,Software power up trigger for DDRMIX" "0,1"
newline
bitfld.long 0x00 18. "MEDIA_ISP_DWP_SW_PUP_REQ,Software power up trigger for MEDIA_ISP_DWP" "0,1"
newline
bitfld.long 0x00 17. "HSIOMIX_SW_PUP_REQ,Software power up trigger for HSIOMIX" "0,1"
newline
bitfld.long 0x00 16. "MIPI_PHY2_SW_PUP_REQ,Software power up trigger for MIPI_PHY2" "0,1"
newline
bitfld.long 0x00 15. "HDMI_PHY_SW_PUP_REQ,Software power up trigger for HDMI_PHY" "0,1"
newline
bitfld.long 0x00 14. "HDMIMIX_SW_PUP_REQ,Software power up trigger for HDMIMIX" "0,1"
newline
bitfld.long 0x00 13. "VPU_VC8K_SW_PUP_REQ,Software power up trigger for VPU_VC8K" "0,1"
newline
bitfld.long 0x00 12. "VPU_G2_SW_PUP_REQ,Software power up trigger for VPU_G2" "0,1"
newline
bitfld.long 0x00 11. "VPU_G1_SW_PUP_REQ,Software power up trigger for VPU_G1" "0,1"
newline
bitfld.long 0x00 10. "MEDIMIX_SW_PUP_REQ,Software power up trigger for MEDIMIX" "0,1"
newline
bitfld.long 0x00 9. "GPU_3D_SW_PUP_REQ,Software power up trigger for GPU_3D" "0,1"
newline
bitfld.long 0x00 8. "VPUMIX_SW_PUP_REQ,Software power up trigger for VPUMIX" "0,1"
newline
bitfld.long 0x00 7. "GPU_SHARE_LOGIC_SW_PUP_REQ,Software power up trigger for GPU_SHARE_LOGIC" "0,1"
newline
bitfld.long 0x00 6. "GPU_2D_SW_PUP_REQ,Software power up trigger for GPU_2D" "0,1"
newline
bitfld.long 0x00 5. "AUDIOMIX_SW_PUP_REQ,Software power up trigger for AUDIOMIX" "0,1"
newline
bitfld.long 0x00 4. "MLMIX_PHY_SW_PUP_REQ,Software power up trigger for MLMIX" "0,1"
newline
bitfld.long 0x00 3. "USB2_PHY_SW_PUP_REQ,Software power up trigger for USB2_PHY" "0,1"
newline
bitfld.long 0x00 2. "USB1_PHY_SW_PUP_REQ,Software power up trigger for USB1_PHY" "0,1"
newline
bitfld.long 0x00 1. "PCIE_PHY_SW_PUP_REQ,Software power up trigger for PCIE_PHY" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_SW_PUP_REQ,Software power up trigger for MIPI_PHY1" "0,1"
group.long 0xDC++0x03
line.long 0x00 "CPU_PGC_SW_PDN_REQ,CPU PGC software down trigger"
bitfld.long 0x00 4. "SCU_A53_SW_PUP_REQ,Software power up trigger for SCU A53 PGC" "0,1"
newline
bitfld.long 0x00 3. "CORE3_A53_SW_PUP_REQ,Software power up trigger for Core3 A53 PGC" "0,1"
newline
bitfld.long 0x00 2. "CORE2_A53_SW_PDN_REQ,Software power down trigger for Core2 A53 PGC" "0,1"
newline
bitfld.long 0x00 1. "CORE1_A53_SW_PDN_REQ,Software power down trigger for Core1 A53 PGC" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_SW_PDN_REQ,Software power down trigger for Core0 A53 PGC" "0,1"
group.long 0xE0++0x03
line.long 0x00 "MIX_PGC_SW_PDN_REQ,MIX PGC software power down trigger"
bitfld.long 0x00 1. "NOC_SW_PDN_REQ,Software power down trigger for NOC PGC" "0,1"
newline
bitfld.long 0x00 0. "MF_SW_PDN_REQ,Software power down trigger for MIX PGC" "0,1"
group.long 0xE4++0x03
line.long 0x00 "PU_PGC_SW_PDN_REQ,PU PGC software down trigger"
bitfld.long 0x00 19. "DDRMIX_SW_PDN_REQ,Software power down trigger for DDRMIX" "0,1"
newline
bitfld.long 0x00 18. "MEDIA_ISP_DWP_SW_PDN_REQ,Software power down trigger for MEDIA_ISP_DWP" "0,1"
newline
bitfld.long 0x00 17. "HSIOMIX_SW_PDN_REQ,Software power down trigger for HSIOMIX" "0,1"
newline
bitfld.long 0x00 16. "MIPI_PHY2_SW_PDN_REQ,Software power down trigger for MIPI_PHY2" "0,1"
newline
bitfld.long 0x00 15. "HDMI_PHY_SW_PDN_REQ,Software power down trigger for HDMI_PHY" "0,1"
newline
bitfld.long 0x00 14. "HDMIMIX_SW_PDN_REQ,Software power down trigger for HDMIMIX" "0,1"
newline
bitfld.long 0x00 13. "VPU_VC8K_SW_PDN_REQ,Software power down trigger for VPU_VC8K" "0,1"
newline
bitfld.long 0x00 12. "_SW_PDN_REQ,Software power down trigger for VPU_G2" "0,1"
newline
bitfld.long 0x00 11. "VPU_G1_SW_PDN_REQ,Software power down trigger for VPU_G1" "0,1"
newline
bitfld.long 0x00 10. "MEDIMIX_SW_PDN_REQ,Software power down trigger for MEDI MIX" "0,1"
newline
bitfld.long 0x00 9. "GPU_3D_SW_PDN_REQ,Software power down trigger for GPU_3D" "0,1"
newline
bitfld.long 0x00 8. "VPUMIX_SHARE_LOGIC_SW_PDN_REQ,Software power down trigger for VPUMIX _SHARE_LOGIC" "0,1"
newline
bitfld.long 0x00 7. "GPU_SHARE_LOGIC_SW_PDN_REQ,Software power down trigger for GPU_SHARE_LOGIC" "0,1"
newline
bitfld.long 0x00 6. "GPU_2D_SW_PDN_REQ,Software power down trigger for GPU_2D" "0,1"
newline
bitfld.long 0x00 5. "AUDIOMIX_SW_PDN_REQ,Software power down trigger for AUDIOMIX" "0,1"
newline
bitfld.long 0x00 4. "MLMIX_SW_PDN_REQ,Software power down trigger for MLMIX" "0,1"
newline
bitfld.long 0x00 3. "USB2_PHY_SW_PDN_REQ,Software power down trigger for USB2_PHY" "0,1"
newline
bitfld.long 0x00 2. "USB1_PHY_SW_PDN_REQ,Software power down trigger for USB1_PHY" "0,1"
newline
bitfld.long 0x00 1. "PCIE_PHY_SW_PDN_REQ,Software power down trigger for PCIE_PHY" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_SW_PDN_REQ,Software power down trigger for MIPI_PHY1" "0,1"
rgroup.long 0x108++0x03
line.long 0x00 "CPU_PGC_PUP_STATUS1,CPU PGC software up trigger status1"
bitfld.long 0x00 4. "SCU_A53_PUP_REQ,no description available" "0,1"
newline
bitfld.long 0x00 3. "CORE3_A53_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 2. "CORE2_A53_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 1. "CORE1_A53_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PUP_STATUS,no description available" "0,1"
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x10C)++0x03
line.long 0x00 "A53_MIX_PGC_PUP_STATUS$1,A53 MIX software up trigger status register"
bitfld.long 0x00 0. "A53_MIX_PGC_PUP_STATUS,no description available" "0,1"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x118)++0x03
line.long 0x00 "M7_MIX_PGC_PUP_STATUS$1,M7 MIX PGC software up trigger status register"
bitfld.long 0x00 0. "M7_MIX_PGC_PUP_STATUS,no description available" "0,1"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x124)++0x03
line.long 0x00 "A53_PU_PGC_PUP_STATUS$1,A53 PU software up trigger status register"
bitfld.long 0x00 19. "A53_DDRMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 18. "A53_MEDIA_ISP_DWP_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 17. "A53_HSIOMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 16. "A53_MIPI_PHY2_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 15. "A53_HDMI_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 14. "A53_HDMIMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 13. "A53_VPU_VC8K_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 12. "A53_VPU_G2_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 11. "A53_VPU_G1_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 10. "A53_MEDIMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 9. "A53_GPU_3D_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 8. "A53_VPUMIX_SHARE_LOGIC_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 7. "A53_GPU_SHARE_LOGIC_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 6. "A53_GPU_2D_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 5. "A53_AUDIOMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 4. "A53_MLMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 3. "A53_USB2_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 2. "A53_USB1_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 1. "A53_PCIE_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 0. "A53_MIPI_PHY1_PUP_STATUS,no description available" "0,1"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x130)++0x03
line.long 0x00 "M7_PU_PGC_PUP_STATUS$1,M7 PU PGC software up trigger status register"
bitfld.long 0x00 19. "M7_DDRMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 18. "M7_MEDIA_ISP_DWP_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 17. "M7_HSIOMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 16. "M7_MIPI_PHY2_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 15. "M7_HDMI_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 14. "M7_HDMIMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 13. "M7_VPU_VC8K_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 12. "M7_VPU_G2_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 11. "M7_VPU_G1_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 10. "M7_MEDIMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 9. "M7_GPU3D_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 8. "M7_VPUMIX_SHARE_LOGIC_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 7. "M7_GPU_SHARE_LOGIC_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 6. "M7_GPU2D_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 5. "M7_AUDIOMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 4. "M7_MLMIX_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 3. "M7_USB2_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 2. "M7_USB1_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 1. "M7_PCIE_PHY_PUP_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 0. "M7_MIPI_PHY1_PUP_STATUS,no description available" "0,1"
repeat.end
rgroup.long 0x13C++0x03
line.long 0x00 "CPU_PGC_PDN_STATUS1,CPU PGC software dn trigger status1"
bitfld.long 0x00 4. "SCU_A53_PDN_REQ,no description available" "0,1"
newline
bitfld.long 0x00 3. "CORE3_A53_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 2. "CORE2_A53_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 1. "CORE1_A53_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_STATUS,no description available" "0,1"
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x140)++0x03
line.long 0x00 "A53_MIX_PGC_PDN_STATUS$1,A53 MIX software down trigger status register"
bitfld.long 0x00 0. "A53_MIX_PGC_PDN_STATUS,no description available" "0,1"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x14C)++0x03
line.long 0x00 "M7_MIX_PGC_PDN_STATUS$1,M7 MIX PGC software power down trigger status register"
bitfld.long 0x00 0. "M7_MIX_PGC_PDN_STATUS,no description available" "0,1"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x158)++0x03
line.long 0x00 "A53_PU_PGC_PDN_STATUS$1,A53 PU PGC software down trigger status"
bitfld.long 0x00 19. "A53_DDRMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 18. "A53_MEDIA_ISP_DWP_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 17. "A53_HSIOMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 16. "A53_MIPI_PHY2_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 15. "A53_HDMI_PHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 14. "A53_HDMIMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 13. "A53_VPU_VC8K_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 12. "A53_VPU_G2_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 11. "A53_VPU_G1_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 10. "A53_MEDIMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 9. "A53_GPU_3D_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 8. "A53_VPUMIX_SHARE_LOGIC_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 7. "A53_GPU_SHARE_LOGIC_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 6. "A53_GPU_2D_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 5. "A53_AUDIOMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 4. "A53_MLMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 3. "A53_USB2_PHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 2. "A53_USB1_PHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 1. "A53_PCIEPHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 0. "A53_MIPI_PHY1_PDN_STATUS,no description available" "0,1"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x164)++0x03
line.long 0x00 "M7_PU_PGC_PDN_STATUS$1,M7 PU PGC software down trigger status"
bitfld.long 0x00 19. "M7_DDRMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 18. "M7_MEDIA_ISP_DWP_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 17. "M7_HSIOMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 16. "M7_MIPI_PHY2_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 15. "M7_HDMI_PHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 14. "M7_HDMIMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 13. "M7_VPU_VC8K_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 12. "M7_VPU_G2_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 11. "M7_VPU_G1_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 10. "M7_MEDIMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 9. "M7_GPU3D_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 8. "M7_VPUMIX_SHARE_LOGIC_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 7. "M7_GPU_SHARE_LOGIC_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 6. "M7_GPU_2D_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 5. "M7_AUDIOMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 4. "M7_MLMIX_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 3. "M7_USB2_PHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 2. "M7_USB1_PHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 1. "M7_PCIE_PHY_PDN_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 0. "M7_MIPI_PHY1_PDN_STATUS,no description available" "0,1"
repeat.end
group.long 0x170++0x03
line.long 0x00 "A53_MIX_PDN_FLG,A53 MIX PDN FLG"
bitfld.long 0x00 0. "A53_MIX_PDN_FLAG,A53 MIX power-down flag" "0,1"
group.long 0x174++0x03
line.long 0x00 "A53_PU_PDN_FLG,A53 PU PDN FLG"
hexmask.long.tbyte 0x00 0.--19. 1. "A53_PU_PDN_FLG,A53 PGC power-down flag"
group.long 0x178++0x03
line.long 0x00 "M7_MIX_PDN_FLG,M7 MIX PDN FLG"
bitfld.long 0x00 0. "M7_MIX_PDN_FLAG,M7_MIX power-down flag" "0,1"
group.long 0x17C++0x03
line.long 0x00 "M7_PU_PDN_FLG,M7 PU PDN FLG"
hexmask.long.tbyte 0x00 0.--19. 1. "M7_PU_PDN_FLG,M7 power-down flag"
group.long 0x180++0x03
line.long 0x00 "LPCR_A53_BSC2,Basic Low power control register of A53 platform"
bitfld.long 0x00 2.--3. "LPM3,CORE3 Setting the low power mode that system will enter on next assertion of dsm_request signal" "0: Remain in RUN mode,1: Transfer to WAIT mode,2: Transfer to STOP mode,?..."
newline
bitfld.long 0x00 0.--1. "LPM2,CORE2 Setting the low power mode that system will enter on next assertion of dsm_request signal" "0: Remain in RUN mode,1: Transfer to WAIT mode,2: Transfer to STOP mode,?..."
group.long 0x190++0x03
line.long 0x00 "PU_PWRHSK,Power handshake register"
rbitfld.long 0x00 31. "GPC_AUDIOMIX_PWRDNACKN,Audiomix noc power down ackn" "0,1"
newline
bitfld.long 0x00 30. "GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN,Mediamix noc and adbs power down ackn" "0,1"
newline
bitfld.long 0x00 29. "GPC_HDMIMIX_NOC_PWRDNACKN,Hdmimix noc power down ackn" "0,1"
newline
bitfld.long 0x00 28. "GPC_NOC2HSIO_ADBS_PWDWNACKN,Main noc 2 hsio and adbs power down ackn" "0,1"
newline
bitfld.long 0x00 27. "GPC_NOC2DDRMIX_PWRDNACKN,Main noc 2 ddrmix power down ackn" "0,1"
newline
bitfld.long 0x00 26. "GPC_VPUMIX_NOX_PWDWNACKN,Vpumix noc power down ackn" "0,1"
newline
bitfld.long 0x00 25. "GPC_GPUMIX_NOC_ADBS_PWRDNACKN,gpumix noc and adbs power down ackn" "0,1"
newline
bitfld.long 0x00 24. "GPC_NOC2MLMIX_PWDWNACKN,Main noc 2 mlmix power down ackn" "0,1"
newline
bitfld.long 0x00 23. "GPC_MLMIX_ADBS_PWRDNACKN,Mlmix adbs power down ackn" "0,1"
newline
bitfld.long 0x00 22. "GPC_SUPERMIX2NOC_ADBS_PWDWNACKN,Supermix 2 noc adbs power down ackn" "0,1"
newline
bitfld.long 0x00 21. "GPC_NOC2SUPERMIX_ADBS_PWDWNACKN,Main noc 2 Supermix adbs power down ackn" "0,1"
newline
bitfld.long 0x00 20. "GPC_NOC2AUDIOMIX_PWDWNACKN,Main noc 2 audiomix power down ackn" "0,1"
newline
bitfld.long 0x00 19. "GPC_DDR1_CACTIVE,DDR1 AXI Clock Active" "0,1"
newline
bitfld.long 0x00 18. "GPC_DDR1_CTRL_REQACK,DDR1 AXI Low-Power Request ack" "0,1"
newline
bitfld.long 0x00 17. "GPC_DDR1_CTRL_CLKACTIVE,DDR1 controller Hardware Low-Power Clock active" "0,1"
newline
bitfld.long 0x00 16. "GPC_DDR1_CTRL_LWPWACKN,DDR1 controller Hardware Low_Power ack" "0,1"
newline
bitfld.long 0x00 15. "GPC_AUDIOMIX_NOC_PWRDNREQN,Audiomix noc power down request" "0,1"
newline
bitfld.long 0x00 14. "GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN,Mediamix noc and adbs power down request" "0,1"
newline
bitfld.long 0x00 13. "GPC_HDMIMIX_NOC_PWRDNREQN,Hdmimix noc power down request" "0,1"
newline
bitfld.long 0x00 12. "GPC_NOC2HSIO_ADBS_PWRDNREQN,Main noc 2 hsio and adbs power down request" "0,1"
newline
bitfld.long 0x00 11. "GPC_NOC2DDRMIX_PWRDNREQN,Main noc 2 ddrmix power down request" "0,1"
newline
bitfld.long 0x00 10. "GPC_VPUMIX_NOC_PWRDNREQN,Vpumix noc power down request" "0,1"
newline
bitfld.long 0x00 9. "GPC_GPUMIX_NOC_ADBS_PWRDNREQN,gpumix noc and adbs power down request" "0,1"
newline
bitfld.long 0x00 8. "GPC_NOC2MLMIX_PWRDNREQN,Main noc 2 mlmix power down request" "0,1"
newline
bitfld.long 0x00 7. "GPC_MLMIX_ADBS_PWRDNREQN,Mlmix adbs power down request" "0,1"
newline
bitfld.long 0x00 6. "GPC_SUPERMIX2NOC_PWRDNREQN,Supermix 2 noc adbs power down request" "0,1"
newline
bitfld.long 0x00 5. "GPC_NOC2SUPERMIX_PWRDNREQN,DISPMIX ADB400 power down request" "0,1"
newline
bitfld.long 0x00 4. "GPC_NOC2AUDIOMIX_PWRDNREQN,Main noc 2 audiomix power down request" "0,1"
newline
bitfld.long 0x00 1. "GPC_DDR1_AXI_CSYSREQ,DDR1 AXI Low-Power Request" "0,1"
newline
bitfld.long 0x00 0. "GPC_DDR1_CORE_CSYSREQ,DDR1 controller Hardware Low-Power Request" "0,1"
group.long 0x194++0x03
line.long 0x00 "IMR1_CORE2_A53,IRQ masking register 1 of A53 core2"
hexmask.long 0x00 0.--31. 1. "IMR1_CORE2_A53,A53 core2 IRQ[31:0] masking bits"
group.long 0x198++0x03
line.long 0x00 "IMR2_CORE2_A53,IRQ masking register 2 of A53 core2"
hexmask.long 0x00 0.--31. 1. "IMR2_CORE2_A53,A53 core2 IRQ[63:32] masking bits"
group.long 0x19C++0x03
line.long 0x00 "IMR3_CORE2_A53,IRQ masking register 3 of A53 core2"
hexmask.long 0x00 0.--31. 1. "IMR3_CORE2_A53,A53 core2 IRQ[95:64] masking bits"
group.long 0x1A0++0x03
line.long 0x00 "IMR4_CORE2_A53,IRQ masking register 4 of A53 core2"
hexmask.long 0x00 0.--31. 1. "IMR4_CORE2_A53,A53 core2 IRQ[127:96] masking bits"
group.long 0x1A4++0x03
line.long 0x00 "IMR5_CORE2_A53,IRQ masking register 5 of A53 core2"
hexmask.long 0x00 0.--31. 1. "IMR5_CORE2_A53,A53 core2 IRQ[159:128] masking bits"
group.long 0x1A8++0x03
line.long 0x00 "IMR1_CORE3_A53,IRQ masking register 1 of A53 core3"
hexmask.long 0x00 0.--31. 1. "IMR1_CORE3_A53,A53 core3 IRQ[31:0] masking bits"
group.long 0x1AC++0x03
line.long 0x00 "IMR2_CORE3_A53,IRQ masking register 2 of A53 core3"
hexmask.long 0x00 0.--31. 1. "IMR2_CORE3_A53,A53 core3 IRQ[63:32] masking bits"
group.long 0x1B0++0x03
line.long 0x00 "IMR3_CORE3_A53,IRQ masking register 3 of A53 core3"
hexmask.long 0x00 0.--31. 1. "IMR3_CORE3_A53,A53 core3 IRQ[95:64] masking bits"
group.long 0x1B4++0x03
line.long 0x00 "IMR4_CORE3_A53,IRQ masking register 4 of A53 core3"
hexmask.long 0x00 0.--31. 1. "IMR4_CORE3_A53,A53 core3 IRQ[127:96] masking bits"
group.long 0x1B8++0x03
line.long 0x00 "IMR5_CORE3_A53,IRQ masking register 5 of A53 core3"
hexmask.long 0x00 0.--31. 1. "IM5_CORE3_A53,A53 core3 IRQ[159:128] masking bits"
group.long 0x1BC++0x03
line.long 0x00 "ACK_SEL_A53_PU,PGC acknowledge signal selection of A53 platform for PUs"
bitfld.long 0x00 31. "HDMI_PHY_PGC_PUP_ACK,Select power down acknowledge signal of HDMI_PHY PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PGC_PDN_ACK,Select power down acknowledge signal of HDMI_PHY PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PGC_PUP_ACK,Select power down acknowledge signal of HDMIMIX PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PGC_PDN_ACK,Select power down acknowledge signal of HDMIMIX PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PGC_PUP_ACK,Select power down acknowledge signal of VPU_VC8K PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PGC_PDN_ACK,Select power down acknowledge signal of VPU_VC8K PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PGC_PUP_ACK,Select power down acknowledge signal of VPU_G2 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PGC_PDN_ACK,Select power down acknowledge signal of VPU_G2 PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PGC_PUP_ACK,Select power down acknowledge signal of VPU_G1 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PGC_PDN_ACK,Select power down acknowledge signal of VPU_G1 PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PGC_PUP_ACK,Select power down acknowledge signal of MEDIMIX PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PGC_PDN_ACK,Select power down acknowledge signal of MEDIMIX PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PGC_PUP_ACK,Select power down acknowledge signal of GPU3D PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PGC_PDN_ACK,Select power down acknowledge signal of GPU3D PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PGC_PUP_ACK,Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PGC_PDN_ACK,Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PGC_PUP_ACK,Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PGC_PDN_ACK,Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PGC_PUP_ACK,Select power down acknowledge signal of GPU_2D PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PGC_PDN_ACK,Select power down acknowledge signal of GPU_2D PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PGC_PUP_ACK,Select power down acknowledge signal of AUDIOMIX PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PGC_PDN_ACK,Select power down acknowledge signal of AUDIOMIX PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PGC_PUP_ACK,Select power down acknowledge signal of MLMIX PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PGC_PDN_ACK,Select power down acknowledge signal of MLMIX PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PGC_PUP_ACK,Select power down acknowledge signal of USB2_PHY PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PGC_PDN_ACK,Select power down acknowledge signal of USB2_PHY PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PGC_PUP_ACK,Select power down acknowledge signal of USB1_PHY PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PGC_PDN_ACK,Select power down acknowledge signal of USB1_PHY PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PGC_PUP_ACK,Select power down acknowledge signal of PCIE_PHY PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PGC_PDN_ACK,Select power down acknowledge signal of PCIE_PHY PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PGC_PUP_ACK,Select power down acknowledge signal of MIPI_PHY1 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PGC_PDN_ACK,Select power down acknowledge signal of MIPI_PHY1 PGC as the power down acknowledge for A53 LPM" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ACK_SEL_A53_PU1,PGC acknowledge signal selection of A53 platform for PUs"
bitfld.long 0x00 7. "DDRMIX_PGC_PUP_ACK,Select power down acknowledge signal of DDRMIX PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PGC_PDN_ACK,Select power down acknowledge signal of DDRMIX PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PGC_PUP_ACK,Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PGC_PDN_ACK,Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PGC_PUP_ACK,Select power down acknowledge signal of HSIOMIX PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PGC_PDN_ACK,Select power down acknowledge signal of HSIOMIX PGC as the power down acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PGC_PUP_ACK,Select power down acknowledge signal of MIPI_PHY2 PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PGC_PDN_ACK,Select power down acknowledge signal of MIPI_PHY2 PGC as the power down acknowledge for A53 LPM" "0,1"
group.long 0x1C4++0x03
line.long 0x00 "ACK_SEL_M7_PU,PGC acknowledge signal selection of M7 platform for PUs"
bitfld.long 0x00 31. "HDMI_PHY_PGC_PUP_ACK,Select power down acknowledge signal of HDMI_PHY PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PGC_PDN_ACK,Select power down acknowledge signal of HDMI_PHY PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PGC_PUP_ACK,Select power down acknowledge signal of HDMIMIX PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PGC_PDN_ACK,Select power down acknowledge signal of HDMIMIX PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PGC_PUP_ACK,Select power down acknowledge signal of VPU_VC8K PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PGC_PDN_ACK,Select power down acknowledge signal of VPU_VC8K PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PGC_PUP_ACK,Select power down acknowledge signal of VPU_G2 PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PGC_PDN_ACK,Select power down acknowledge signal of VPU_G2 PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PGC_PUP_ACK,Select power down acknowledge signal of VPU_G1 PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PGC_PDN_ACK,Select power down acknowledge signal of VPU_G1 PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PGC_PUP_ACK,Select power down acknowledge signal of MEDIMIX PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PGC_PDN_ACK,Select power down acknowledge signal of MEDIMIX PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PGC_PUP_ACK,Select power down acknowledge signal of GPU3D PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PGC_PDN_ACK,Select power down acknowledge signal of GPU3D PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PGC_PUP_ACK,Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PGC_PDN_ACK,Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PGC_PUP_ACK,Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PGC_PDN_ACK,Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PGC_PUP_ACK,Select power down acknowledge signal of GPU_2D PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PGC_PDN_ACK,Select power down acknowledge signal of GPU_2D PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PGC_PUP_ACK,Select power down acknowledge signal of AUDIOMIX PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PGC_PDN_ACK,Select power down acknowledge signal of AUDIOMIX PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PGC_PUP_ACK,Select power down acknowledge signal of MLMIX PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PGC_PDN_ACK,Select power down acknowledge signal of MLMIX PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PGC_PUP_ACK,Select power down acknowledge signal of USB2_PHY PGC as the power up acknowledge for A53 LPM" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PGC_PDN_ACK,Select power down acknowledge signal of USB2_PHY PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PGC_PUP_ACK,Select power down acknowledge signal of USB1_PHY PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PGC_PDN_ACK,Select power down acknowledge signal of USB1_PHY PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PGC_PUP_ACK,Select power down acknowledge signal of PCIE_PHY PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PGC_PDN_ACK,Select power down acknowledge signal of PCIE_PHY PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PGC_PUP_ACK,Select power down acknowledge signal of MIPI_PHY1 PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PGC_PDN_ACK,Select power down acknowledge signal of MIPI_PHY1 PGC as the power down acknowledge for M7 LPM" "0,1"
group.long 0x1C8++0x03
line.long 0x00 "ACK_SEL_M7_PU1,PGC acknowledge signal selection of M7 platform for PUs"
bitfld.long 0x00 7. "DDRMIX_PGC_PUP_ACK,Select power down acknowledge signal of DDRMIX PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PGC_PDN_ACK,Select power down acknowledge signal of DDRMIX PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PGC_PUP_ACK,Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PGC_PDN_ACK,Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PGC_PUP_ACK,Select power down acknowledge signal of HSIOMIX PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PGC_PDN_ACK,Select power down acknowledge signal of HSIOMIX PGC as the power down acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PGC_PUP_ACK,Select power down acknowledge signal of MIPI_PHY2 PGC as the power up acknowledge for M7 LPM" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PGC_PDN_ACK,Select power down acknowledge signal of MIPI_PHY2 PGC as the power down acknowledge for M7 LPM" "0,1"
group.long 0x1CC++0x03
line.long 0x00 "PGC_CPU_A53_MAPPING,PGC CPU A53 mapping"
bitfld.long 0x00 21. "DDRMIX_DOMAIN,DDR mapping" "0: Don't map DDR to A53 domain,1: Map DDR to A53 domain"
newline
bitfld.long 0x00 20. "MEDIA_ISP_DWP_DOMAIN,MEDIA_ISP_DWP_DOMAIN mapping" "0: Don't map MEDIA_ISP_DWP_DOMAIN to A53 domain,1: Map DDR to MEDIA_ISP_DWP_DOMAIN domain"
newline
bitfld.long 0x00 19. "HSIOMIX_DOMAIN,HSIOMIX mapping" "0: Don't map HSIOMIX to A53 domain,1: Map HSIOMIX to A53 domain"
newline
bitfld.long 0x00 18. "MIPI_PHY2_DOMAIN,MIPI PHY2 mapping" "0: Don't map MIPI PHY2 to A53 domain,1: Map MIPI PHY2 to A53 domain"
newline
bitfld.long 0x00 17. "HDMI_PHY_DOMAIN,HDMI PHY mapping" "0: Don't map HDMI PHY to A53 domain,1: Map HDMI PHY to A53 domain"
newline
bitfld.long 0x00 16. "HDMIMIX_DOMAIN,HDMI mapping" "0: Don't map HDMI to A53 domain,1: Map HDMI to A53 domain"
newline
bitfld.long 0x00 15. "VPU_VC8K_DOMAIN,VPU_VC8K mapping" "0: Don't map VPU_VC8K to A53 domain,1: Map VPU_VC8K to A53 domain"
newline
bitfld.long 0x00 14. "VPU_G2_DOMAIN,VPU_G2 mapping" "0: Don't map VPU_G1 to A53 domain,1: Map VPU_G1 to A53 domain"
newline
bitfld.long 0x00 13. "VPU_G1_DOMAIN,VPU_G1 mapping" "0: Don't map VPU_G1 to A53 domain,1: Map VPU_G1 to A53 domain"
newline
bitfld.long 0x00 12. "MEDIMIX_DOMAIN,MEDIMIX mapping" "0: Don't map MEDIMIX to A53 domain,1: Map MEDIMIX to A53 domain"
newline
bitfld.long 0x00 11. "GPU3D_DOMAIN,GPU3D mapping" "0: Don't map GPU2D to A53 domain,1: Map GPU2D to A53 domain"
newline
bitfld.long 0x00 10. "VPUMIX_SHARE_LOGIC_DOMAIN,VPUMIX Share Logic mapping" "0: Don't map VPUMIX Share Logic to A53 domain,1: Map VPUMIX Share Logic to A53 domain"
newline
bitfld.long 0x00 9. "GPU_SHARE_LOGIC_DOMAIN,GPU_SHARE_LOGIC mapping" "0: Don't map GPU Share Logic to A53 domain,1: Map GPU Share Logic to A53 domain"
newline
bitfld.long 0x00 8. "GPU_2D_DOMAIN,GPU2D mapping" "0: Don't map GPU2D to A53 domain,1: Map GPU2D to A53 domain"
newline
bitfld.long 0x00 7. "AUDIOMIX_DOMAIN,AUDIOMIX mapping" "0: Don't map AUDIOMIX to A53 domain,1: Map AUDIOMIX to A53 domain"
newline
bitfld.long 0x00 6. "MLMIX_DOMAIN,MLMIX mapping" "0: Don't map MLMIX to A53 domain,1: Map MLMIX to A53 domain"
newline
bitfld.long 0x00 5. "USB2_PHY_DOMAIN,USB2_PHY mapping" "0: Don't map USB2_PHY to A53 domain,1: Map USB2_PHY to A53 domain"
newline
bitfld.long 0x00 4. "USB1_PHY_DOMAIN,USB1_PHY mapping" "0: Don't map USB1_PHY to A53 domain,1: Map USB1_PHY to A53 domain"
newline
bitfld.long 0x00 3. "PCIE_PHY_DOMAIN,PCIE_PHY mapping" "0: Don't map PCIE_PHY to A53 domain,1: Map PCIE_PHY to A53 domain"
newline
bitfld.long 0x00 2. "MIPI_PHY1_DOMAIN,MIPI_PHY1 mapping" "0: Don't map MIPI_PHY1 to A53 domain,1: Map MIPI_PHY1 to A53 domain"
newline
bitfld.long 0x00 1. "MIX1_NOC_DOMAIN,MIX1 (NOC) mapping" "0: Don't map NOC to A53 domain,1: Map NOC to A53 domain"
newline
bitfld.long 0x00 0. "MIX0_SUPERMIXM7_DOMAIN,MIX0 (SUPERMIXM7) mapping" "0: Don't map M7 to A53 domain,1: MIX0_SUPERMIXM7_DOMAIN_1"
group.long 0x1D0++0x03
line.long 0x00 "PGC_CPU_M7_MAPPING,PGC CPU M7 mapping"
bitfld.long 0x00 21. "DDRMIX_DOMAIN,DDR mapping" "0: Don't map DDR to M7 domain,1: Map DDR to M7 domain"
newline
bitfld.long 0x00 20. "MEDIA_ISP_DWP_DOMAIN,MEDIA_ISP_DWP_DOMAIN mapping" "0: Don't map MEDIA_ISP_DWP_DOMAIN to M7 domain,1: Map MEDIA_ISP_DWP_DOMAIN to M7 domain"
newline
bitfld.long 0x00 19. "HSIOMIX_DOMAIN,HSIOMIX mapping" "0: Don't map HSIOMIX to M7 domain,1: Map HSIOMIX to M7 domain"
newline
bitfld.long 0x00 18. "MIPI_PHY2_DOMAIN,MIPI PHY2 mapping" "0: Don't map MIPI PHY2 to M7 domain,1: Map MIPI PHY2 to M7 domain"
newline
bitfld.long 0x00 17. "HDMI_PHY_DOMAIN,HDMI PHY mapping" "0: Don't map HDMI PHY to M7 domain,1: Map HDMI PHY to M7 domain"
newline
bitfld.long 0x00 16. "HDMIMIX_DOMAIN,HDMI mapping" "0: Don't map HDMI to M7 domain,1: Map HDMI to M7 domain"
newline
bitfld.long 0x00 15. "VPU_VC8K_DOMAIN,VPU_VC8K mapping" "0: Don't map VPU_VC8K to M7 domain,1: Map VPU_VC8K to M7 domain"
newline
bitfld.long 0x00 14. "VPU_G2_DOMAIN,VPU_G2 mapping" "0: Don't map VPU_G1 to M7 domain,1: Map VPU_G1 to M7 domain"
newline
bitfld.long 0x00 13. "VPU_G1_DOMAIN,VPU_G1 mapping" "0: Don't map VPU_G1 to M7 domain,1: Map VPU_G1 to M7 domain"
newline
bitfld.long 0x00 12. "MEDIMIX_DOMAIN,MEDIMIX mapping" "0: Don't map MEDIMIX to M7 domain,1: Map MEDIMIX to M7 domain"
newline
bitfld.long 0x00 11. "GPU3D_DOMAIN,GPU3D mapping" "0: Don't map GPU2D to M7 domain,1: Map GPU2D to M7 domain"
newline
bitfld.long 0x00 10. "VPUMIX_SHARE_LOGIC_DOMAIN,VPUMIX Share Logic mapping" "0: Don't map VPUMIX Share Logic to M7 domain,1: Map VPUMIX Share Logic to M7 domain"
newline
bitfld.long 0x00 9. "GPU_SHARE_LOGIC_DOMAIN,GPU_SHARE_LOGIC mapping" "0: Don't map GPU Share Logic to M7 domain,1: Map GPU Share Logic to M7 domain"
newline
bitfld.long 0x00 8. "GPU_2D_DOMAIN,GPU2D mapping" "0: Don't map GPU2D to M7 domain,1: Map GPU2D to M7 domain"
newline
bitfld.long 0x00 7. "AUDIOMIX_DOMAIN,AUDIOMIX mapping" "0: Don't map AUDIOMIX to M7 domain,1: Map AUDIOMIX to M7 domain"
newline
bitfld.long 0x00 6. "MLMIX_DOMAIN,MLMIX mapping" "0: Don't map MLMIX to M7 domain,1: Map MLMIX to M7 domain"
newline
bitfld.long 0x00 5. "USB2_PHY_DOMAIN,USB2_PHY mapping" "0: Don't map USB2_PHY to M7 domain,1: Map USB2_PHY to M7 domain"
newline
bitfld.long 0x00 4. "USB1_PHY_DOMAIN,USB1_PHY mapping" "0: Don't map USB1_PHY to M7 domain,1: Map USB1_PHY to M7 domain"
newline
bitfld.long 0x00 3. "PCIE_PHY_DOMAIN,PCIE_PHY mapping" "0: Don't map PCIE_PHY to M7 domain,1: Map PCIE_PHY to M7 domain"
newline
bitfld.long 0x00 2. "MIPI_PHY1_DOMAIN,MIPI_PHY1 mapping" "0: Don't map MIPI_PHY1 to M7 domain,1: Map MIPI_PHY1 to M7 domain"
newline
bitfld.long 0x00 1. "MIX1_NOC_DOMAIN,MIX1 (NOC) mapping" "0: Don't map MIX1_NOC to M7 domain,1: Map MIX1_NOC to M7 domain"
newline
bitfld.long 0x00 0. "MIX0_SUPERMIXM7_DOMAIN,MIX0 (SUPERMIXM7) mapping" "0: Don't map MIX0_SUPERMIXM7 to M7 domain,1: Map MIX0_SUPERMIXM7 to M7 domain"
group.long 0x200++0x03
line.long 0x00 "SLT0_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x204++0x03
line.long 0x00 "SLT1_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x208++0x03
line.long 0x00 "SLT2_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x20C++0x03
line.long 0x00 "SLT3_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x210++0x03
line.long 0x00 "SLT4_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x214++0x03
line.long 0x00 "SLT5_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x218++0x03
line.long 0x00 "SLT6_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x21C++0x03
line.long 0x00 "SLT7_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x220++0x03
line.long 0x00 "SLT8_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x224++0x03
line.long 0x00 "SLT9_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x228++0x03
line.long 0x00 "SLT10_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x22C++0x03
line.long 0x00 "SLT11_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x230++0x03
line.long 0x00 "SLT12_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x234++0x03
line.long 0x00 "SLT13_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x238++0x03
line.long 0x00 "SLT14_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x23C++0x03
line.long 0x00 "SLT15_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x240++0x03
line.long 0x00 "SLT16_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x244++0x03
line.long 0x00 "SLT17_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x248++0x03
line.long 0x00 "SLT18_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x24C++0x03
line.long 0x00 "SLT19_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x250++0x03
line.long 0x00 "SLT20_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x254++0x03
line.long 0x00 "SLT21_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x258++0x03
line.long 0x00 "SLT22_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x25C++0x03
line.long 0x00 "SLT23_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x260++0x03
line.long 0x00 "SLT24_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x264++0x03
line.long 0x00 "SLT25_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x268++0x03
line.long 0x00 "SLT26_CFG,Slot configure register for CPUs"
bitfld.long 0x00 13. "NOC_PUP_SLOT_CONTROL,NOC Power-up slot control" "0,1"
newline
bitfld.long 0x00 12. "NOC_PDN_SLOT_CONTROL,NOC Power-down slot control" "0,1"
newline
bitfld.long 0x00 9. "SCU_PUP_SLOT_CONTROL,SCU Power-up slot control" "0,1"
newline
bitfld.long 0x00 8. "SCU_PDN_SLOT_CONTROL,SCU Power-down slot control" "0,1"
newline
bitfld.long 0x00 7. "CORE3_A53_PUP_SLOT_CONTROL,CORE3 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 6. "CORE3_A53_PDN_SLOT_CONTROL,CORE3 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 5. "CORE2_A53_PUP_SLOT_CONTROL,CORE2 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 4. "CORE2_A53_PDN_SLOT_CONTROL,CORE2 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 3. "CORE1_A53_PUP_SLOT_CONTROL,CORE1 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 2. "CORE1_A53_PDN_SLOT_CONTROL,CORE1 A53 Power-down slot control" "0,1"
newline
bitfld.long 0x00 1. "CORE0_A53_PUP_SLOT_CONTROL,CORE0 A53 Power-up slot control" "0,1"
newline
bitfld.long 0x00 0. "CORE0_A53_PDN_SLOT_CONTROL,CORE0 A53 Power-down slot control" "0,1"
group.long 0x280++0x03
line.long 0x00 "SLT0_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x288++0x03
line.long 0x00 "SLT1_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x290++0x03
line.long 0x00 "SLT2_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x298++0x03
line.long 0x00 "SLT3_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2A0++0x03
line.long 0x00 "SLT4_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2A8++0x03
line.long 0x00 "SLT5_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2B0++0x03
line.long 0x00 "SLT6_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2B8++0x03
line.long 0x00 "SLT7_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2C0++0x03
line.long 0x00 "SLT8_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2C8++0x03
line.long 0x00 "SLT9_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2D0++0x03
line.long 0x00 "SLT10_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2D8++0x03
line.long 0x00 "SLT11_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2E0++0x03
line.long 0x00 "SLT12_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2E8++0x03
line.long 0x00 "SLT13_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2F0++0x03
line.long 0x00 "SLT14_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x2F8++0x03
line.long 0x00 "SLT15_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x300++0x03
line.long 0x00 "SLT16_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x308++0x03
line.long 0x00 "SLT17_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x310++0x03
line.long 0x00 "SLT18_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x318++0x03
line.long 0x00 "SLT19_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x320++0x03
line.long 0x00 "SLT20_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x328++0x03
line.long 0x00 "SLT21_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x330++0x03
line.long 0x00 "SLT22_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x338++0x03
line.long 0x00 "SLT23_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x340++0x03
line.long 0x00 "SLT24_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x348++0x03
line.long 0x00 "SLT25_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x350++0x03
line.long 0x00 "SLT26_CFG_PU,Slot configure register for PGC PUs"
bitfld.long 0x00 31. "HDMI_PHY_PUP_SLOT_CONTROL,HDMI_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 30. "HDMI_PHY_PDN_SLOT_CONTROL,HDMI_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 29. "HDMIMIX_PUP_SLOT_CONTROL,HDMIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 28. "HDMIMIX_PDN_SLOT_CONTROL,HDMIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 27. "VPU_VC8K_PUP_SLOT_CONTROL,VPU_VC8K power up slot control" "0,1"
newline
bitfld.long 0x00 26. "VPU_VC8K_PDN_SLOT_CONTROL,VPU_VC8K power down slot control" "0,1"
newline
bitfld.long 0x00 25. "VPU_G2_PUP_SLOT_CONTROL,VPU_G2 power up slot control" "0,1"
newline
bitfld.long 0x00 24. "VPU_G2_PDN_SLOT_CONTROL,VPU_G2 power down slot control" "0,1"
newline
bitfld.long 0x00 23. "VPU_G1_PUP_SLOT_CONTROL,VPU_G1 power up slot control" "0,1"
newline
bitfld.long 0x00 22. "VPU_G1_PDN_SLOT_CONTROL,VPU_G1 power down slot control" "0,1"
newline
bitfld.long 0x00 21. "MEDIMIX_PUP_SLOT_CONTROL,MEDIMIX power up slot control" "0,1"
newline
bitfld.long 0x00 20. "MEDIMIX_PDN_SLOT_CONTROL,MEDIMIX power down slot control" "0,1"
newline
bitfld.long 0x00 19. "GPU3D_PUP_SLOT_CONTROL,GPU3D power up slot control" "0,1"
newline
bitfld.long 0x00 18. "GPU3D_PDN_SLOT_CONTROL,GPU3D power down slot control" "0,1"
newline
bitfld.long 0x00 17. "VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 16. "VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL,VPUMIX_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 15. "GPU_SHARE_LOGIC_PUP_SLOT_CONTROL,GPU_SHARE_LOGIC power up slot control" "0,1"
newline
bitfld.long 0x00 14. "GPU_SHARE_LOGIC_PDN_SLOT_CONTROL,GPU_SHARE_LOGIC power down slot control" "0,1"
newline
bitfld.long 0x00 13. "GPU_2D_PUP_SLOT_CONTROL,GPU_2D power up slot control" "0,1"
newline
bitfld.long 0x00 12. "GPU_2D_PDN_SLOT_CONTROL,GPU_2D power down slot control" "0,1"
newline
bitfld.long 0x00 11. "AUDIOMIX_PUP_SLOT_CONTROL,AUDIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 10. "AUDIOMIX_PDN_SLOT_CONTROL,AUDIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 9. "MLMIX_PUP_SLOT_CONTROL,MLMIX power up slot control" "0,1"
newline
bitfld.long 0x00 8. "MLMIX_PDN_SLOT_CONTROL,MLMIX power down slot control" "0,1"
newline
bitfld.long 0x00 7. "USB2_PHY_PUP_SLOT_CONTROL,USB2_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 6. "USB2_PHY_PDN_SLOT_CONTROL,USB2_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 5. "USB1_PHY_PUP_SLOT_CONTROL,USB1_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 4. "USB1_PHY_PDN_SLOT_CONTROL,USB1_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 3. "PCIE_PHY_PUP_SLOT_CONTROL,PCIE_PHY power up slot control" "0,1"
newline
bitfld.long 0x00 2. "PCIE_PHY_PDN_SLOT_CONTROL,PCIE_PHY power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY1_PUP_SLOT_CONTROL,MIPI_PHY1 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY1_PDN_SLOT_CONTROL,MIPI_PHY1 power down slot control" "0,1"
group.long 0x284++0x03
line.long 0x00 "SLT0_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x28C++0x03
line.long 0x00 "SLT1_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x294++0x03
line.long 0x00 "SLT2_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x29C++0x03
line.long 0x00 "SLT3_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2A4++0x03
line.long 0x00 "SLT4_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2AC++0x03
line.long 0x00 "SLT5_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2B4++0x03
line.long 0x00 "SLT6_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2BC++0x03
line.long 0x00 "SLT7_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2C4++0x03
line.long 0x00 "SLT8_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2CC++0x03
line.long 0x00 "SLT9_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2D4++0x03
line.long 0x00 "SLT10_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2DC++0x03
line.long 0x00 "SLT11_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2E4++0x03
line.long 0x00 "SLT12_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2EC++0x03
line.long 0x00 "SLT13_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2F4++0x03
line.long 0x00 "SLT14_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x2FC++0x03
line.long 0x00 "SLT15_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x304++0x03
line.long 0x00 "SLT16_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x30C++0x03
line.long 0x00 "SLT17_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x314++0x03
line.long 0x00 "SLT18_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x31C++0x03
line.long 0x00 "SLT19_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
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bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x324++0x03
line.long 0x00 "SLT20_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
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bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
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bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
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bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x32C++0x03
line.long 0x00 "SLT21_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
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bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x334++0x03
line.long 0x00 "SLT22_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
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bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
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bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
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bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
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bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x33C++0x03
line.long 0x00 "SLT23_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x344++0x03
line.long 0x00 "SLT24_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x34C++0x03
line.long 0x00 "SLT25_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
group.long 0x354++0x03
line.long 0x00 "SLT26_CFG_PU1,Extended slot configure register for PGC PUs"
bitfld.long 0x00 9. "M7_PUP_SLOT_CONTROL,M7 power up slot control" "0,1"
newline
bitfld.long 0x00 8. "M7_PDN_SLOT_CONTROL,M7 power down slot control" "0,1"
newline
bitfld.long 0x00 7. "DDRMIX_PUP_SLOT_CONTROL,DDRMIX power up slot control" "0,1"
newline
bitfld.long 0x00 6. "DDRMIX_PDN_SLOT_CONTROL,DDRMIX power down slot control" "0,1"
newline
bitfld.long 0x00 5. "MEDIA_ISP_DWP_PUP_SLOT_CONTROL,MEDIA_ISP_DWP power up slot control" "0,1"
newline
bitfld.long 0x00 4. "MEDIA_ISP_DWP_PDN_SLOT_CONTROL,MEDIA_ISP_DWP power down slot control" "0,1"
newline
bitfld.long 0x00 3. "HSIOMIX_PUP_SLOT_CONTROL,HSIOMIX power up slot control" "0,1"
newline
bitfld.long 0x00 2. "HSIOMIX_PDN_SLOT_CONTROL,HSIOMIX power down slot control" "0,1"
newline
bitfld.long 0x00 1. "MIPI_PHY2_PUP_SLOT_CONTROL,MIPI_PHY2 power up slot control" "0,1"
newline
bitfld.long 0x00 0. "MIPI_PHY2_PDN_SLOT_CONTROL,MIPI_PHY2 power down slot control" "0,1"
tree.end
tree "GPC_PGC"
base ad:0x303A0000
group.long 0x800++0x03
line.long 0x00 "A53CORE0_CTRL,GPC PGC Control Register for PGC CPUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0x804++0x03
line.long 0x00 "A53CORE0_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x808++0x03
line.long 0x00 "A53CORE0_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80C++0x03
line.long 0x00 "A53CORE0_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0x840++0x03
line.long 0x00 "A53CORE1_CTRL,GPC PGC Control Register for PGC CPUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0x844++0x03
line.long 0x00 "A53CORE1_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x848++0x03
line.long 0x00 "A53CORE1_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x84C++0x03
line.long 0x00 "A53CORE1_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0x880++0x03
line.long 0x00 "A53CORE2_CTRL,GPC PGC Control Register for PGC CPUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0x884++0x03
line.long 0x00 "A53CORE2_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x888++0x03
line.long 0x00 "A53CORE2_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x88C++0x03
line.long 0x00 "A53CORE2_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0x8C0++0x03
line.long 0x00 "A53CORE3_CTRL,GPC PGC Control Register for PGC CPUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0x8C4++0x03
line.long 0x00 "A53CORE3_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8C8++0x03
line.long 0x00 "A53CORE3_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8CC++0x03
line.long 0x00 "A53CORE3_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0x900++0x03
line.long 0x00 "A53SCU_CTRL,GPC PGC Control Register for PGC CPUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0x904++0x03
line.long 0x00 "A53SCU_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x908++0x03
line.long 0x00 "A53SCU_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x90C++0x03
line.long 0x00 "A53SCU_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xA40++0x03
line.long 0x00 "NOC_MIX_CTRL,GPC PGC Control Register for PGC MIX"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "MIX_PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xA44++0x03
line.long 0x00 "NOC_MIX_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 6. "PUP_WAIT_SCALL_OUT,After SCALL asserting to 1'b0 wait handshake signal SCALL_OUT to return to 1'b0 (This register control only for MIX Type PGC)" "0,1"
group.long 0xA48++0x03
line.long 0x00 "NOC_MIX_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA4C++0x03
line.long 0x00 "NOC_MIX_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
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rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xB00++0x03
line.long 0x00 "PU0_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xB04++0x03
line.long 0x00 "PU0_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB08++0x03
line.long 0x00 "PU0_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB0C++0x03
line.long 0x00 "PU0_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
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rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xB40++0x03
line.long 0x00 "PU1_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xB44++0x03
line.long 0x00 "PU1_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB48++0x03
line.long 0x00 "PU1_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB4C++0x03
line.long 0x00 "PU1_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xB80++0x03
line.long 0x00 "PU2_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xB84++0x03
line.long 0x00 "PU2_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB88++0x03
line.long 0x00 "PU2_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB8C++0x03
line.long 0x00 "PU2_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xBC0++0x03
line.long 0x00 "PU3_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xBC4++0x03
line.long 0x00 "PU3_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBC8++0x03
line.long 0x00 "PU3_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBCC++0x03
line.long 0x00 "PU3_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xC00++0x03
line.long 0x00 "PU4_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xC04++0x03
line.long 0x00 "PU4_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC08++0x03
line.long 0x00 "PU4_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC0C++0x03
line.long 0x00 "PU4_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xC40++0x03
line.long 0x00 "PU5_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xC44++0x03
line.long 0x00 "PU5_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC48++0x03
line.long 0x00 "PU5_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4C++0x03
line.long 0x00 "PU5_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xC80++0x03
line.long 0x00 "PU6_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xC84++0x03
line.long 0x00 "PU6_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC88++0x03
line.long 0x00 "PU6_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC8C++0x03
line.long 0x00 "PU6_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xCC0++0x03
line.long 0x00 "PU7_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xCC4++0x03
line.long 0x00 "PU7_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCC8++0x03
line.long 0x00 "PU7_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCCC++0x03
line.long 0x00 "PU7_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xD00++0x03
line.long 0x00 "PU8_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xD04++0x03
line.long 0x00 "PU8_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD08++0x03
line.long 0x00 "PU8_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD0C++0x03
line.long 0x00 "PU8_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xD40++0x03
line.long 0x00 "PU9_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xD44++0x03
line.long 0x00 "PU9_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD48++0x03
line.long 0x00 "PU9_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD4C++0x03
line.long 0x00 "PU9_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xD80++0x03
line.long 0x00 "PU10_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xD84++0x03
line.long 0x00 "PU10_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD88++0x03
line.long 0x00 "PU10_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD8C++0x03
line.long 0x00 "PU10_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
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rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xDC0++0x03
line.long 0x00 "PU11_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xDC4++0x03
line.long 0x00 "PU11_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xDC8++0x03
line.long 0x00 "PU11_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xDCC++0x03
line.long 0x00 "PU11_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xE00++0x03
line.long 0x00 "PU12_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xE04++0x03
line.long 0x00 "PU12_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE08++0x03
line.long 0x00 "PU12_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE0C++0x03
line.long 0x00 "PU12_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xE40++0x03
line.long 0x00 "PU13_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xE44++0x03
line.long 0x00 "PU13_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE48++0x03
line.long 0x00 "PU13_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE4C++0x03
line.long 0x00 "PU13_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xE80++0x03
line.long 0x00 "PU14_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xE84++0x03
line.long 0x00 "PU14_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE88++0x03
line.long 0x00 "PU14_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE8C++0x03
line.long 0x00 "PU14_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xEC0++0x03
line.long 0x00 "PU15_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xEC4++0x03
line.long 0x00 "PU15_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xEC8++0x03
line.long 0x00 "PU15_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xECC++0x03
line.long 0x00 "PU15_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xF00++0x03
line.long 0x00 "PU16_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xF04++0x03
line.long 0x00 "PU16_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF08++0x03
line.long 0x00 "PU16_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF0C++0x03
line.long 0x00 "PU16_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xF40++0x03
line.long 0x00 "PU17_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xF44++0x03
line.long 0x00 "PU17_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF48++0x03
line.long 0x00 "PU17_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF4C++0x03
line.long 0x00 "PU17_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
newline
rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
newline
rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xF80++0x03
line.long 0x00 "PU18_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xF84++0x03
line.long 0x00 "PU18_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF88++0x03
line.long 0x00 "PU18_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF8C++0x03
line.long 0x00 "PU18_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
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rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
group.long 0xFC0++0x03
line.long 0x00 "PU19_CTRL,GPC PGC Control Register for PGC PUs"
bitfld.long 0x00 24.--29. "MEMPWR_TCD1_TDR_TRM,After scu pdn_req count this value to assert A53 mempwr to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "L2RETN_TCD1_TDR,After scu pdn_req count this value to assert A53 l2retn to 1'b0 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "DFTRAM_TCD1,After scu pdn_req count this value to assert A53 dftram to 1'b1 Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1.--6. "L2RSTDIS,After scu pdn_req count this value to assert A53 l2rstdis to 1'b1 it will be clear automatically once any of A53 core0/core1/core2/core3 is wakeup Can't be programmed to zero (This register control only for SCU Type PGC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "PCR,Power ControlPCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up" "0: Do not switch off power even if pdn_req is..,1: Switch off power when pdn_req is asserted"
group.long 0xFC4++0x03
line.long 0x00 "PU19_PUPSCR,GPC PGC Up Sequence Control Register"
hexmask.long.word 0x00 7.--22. 1. "SW2ISO,After asserting switch_b the PGC waits a number of clocks equal to the value of SW2ISO before negating isolation"
bitfld.long 0x00 0.--5. "SW,After a power-up request (pup_req assertion) the PGC waits a number of clocks equal to the value of SW before asserting switch_b SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xFC8++0x03
line.long 0x00 "PU19_PDNSCR,GPC PGC Down Sequence Control Register"
bitfld.long 0x00 8.--13. "ISO2SW,After asserting isolation(by pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO2SW before negating switch_b ISO2SW must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "ISO,After a power-down request (pdn_req assertion) the PGC waits a number of clocks equal to the value of ISO before asserting isolation ISO must not be programmed to zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xFCC++0x03
line.long 0x00 "PU19_SR,GPC PGC Status Register"
hexmask.long.word 0x00 8.--17. 1. "L2RSTDIS_DEASSERT_CNT,Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up This value can't be programmed to zero (This register control only for SCU Type PGC)"
bitfld.long 0x00 3.--6. "PUP_CLK_DIV_SEL,Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC ipg_clk(66MHz) for MIX/PU Type PGC)" "0: PUP_CLK_DIV_SEL_0,1: PUP_CLK_DIV_SEL_1,2: PUP_CLK_DIV_SEL_2,3: PUP_CLK_DIV_SEL_3,4: PUP_CLK_DIV_SEL_4,5: PUP_CLK_DIV_SEL_5,6: PUP_CLK_DIV_SEL_6,7: PUP_CLK_DIV_SEL_7,8: PUP_CLK_DIV_SEL_8,9: PUP_CLK_DIV_SEL_9,10: PUP_CLK_DIV_SEL_10,11: PUP_CLK_DIV_SEL_11,12: PUP_CLK_DIV_SEL_12,13: PUP_CLK_DIV_SEL_13,14: PUP_CLK_DIV_SEL_14,15: PUP_CLK_DIV_SEL_15"
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rbitfld.long 0x00 2. "ALLOFF_FLAG,All-off flag" "0: A53 is not wakeup from ALL_OFF mode,1: A53 is wakeup from ALL_OFF mode"
rbitfld.long 0x00 1. "L2RETN_FLAG,L2 Retention Flag Software should write 1 to clear this flag after A53 is wakeup from L2 retention mode otherwise it will always keep to 1 (This register control only for SCU Type PGC)" "0: A53 is not wakeup from L2 retention mode,1: A53 is wakeup from L2 retention mode"
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rbitfld.long 0x00 0. "PSR,Power status" "0: The target subsystem was not powered down for..,1: The target subsystem was powered down for the.."
tree.end
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
repeat 5. (list 1. 2. 3. 4. 5.) (list ad:0x30200000 ad:0x30210000 ad:0x30220000 ad:0x30230000 ad:0x30240000)
tree "GPIO$1"
base $2
group.long 0x00++0x03
line.long 0x00 "DR,GPIO data register"
hexmask.long 0x00 0.--31. 1. "DR,Data bits"
group.long 0x04++0x03
line.long 0x00 "GDIR,GPIO direction register"
hexmask.long 0x00 0.--31. 1. "GDIR,GPIO direction bits"
rgroup.long 0x08++0x03
line.long 0x00 "PSR,GPIO pad status register"
hexmask.long 0x00 0.--31. 1. "PSR,GPIO pad status bits (status bits)"
group.long 0x0C++0x03
line.long 0x00 "ICR1,GPIO interrupt configuration register1"
bitfld.long 0x00 30.--31. "ICR15,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 28.--29. "ICR14,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 26.--27. "ICR13,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 24.--25. "ICR12,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 22.--23. "ICR11,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 20.--21. "ICR10,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 18.--19. "ICR9,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 16.--17. "ICR8,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 14.--15. "ICR7,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 12.--13. "ICR6,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 10.--11. "ICR5,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 8.--9. "ICR4,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 6.--7. "ICR3,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 4.--5. "ICR2,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 2.--3. "ICR1,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 0.--1. "ICR0,Interrupt configuration 1 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
group.long 0x10++0x03
line.long 0x00 "ICR2,GPIO interrupt configuration register2"
bitfld.long 0x00 30.--31. "ICR31,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 28.--29. "ICR30,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 26.--27. "ICR29,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 24.--25. "ICR28,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 22.--23. "ICR27,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 20.--21. "ICR26,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 18.--19. "ICR25,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 16.--17. "ICR24,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 14.--15. "ICR23,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 12.--13. "ICR22,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 10.--11. "ICR21,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 8.--9. "ICR20,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 6.--7. "ICR19,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 4.--5. "ICR18,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
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bitfld.long 0x00 2.--3. "ICR17,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
bitfld.long 0x00 0.--1. "ICR16,Interrupt configuration 2 fields" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
group.long 0x14++0x03
line.long 0x00 "IMR,GPIO interrupt mask register"
hexmask.long 0x00 0.--31. 1. "IMR,Interrupt Mask bits"
group.long 0x18++0x03
line.long 0x00 "ISR,GPIO interrupt status register"
hexmask.long 0x00 0.--31. 1. "ISR,Interrupt status bits - Bit n of this register is asserted (active high) when the active condition (as determined by the corresponding ICR bit) is detected on the GPIO input and is waiting for service"
group.long 0x1C++0x03
line.long 0x00 "EDGE_SEL,GPIO edge select register"
hexmask.long 0x00 0.--31. 1. "GPIO_EDGE_SEL,Edge select"
tree.end
repeat.end
tree.end
tree "GPMI (General Purpose Media Interface)"
base ad:0x33002000
group.long 0x00++0x03
line.long 0x00 "CTRL0,GPMI Control Register 0 Description"
bitfld.long 0x00 31. "SFTRST,Set to zero for normal operation" "0,1"
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bitfld.long 0x00 30. "CLKGATE,Set this bit zero for normal operation" "0,1"
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bitfld.long 0x00 29. "RUN,The GPMI is busy running a command whenever this bit is set to '1'" "0,1"
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bitfld.long 0x00 28. "DEV_IRQ_EN,When set to '1' and ATA_IRQ pin is asserted the GPMI_IRQ output will assert" "0,1"
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bitfld.long 0x00 27. "LOCK_CS,For ATA/NAND mode" "0,1"
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bitfld.long 0x00 26. "UDMA,DISABLED = 0x0 Use ATA-PIO mode on the external bus" "0: Use ATA-PIO mode on the external bus,1: Use ATA-Ultra DMA mode on the external bus"
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bitfld.long 0x00 24.--25. "COMMAND_MODE,WRITE = 0x0 Write mode" "0: COMMAND_MODE_0,1: COMMAND_MODE_1,2: Read and Compare Mode (setting sense flop),3: Wait for Ready"
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bitfld.long 0x00 23. "WORD_LENGTH,This bit should only be changed when RUN==0" "?,1: 8-bit Data Bus mode"
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bitfld.long 0x00 20.--22. "CS,Selects which chip select is active for this command" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "ADDRESS,Specifies the three address lines for ATA mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "ADDRESS_INCREMENT,In ATA mode the address will increment with each cycle" "0: Address does not increment,1: ADDRESS_INCREMENT_1"
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hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,Number of bytes to transfer for this command"
group.long 0x04++0x03
line.long 0x00 "CTRL0_SET,GPMI Control Register 0 Description"
bitfld.long 0x00 31. "SFTRST,Set to zero for normal operation" "0,1"
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bitfld.long 0x00 30. "CLKGATE,Set this bit zero for normal operation" "0,1"
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bitfld.long 0x00 29. "RUN,The GPMI is busy running a command whenever this bit is set to '1'" "0,1"
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bitfld.long 0x00 28. "DEV_IRQ_EN,When set to '1' and ATA_IRQ pin is asserted the GPMI_IRQ output will assert" "0,1"
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bitfld.long 0x00 27. "LOCK_CS,For ATA/NAND mode" "0,1"
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bitfld.long 0x00 26. "UDMA,DISABLED = 0x0 Use ATA-PIO mode on the external bus" "0: Use ATA-PIO mode on the external bus,1: Use ATA-Ultra DMA mode on the external bus"
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bitfld.long 0x00 24.--25. "COMMAND_MODE,WRITE = 0x0 Write mode" "0: COMMAND_MODE_0,1: COMMAND_MODE_1,2: Read and Compare Mode (setting sense flop),3: Wait for Ready"
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bitfld.long 0x00 23. "WORD_LENGTH,This bit should only be changed when RUN==0" "?,1: 8-bit Data Bus mode"
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bitfld.long 0x00 20.--22. "CS,Selects which chip select is active for this command" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "ADDRESS,Specifies the three address lines for ATA mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "ADDRESS_INCREMENT,In ATA mode the address will increment with each cycle" "0: Address does not increment,1: ADDRESS_INCREMENT_1"
newline
hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,Number of bytes to transfer for this command"
group.long 0x08++0x03
line.long 0x00 "CTRL0_CLR,GPMI Control Register 0 Description"
bitfld.long 0x00 31. "SFTRST,Set to zero for normal operation" "0,1"
newline
bitfld.long 0x00 30. "CLKGATE,Set this bit zero for normal operation" "0,1"
newline
bitfld.long 0x00 29. "RUN,The GPMI is busy running a command whenever this bit is set to '1'" "0,1"
newline
bitfld.long 0x00 28. "DEV_IRQ_EN,When set to '1' and ATA_IRQ pin is asserted the GPMI_IRQ output will assert" "0,1"
newline
bitfld.long 0x00 27. "LOCK_CS,For ATA/NAND mode" "0,1"
newline
bitfld.long 0x00 26. "UDMA,DISABLED = 0x0 Use ATA-PIO mode on the external bus" "0: Use ATA-PIO mode on the external bus,1: Use ATA-Ultra DMA mode on the external bus"
newline
bitfld.long 0x00 24.--25. "COMMAND_MODE,WRITE = 0x0 Write mode" "0: COMMAND_MODE_0,1: COMMAND_MODE_1,2: Read and Compare Mode (setting sense flop),3: Wait for Ready"
newline
bitfld.long 0x00 23. "WORD_LENGTH,This bit should only be changed when RUN==0" "?,1: 8-bit Data Bus mode"
newline
bitfld.long 0x00 20.--22. "CS,Selects which chip select is active for this command" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--19. "ADDRESS,Specifies the three address lines for ATA mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "ADDRESS_INCREMENT,In ATA mode the address will increment with each cycle" "0: Address does not increment,1: ADDRESS_INCREMENT_1"
newline
hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,Number of bytes to transfer for this command"
group.long 0x0C++0x03
line.long 0x00 "CTRL0_TOG,GPMI Control Register 0 Description"
bitfld.long 0x00 31. "SFTRST,Set to zero for normal operation" "0,1"
newline
bitfld.long 0x00 30. "CLKGATE,Set this bit zero for normal operation" "0,1"
newline
bitfld.long 0x00 29. "RUN,The GPMI is busy running a command whenever this bit is set to '1'" "0,1"
newline
bitfld.long 0x00 28. "DEV_IRQ_EN,When set to '1' and ATA_IRQ pin is asserted the GPMI_IRQ output will assert" "0,1"
newline
bitfld.long 0x00 27. "LOCK_CS,For ATA/NAND mode" "0,1"
newline
bitfld.long 0x00 26. "UDMA,DISABLED = 0x0 Use ATA-PIO mode on the external bus" "0: Use ATA-PIO mode on the external bus,1: Use ATA-Ultra DMA mode on the external bus"
newline
bitfld.long 0x00 24.--25. "COMMAND_MODE,WRITE = 0x0 Write mode" "0: COMMAND_MODE_0,1: COMMAND_MODE_1,2: Read and Compare Mode (setting sense flop),3: Wait for Ready"
newline
bitfld.long 0x00 23. "WORD_LENGTH,This bit should only be changed when RUN==0" "?,1: 8-bit Data Bus mode"
newline
bitfld.long 0x00 20.--22. "CS,Selects which chip select is active for this command" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--19. "ADDRESS,Specifies the three address lines for ATA mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "ADDRESS_INCREMENT,In ATA mode the address will increment with each cycle" "0: Address does not increment,1: ADDRESS_INCREMENT_1"
newline
hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,Number of bytes to transfer for this command"
group.long 0x10++0x03
line.long 0x00 "COMPARE,GPMI Compare Register Description"
hexmask.long.word 0x00 16.--31. 1. "MASK,16-bit mask which is applied after the read data is XORed with the REFERENCE bit field"
newline
hexmask.long.word 0x00 0.--15. 1. "REFERENCE,16-bit value which is XORed with data read from the NAND device"
group.long 0x20++0x03
line.long 0x00 "ECCCTRL,GPMI Integrated ECC Control Register Description"
hexmask.long.word 0x00 16.--31. 1. "HANDLE,This is a register available to software to attach an identifier to a transaction in progress"
newline
bitfld.long 0x00 15. "RSVD2,Always write zeroes to this bit field" "0,1"
newline
bitfld.long 0x00 13.--14. "ECC_CMD,ECC Command information" "0,1,2,3"
newline
bitfld.long 0x00 12. "ENABLE_ECC,Enable ECC processing of GPMI transfers" "0,1"
newline
bitfld.long 0x00 11. "RANDOMIZER_ENABLE,Enable randomizer function" "0: RANDOMIZER_ENABLE_0,1: RANDOMIZER_ENABLE_1"
newline
bitfld.long 0x00 9.--10. "RANDOMIZER_TYPE,Set randomizer type" "0: RANDOMIZER_TYPE_0,1: RANDOMIZER_TYPE_1,?..."
newline
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,ECC buffer information"
group.long 0x24++0x03
line.long 0x00 "ECCCTRL_SET,GPMI Integrated ECC Control Register Description"
hexmask.long.word 0x00 16.--31. 1. "HANDLE,This is a register available to software to attach an identifier to a transaction in progress"
newline
bitfld.long 0x00 15. "RSVD2,Always write zeroes to this bit field" "0,1"
newline
bitfld.long 0x00 13.--14. "ECC_CMD,ECC Command information" "0,1,2,3"
newline
bitfld.long 0x00 12. "ENABLE_ECC,Enable ECC processing of GPMI transfers" "0,1"
newline
bitfld.long 0x00 11. "RANDOMIZER_ENABLE,Enable randomizer function" "0: RANDOMIZER_ENABLE_0,1: RANDOMIZER_ENABLE_1"
newline
bitfld.long 0x00 9.--10. "RANDOMIZER_TYPE,Set randomizer type" "0: RANDOMIZER_TYPE_0,1: RANDOMIZER_TYPE_1,?..."
newline
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,ECC buffer information"
group.long 0x28++0x03
line.long 0x00 "ECCCTRL_CLR,GPMI Integrated ECC Control Register Description"
hexmask.long.word 0x00 16.--31. 1. "HANDLE,This is a register available to software to attach an identifier to a transaction in progress"
newline
bitfld.long 0x00 15. "RSVD2,Always write zeroes to this bit field" "0,1"
newline
bitfld.long 0x00 13.--14. "ECC_CMD,ECC Command information" "0,1,2,3"
newline
bitfld.long 0x00 12. "ENABLE_ECC,Enable ECC processing of GPMI transfers" "0,1"
newline
bitfld.long 0x00 11. "RANDOMIZER_ENABLE,Enable randomizer function" "0: RANDOMIZER_ENABLE_0,1: RANDOMIZER_ENABLE_1"
newline
bitfld.long 0x00 9.--10. "RANDOMIZER_TYPE,Set randomizer type" "0: RANDOMIZER_TYPE_0,1: RANDOMIZER_TYPE_1,?..."
newline
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,ECC buffer information"
group.long 0x2C++0x03
line.long 0x00 "ECCCTRL_TOG,GPMI Integrated ECC Control Register Description"
hexmask.long.word 0x00 16.--31. 1. "HANDLE,This is a register available to software to attach an identifier to a transaction in progress"
newline
bitfld.long 0x00 15. "RSVD2,Always write zeroes to this bit field" "0,1"
newline
bitfld.long 0x00 13.--14. "ECC_CMD,ECC Command information" "0,1,2,3"
newline
bitfld.long 0x00 12. "ENABLE_ECC,Enable ECC processing of GPMI transfers" "0,1"
newline
bitfld.long 0x00 11. "RANDOMIZER_ENABLE,Enable randomizer function" "0: RANDOMIZER_ENABLE_0,1: RANDOMIZER_ENABLE_1"
newline
bitfld.long 0x00 9.--10. "RANDOMIZER_TYPE,Set randomizer type" "0: RANDOMIZER_TYPE_0,1: RANDOMIZER_TYPE_1,?..."
newline
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,ECC buffer information"
group.long 0x30++0x03
line.long 0x00 "ECCCOUNT,GPMI Integrated ECC Transfer Count Register Description"
hexmask.long.byte 0x00 16.--23. 1. "RANDOMIZER_PAGE,Set NAND page number needed to be randomized"
newline
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of bytes to pass through ECC"
group.long 0x40++0x03
line.long 0x00 "PAYLOAD,GPMI Payload Address Register Description"
hexmask.long 0x00 2.--31. 1. "ADDRESS,Pointer to an array of one or more 512 byte payload buffers"
newline
rbitfld.long 0x00 0.--1. "RSVD0,Always write zeroes to this bit field" "0,1,2,3"
group.long 0x50++0x03
line.long 0x00 "AUXILIARY,GPMI Auxiliary Address Register Description"
hexmask.long 0x00 2.--31. 1. "ADDRESS,Pointer to ECC control structure and meta-data storage"
newline
rbitfld.long 0x00 0.--1. "RSVD0,Always write zeroes to this bit field" "0,1,2,3"
group.long 0x60++0x03
line.long 0x00 "CTRL1,GPMI Control Register 1 Description"
bitfld.long 0x00 31. "DEV_CLK_STOP,set this bit to 1 will stop gpmi io working clk" "0,1"
newline
bitfld.long 0x00 30. "SSYNC_CLK_STOP,set this bit to 1 will stop the source synchronous mode clk" "0,1"
newline
bitfld.long 0x00 29. "WRITE_CLK_STOP,In onfi source synchronous mode host may save power during the data write cycles by holding the CLK signal high (i" "0,1"
newline
bitfld.long 0x00 28. "TOGGLE_MODE,enable samsung toggle mode" "0,1"
newline
bitfld.long 0x00 27. "GPMI_CLK_DIV2_EN,This bit should be reset to 0 in asynchronous mode" "0: internal factor-2 clock divider is disabled,1: internal factor-2 clock divider is enabled"
newline
bitfld.long 0x00 26. "UPDATE_CS,force the CS value is be updated to external chip select pin even GPMI is idle" "0,1"
newline
bitfld.long 0x00 25. "SSYNCMODE,source synchronouse mode 1 or asynchrous mode 0" "0,1"
newline
bitfld.long 0x00 24. "DECOUPLE_CS,Decouple Chip Select from DMA Channel" "0,1"
newline
bitfld.long 0x00 22.--23. "WRN_DLY_SEL,Since the GPMI write strobe (WRN) is a fast clock pin the delay on this signal can be programmed to match the load on this pin" "0,1,2,3"
newline
bitfld.long 0x00 21. "TEST_TRIGGER,Test Trigger Enable" "0: TEST_TRIGGER_0,1: TEST_TRIGGER_1"
newline
bitfld.long 0x00 20. "TIMEOUT_IRQ_EN,Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and Nand mode" "0,1"
newline
bitfld.long 0x00 19. "GANGED_RDYBUSY,Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "0,1"
newline
bitfld.long 0x00 18. "BCH_MODE,This bit selects which error correction unit will access GPMI" "0,1"
newline
bitfld.long 0x00 17. "DLL_ENABLE,Set this bit to 1 to enable the GPMI DLL" "0,1"
newline
bitfld.long 0x00 16. "HALF_PERIOD,Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation" "0,1"
newline
bitfld.long 0x00 12.--15. "RDN_DELAY,This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "DMA2ECC_MODE,This is mainly for testing HWECC without involving the Nand device" "0,1"
newline
bitfld.long 0x00 10. "DEV_IRQ,This bit is set when an Interrupt is received from the ATA device" "0,1"
newline
bitfld.long 0x00 9. "TIMEOUT_IRQ,This bit is set when a timeout occurs using the Device_Busy_Timeout value" "0,1"
newline
bitfld.long 0x00 8. "BURST_EN,When set to 1 each DMA request will generate a 4-transfer burst on the APB bus" "0,1"
newline
bitfld.long 0x00 7. "ABORT_WAIT_REQUEST,Request to abort wait for ready command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL" "0,1"
newline
bitfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "DEV_RESET,ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted)" "0: NANDF_WP_B pin is held low (asserted),1: NANDF_WP_B pin is held high (de-asserted)"
newline
bitfld.long 0x00 2. "ATA_IRQRDY_POLARITY,For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit" "0: External RDY_BUSY[1] and RDY_BUSY[0] pins are..,1: External RDY_BUSY[1] and RDY_BUSY[0] pins are.."
newline
bitfld.long 0x00 1. "CAMERA_MODE,When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface" "0,1"
newline
bitfld.long 0x00 0. "GPMI_MODE,ATA mode is only supported on channel zero" "0: GPMI_MODE_0,1: GPMI_MODE_1"
group.long 0x64++0x03
line.long 0x00 "CTRL1_SET,GPMI Control Register 1 Description"
bitfld.long 0x00 31. "DEV_CLK_STOP,set this bit to 1 will stop gpmi io working clk" "0,1"
newline
bitfld.long 0x00 30. "SSYNC_CLK_STOP,set this bit to 1 will stop the source synchronous mode clk" "0,1"
newline
bitfld.long 0x00 29. "WRITE_CLK_STOP,In onfi source synchronous mode host may save power during the data write cycles by holding the CLK signal high (i" "0,1"
newline
bitfld.long 0x00 28. "TOGGLE_MODE,enable samsung toggle mode" "0,1"
newline
bitfld.long 0x00 27. "GPMI_CLK_DIV2_EN,This bit should be reset to 0 in asynchronous mode" "0: internal factor-2 clock divider is disabled,1: internal factor-2 clock divider is enabled"
newline
bitfld.long 0x00 26. "UPDATE_CS,force the CS value is be updated to external chip select pin even GPMI is idle" "0,1"
newline
bitfld.long 0x00 25. "SSYNCMODE,source synchronouse mode 1 or asynchrous mode 0" "0,1"
newline
bitfld.long 0x00 24. "DECOUPLE_CS,Decouple Chip Select from DMA Channel" "0,1"
newline
bitfld.long 0x00 22.--23. "WRN_DLY_SEL,Since the GPMI write strobe (WRN) is a fast clock pin the delay on this signal can be programmed to match the load on this pin" "0,1,2,3"
newline
bitfld.long 0x00 21. "TEST_TRIGGER,Test Trigger Enable" "0: TEST_TRIGGER_0,1: TEST_TRIGGER_1"
newline
bitfld.long 0x00 20. "TIMEOUT_IRQ_EN,Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and Nand mode" "0,1"
newline
bitfld.long 0x00 19. "GANGED_RDYBUSY,Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "0,1"
newline
bitfld.long 0x00 18. "BCH_MODE,This bit selects which error correction unit will access GPMI" "0,1"
newline
bitfld.long 0x00 17. "DLL_ENABLE,Set this bit to 1 to enable the GPMI DLL" "0,1"
newline
bitfld.long 0x00 16. "HALF_PERIOD,Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation" "0,1"
newline
bitfld.long 0x00 12.--15. "RDN_DELAY,This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "DMA2ECC_MODE,This is mainly for testing HWECC without involving the Nand device" "0,1"
newline
bitfld.long 0x00 10. "DEV_IRQ,This bit is set when an Interrupt is received from the ATA device" "0,1"
newline
bitfld.long 0x00 9. "TIMEOUT_IRQ,This bit is set when a timeout occurs using the Device_Busy_Timeout value" "0,1"
newline
bitfld.long 0x00 8. "BURST_EN,When set to 1 each DMA request will generate a 4-transfer burst on the APB bus" "0,1"
newline
bitfld.long 0x00 7. "ABORT_WAIT_REQUEST,Request to abort wait for ready command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL" "0,1"
newline
bitfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "DEV_RESET,ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted)" "0: NANDF_WP_B pin is held low (asserted),1: NANDF_WP_B pin is held high (de-asserted)"
newline
bitfld.long 0x00 2. "ATA_IRQRDY_POLARITY,For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit" "0: External RDY_BUSY[1] and RDY_BUSY[0] pins are..,1: External RDY_BUSY[1] and RDY_BUSY[0] pins are.."
newline
bitfld.long 0x00 1. "CAMERA_MODE,When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface" "0,1"
newline
bitfld.long 0x00 0. "GPMI_MODE,ATA mode is only supported on channel zero" "0: GPMI_MODE_0,1: GPMI_MODE_1"
group.long 0x68++0x03
line.long 0x00 "CTRL1_CLR,GPMI Control Register 1 Description"
bitfld.long 0x00 31. "DEV_CLK_STOP,set this bit to 1 will stop gpmi io working clk" "0,1"
newline
bitfld.long 0x00 30. "SSYNC_CLK_STOP,set this bit to 1 will stop the source synchronous mode clk" "0,1"
newline
bitfld.long 0x00 29. "WRITE_CLK_STOP,In onfi source synchronous mode host may save power during the data write cycles by holding the CLK signal high (i" "0,1"
newline
bitfld.long 0x00 28. "TOGGLE_MODE,enable samsung toggle mode" "0,1"
newline
bitfld.long 0x00 27. "GPMI_CLK_DIV2_EN,This bit should be reset to 0 in asynchronous mode" "0: internal factor-2 clock divider is disabled,1: internal factor-2 clock divider is enabled"
newline
bitfld.long 0x00 26. "UPDATE_CS,force the CS value is be updated to external chip select pin even GPMI is idle" "0,1"
newline
bitfld.long 0x00 25. "SSYNCMODE,source synchronouse mode 1 or asynchrous mode 0" "0,1"
newline
bitfld.long 0x00 24. "DECOUPLE_CS,Decouple Chip Select from DMA Channel" "0,1"
newline
bitfld.long 0x00 22.--23. "WRN_DLY_SEL,Since the GPMI write strobe (WRN) is a fast clock pin the delay on this signal can be programmed to match the load on this pin" "0,1,2,3"
newline
bitfld.long 0x00 21. "TEST_TRIGGER,Test Trigger Enable" "0: TEST_TRIGGER_0,1: TEST_TRIGGER_1"
newline
bitfld.long 0x00 20. "TIMEOUT_IRQ_EN,Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and Nand mode" "0,1"
newline
bitfld.long 0x00 19. "GANGED_RDYBUSY,Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "0,1"
newline
bitfld.long 0x00 18. "BCH_MODE,This bit selects which error correction unit will access GPMI" "0,1"
newline
bitfld.long 0x00 17. "DLL_ENABLE,Set this bit to 1 to enable the GPMI DLL" "0,1"
newline
bitfld.long 0x00 16. "HALF_PERIOD,Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation" "0,1"
newline
bitfld.long 0x00 12.--15. "RDN_DELAY,This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "DMA2ECC_MODE,This is mainly for testing HWECC without involving the Nand device" "0,1"
newline
bitfld.long 0x00 10. "DEV_IRQ,This bit is set when an Interrupt is received from the ATA device" "0,1"
newline
bitfld.long 0x00 9. "TIMEOUT_IRQ,This bit is set when a timeout occurs using the Device_Busy_Timeout value" "0,1"
newline
bitfld.long 0x00 8. "BURST_EN,When set to 1 each DMA request will generate a 4-transfer burst on the APB bus" "0,1"
newline
bitfld.long 0x00 7. "ABORT_WAIT_REQUEST,Request to abort wait for ready command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL" "0,1"
newline
bitfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "DEV_RESET,ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted)" "0: NANDF_WP_B pin is held low (asserted),1: NANDF_WP_B pin is held high (de-asserted)"
newline
bitfld.long 0x00 2. "ATA_IRQRDY_POLARITY,For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit" "0: External RDY_BUSY[1] and RDY_BUSY[0] pins are..,1: External RDY_BUSY[1] and RDY_BUSY[0] pins are.."
newline
bitfld.long 0x00 1. "CAMERA_MODE,When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface" "0,1"
newline
bitfld.long 0x00 0. "GPMI_MODE,ATA mode is only supported on channel zero" "0: GPMI_MODE_0,1: GPMI_MODE_1"
group.long 0x6C++0x03
line.long 0x00 "CTRL1_TOG,GPMI Control Register 1 Description"
bitfld.long 0x00 31. "DEV_CLK_STOP,set this bit to 1 will stop gpmi io working clk" "0,1"
newline
bitfld.long 0x00 30. "SSYNC_CLK_STOP,set this bit to 1 will stop the source synchronous mode clk" "0,1"
newline
bitfld.long 0x00 29. "WRITE_CLK_STOP,In onfi source synchronous mode host may save power during the data write cycles by holding the CLK signal high (i" "0,1"
newline
bitfld.long 0x00 28. "TOGGLE_MODE,enable samsung toggle mode" "0,1"
newline
bitfld.long 0x00 27. "GPMI_CLK_DIV2_EN,This bit should be reset to 0 in asynchronous mode" "0: internal factor-2 clock divider is disabled,1: internal factor-2 clock divider is enabled"
newline
bitfld.long 0x00 26. "UPDATE_CS,force the CS value is be updated to external chip select pin even GPMI is idle" "0,1"
newline
bitfld.long 0x00 25. "SSYNCMODE,source synchronouse mode 1 or asynchrous mode 0" "0,1"
newline
bitfld.long 0x00 24. "DECOUPLE_CS,Decouple Chip Select from DMA Channel" "0,1"
newline
bitfld.long 0x00 22.--23. "WRN_DLY_SEL,Since the GPMI write strobe (WRN) is a fast clock pin the delay on this signal can be programmed to match the load on this pin" "0,1,2,3"
newline
bitfld.long 0x00 21. "TEST_TRIGGER,Test Trigger Enable" "0: TEST_TRIGGER_0,1: TEST_TRIGGER_1"
newline
bitfld.long 0x00 20. "TIMEOUT_IRQ_EN,Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only and for WAIT_FOR_READY commands in both ATA and Nand mode" "0,1"
newline
bitfld.long 0x00 19. "GANGED_RDYBUSY,Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "0,1"
newline
bitfld.long 0x00 18. "BCH_MODE,This bit selects which error correction unit will access GPMI" "0,1"
newline
bitfld.long 0x00 17. "DLL_ENABLE,Set this bit to 1 to enable the GPMI DLL" "0,1"
newline
bitfld.long 0x00 16. "HALF_PERIOD,Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation" "0,1"
newline
bitfld.long 0x00 12.--15. "RDN_DELAY,This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "DMA2ECC_MODE,This is mainly for testing HWECC without involving the Nand device" "0,1"
newline
bitfld.long 0x00 10. "DEV_IRQ,This bit is set when an Interrupt is received from the ATA device" "0,1"
newline
bitfld.long 0x00 9. "TIMEOUT_IRQ,This bit is set when a timeout occurs using the Device_Busy_Timeout value" "0,1"
newline
bitfld.long 0x00 8. "BURST_EN,When set to 1 each DMA request will generate a 4-transfer burst on the APB bus" "0,1"
newline
bitfld.long 0x00 7. "ABORT_WAIT_REQUEST,Request to abort wait for ready command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL" "0,1"
newline
bitfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "DEV_RESET,ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted)" "0: NANDF_WP_B pin is held low (asserted),1: NANDF_WP_B pin is held high (de-asserted)"
newline
bitfld.long 0x00 2. "ATA_IRQRDY_POLARITY,For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit" "0: External RDY_BUSY[1] and RDY_BUSY[0] pins are..,1: External RDY_BUSY[1] and RDY_BUSY[0] pins are.."
newline
bitfld.long 0x00 1. "CAMERA_MODE,When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface" "0,1"
newline
bitfld.long 0x00 0. "GPMI_MODE,ATA mode is only supported on channel zero" "0: GPMI_MODE_0,1: GPMI_MODE_1"
group.long 0x70++0x03
line.long 0x00 "TIMING0,GPMI Timing Register 0 Description"
hexmask.long.byte 0x00 24.--31. 1. "RSVD1,Always write zeroes to this bit field"
newline
hexmask.long.byte 0x00 16.--23. 1. "ADDRESS_SETUP,Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted"
newline
hexmask.long.byte 0x00 8.--15. 1. "DATA_HOLD,Data bus hold time in GPMICLK cycles"
newline
hexmask.long.byte 0x00 0.--7. 1. "DATA_SETUP,Data bus setup time in GPMICLK cycles"
group.long 0x80++0x03
line.long 0x00 "TIMING1,GPMI Timing Register 1 Description"
hexmask.long.word 0x00 16.--31. 1. "DEVICE_BUSY_TIMEOUT,Timeout waiting for NAND Ready/Busy or ATA IRQ"
newline
hexmask.long.word 0x00 0.--15. 1. "RSVD1,Always write zeroes to this bit field"
group.long 0x90++0x03
line.long 0x00 "TIMING2,GPMI Timing Register 2 Description"
bitfld.long 0x00 29.--31. "TRPSTH,Only for Toggle NAND timing control delay TRPSTH GPMICLK cycles for CEn_B high to RE_B high A value of zero is interpreted as 8" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 27.--28. "TCR,Only for Toggle NAND timing control delay (TCR+1) GPMICLK cycles for CEn_B low to RE_B low 0 is less than or equal to TCR which is less than the PREAMBLE_DELAY" "0,1,2,3"
newline
bitfld.long 0x00 24.--26. "READ_LATENCY,This field is for double data rate read latency configuration" "0: READ LATENCY is 0,1: READ LATENCY is 1,2: READ LATENCY is 2,3: READ LATENCY is 3,4: READ LATENCY is 4,5: READ LATENCY is 5,?..."
newline
rbitfld.long 0x00 21.--23. "RSVD0,Always write zeroes to this bit field" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--20. "CE_DELAY,GPMI dealy from CEn assert to W/Rn changing edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12.--15. "PREAMBLE_DELAY,GPMI pre-amble delay in GPMICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "POSTAMBLE_DELAY,GPMI post-amble delay in GPMICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "CMDADD_PAUSE,GPMI delay time from command or addres pause to command or address resume in GPMICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DATA_PAUSE,GPMI delay time from data pause to data resume in GPMICLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x03
line.long 0x00 "DATA,GPMI DMA Data Transfer Register Description"
hexmask.long 0x00 0.--31. 1. "DATA,In 8-bit mode one two three or four bytes can can be accessed to send the same number of bus cycles"
rgroup.long 0xB0++0x03
line.long 0x00 "STAT,GPMI Status Register Description"
hexmask.long.byte 0x00 24.--31. 1. "READY_BUSY,Read-only view of NAND Ready_Busy Input pins"
newline
hexmask.long.byte 0x00 16.--23. 1. "RDY_TIMEOUT,State of the RDY/BUSY Timeout Flags"
newline
bitfld.long 0x00 15. "DEV7_ERROR,DMA channel 7 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 14. "DEV6_ERROR,DMA channel 6 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 13. "DEV5_ERROR,DMA channel 5 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 12. "DEV4_ERROR,DMA channel 4 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 11. "DEV3_ERROR,DMA channel 3 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 10. "DEV2_ERROR,DMA channel 2 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 9. "DEV1_ERROR,DMA channel 1 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 8. "DEV0_ERROR,DMA channel 0 (Timeout or compare failure depending on COMMAND_MODE)" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
newline
bitfld.long 0x00 5.--7. "RSVD1,Always write zeroes to this bit field" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "ATA_IRQ,Status of the ATA_IRQ input pin" "0,1"
newline
bitfld.long 0x00 3. "INVALID_BUFFER_MASK,Buffer Mask Validity bit" "0: ECC Buffer Mask is not invalid,1: ECC Buffer Mask is invalid"
newline
bitfld.long 0x00 2. "FIFO_EMPTY,NOT_EMPTY = 0x0 FIFO is not empty" "0: FIFO is not empty,1: FIFO is empty"
newline
bitfld.long 0x00 1. "FIFO_FULL,NOT_FULL = 0x0 FIFO is not full" "0: FIFO is not full,1: FIFO is full"
newline
bitfld.long 0x00 0. "PRESENT,UNAVAILABLE = 0x0 GPMI is not present in this product" "0: GPMI is not present in this product,1: GPMI is present is in this product"
rgroup.long 0xC0++0x03
line.long 0x00 "DEBUG,GPMI Debug Information Register Description"
hexmask.long.byte 0x00 24.--31. 1. "WAIT_FOR_READY_END,Read Only view of the Wait_For_Ready End toggle signals to DMA"
newline
hexmask.long.byte 0x00 16.--23. 1. "DMA_SENSE,Read-only view of sense state of the 8 DMA channels"
newline
hexmask.long.byte 0x00 8.--15. 1. "DMAREQ,Read-only view of DMA request line for 8 DMA channels"
newline
hexmask.long.byte 0x00 0.--7. 1. "CMD_END,Read Only view of the Command End toggle signals to DMA"
rgroup.long 0xD0++0x03
line.long 0x00 "VERSION,GPMI Version Register Description"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value reflecting the MAJOR field of the RTL version"
newline
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value reflecting the MINOR field of the RTL version"
newline
hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the RTL version"
group.long 0xE0++0x03
line.long 0x00 "DEBUG2,GPMI Debug2 Information Register Description"
bitfld.long 0x00 28.--31. "RSVD1,Always write zeroes to this bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 24.--27. "UDMA_STATE,USM_IDLE = 4'h0 idle USM_DMARQ = 4'h1 DMA req USM_ACK = 4'h2 DMA ACK USM_FIFO_E = 4'h3 Fifo empty USM_WPAUSE = 4'h4 WR DMA Paused by device USM_TSTRB = 4'h5 Toggle HSTROBE USM_CAPTUR = 4'h6 Capture Stage (data sampled with DSTROBE is valid).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 23. "BUSY,When asserted the GPMI is busy" "0,1"
newline
rbitfld.long 0x00 20.--22. "PIN_STATE,parameter PSM_IDLE = 3'h0 PSM_BYTCNT = 3'h1 PSM_ADDR = 3'h2 PSM_STALL = 3'h3 PSM_STROBE = 3'h4 PSM_ATARDY = 3'h5 PSM_DHOLD = 3'h6 PSM_DONE = 3'h7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 16.--19. "MAIN_STATE,parameter MSM_IDLE = 4'h0 MSM_BYTCNT = 4'h1 MSM_WAITFE = 4'h2 MSM_WAITFR = 4'h3 MSM_DMAREQ = 4'h4 MSM_DMAACK = 4'h5 MSM_WAITFF = 4'h6 MSM_LDFIFO = 4'h7 MSM_LDDMAR = 4'h8 MSM_RDCMP = 4'h9 MSM_DONE = 4'hA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 12.--15. "SYND2GPMI_BE,Data byte enable Input from BCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 11. "GPMI2SYND_VALID,Data handshake output to BCH" "0,1"
newline
rbitfld.long 0x00 10. "GPMI2SYND_READY,Data handshake output to BCH" "0,1"
newline
rbitfld.long 0x00 9. "SYND2GPMI_VALID,Data handshake Input from BCH" "0,1"
newline
rbitfld.long 0x00 8. "SYND2GPMI_READY,Data handshake Input from BCH" "0,1"
newline
bitfld.long 0x00 7. "VIEW_DELAYED_RDN,Set to a 1 to select the delayed feedback RE_B to drive the GPMI_ADDR[0] (Nand CLE) pin" "0,1"
newline
rbitfld.long 0x00 6. "UPDATE_WINDOW,A 1 indicates that the DLL is busy generating the required delay" "0,1"
newline
rbitfld.long 0x00 0.--5. "RDN_TAP,This is the DLL tap calculated by the DLL controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xF0++0x03
line.long 0x00 "DEBUG3,GPMI Debug3 Information Register Description"
hexmask.long.word 0x00 16.--31. 1. "APB_WORD_CNTR,Reflects the number of bytes remains to be transferred on the APB bus"
newline
hexmask.long.word 0x00 0.--15. 1. "DEV_WORD_CNTR,Reflects the number of bytes remains to be transferred on the ATA/Nand bus"
group.long 0x100++0x03
line.long 0x00 "READ_DDR_DLL_CTRL,GPMI Double Rate Read DLL Control Register Description"
bitfld.long 0x00 28.--31. "REF_UPDATE_INT,This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 20.--27. 1. "SLV_UPDATE_INT,Setting a value greater than 0 in this field shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles"
newline
rbitfld.long 0x00 18.--19. "RSVD1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x00 10.--17. 1. "SLV_OVERRIDE_VAL,When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually"
newline
bitfld.long 0x00 9. "SLV_OVERRIDE,Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL to set 0 to disable manual override" "0,1"
newline
bitfld.long 0x00 8. "REFCLK_ON,set this bit to 1 will turn on the reference clock" "0,1"
newline
bitfld.long 0x00 7. "GATE_UPDATE,Setting this bit to 1 forces the slave delay line not update" "0,1"
newline
bitfld.long 0x00 3.--6. "SLV_DLY_TARGET,The delay target for the read clock is can be programmed in 1/16th increments of an GPMICLK half-period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "SLV_FORCE_UPD,Setting this bit to 1 forces the slave delay line to update to the DLL calibrated value immediately" "0,1"
newline
bitfld.long 0x00 1. "RESET,Setting this bit to 1 force a reset on DLL" "0,1"
newline
bitfld.long 0x00 0. "ENABLE,Set this bit to 1 to enable the DLL and delay chain otherwise set to 0 to bypasses DLL" "0,1"
group.long 0x110++0x03
line.long 0x00 "WRITE_DDR_DLL_CTRL,GPMI Double Rate Write DLL Control Register Description"
bitfld.long 0x00 28.--31. "REF_UPDATE_INT,This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 20.--27. 1. "SLV_UPDATE_INT,Setting a value greater than 0 in this field shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles"
newline
rbitfld.long 0x00 18.--19. "RSVD1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x00 10.--17. 1. "SLV_OVERRIDE_VAL,When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually"
newline
bitfld.long 0x00 9. "SLV_OVERRIDE,Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL to set 0 to disable manual override" "0,1"
newline
bitfld.long 0x00 8. "REFCLK_ON,set this bit to 1 will turn on the reference clock" "0,1"
newline
bitfld.long 0x00 7. "GATE_UPDATE,Setting this bit to 1 forces the slave delay line not update" "0,1"
newline
bitfld.long 0x00 3.--6. "SLV_DLY_TARGET,The delay target for the read clock can be programmed in 1/16th increments of an GPMICLK half-period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "SLV_FORCE_UPD,Setting this bit to 1 forces the slave delay line to update to the DLL calibrated value immediately" "0,1"
newline
bitfld.long 0x00 1. "RESET,Setting this bit to 1 force a reset on DLL" "0,1"
newline
bitfld.long 0x00 0. "ENABLE,Set this bit to 1 to enable the DLL and delay chain otherwise set to 0 to bypasses DLL" "0,1"
rgroup.long 0x120++0x03
line.long 0x00 "READ_DDR_DLL_STS,GPMI Double Rate Read DLL Status Register Description"
hexmask.long.byte 0x00 25.--31. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 17.--24. 1. "REF_SEL,Reference delay line select status"
newline
bitfld.long 0x00 16. "REF_LOCK,Reference DLL lock status" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x00 1.--8. 1. "SLV_SEL,Slave delay line select status"
newline
bitfld.long 0x00 0. "SLV_LOCK,Slave delay-line lock status" "0,1"
rgroup.long 0x130++0x03
line.long 0x00 "WRITE_DDR_DLL_STS,GPMI Double Rate Write DLL Status Register Description"
hexmask.long.byte 0x00 25.--31. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 17.--24. 1. "REF_SEL,Reference delay line select status"
newline
bitfld.long 0x00 16. "REF_LOCK,Reference DLL lock status" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x00 1.--8. 1. "SLV_SEL,Slave delay line select status"
newline
bitfld.long 0x00 0. "SLV_LOCK,Slave delay-line lock status" "0,1"
tree.end
tree "GPT (General Purpose Timer)"
repeat 6. (list 1. 2. 3. 4. 5. 6.) (list ad:0x302D0000 ad:0x302E0000 ad:0x302F0000 ad:0x30700000 ad:0x306F0000 ad:0x306E0000)
tree "GPT$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CR,GPT Control Register"
bitfld.long 0x00 31. "FO3,FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)" "0: Writing a 0 has no effect,1: Causes the programmed pin action on the timer.."
bitfld.long 0x00 30. "FO2,See F03" "0,1"
newline
bitfld.long 0x00 29. "FO1,See F03" "0,1"
bitfld.long 0x00 26.--28. "OM3,OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode" "0: Output disconnected,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate an active low pulse (that is one..,5: Generate an active low pulse (that is one..,6: Generate an active low pulse (that is one..,7: Generate an active low pulse (that is one.."
newline
bitfld.long 0x00 23.--25. "OM2,See OM3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "OM1,See OM3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 18.--19. "IM2,IM2 (bits 19-18 Input Capture Channel 2 operating mode) IM1 (bits 17-16 Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n) which will trigger a capture event" "0: capture disabled,1: capture on rising edge only,2: capture on falling edge only,3: capture on both edges"
bitfld.long 0x00 16.--17. "IM1,See IM2" "0,1,2,3"
newline
bitfld.long 0x00 15. "SWR,Software reset" "0: GPT is not in reset state,1: GPT is in reset state"
bitfld.long 0x00 10. "EN_24M,Enable 24 MHz clock input from crystal" "0: 24M clock disabled,1: 24M clock enabled"
newline
bitfld.long 0x00 9. "FRR,Free-Run or Restart mode" "0: Restart mode,1: Free-Run mode"
bitfld.long 0x00 6.--8. "CLKSRC,Clock Source select" "0: CLKSRC_0,1: Peripheral Clock (ipg_clk),2: High Frequency Reference Clock..,3: External Clock,4: Low Frequency Reference Clock (ipg_clk_32k),5: Crystal oscillator as Reference Clock..,?..."
newline
bitfld.long 0x00 5. "STOPEN,GPT Stop Mode enable" "0: GPT is disabled in Stop mode,1: GPT is enabled in Stop mode"
bitfld.long 0x00 4. "DOZEEN,GPT Doze Mode Enable" "0: GPT is disabled in doze mode,1: GPT is enabled in doze mode"
newline
bitfld.long 0x00 3. "WAITEN,GPT Wait Mode enable" "0: GPT is disabled in wait mode,1: GPT is enabled in wait mode"
bitfld.long 0x00 2. "DBGEN,GPT debug mode enable" "0: GPT is disabled in debug mode,1: GPT is enabled in debug mode"
newline
bitfld.long 0x00 1. "ENMOD,GPT Enable mode" "0: GPT counter will retain its value when it is..,1: GPT counter value is reset to 0 when it is.."
bitfld.long 0x00 0. "EN,GPT Enable" "0: GPT is disabled,1: GPT is enabled"
group.long 0x04++0x03
line.long 0x00 "PR,GPT Prescaler Register"
bitfld.long 0x00 12.--15. "PRESCALER24M,Prescaler bits" "0: PRESCALER24M_0,1: PRESCALER24M_1,?,?,?,?,?,?,?,?,?,?,?,?,?,15: PRESCALER24M_15"
hexmask.long.word 0x00 0.--11. 1. "PRESCALER,Prescaler bits"
group.long 0x08++0x03
line.long 0x00 "SR,GPT Status Register"
eventfld.long 0x00 5. "ROV,Rollover Flag" "0: Rollover has not occurred,1: Rollover has occurred"
eventfld.long 0x00 4. "IF2,IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n" "0: Capture event has not occurred,1: Capture event has occurred"
newline
eventfld.long 0x00 3. "IF1,See IF2" "0,1"
eventfld.long 0x00 2. "OF3,OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n" "0: Compare event has not occurred,1: Compare event has occurred"
newline
eventfld.long 0x00 1. "OF2,See OF3" "0,1"
eventfld.long 0x00 0. "OF1,See OF3" "0,1"
group.long 0x0C++0x03
line.long 0x00 "IR,GPT Interrupt Register"
bitfld.long 0x00 5. "ROVIE,Rollover Interrupt Enable" "0: Rollover interrupt is disabled,1: Rollover interrupt enabled"
bitfld.long 0x00 4. "IF2IE,IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable" "0: IF2IE Input Capture n Interrupt Enable is..,1: IF2IE Input Capture n Interrupt Enable is.."
newline
bitfld.long 0x00 3. "IF1IE,See IF2IE" "0,1"
bitfld.long 0x00 2. "OF3IE,OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt" "0: Output Compare Channel n interrupt is disabled,1: Output Compare Channel n interrupt is enabled"
newline
bitfld.long 0x00 1. "OF2IE,See OF3IE" "0,1"
bitfld.long 0x00 0. "OF1IE,See OF3IE" "0,1"
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
group.long ($2+0x10)++0x03
line.long 0x00 "OCR$1,GPT Output Compare Register $1"
hexmask.long 0x00 0.--31. 1. "COMP,Compare Value"
repeat.end
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
rgroup.long ($2+0x1C)++0x03
line.long 0x00 "ICR$1,GPT Input Capture Register $1"
hexmask.long 0x00 0.--31. 1. "CAPT,Capture Value"
repeat.end
rgroup.long 0x24++0x03
line.long 0x00 "CNT,GPT Counter Register"
hexmask.long 0x00 0.--31. 1. "COUNT,Counter Value"
tree.end
repeat.end
tree.end
tree "HDCP"
tree "HDCP"
base ad:0x32FDD000
group.byte 0x00++0x00
line.byte 0x00 "a_hdcpcfg0,HDCP Enable and Functional Control Configuration Register 0"
bitfld.byte 0x00 7. "ELVena,Enables the Enhanced Link Verification from the transmitter's side" "0,1"
bitfld.byte 0x00 6. "I2Cfastmode,Enable the I2C fast mode option from the transmitter's side" "0,1"
newline
bitfld.byte 0x00 5. "bypencryption,Bypasses all the data encryption stages" "0,1"
bitfld.byte 0x00 4. "syncricheck,Configures if the Ri check should be done at every 2s even or synchronously to every 128 encrypted frame" "0,1"
newline
rbitfld.byte 0x00 3. "avmute,This register holds the current AVMUTE state of the DWC_hdmi_tx controller as expected to be perceived by the connected HDMI/HDCP sink device" "0,1"
bitfld.byte 0x00 2. "rxdetect,Information that a sink device was detected connected to the HDMI port" "0,1"
newline
bitfld.byte 0x00 1. "en11feature,Enable the use of features 1" "0,1"
bitfld.byte 0x00 0. "hdmidvi,Configures the transmitter to operate with a HDMI capable device or with a DVI device" "0,1"
group.byte 0x01++0x00
line.byte 0x00 "a_hdcpcfg1,HDCP Software Reset and Functional Control Configuration Register 1"
bitfld.byte 0x00 5.--7. "spare,Reserved as spare register with no associated functionality" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 4. "hdcp_lock,Lock the HDCP bypass and encryption disable mechanisms" "0,1"
newline
bitfld.byte 0x00 3. "dissha1check,Disables the request to the API processor to verify the SHA1 message digest of a received KSV List" "0,1"
bitfld.byte 0x00 2. "ph2upshftenc,Enables the encoding of packet header in the tmdsch0 bit[0] with cipher[2] instead of the tmdsch0 bit[2] Note: This bit must always be set to 1 for all PHYs (PHY GEN1 PHY GEN2 and non-Synopsys PHY)" "0,1"
newline
bitfld.byte 0x00 1. "encryptiondisable,Disable encryption without losing authentication" "0,1"
bitfld.byte 0x00 0. "swreset,Software reset signal active by writing a zero and auto cleared to 1 in the following cycle" "0,1"
rgroup.byte 0x02++0x00
line.byte 0x00 "a_hdcpobs0,HDCP Observation Register 0"
bitfld.byte 0x00 4.--7. "STATEA,Observability register informs in which state the authentication machine is on" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 1.--3. "SUBSTATEA,Observability register informs in which sub-state the authentication is on" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0. "hdcpengaged,Informs that the current HDMI link has the HDCP protocol fully engaged" "0,1"
rgroup.byte 0x03++0x00
line.byte 0x00 "a_hdcpobs1,HDCP Observation Register 1"
bitfld.byte 0x00 4.--6. "STATEOEG,Observability register informs in which state the OESS machine is on" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--3. "STATER,Observability register informs in which state the revocation machine is on" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x04++0x00
line.byte 0x00 "a_hdcpobs2,HDCP Observation Register 2"
bitfld.byte 0x00 3.--5. "STATEE,Observability register informs in which state the cipher machine is on" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "STATEEEG,Observability register informs in which state the EESS machine is on" "0,1,2,3,4,5,6,7"
rgroup.byte 0x05++0x00
line.byte 0x00 "a_hdcpobs3,HDCP Observation Register 3"
bitfld.byte 0x00 7. "HDMI_RESERVED_1,Register read from attached sink device: Bcap(0x40) bit 7" "0,1"
bitfld.byte 0x00 6. "REPEATER,Register read from attached sink device: Bcap(0x40) bit 6" "0,1"
newline
bitfld.byte 0x00 5. "KSV_FIFO_READY,Register read from attached sink device: Bcap(0x40) bit 5" "0,1"
bitfld.byte 0x00 4. "FAST_I2C,Register read from attached sink device: Bcap(0x40) bit 4" "0,1"
newline
bitfld.byte 0x00 3. "HDMI_RESERVED_2,Register read from attached sink device: Bstatus(0x41) bit 13" "0,1"
bitfld.byte 0x00 2. "HDMI_MODE,Register read from attached sink device: Bstatus(0x41) bit 12" "0,1"
newline
bitfld.byte 0x00 1. "FEATURES_1_1,Register read from attached sink device: Bcap(0x40) bit 1" "0,1"
bitfld.byte 0x00 0. "FAST_REAUTHENTICATION,Register read from attached sink device: Bcap(0x40) bit 0" "0,1"
wgroup.byte 0x06++0x00
line.byte 0x00 "a_apiintclr,HDCP Interrupt Clear Register Write only register active high and auto cleared cleans the respective interruption in the interrupt status register"
bitfld.byte 0x00 7. "HDCP_engaged,Clears the interruption related to HDCP authentication process successful" "0,1"
bitfld.byte 0x00 6. "HDCP_failed,Clears the interruption related to HDCP authentication process failed" "0,1"
newline
bitfld.byte 0x00 5. "KSVsha1calcdoneint,Clears the interruption related to SHA1 verification has been done" "0,1"
bitfld.byte 0x00 4. "I2Cnack,Clears the interruption related to I2C NACK reception" "0,1"
newline
bitfld.byte 0x00 3. "Lostarbitration,Clears the interruption related to I2C arbitration lost" "0,1"
bitfld.byte 0x00 2. "Keepouterrorint,Clears the interruption related to keep out window error" "0,1"
newline
bitfld.byte 0x00 0. "KSVaccessint,Clears the interruption related to KSV memory access grant for Read-Write access" "0,1"
rgroup.byte 0x07++0x00
line.byte 0x00 "a_apiintstat,HDCP Interrupt Status Register Read only register reports the interruption which caused the activation of the interruption output pin"
bitfld.byte 0x00 7. "HDCP_engaged,Notifies that the HDCP authentication process was successful" "0,1"
bitfld.byte 0x00 6. "HDCP_failed,Notifies that the HDCP authentication process was failed" "0,1"
newline
bitfld.byte 0x00 5. "KSVsha1calcdoneint,Notifies that the HDCP13TCTRL block SHA1 verification has been done" "0,1"
bitfld.byte 0x00 4. "I2Cnack,Notifies that the I2C received a NACK from slave device" "0,1"
newline
bitfld.byte 0x00 3. "Lostarbitration,Notifies that the I2C lost the arbitration to communicate" "0,1"
bitfld.byte 0x00 2. "Keepouterrorint,Notifies that during the keep out window the ctlout[3:0] bus was used besides control period" "0,1"
newline
bitfld.byte 0x00 0. "KSVaccessint,Notifies that the KSV memory access as been guaranteed for Read-Write access" "0,1"
group.byte 0x08++0x00
line.byte 0x00 "a_apiintmsk,HDCP Interrupt Mask Register The configuration of this register mask a given setup of interruption disabling them from generating interruption pulses in the interruption output pin"
bitfld.byte 0x00 7. "HDCP_engaged,Masks the interruption related to HDCP authentication process successful" "0,1"
bitfld.byte 0x00 6. "HDCP_failed,Masks the interruption related to HDCP authentication process failed" "0,1"
newline
bitfld.byte 0x00 5. "KSVsha1calcdoneint,Masks the interruption related to SHA1 verification has been done" "0,1"
bitfld.byte 0x00 4. "I2Cnack,Masks the interruption related to I2C NACK reception" "0,1"
newline
bitfld.byte 0x00 3. "Lostarbitration,Masks the interruption related to I2C arbitration lost" "0,1"
bitfld.byte 0x00 2. "Keepouterrorint,Masks the interruption related to keep out window error" "0,1"
newline
bitfld.byte 0x00 1. "spare,Reserved as spare register with no associated functionality" "0,1"
bitfld.byte 0x00 0. "KSVaccessint,Masks the interruption related to KSV memory access grant for Read-Write access" "0,1"
group.byte 0x09++0x00
line.byte 0x00 "a_vidpolcfg,HDCP Video Polarity Configuration Register"
bitfld.byte 0x00 5.--6. "unencryptconf,Configuration of the color sent when sending unencrypted video data For a complete table showing the color results (RGB) refer to the Color Configuration When Sending Unencrypted Video Data figure in Chapter 2 Functional Description" "0,1,2,3"
bitfld.byte 0x00 4. "dataenpol,Configuration of the video data enable polarity" "0,1"
newline
bitfld.byte 0x00 3. "vsyncpol,Configuration of the video Vertical synchronism polarity" "0,1"
bitfld.byte 0x00 2. "spare_2,Reserved as spare bit with no associated functionality" "0,1"
newline
bitfld.byte 0x00 1. "hsyncpol,Configuration of the video Horizontal synchronism polarity" "0,1"
bitfld.byte 0x00 0. "spare_1,Reserved as spare bit with no associated functionality" "0,1"
group.byte 0x0A++0x00
line.byte 0x00 "a_oesswcfg,HDCP OESS WOO Configuration Register Pulse width of the encryption enable (CTL3) signal in the HDCP OESS mode"
hexmask.byte 0x00 0.--7. 1. "a_oesswcfg,HDCP OESS WOO Configuration Register"
rgroup.byte 0x14++0x00
line.byte 0x00 "a_coreverlsb,HDCP Controller Version Register LSB Design ID number"
hexmask.byte 0x00 0.--7. 1. "a_coreverlsb,HDCP Controller Version Register LSB"
rgroup.byte 0x15++0x00
line.byte 0x00 "a_corevermsb,HDCP Controller Version Register MSB Revision ID number"
hexmask.byte 0x00 0.--7. 1. "a_corevermsb,HDCP Controller Version Register MSB"
group.byte 0x16++0x00
line.byte 0x00 "a_ksvmemctrl,HDCP KSV Memory Control Register The KSVCTRLupd bit is a notification flag"
rbitfld.byte 0x00 4. "KSVsha1status,Notification whether the KSV list message digest is correct from the controller: 1'b1 if digest message verification failed 1'b0 if digest message verification succeeded" "0,1"
bitfld.byte 0x00 2. "KSVCTRLupd,Set to inform that the KSV list in memory has been analyzed and the response to the Message Digest has been updated if on configurations on software SHA-1 calculation" "0,1"
newline
rbitfld.byte 0x00 1. "KSVMEMaccess,Notification that the KSV memory access as been guaranteed" "0,1"
bitfld.byte 0x00 0. "KSVMEMrequest,Request access to the KSV memory must be de-asserted after the access is completed by the system" "0,1"
group.byte 0x2B9++0x00
line.byte 0x00 "hdcp_revoc_size_0,HDCP Revocation KSV List Size Register 0"
hexmask.byte 0x00 0.--7. 1. "hdcp_revoc_size_0,Register containing the LSB of KSV list size (ksv_list_size[7:0])"
group.byte 0x2BA++0x00
line.byte 0x00 "hdcp_revoc_size_1,HDCP Revocation KSV List Size Register 1"
hexmask.byte 0x00 0.--7. 1. "hdcp_revoc_size_1,Register containing the MSB of KSV list size (ksv_list_size[15:8])"
rgroup.byte 0x2800++0x00
line.byte 0x00 "hdcpreg_bksv0,HDCP KSV Status Register 0"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_bksv0,Contains the value of BKSV[7:0]"
rgroup.byte 0x2801++0x00
line.byte 0x00 "hdcpreg_bksv1,HDCP KSV Status Register 1"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_bksv1,Contains the value of BKSV[15:8]"
rgroup.byte 0x2802++0x00
line.byte 0x00 "hdcpreg_bksv2,HDCP KSV Status Register 2"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_bksv2,Contains the value of BKSV[23:16]"
rgroup.byte 0x2803++0x00
line.byte 0x00 "hdcpreg_bksv3,HDCP KSV Status Register 3"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_bksv3,Contains the value of BKSV[31:24]"
rgroup.byte 0x2804++0x00
line.byte 0x00 "hdcpreg_bksv4,HDCP KSV Status Register 4"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_bksv4,Contains the value of BKSV[39:32]"
group.byte 0x2805++0x00
line.byte 0x00 "hdcpreg_anconf,HDCP AN Bypass Control Register"
bitfld.byte 0x00 0. "oanbypass,- When oanbypass=1 the value of AN used in the HDCP engine comes from the hdcpreg_an0 to hdcpreg_an7 registers" "0,1"
group.byte 0x2806++0x00
line.byte 0x00 "hdcpreg_an0,HDCP Forced AN Register 0"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an0,Contains the value of AN[7:0]"
group.byte 0x2807++0x00
line.byte 0x00 "hdcpreg_an1,HDCP Forced AN Register 1"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an1,Contains the value of AN[15:8]"
group.byte 0x2808++0x00
line.byte 0x00 "hdcpreg_an2,HDCP forced AN Register 2"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an2,Contains the value of AN[23:16]"
group.byte 0x2809++0x00
line.byte 0x00 "hdcpreg_an3,HDCP Forced AN Register 3"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an3,Contains the value of AN[31:24]"
group.byte 0x280A++0x00
line.byte 0x00 "hdcpreg_an4,HDCP Forced AN Register 4"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an4,Contains the value of AN[39:32]"
group.byte 0x280B++0x00
line.byte 0x00 "hdcpreg_an5,HDCP Forced AN Register 5"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an5,Contains the value of AN[47:40]"
group.byte 0x280C++0x00
line.byte 0x00 "hdcpreg_an6,HDCP Forced AN Register 6"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an6,Contains the value of AN[55:48]"
group.byte 0x280D++0x00
line.byte 0x00 "hdcpreg_an7,HDCP Forced AN Register 7"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_an7,Contains the value of BKSV[63:56]"
group.byte 0x280E++0x00
line.byte 0x00 "hdcpreg_rmlctl,HDCP Encrypted Device Private Keys Control Register This register is the control register for the software programmable encrypted DPK embedded storage feature"
bitfld.byte 0x00 0. "odpk_decrypt_enable,When set (1'b1) this bit activates the decryption of the Device Private keys" "0,1"
rgroup.byte 0x280F++0x00
line.byte 0x00 "hdcpreg_rmlsts,HDCP Encrypted DPK Status Register The required software configuration sequence is documented in the DesignWare Cores HDMI Transmitter User Guide in the Programming chapter Section 3"
bitfld.byte 0x00 6. "idpk_wr_ok_sts,When high (1'b1) it indicates that a DPK write is allowed" "0,1"
bitfld.byte 0x00 0.--5. "idpk_data_index,Current Device Private Key being written plus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
wgroup.byte 0x2810++0x00
line.byte 0x00 "hdcpreg_seed0,HDCP Encrypted DPK Seed Register 0 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_seed0,Least significant byte of the decryption seed value (dpk_decrypt_seed[7:0])"
wgroup.byte 0x2811++0x00
line.byte 0x00 "hdcpreg_seed1,HDCP Encrypted DPK Seed Register 1 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys"
hexmask.byte 0x00 0.--7. 1. "hdcpreg_seed1,Most significant byte of the decryption seed value (dpk_decrypt_seed[15:8])"
wgroup.byte 0x2812++0x00
line.byte 0x00 "hdcpreg_dpk0,HDCP Encrypted DPK Data Register 0 This register contains an HDCP DPK byte"
hexmask.byte 0x00 0.--7. 1. "dpk_data,Byte of the encrypted DPK value"
wgroup.byte 0x2813++0x00
line.byte 0x00 "hdcpreg_dpk1,HDCP Encrypted DPK Data Register 1 This register contains an HDCP DPK byte"
hexmask.byte 0x00 0.--7. 1. "dpk_data,Byte of the encrypted DPK value"
wgroup.byte 0x2814++0x00
line.byte 0x00 "hdcpreg_dpk2,HDCP Encrypted DPK Data Register 2 This register contains an HDCP DPK byte"
hexmask.byte 0x00 0.--7. 1. "dpk_data,Byte of the encrypted DPK value"
wgroup.byte 0x2815++0x00
line.byte 0x00 "hdcpreg_dpk3,HDCP Encrypted DPK Data Register 3 This register contains an HDCP DPK byte"
hexmask.byte 0x00 0.--7. 1. "dpk_data,Byte of the encrypted DPK value"
wgroup.byte 0x2816++0x00
line.byte 0x00 "hdcpreg_dpk4,HDCP Encrypted DPK Data Register 4 This register contains an HDCP DPK byte"
hexmask.byte 0x00 0.--7. 1. "dpk_data,Byte of the encrypted DPK value"
wgroup.byte 0x2817++0x00
line.byte 0x00 "hdcpreg_dpk5,HDCP Encrypted DPK Data Register 5 This register contains an HDCP DPK byte"
hexmask.byte 0x00 0.--7. 1. "dpk_data,Contains the value of DPK[x][47:40]"
wgroup.byte 0x2818++0x00
line.byte 0x00 "hdcpreg_dpk6,HDCP Encrypted DPK Data Register 6 This register contains an HDCP DPK byte"
hexmask.byte 0x00 0.--7. 1. "dpk_data,Contains the value of DPK[x][55:48]"
tree.end
tree "HDCP22"
base ad:0x32FDF900
rgroup.byte 0x00++0x00
line.byte 0x00 "hdcp22reg_id,HDCP 2"
bitfld.byte 0x00 2. "hdcp22_3rdparty,Indicates that External HDCP 2" "0,1"
bitfld.byte 0x00 1. "hdcp22_externalif,Indicates that External HDCP 2" "0,1"
group.byte 0x04++0x00
line.byte 0x00 "hdcp22reg_ctrl,HDCP 2"
bitfld.byte 0x00 5. "hpd_ovr_val,HPD Override Value" "0,1"
bitfld.byte 0x00 4. "hpd_ovr_en,HPD Override enable" "0,1"
newline
bitfld.byte 0x00 2. "hdcp22_ovr_val,HDCP 2" "0,1"
bitfld.byte 0x00 1. "hdcp22_ovr_en,HDCP 2" "0,1"
newline
bitfld.byte 0x00 0. "hdcp22_switch_lck,HDCP 2" "0,1"
group.byte 0x05++0x00
line.byte 0x00 "hdcp22reg_ctrl1,HDCP 2"
bitfld.byte 0x00 4.--7. "hdcp22_cd_ovr_val,HDCP color depth override value which is sent through the HDCP 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 3. "hdcp22_cd_ovr_en,HDCP 2" "0,1"
newline
bitfld.byte 0x00 1. "hdcp22_avmute_ovr_val,HDCP AV_MUTE override value which is sent through the HDCP 2" "0,1"
bitfld.byte 0x00 0. "hdcp22_avmute_ovr_en,HDCP 2" "0,1"
rgroup.byte 0x08++0x00
line.byte 0x00 "hdcp22reg_sts,HDCP 2"
bitfld.byte 0x00 3. "hdcp_decrypted_sts,Value of HDCP 2" "0,1"
bitfld.byte 0x00 2. "hdcp22_switch_sts,HDCP 2" "0,1"
newline
bitfld.byte 0x00 1. "hdcp_avmute_sts,HDCP 2" "0,1"
bitfld.byte 0x00 0. "hdmi_hpd_sts,HDCP 2" "0,1"
group.byte 0x0C++0x00
line.byte 0x00 "hdcp22reg_mask,HDCP 2"
bitfld.byte 0x00 5. "mask_hdcp_decrypted_chg,Active high interrupt mask to HDCP 2" "0,1"
bitfld.byte 0x00 4. "mask_hdcp_authentication_fail,Active high interrupt mask to HDCP 2" "0,1"
newline
bitfld.byte 0x00 3. "mask_hdcp_authenticated,Active high interrupt mask to HDCP 2" "0,1"
bitfld.byte 0x00 2. "mask_hdcp_authentication_lost,Active high interrupt mask to HDCP 2" "0,1"
newline
bitfld.byte 0x00 1. "mask_hdcp2_not_capable,Active high interrupt mask to HDCP 2" "0,1"
bitfld.byte 0x00 0. "mask_hdcp2_capable,Active high interrupt mask to HDCP 2" "0,1"
group.byte 0x0F++0x00
line.byte 0x00 "hdcp22reg_stat,HDCP 2"
eventfld.byte 0x00 5. "st_hdcp_decrypted_chg,HDCP 2" "0,1"
eventfld.byte 0x00 4. "st_hdcp_authentication_fail,HDCP 2" "0,1"
newline
eventfld.byte 0x00 3. "st_hdcp_authenticated,HDCP 2" "0,1"
eventfld.byte 0x00 2. "st_hdcp_authentication_lost,HDCP 2" "0,1"
newline
eventfld.byte 0x00 1. "st_hdcp2_not_capable,HDCP 2" "0,1"
eventfld.byte 0x00 0. "st_hdcp2_capable,HDCP 2" "0,1"
group.byte 0x12++0x00
line.byte 0x00 "hdcp22reg_mute,HDCP 2"
bitfld.byte 0x00 5. "mute_hdcp_decrypted_chg,Active high interrupt mute to HDCP 2" "0,1"
bitfld.byte 0x00 4. "mute_hdcp_authentication_fail,Active high interrupt mute to HDCP 2" "0,1"
newline
bitfld.byte 0x00 3. "mute_hdcp_authenticated,Active high interrupt mute to HDCP 2" "0,1"
bitfld.byte 0x00 2. "mute_hdcp_authentication_lost,Active high interrupt mute to HDCP 2" "0,1"
newline
bitfld.byte 0x00 1. "mute_hdcp2_not_capable,Active high interrupt mute to HDCP 2" "0,1"
bitfld.byte 0x00 0. "mute_hdcp2_capable,Active high interrupt mute to HDCP 2" "0,1"
tree.end
tree.end
tree "HDMI_TRNG"
base ad:0x32FD3000
group.long 0x00++0x03
line.long 0x00 "CTRL,This register causes the DWC_trng to execute one of a number of actions"
bitfld.long 0x00 0.--2. "CMD,Execute a command" "0: Execute a NOP,1: Generate a random number,2: Execute a random reseed,3: Execute a nonce reseed,?..."
rgroup.long 0x04++0x03
line.long 0x00 "STAT,The NONCE_MODE field indicates that the engine is currently waiting for the host to load a nonce through the SEEDx registers"
bitfld.long 0x00 31. "RAND_RESEEDING,Current state of random seed generation operations" "0: No random reseed generation process in progress,1: Random reseed generation process in progress"
bitfld.long 0x00 30. "RAND_GENERATING,Current state of random number generation operations" "0: No random number generation process in progress,1: Random number generation process in progress"
newline
bitfld.long 0x00 27. "SRVC_RQST,Current state of unacknowledged request indicator" "0: No unacknowledged service request,1: Unacknowledged service request"
bitfld.long 0x00 16.--18. "LAST_RESEED,Action which loaded current seed" "0: Reseeded by host random reseed command,?,?,3: Reseeded by nonce,4: Reseeded by <b>I_reseed</b> driven to 1 or..,?,?,7: Unseeded (zeroized state)"
newline
bitfld.long 0x00 9. "SEEDED,Current SEEDED state" "0: PRNG core is not seeded,1: PRNG core is seeded"
bitfld.long 0x00 8. "MISSION_MODE,Reflects state of SMODE" "0,1"
newline
bitfld.long 0x00 3. "R256,Reflects state of MODE" "0,1"
bitfld.long 0x00 2. "NONCE_MODE,Current state of NONCE mode" "0: Nonce mode disabled,1: Nonce mode enabled"
group.long 0x0C++0x03
line.long 0x00 "SMODE,This register is used to enable or disable certain mission-mode run-time features within the core"
hexmask.long.byte 0x00 16.--23. 1. "MAX_REJECTS,Maximum number of consecutive bit rejections before issuing ring tweak"
bitfld.long 0x00 8. "MISSION_MODE,Sets the operating mode to TEST or MISSION" "0: Test mode (access to internal state and test..,1: Mission mode (no access to internal state)"
newline
bitfld.long 0x00 2. "NONCE_MODE,Sets the reseed mode to nonce or random" "0: Disable nonce mode,1: Enable nonce mode"
group.long 0x10++0x03
line.long 0x00 "IE,This register is used to enable or disable interrupts within the DWC_trng"
bitfld.long 0x00 31. "GLBL_EN,Global interrupt enable" "0: Globally disable interrupts,1: Globally enable interrupts"
bitfld.long 0x00 4. "LFSR_LOCKUP_EN,Include or exclude LFSR_LOCKUP interrupt contribution" "0: Disable <b>LFSR_LOCKUP</b> interrupt..,1: Enable <b>LFSR_LOCKUP</b> interrupt.."
newline
bitfld.long 0x00 3. "RQST_ALARM_EN,Include or exclude RQST_ALARM interrupt contribution" "0: Disable <b>RQST_ALARM</b> interrupt..,1: Enable <b>RQST_ALARM</b> interrupt contribution"
bitfld.long 0x00 2. "AGE_ALARM_EN,Include or exclude AGE_ALARM interrupt contribution" "0: Disable <b>AGE_ALARM</b> interrupt contribution,1: Enable <b>AGE_ALARM</b> interrupt contribution"
newline
bitfld.long 0x00 1. "SEED_DONE_EN,Include or exclude SEED_DONE interrupt contribution" "0: Disable <b>SEED_DONE</b> interrupt contribution,1: Enable <b>SEED_DONE</b> interrupt contribution"
bitfld.long 0x00 0. "RAND_RDY_EN,Include or exclude RAND_RDY interrupt contribution" "0: Disable <b>RAND_RDY</b> interrupt contribution,1: Enable <b>RAND_RDY</b> interrupt contribution"
group.long 0x14++0x03
line.long 0x00 "ISTAT,This register allows the user to monitor the interrupt and/or status contributions of the DWC_trng"
eventfld.long 0x00 4. "LFSR_LOCKUP,Status and acknowledgment (clearing) of LFSR_LOCKUP indicator" "0: No unacknowledged LFSR_LOCKUP indicator,1: Unacknowledged LFSR_LOCKUP indicator"
eventfld.long 0x00 3. "RQST_ALARM,Status and acknowledgment (clearing) of RQST_ALARM indicator" "0: No unacknowledged RQST_ALARM indicator,1: Unacknowledged RQST_ALARM indicator"
newline
eventfld.long 0x00 2. "AGE_ALARM,Status and acknowledgment (clearing) of AGE_ALARM indicator" "0: No unacknowledged AGE_ALARM indicator,1: Unacknowledged AGE_ALARM indicator"
eventfld.long 0x00 1. "SEED_DONE,Status and acknowledgment (clearing) of SEED_DONE indicator" "0: No unacknowledged SEED_DONE indicator,1: Unacknowledged SEED_DONE indicator"
newline
eventfld.long 0x00 0. "RAND_RDY,Status and acknowledgment (clearing) of RAND_RDY indicator" "0: No unacknowledged RAND_RDY indicator,1: Unacknowledged RAND_RDY indicator"
rgroup.long 0x18++0x03
line.long 0x00 "COREKIT_REL,Contains the coreKit release information"
bitfld.long 0x00 28.--31. "EXT_ENUM,Indicates the coreKit release extension type" "0: EXT_ENUM_GA,1: EXT_ENUM_LCA,2: EXT_ENUM_EA,3: EXT_ENUM_LP,4: EXT_ENUM_LPC,5: EXT_ENUM_SOW,?..."
hexmask.long.byte 0x00 16.--23. 1. "EXT_VER,Indicates the coreKit release extension version number"
newline
hexmask.long.word 0x00 0.--15. 1. "REL_NUM,Indicates the coreKit release version in pseudo-BCD"
rgroup.long 0x1C++0x03
line.long 0x00 "FEATURES,Contains the build-time parameter enumerations"
bitfld.long 0x00 4.--6. "DIAG_LEVEL,Level of diagnostic support provided" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "MISSION_MODE_RESET_STATE,Indicates state of SMODE" "0: Resets to TEST_MODE,1: Resets to MISSION_MODE"
newline
bitfld.long 0x00 2. "RAND_SEED_AVAIL,Indicates the ring-oscillator sub-section is present" "0: No ring-oscillator seed generator present,1: Ring-oscillator seed generator present"
bitfld.long 0x00 0.--1. "MAX_RAND_LENGTH,Maximum length of the PRNG RANDx register set" "0: PRNG set up for 128-bit maximum,1: PRNG set up for 256-bit maximum,?..."
rgroup.long 0x20++0x03
line.long 0x00 "RAND0,The RAND0 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 0"
rgroup.long 0x24++0x03
line.long 0x00 "RAND1,The RAND1 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 1"
rgroup.long 0x28++0x03
line.long 0x00 "RAND2,The RAND2 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 2"
rgroup.long 0x2C++0x03
line.long 0x00 "RAND3,The RAND3 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 3"
rgroup.long 0x30++0x03
line.long 0x00 "RAND4,The RAND4 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 4"
rgroup.long 0x34++0x03
line.long 0x00 "RAND5,The RAND5 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 5"
rgroup.long 0x38++0x03
line.long 0x00 "RAND6,The RAND6 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 6"
rgroup.long 0x3C++0x03
line.long 0x00 "RAND7,The RAND7 register is part of the RANDx register set which are used by the host to read the newly generated random number"
hexmask.long 0x00 0.--31. 1. "RAND,Random data word 7"
rgroup.long 0x40++0x03
line.long 0x00 "SEED0,The SEED0 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 0"
rgroup.long 0x44++0x03
line.long 0x00 "SEED1,The SEED1 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 1"
rgroup.long 0x48++0x03
line.long 0x00 "SEED2,The SEED2 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 2"
rgroup.long 0x4C++0x03
line.long 0x00 "SEED3,The SEED3 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 3"
rgroup.long 0x50++0x03
line.long 0x00 "SEED4,The SEED4 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 4"
rgroup.long 0x54++0x03
line.long 0x00 "SEED5,The SEED5 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 5"
rgroup.long 0x58++0x03
line.long 0x00 "SEED6,The SEED6 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 6"
rgroup.long 0x5C++0x03
line.long 0x00 "SEED7,The SEED7 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng"
hexmask.long 0x00 0.--31. 1. "SEED,Seed data word 7"
group.long 0x60++0x03
line.long 0x00 "AUTO_RQSTS,This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host"
hexmask.long.word 0x00 0.--15. 1. "RQSTS,"
group.long 0x64++0x03
line.long 0x00 "AUTO_AGE,This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host"
hexmask.long.word 0x00 0.--15. 1. "AGE,"
rgroup.long 0x68++0x03
line.long 0x00 "BUILD_CONFIG,Contains the build-time parameter enumerations"
bitfld.long 0x00 12.--15. "ESM_PORTS,Indicates number of ESM arbitration ports available minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--10. "DIAGNOSTIC_LEVEL,Level of diagnostic support provided" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5. "AUTO_RESEED_LOOPBACK,Indicates auto-reseed configuration setting" "0: No auto-reseed loopback,1: Auto-reseed loopback present"
bitfld.long 0x00 4. "MODE_AFTER_RST,Indicates state of SMODE" "0: Resets to TEST_MODE,1: Resets to MISSION_MODE"
newline
bitfld.long 0x00 3. "PRNG_LEN_AFTER_RST,State of MODE" "0: PRNG length set to 128-bit after reset,1: PRNG length set to 256-bit after reset"
bitfld.long 0x00 2. "MAX_PRNG_LEN,Maximum length of the PRNG RANDx register set" "0: PRNG set up for 128-bit maximum,1: PRNG set up for 256-bit maximum"
newline
bitfld.long 0x00 0.--1. "CORE_TYPE,Configured I/O style (license controlled)" "0: 5-Wire control/status I/O,1: CORE_TYPE_ESM_NONCE,2: ESM nonce I/O with multi-ESM support,?..."
tree.end
tree "HDMI_TX_BLK_CTL"
base ad:0x32FC0000
group.long 0x00++0x03
line.long 0x00 "RTX_GENERAL,HDMI_RTX_GENERAL CONFIG"
bitfld.long 0x00 8. "LCDIF_AXI_LIMIT_EN,Enables the AXI Read Beat count limiter the beat limit value is given by the 16b value LCDIF_AXI_BEAT_LIMIT" "0,1"
bitfld.long 0x00 4.--5. "HDCP_AXI_ADDR_EXTN,HDCP_AXI_ADDR_EXTN control" "0,1,2,3"
newline
bitfld.long 0x00 0. "DEBUG_LOCKOUT_EN,RESERVED" "0,1"
group.long 0x04++0x03
line.long 0x00 "RTX_GENERAL_SET,HDMI_RTX_GENERAL CONFIG"
bitfld.long 0x00 8. "LCDIF_AXI_LIMIT_EN,Enables the AXI Read Beat count limiter the beat limit value is given by the 16b value LCDIF_AXI_BEAT_LIMIT" "0,1"
bitfld.long 0x00 4.--5. "HDCP_AXI_ADDR_EXTN,HDCP_AXI_ADDR_EXTN control" "0,1,2,3"
newline
bitfld.long 0x00 0. "DEBUG_LOCKOUT_EN,RESERVED" "0,1"
group.long 0x08++0x03
line.long 0x00 "RTX_GENERAL_CLR,HDMI_RTX_GENERAL CONFIG"
eventfld.long 0x00 8. "LCDIF_AXI_LIMIT_EN,Enables the AXI Read Beat count limiter the beat limit value is given by the 16b value LCDIF_AXI_BEAT_LIMIT" "0,1"
eventfld.long 0x00 4.--5. "HDCP_AXI_ADDR_EXTN,HDCP_AXI_ADDR_EXTN control" "0,1,2,3"
newline
eventfld.long 0x00 0. "DEBUG_LOCKOUT_EN,RESERVED" "0,1"
group.long 0x0C++0x03
line.long 0x00 "RTX_GENERAL_TOG,HDMI_RTX_GENERAL CONFIG"
bitfld.long 0x00 8. "LCDIF_AXI_LIMIT_EN,Enables the AXI Read Beat count limiter the beat limit value is given by the 16b value LCDIF_AXI_BEAT_LIMIT" "0,1"
bitfld.long 0x00 4.--5. "HDCP_AXI_ADDR_EXTN,HDCP_AXI_ADDR_EXTN control" "0,1,2,3"
newline
bitfld.long 0x00 0. "DEBUG_LOCKOUT_EN,RESERVED" "0,1"
group.long 0x10++0x03
line.long 0x00 "RTX_GENERAL_1,HDMI_RTX_GENERAL CONFIG"
hexmask.long.word 0x00 0.--15. 1. "LCDIF_AXI_BEAT_LIMIT,LCDIF_AXI_BEAT_LIMIT"
group.long 0x14++0x03
line.long 0x00 "RTX_GENERAL_1_SET,HDMI_RTX_GENERAL CONFIG"
hexmask.long.word 0x00 0.--15. 1. "LCDIF_AXI_BEAT_LIMIT,LCDIF_AXI_BEAT_LIMIT"
group.long 0x18++0x03
line.long 0x00 "RTX_GENERAL_1_CLR,HDMI_RTX_GENERAL CONFIG"
hexmask.long.word 0x00 0.--15. 1. "LCDIF_AXI_BEAT_LIMIT,LCDIF_AXI_BEAT_LIMIT"
group.long 0x1C++0x03
line.long 0x00 "RTX_GENERAL_1_TOG,HDMI_RTX_GENERAL CONFIG"
hexmask.long.word 0x00 0.--15. 1. "LCDIF_AXI_BEAT_LIMIT,LCDIF_AXI_BEAT_LIMIT"
group.long 0x20++0x03
line.long 0x00 "RTX_RESET_CTL0,HDMI_RTX_RESET_CTL0"
bitfld.long 0x00 23. "VSFD_RESETN,VSFD_RESETN control" "0,1"
bitfld.long 0x00 22. "VID_LINK_SLV_RESETN,VID_LINK_SLV_RESETN control" "0,1"
newline
bitfld.long 0x00 20. "TX_TRNG_RESETN,TX_TRNG_RESETN control" "0,1"
bitfld.long 0x00 18. "PAI_RESETN,PAI_RESETN control" "0,1"
newline
bitfld.long 0x00 16. "IRQ_RESETN,IRQ_RESETN control" "0,1"
bitfld.long 0x00 15. "HRV_MWR_RESETN,HRV_MWR_RESETN control" "0,1"
newline
bitfld.long 0x00 14. "TX_SEC_MEM_RESETN,RESERVED" "0,1"
bitfld.long 0x00 13. "TX_KSV_MEM_RESETN,KSV Mem reset control" "0,1"
newline
bitfld.long 0x00 12. "TX_PHY_PRESETN,TX_PHY_PRESETN control" "0,1"
bitfld.long 0x00 11. "TX_APBRSTZ,TX_APBRSTZ control" "0,1"
newline
bitfld.long 0x00 10. "TX_RSTZ,TX_RSTZ control" "0,1"
bitfld.long 0x00 7. "FDCC_HDMI_RESETN,FDCC_HDMI_RESETN control" "0,1"
newline
bitfld.long 0x00 6. "FDCC_RESETN,FDCC_RESETN control" "0,1"
bitfld.long 0x00 5. "LCDIF_APB_RESET_N,LCDIF_APB_RESET_N control" "0,1"
newline
bitfld.long 0x00 4. "LCDIF_ASYNC_RESET_N,LCDIF_ASYNC_RESET_N control" "0,1"
bitfld.long 0x00 0. "NOC_RESET_N,NOC_RESET_N control" "0,1"
group.long 0x24++0x03
line.long 0x00 "RTX_RESET_CTL0_SET,HDMI_RTX_RESET_CTL0"
bitfld.long 0x00 23. "VSFD_RESETN,VSFD_RESETN control" "0,1"
bitfld.long 0x00 22. "VID_LINK_SLV_RESETN,VID_LINK_SLV_RESETN control" "0,1"
newline
bitfld.long 0x00 20. "TX_TRNG_RESETN,TX_TRNG_RESETN control" "0,1"
bitfld.long 0x00 18. "PAI_RESETN,PAI_RESETN control" "0,1"
newline
bitfld.long 0x00 16. "IRQ_RESETN,IRQ_RESETN control" "0,1"
bitfld.long 0x00 15. "HRV_MWR_RESETN,HRV_MWR_RESETN control" "0,1"
newline
bitfld.long 0x00 14. "TX_SEC_MEM_RESETN,RESERVED" "0,1"
bitfld.long 0x00 13. "TX_KSV_MEM_RESETN,KSV Mem reset control" "0,1"
newline
bitfld.long 0x00 12. "TX_PHY_PRESETN,TX_PHY_PRESETN control" "0,1"
bitfld.long 0x00 11. "TX_APBRSTZ,TX_APBRSTZ control" "0,1"
newline
bitfld.long 0x00 10. "TX_RSTZ,TX_RSTZ control" "0,1"
bitfld.long 0x00 7. "FDCC_HDMI_RESETN,FDCC_HDMI_RESETN control" "0,1"
newline
bitfld.long 0x00 6. "FDCC_RESETN,FDCC_RESETN control" "0,1"
bitfld.long 0x00 5. "LCDIF_APB_RESET_N,LCDIF_APB_RESET_N control" "0,1"
newline
bitfld.long 0x00 4. "LCDIF_ASYNC_RESET_N,LCDIF_ASYNC_RESET_N control" "0,1"
bitfld.long 0x00 0. "NOC_RESET_N,NOC_RESET_N control" "0,1"
group.long 0x28++0x03
line.long 0x00 "RTX_RESET_CTL0_CLR,HDMI_RTX_RESET_CTL0"
eventfld.long 0x00 23. "VSFD_RESETN,VSFD_RESETN control" "0,1"
eventfld.long 0x00 22. "VID_LINK_SLV_RESETN,VID_LINK_SLV_RESETN control" "0,1"
newline
eventfld.long 0x00 20. "TX_TRNG_RESETN,TX_TRNG_RESETN control" "0,1"
eventfld.long 0x00 18. "PAI_RESETN,PAI_RESETN control" "0,1"
newline
eventfld.long 0x00 16. "IRQ_RESETN,IRQ_RESETN control" "0,1"
eventfld.long 0x00 15. "HRV_MWR_RESETN,HRV_MWR_RESETN control" "0,1"
newline
eventfld.long 0x00 14. "TX_SEC_MEM_RESETN,RESERVED" "0,1"
eventfld.long 0x00 13. "TX_KSV_MEM_RESETN,KSV Mem reset control" "0,1"
newline
eventfld.long 0x00 12. "TX_PHY_PRESETN,TX_PHY_PRESETN control" "0,1"
eventfld.long 0x00 11. "TX_APBRSTZ,TX_APBRSTZ control" "0,1"
newline
eventfld.long 0x00 10. "TX_RSTZ,TX_RSTZ control" "0,1"
eventfld.long 0x00 7. "FDCC_HDMI_RESETN,FDCC_HDMI_RESETN control" "0,1"
newline
eventfld.long 0x00 6. "FDCC_RESETN,FDCC_RESETN control" "0,1"
eventfld.long 0x00 5. "LCDIF_APB_RESET_N,LCDIF_APB_RESET_N control" "0,1"
newline
eventfld.long 0x00 4. "LCDIF_ASYNC_RESET_N,LCDIF_ASYNC_RESET_N control" "0,1"
eventfld.long 0x00 0. "NOC_RESET_N,NOC_RESET_N control" "0,1"
group.long 0x2C++0x03
line.long 0x00 "RTX_RESET_CTL0_TOG,HDMI_RTX_RESET_CTL0"
bitfld.long 0x00 23. "VSFD_RESETN,VSFD_RESETN control" "0,1"
bitfld.long 0x00 22. "VID_LINK_SLV_RESETN,VID_LINK_SLV_RESETN control" "0,1"
newline
bitfld.long 0x00 20. "TX_TRNG_RESETN,TX_TRNG_RESETN control" "0,1"
bitfld.long 0x00 18. "PAI_RESETN,PAI_RESETN control" "0,1"
newline
bitfld.long 0x00 16. "IRQ_RESETN,IRQ_RESETN control" "0,1"
bitfld.long 0x00 15. "HRV_MWR_RESETN,HRV_MWR_RESETN control" "0,1"
newline
bitfld.long 0x00 14. "TX_SEC_MEM_RESETN,RESERVED" "0,1"
bitfld.long 0x00 13. "TX_KSV_MEM_RESETN,KSV Mem reset control" "0,1"
newline
bitfld.long 0x00 12. "TX_PHY_PRESETN,TX_PHY_PRESETN control" "0,1"
bitfld.long 0x00 11. "TX_APBRSTZ,TX_APBRSTZ control" "0,1"
newline
bitfld.long 0x00 10. "TX_RSTZ,TX_RSTZ control" "0,1"
bitfld.long 0x00 7. "FDCC_HDMI_RESETN,FDCC_HDMI_RESETN control" "0,1"
newline
bitfld.long 0x00 6. "FDCC_RESETN,FDCC_RESETN control" "0,1"
bitfld.long 0x00 5. "LCDIF_APB_RESET_N,LCDIF_APB_RESET_N control" "0,1"
newline
bitfld.long 0x00 4. "LCDIF_ASYNC_RESET_N,LCDIF_ASYNC_RESET_N control" "0,1"
bitfld.long 0x00 0. "NOC_RESET_N,NOC_RESET_N control" "0,1"
group.long 0x40++0x03
line.long 0x00 "RTX_CLK_CTL0,HDMI_RTX_CLK_CTL0"
bitfld.long 0x00 20. "LCDIF_SPU_CLK_EN,clock enable for lcdif spu_clk input" "0,1"
bitfld.long 0x00 19. "LCDIF_PIX_CLK_EN,clock enable for lcdif pix_clk input" "0,1"
newline
bitfld.long 0x00 18. "LCDIF_PDI_CLK_EN,clock enable for lcdif pdi_clk input" "0,1"
bitfld.long 0x00 17. "LCDIF_B_CLK_EN,clock enable for lcdif bus_clk input" "0,1"
newline
bitfld.long 0x00 16. "LCDIF_APB_CLK_EN,clock enable for lcdif apb_clk input" "0,1"
bitfld.long 0x00 11. "NOC_HDCP_CLK_EN,clock enable for the NOC hdcp_clk" "0,1"
newline
bitfld.long 0x00 10. "NOC_HDMI_CLK_EN,clock enable for the NOC bus_clk enable" "0,1"
bitfld.long 0x00 9. "IRQS_CLK_EN,clock control for the irq_steer block" "0,1"
newline
bitfld.long 0x00 8. "PD1_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 7. "GLOBAL_TX_PIX_CLK_EN,TX pix clk control" "0,1"
newline
bitfld.long 0x00 6. "GLOBAL_AUD_PLL_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 5. "GLOBAL_XTAL32K_CLK_EN,GLOBAL_XTAL32K_CLK_EN control" "0,1"
newline
bitfld.long 0x00 4. "GLOBAL_XTAL24M_CLK_EN,GLOBAL_XTAL24M_CLK_EN control" "0,1"
bitfld.long 0x00 3. "GLOBAL_XTAL27M_CLK_EN,GLOBAL_XTAL27M_CLK_EN control" "0,1"
newline
bitfld.long 0x00 2. "GLOBAL_REF266M_CLK_EN,GLOBAL_REF266M_CLK_EN control" "0,1"
bitfld.long 0x00 1. "GLOBAL_B_CLK_EN,GLOBAL_B_CLK_EN control" "0,1"
newline
bitfld.long 0x00 0. "GLOBAL_APB_CLK_EN,GLOBAL_APB_CLK_EN control" "0,1"
group.long 0x44++0x03
line.long 0x00 "RTX_CLK_CTL0_SET,HDMI_RTX_CLK_CTL0"
bitfld.long 0x00 20. "LCDIF_SPU_CLK_EN,clock enable for lcdif spu_clk input" "0,1"
bitfld.long 0x00 19. "LCDIF_PIX_CLK_EN,clock enable for lcdif pix_clk input" "0,1"
newline
bitfld.long 0x00 18. "LCDIF_PDI_CLK_EN,clock enable for lcdif pdi_clk input" "0,1"
bitfld.long 0x00 17. "LCDIF_B_CLK_EN,clock enable for lcdif bus_clk input" "0,1"
newline
bitfld.long 0x00 16. "LCDIF_APB_CLK_EN,clock enable for lcdif apb_clk input" "0,1"
bitfld.long 0x00 11. "NOC_HDCP_CLK_EN,clock enable for the NOC hdcp_clk" "0,1"
newline
bitfld.long 0x00 10. "NOC_HDMI_CLK_EN,clock enable for the NOC bus_clk enable" "0,1"
bitfld.long 0x00 9. "IRQS_CLK_EN,clock control for the irq_steer block" "0,1"
newline
bitfld.long 0x00 8. "PD1_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 7. "GLOBAL_TX_PIX_CLK_EN,TX pix clk control" "0,1"
newline
bitfld.long 0x00 6. "GLOBAL_AUD_PLL_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 5. "GLOBAL_XTAL32K_CLK_EN,GLOBAL_XTAL32K_CLK_EN control" "0,1"
newline
bitfld.long 0x00 4. "GLOBAL_XTAL24M_CLK_EN,GLOBAL_XTAL24M_CLK_EN control" "0,1"
bitfld.long 0x00 3. "GLOBAL_XTAL27M_CLK_EN,GLOBAL_XTAL27M_CLK_EN control" "0,1"
newline
bitfld.long 0x00 2. "GLOBAL_REF266M_CLK_EN,GLOBAL_REF266M_CLK_EN control" "0,1"
bitfld.long 0x00 1. "GLOBAL_B_CLK_EN,GLOBAL_B_CLK_EN control" "0,1"
newline
bitfld.long 0x00 0. "GLOBAL_APB_CLK_EN,GLOBAL_APB_CLK_EN control" "0,1"
group.long 0x48++0x03
line.long 0x00 "RTX_CLK_CTL0_CLR,HDMI_RTX_CLK_CTL0"
eventfld.long 0x00 20. "LCDIF_SPU_CLK_EN,clock enable for lcdif spu_clk input" "0,1"
eventfld.long 0x00 19. "LCDIF_PIX_CLK_EN,clock enable for lcdif pix_clk input" "0,1"
newline
eventfld.long 0x00 18. "LCDIF_PDI_CLK_EN,clock enable for lcdif pdi_clk input" "0,1"
eventfld.long 0x00 17. "LCDIF_B_CLK_EN,clock enable for lcdif bus_clk input" "0,1"
newline
eventfld.long 0x00 16. "LCDIF_APB_CLK_EN,clock enable for lcdif apb_clk input" "0,1"
eventfld.long 0x00 11. "NOC_HDCP_CLK_EN,clock enable for the NOC hdcp_clk" "0,1"
newline
eventfld.long 0x00 10. "NOC_HDMI_CLK_EN,clock enable for the NOC bus_clk enable" "0,1"
eventfld.long 0x00 9. "IRQS_CLK_EN,clock control for the irq_steer block" "0,1"
newline
eventfld.long 0x00 8. "PD1_CLK_EN,RESERVED" "0,1"
eventfld.long 0x00 7. "GLOBAL_TX_PIX_CLK_EN,TX pix clk control" "0,1"
newline
eventfld.long 0x00 6. "GLOBAL_AUD_PLL_CLK_EN,RESERVED" "0,1"
eventfld.long 0x00 5. "GLOBAL_XTAL32K_CLK_EN,GLOBAL_XTAL32K_CLK_EN control" "0,1"
newline
eventfld.long 0x00 4. "GLOBAL_XTAL24M_CLK_EN,GLOBAL_XTAL24M_CLK_EN control" "0,1"
eventfld.long 0x00 3. "GLOBAL_XTAL27M_CLK_EN,GLOBAL_XTAL27M_CLK_EN control" "0,1"
newline
eventfld.long 0x00 2. "GLOBAL_REF266M_CLK_EN,GLOBAL_REF266M_CLK_EN control" "0,1"
eventfld.long 0x00 1. "GLOBAL_B_CLK_EN,GLOBAL_B_CLK_EN control" "0,1"
newline
eventfld.long 0x00 0. "GLOBAL_APB_CLK_EN,GLOBAL_APB_CLK_EN control" "0,1"
group.long 0x4C++0x03
line.long 0x00 "RTX_CLK_CTL0_TOG,HDMI_RTX_CLK_CTL0"
bitfld.long 0x00 20. "LCDIF_SPU_CLK_EN,clock enable for lcdif spu_clk input" "0,1"
bitfld.long 0x00 19. "LCDIF_PIX_CLK_EN,clock enable for lcdif pix_clk input" "0,1"
newline
bitfld.long 0x00 18. "LCDIF_PDI_CLK_EN,clock enable for lcdif pdi_clk input" "0,1"
bitfld.long 0x00 17. "LCDIF_B_CLK_EN,clock enable for lcdif bus_clk input" "0,1"
newline
bitfld.long 0x00 16. "LCDIF_APB_CLK_EN,clock enable for lcdif apb_clk input" "0,1"
bitfld.long 0x00 11. "NOC_HDCP_CLK_EN,clock enable for the NOC hdcp_clk" "0,1"
newline
bitfld.long 0x00 10. "NOC_HDMI_CLK_EN,clock enable for the NOC bus_clk enable" "0,1"
bitfld.long 0x00 9. "IRQS_CLK_EN,clock control for the irq_steer block" "0,1"
newline
bitfld.long 0x00 8. "PD1_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 7. "GLOBAL_TX_PIX_CLK_EN,TX pix clk control" "0,1"
newline
bitfld.long 0x00 6. "GLOBAL_AUD_PLL_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 5. "GLOBAL_XTAL32K_CLK_EN,GLOBAL_XTAL32K_CLK_EN control" "0,1"
newline
bitfld.long 0x00 4. "GLOBAL_XTAL24M_CLK_EN,GLOBAL_XTAL24M_CLK_EN control" "0,1"
bitfld.long 0x00 3. "GLOBAL_XTAL27M_CLK_EN,GLOBAL_XTAL27M_CLK_EN control" "0,1"
newline
bitfld.long 0x00 2. "GLOBAL_REF266M_CLK_EN,GLOBAL_REF266M_CLK_EN control" "0,1"
bitfld.long 0x00 1. "GLOBAL_B_CLK_EN,GLOBAL_B_CLK_EN control" "0,1"
newline
bitfld.long 0x00 0. "GLOBAL_APB_CLK_EN,GLOBAL_APB_CLK_EN control" "0,1"
group.long 0x50++0x03
line.long 0x00 "RTX_CLK_CTL1,HDMI_RTX_CLK_CTL1"
bitfld.long 0x00 30. "TX_TRNG_APB_CLK_EN,TX_TRNG_APB_CLK_EN control" "0,1"
bitfld.long 0x00 29. "TX_MEM_266M_CLK_EN,RESERVED" "0,1"
newline
bitfld.long 0x00 28. "TX_VID_LINK_PIX_CLK_EN,TX_VID_LINK_PIX_CLK_EN control" "0,1"
bitfld.long 0x00 27. "TX_TRNG_SKP_CLK_EN,TX_TRNG_SKP_CLK_EN control" "0,1"
newline
bitfld.long 0x00 26. "PAI_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 25. "TX_SEC_MEM_CLK_EN,TX_SEC_MEM_CLK_EN control" "0,1"
newline
bitfld.long 0x00 24. "TX_PHY_INT_CLK_EN,TX_PHY_INT_CLK_EN control" "0,1"
bitfld.long 0x00 23. "TX_PHY_PIXEL_CLK_EN,RESERVED" "0,1"
newline
bitfld.long 0x00 22. "TX_PHY_APB_CLK_EN,TX_PHY_APB_CLK_EN control" "0,1"
bitfld.long 0x00 21. "TX_PREP_CLK_EN,TX_PREP_CLK_EN control" "0,1"
newline
bitfld.long 0x00 20. "TX_SKP_CLK_EN,TX_SKP_CLK_EN control" "0,1"
bitfld.long 0x00 19. "TX_SFR_CLK_EN,TX_SFR_CLK_EN control" "0,1"
newline
bitfld.long 0x00 18. "TX_PIXEL_CLK_EN,TX_PIXEL_CLK_EN control" "0,1"
bitfld.long 0x00 17. "TX_GPA_CLK_EN,TX_GPA_CLK_EN control" "0,1"
newline
bitfld.long 0x00 16. "TX_ESM_CLK_EN,TX_ESM_CLK_EN control" "0,1"
bitfld.long 0x00 15. "TX_CEC_CLK_EN,TX_CEC_CLK_EN control" "0,1"
newline
bitfld.long 0x00 14. "TX_APB_CLK_EN,TX_APB_CLK_EN control" "0,1"
bitfld.long 0x00 13. "TX_HPI_CLK_EN,TX_HPI_CLK_EN control" "0,1"
newline
bitfld.long 0x00 12. "HTX_PIPE_CLK_SEL,HTX_PIPE_CLK_SEL control" "0,1"
bitfld.long 0x00 11. "lcdif_clk_sel,lcdif_clk_sel control" "0,1"
newline
bitfld.long 0x00 10. "htxphy_clk_sel,htxphy_clk_sel control" "0,1"
bitfld.long 0x00 9. "fdcc_clk_sel,RESERVED" "0,1"
newline
bitfld.long 0x00 8. "vpll_clk_sel,RESERVED" "0,1"
bitfld.long 0x00 6. "VSFD_CEA_CLK_EN,VSFD_CEA_CLK_EN control" "0,1"
newline
bitfld.long 0x00 5. "HRV_MWR_CEA_CLK_EN,HRV_MWR_CEA_CLK_EN control" "0,1"
bitfld.long 0x00 4. "HRV_MWR_B_CLK_EN,HRV_MWR_B_CLK_EN control" "0,1"
newline
bitfld.long 0x00 3. "HRV_MWR_APB_CLK_EN,HRV_MWR_APB_CLK_EN control" "0,1"
bitfld.long 0x00 2. "FDCC_REF_CLK_EN,FDCC_REF_CLK_EN control" "0,1"
newline
bitfld.long 0x00 1. "FDCC_IHDMI_CLK_EN,RESERVED" "0,1"
group.long 0x54++0x03
line.long 0x00 "RTX_CLK_CTL1_SET,HDMI_RTX_CLK_CTL1"
bitfld.long 0x00 30. "TX_TRNG_APB_CLK_EN,TX_TRNG_APB_CLK_EN control" "0,1"
bitfld.long 0x00 29. "TX_MEM_266M_CLK_EN,RESERVED" "0,1"
newline
bitfld.long 0x00 28. "TX_VID_LINK_PIX_CLK_EN,TX_VID_LINK_PIX_CLK_EN control" "0,1"
bitfld.long 0x00 27. "TX_TRNG_SKP_CLK_EN,TX_TRNG_SKP_CLK_EN control" "0,1"
newline
bitfld.long 0x00 26. "PAI_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 25. "TX_SEC_MEM_CLK_EN,TX_SEC_MEM_CLK_EN control" "0,1"
newline
bitfld.long 0x00 24. "TX_PHY_INT_CLK_EN,TX_PHY_INT_CLK_EN control" "0,1"
bitfld.long 0x00 23. "TX_PHY_PIXEL_CLK_EN,RESERVED" "0,1"
newline
bitfld.long 0x00 22. "TX_PHY_APB_CLK_EN,TX_PHY_APB_CLK_EN control" "0,1"
bitfld.long 0x00 21. "TX_PREP_CLK_EN,TX_PREP_CLK_EN control" "0,1"
newline
bitfld.long 0x00 20. "TX_SKP_CLK_EN,TX_SKP_CLK_EN control" "0,1"
bitfld.long 0x00 19. "TX_SFR_CLK_EN,TX_SFR_CLK_EN control" "0,1"
newline
bitfld.long 0x00 18. "TX_PIXEL_CLK_EN,TX_PIXEL_CLK_EN control" "0,1"
bitfld.long 0x00 17. "TX_GPA_CLK_EN,TX_GPA_CLK_EN control" "0,1"
newline
bitfld.long 0x00 16. "TX_ESM_CLK_EN,TX_ESM_CLK_EN control" "0,1"
bitfld.long 0x00 15. "TX_CEC_CLK_EN,TX_CEC_CLK_EN control" "0,1"
newline
bitfld.long 0x00 14. "TX_APB_CLK_EN,TX_APB_CLK_EN control" "0,1"
bitfld.long 0x00 13. "TX_HPI_CLK_EN,TX_HPI_CLK_EN control" "0,1"
newline
bitfld.long 0x00 12. "HTX_PIPE_CLK_SEL,HTX_PIPE_CLK_SEL control" "0,1"
bitfld.long 0x00 11. "lcdif_clk_sel,lcdif_clk_sel control" "0,1"
newline
bitfld.long 0x00 10. "htxphy_clk_sel,htxphy_clk_sel control" "0,1"
bitfld.long 0x00 9. "fdcc_clk_sel,RESERVED" "0,1"
newline
bitfld.long 0x00 8. "vpll_clk_sel,RESERVED" "0,1"
bitfld.long 0x00 6. "VSFD_CEA_CLK_EN,VSFD_CEA_CLK_EN control" "0,1"
newline
bitfld.long 0x00 5. "HRV_MWR_CEA_CLK_EN,HRV_MWR_CEA_CLK_EN control" "0,1"
bitfld.long 0x00 4. "HRV_MWR_B_CLK_EN,HRV_MWR_B_CLK_EN control" "0,1"
newline
bitfld.long 0x00 3. "HRV_MWR_APB_CLK_EN,HRV_MWR_APB_CLK_EN control" "0,1"
bitfld.long 0x00 2. "FDCC_REF_CLK_EN,FDCC_REF_CLK_EN control" "0,1"
newline
bitfld.long 0x00 1. "FDCC_IHDMI_CLK_EN,RESERVED" "0,1"
group.long 0x58++0x03
line.long 0x00 "RTX_CLK_CTL1_CLR,HDMI_RTX_CLK_CTL1"
eventfld.long 0x00 30. "TX_TRNG_APB_CLK_EN,TX_TRNG_APB_CLK_EN control" "0,1"
eventfld.long 0x00 29. "TX_MEM_266M_CLK_EN,RESERVED" "0,1"
newline
eventfld.long 0x00 28. "TX_VID_LINK_PIX_CLK_EN,TX_VID_LINK_PIX_CLK_EN control" "0,1"
eventfld.long 0x00 27. "TX_TRNG_SKP_CLK_EN,TX_TRNG_SKP_CLK_EN control" "0,1"
newline
eventfld.long 0x00 26. "PAI_CLK_EN,RESERVED" "0,1"
eventfld.long 0x00 25. "TX_SEC_MEM_CLK_EN,TX_SEC_MEM_CLK_EN control" "0,1"
newline
eventfld.long 0x00 24. "TX_PHY_INT_CLK_EN,TX_PHY_INT_CLK_EN control" "0,1"
eventfld.long 0x00 23. "TX_PHY_PIXEL_CLK_EN,RESERVED" "0,1"
newline
eventfld.long 0x00 22. "TX_PHY_APB_CLK_EN,TX_PHY_APB_CLK_EN control" "0,1"
eventfld.long 0x00 21. "TX_PREP_CLK_EN,TX_PREP_CLK_EN control" "0,1"
newline
eventfld.long 0x00 20. "TX_SKP_CLK_EN,TX_SKP_CLK_EN control" "0,1"
eventfld.long 0x00 19. "TX_SFR_CLK_EN,TX_SFR_CLK_EN control" "0,1"
newline
eventfld.long 0x00 18. "TX_PIXEL_CLK_EN,TX_PIXEL_CLK_EN control" "0,1"
eventfld.long 0x00 17. "TX_GPA_CLK_EN,TX_GPA_CLK_EN control" "0,1"
newline
eventfld.long 0x00 16. "TX_ESM_CLK_EN,TX_ESM_CLK_EN control" "0,1"
eventfld.long 0x00 15. "TX_CEC_CLK_EN,TX_CEC_CLK_EN control" "0,1"
newline
eventfld.long 0x00 14. "TX_APB_CLK_EN,TX_APB_CLK_EN control" "0,1"
eventfld.long 0x00 13. "TX_HPI_CLK_EN,TX_HPI_CLK_EN control" "0,1"
newline
eventfld.long 0x00 12. "HTX_PIPE_CLK_SEL,HTX_PIPE_CLK_SEL control" "0,1"
eventfld.long 0x00 11. "lcdif_clk_sel,lcdif_clk_sel control" "0,1"
newline
eventfld.long 0x00 10. "htxphy_clk_sel,htxphy_clk_sel control" "0,1"
eventfld.long 0x00 9. "fdcc_clk_sel,RESERVED" "0,1"
newline
eventfld.long 0x00 8. "vpll_clk_sel,RESERVED" "0,1"
eventfld.long 0x00 6. "VSFD_CEA_CLK_EN,VSFD_CEA_CLK_EN control" "0,1"
newline
eventfld.long 0x00 5. "HRV_MWR_CEA_CLK_EN,HRV_MWR_CEA_CLK_EN control" "0,1"
eventfld.long 0x00 4. "HRV_MWR_B_CLK_EN,HRV_MWR_B_CLK_EN control" "0,1"
newline
eventfld.long 0x00 3. "HRV_MWR_APB_CLK_EN,HRV_MWR_APB_CLK_EN control" "0,1"
eventfld.long 0x00 2. "FDCC_REF_CLK_EN,FDCC_REF_CLK_EN control" "0,1"
newline
eventfld.long 0x00 1. "FDCC_IHDMI_CLK_EN,RESERVED" "0,1"
group.long 0x5C++0x03
line.long 0x00 "RTX_CLK_CTL1_TOG,HDMI_RTX_CLK_CTL1"
bitfld.long 0x00 30. "TX_TRNG_APB_CLK_EN,TX_TRNG_APB_CLK_EN control" "0,1"
bitfld.long 0x00 29. "TX_MEM_266M_CLK_EN,RESERVED" "0,1"
newline
bitfld.long 0x00 28. "TX_VID_LINK_PIX_CLK_EN,TX_VID_LINK_PIX_CLK_EN control" "0,1"
bitfld.long 0x00 27. "TX_TRNG_SKP_CLK_EN,TX_TRNG_SKP_CLK_EN control" "0,1"
newline
bitfld.long 0x00 26. "PAI_CLK_EN,RESERVED" "0,1"
bitfld.long 0x00 25. "TX_SEC_MEM_CLK_EN,TX_SEC_MEM_CLK_EN control" "0,1"
newline
bitfld.long 0x00 24. "TX_PHY_INT_CLK_EN,TX_PHY_INT_CLK_EN control" "0,1"
bitfld.long 0x00 23. "TX_PHY_PIXEL_CLK_EN,RESERVED" "0,1"
newline
bitfld.long 0x00 22. "TX_PHY_APB_CLK_EN,TX_PHY_APB_CLK_EN control" "0,1"
bitfld.long 0x00 21. "TX_PREP_CLK_EN,TX_PREP_CLK_EN control" "0,1"
newline
bitfld.long 0x00 20. "TX_SKP_CLK_EN,TX_SKP_CLK_EN control" "0,1"
bitfld.long 0x00 19. "TX_SFR_CLK_EN,TX_SFR_CLK_EN control" "0,1"
newline
bitfld.long 0x00 18. "TX_PIXEL_CLK_EN,TX_PIXEL_CLK_EN control" "0,1"
bitfld.long 0x00 17. "TX_GPA_CLK_EN,TX_GPA_CLK_EN control" "0,1"
newline
bitfld.long 0x00 16. "TX_ESM_CLK_EN,TX_ESM_CLK_EN control" "0,1"
bitfld.long 0x00 15. "TX_CEC_CLK_EN,TX_CEC_CLK_EN control" "0,1"
newline
bitfld.long 0x00 14. "TX_APB_CLK_EN,TX_APB_CLK_EN control" "0,1"
bitfld.long 0x00 13. "TX_HPI_CLK_EN,TX_HPI_CLK_EN control" "0,1"
newline
bitfld.long 0x00 12. "HTX_PIPE_CLK_SEL,HTX_PIPE_CLK_SEL control" "0,1"
bitfld.long 0x00 11. "lcdif_clk_sel,lcdif_clk_sel control" "0,1"
newline
bitfld.long 0x00 10. "htxphy_clk_sel,htxphy_clk_sel control" "0,1"
bitfld.long 0x00 9. "fdcc_clk_sel,RESERVED" "0,1"
newline
bitfld.long 0x00 8. "vpll_clk_sel,RESERVED" "0,1"
bitfld.long 0x00 6. "VSFD_CEA_CLK_EN,VSFD_CEA_CLK_EN control" "0,1"
newline
bitfld.long 0x00 5. "HRV_MWR_CEA_CLK_EN,HRV_MWR_CEA_CLK_EN control" "0,1"
bitfld.long 0x00 4. "HRV_MWR_B_CLK_EN,HRV_MWR_B_CLK_EN control" "0,1"
newline
bitfld.long 0x00 3. "HRV_MWR_APB_CLK_EN,HRV_MWR_APB_CLK_EN control" "0,1"
bitfld.long 0x00 2. "FDCC_REF_CLK_EN,FDCC_REF_CLK_EN control" "0,1"
newline
bitfld.long 0x00 1. "FDCC_IHDMI_CLK_EN,RESERVED" "0,1"
group.long 0x60++0x03
line.long 0x00 "RTX_CLK_CTL2,RTX_CLK_CTL2"
bitfld.long 0x00 30.--31. "PAI_AUD_CLK_CTL,Used to bypass the programmable clock controls for aud_clk input of HTX_PAI" "0,1,2,3"
bitfld.long 0x00 28.--29. "PAI_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HTX_PAI" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "TX_PHY_INT_CLK_CTL,Used to bypass the programmable clock controls for int_clk input of the HDMI TX PHY" "0,1,2,3"
bitfld.long 0x00 24.--25. "TX_PHY_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of the HDMI TX PHY" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "HDMI_TX_PREP_CLK_CTL,Used to bypass the programmable clock controls for prep_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 20.--21. "HDMI_TX_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "HDMI_TX_SFR_CLK_CTL,Used to bypass the programmable clock controls for sfr_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 16.--17. "HDMI_TX_PIX_CLK_CTL,Used to bypass the programmable clock controls for ipixel_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "HDMI_TX_GPA_CLK_CTL,Used to bypass the programmable clock controls for gpa_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 12.--13. "HDMI_TX_ESM_CLK_CTL,Used to bypass the programmable clock controls for esm_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "HDMI_TX_CEC_CLK_CTL,Used to bypass the programmable clock controls for cec_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 8.--9. "HDMI_TX_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "HDMI_TX_HPI_CLK_CTL,Used to bypass the programmable clock controls for hpi_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 4.--5. "FDCC_REF_CLK_CTL,Used to bypass the programmable clock controls for FDCC ref clock" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "FDCC_APB_CLK_CTL,Used to bypass the programmable clock controls for FDCC apb clock" "0,1,2,3"
bitfld.long 0x00 0.--1. "IRQS_CLK_CTL,Used to bypass the programmable clock controls for IRQ_STEER" "0,1,2,3"
group.long 0x64++0x03
line.long 0x00 "RTX_CLK_CTL2_SET,RTX_CLK_CTL2"
bitfld.long 0x00 30.--31. "PAI_AUD_CLK_CTL,Used to bypass the programmable clock controls for aud_clk input of HTX_PAI" "0,1,2,3"
bitfld.long 0x00 28.--29. "PAI_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HTX_PAI" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "TX_PHY_INT_CLK_CTL,Used to bypass the programmable clock controls for int_clk input of the HDMI TX PHY" "0,1,2,3"
bitfld.long 0x00 24.--25. "TX_PHY_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of the HDMI TX PHY" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "HDMI_TX_PREP_CLK_CTL,Used to bypass the programmable clock controls for prep_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 20.--21. "HDMI_TX_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "HDMI_TX_SFR_CLK_CTL,Used to bypass the programmable clock controls for sfr_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 16.--17. "HDMI_TX_PIX_CLK_CTL,Used to bypass the programmable clock controls for ipixel_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "HDMI_TX_GPA_CLK_CTL,Used to bypass the programmable clock controls for gpa_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 12.--13. "HDMI_TX_ESM_CLK_CTL,Used to bypass the programmable clock controls for esm_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "HDMI_TX_CEC_CLK_CTL,Used to bypass the programmable clock controls for cec_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 8.--9. "HDMI_TX_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "HDMI_TX_HPI_CLK_CTL,Used to bypass the programmable clock controls for hpi_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 4.--5. "FDCC_REF_CLK_CTL,Used to bypass the programmable clock controls for FDCC ref clock" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "FDCC_APB_CLK_CTL,Used to bypass the programmable clock controls for FDCC apb clock" "0,1,2,3"
bitfld.long 0x00 0.--1. "IRQS_CLK_CTL,Used to bypass the programmable clock controls for IRQ_STEER" "0,1,2,3"
group.long 0x68++0x03
line.long 0x00 "RTX_CLK_CTL2_CLR,RTX_CLK_CTL2"
eventfld.long 0x00 30.--31. "PAI_AUD_CLK_CTL,Used to bypass the programmable clock controls for aud_clk input of HTX_PAI" "0,1,2,3"
eventfld.long 0x00 28.--29. "PAI_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HTX_PAI" "0,1,2,3"
newline
eventfld.long 0x00 26.--27. "TX_PHY_INT_CLK_CTL,Used to bypass the programmable clock controls for int_clk input of the HDMI TX PHY" "0,1,2,3"
eventfld.long 0x00 24.--25. "TX_PHY_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of the HDMI TX PHY" "0,1,2,3"
newline
eventfld.long 0x00 22.--23. "HDMI_TX_PREP_CLK_CTL,Used to bypass the programmable clock controls for prep_clk input of HDMI TX" "0,1,2,3"
eventfld.long 0x00 20.--21. "HDMI_TX_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of HDMI TX" "0,1,2,3"
newline
eventfld.long 0x00 18.--19. "HDMI_TX_SFR_CLK_CTL,Used to bypass the programmable clock controls for sfr_clk input of HDMI TX" "0,1,2,3"
eventfld.long 0x00 16.--17. "HDMI_TX_PIX_CLK_CTL,Used to bypass the programmable clock controls for ipixel_clk input of HDMI TX" "0,1,2,3"
newline
eventfld.long 0x00 14.--15. "HDMI_TX_GPA_CLK_CTL,Used to bypass the programmable clock controls for gpa_clk input of HDMI TX" "0,1,2,3"
eventfld.long 0x00 12.--13. "HDMI_TX_ESM_CLK_CTL,Used to bypass the programmable clock controls for esm_clk input of HDMI TX" "0,1,2,3"
newline
eventfld.long 0x00 10.--11. "HDMI_TX_CEC_CLK_CTL,Used to bypass the programmable clock controls for cec_clk input of HDMI TX" "0,1,2,3"
eventfld.long 0x00 8.--9. "HDMI_TX_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HDMI TX" "0,1,2,3"
newline
eventfld.long 0x00 6.--7. "HDMI_TX_HPI_CLK_CTL,Used to bypass the programmable clock controls for hpi_clk input of HDMI TX" "0,1,2,3"
eventfld.long 0x00 4.--5. "FDCC_REF_CLK_CTL,Used to bypass the programmable clock controls for FDCC ref clock" "0,1,2,3"
newline
eventfld.long 0x00 2.--3. "FDCC_APB_CLK_CTL,Used to bypass the programmable clock controls for FDCC apb clock" "0,1,2,3"
eventfld.long 0x00 0.--1. "IRQS_CLK_CTL,Used to bypass the programmable clock controls for IRQ_STEER" "0,1,2,3"
group.long 0x6C++0x03
line.long 0x00 "RTX_CLK_CTL2_TOG,RTX_CLK_CTL2"
bitfld.long 0x00 30.--31. "PAI_AUD_CLK_CTL,Used to bypass the programmable clock controls for aud_clk input of HTX_PAI" "0,1,2,3"
bitfld.long 0x00 28.--29. "PAI_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HTX_PAI" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "TX_PHY_INT_CLK_CTL,Used to bypass the programmable clock controls for int_clk input of the HDMI TX PHY" "0,1,2,3"
bitfld.long 0x00 24.--25. "TX_PHY_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of the HDMI TX PHY" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "HDMI_TX_PREP_CLK_CTL,Used to bypass the programmable clock controls for prep_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 20.--21. "HDMI_TX_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "HDMI_TX_SFR_CLK_CTL,Used to bypass the programmable clock controls for sfr_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 16.--17. "HDMI_TX_PIX_CLK_CTL,Used to bypass the programmable clock controls for ipixel_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "HDMI_TX_GPA_CLK_CTL,Used to bypass the programmable clock controls for gpa_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 12.--13. "HDMI_TX_ESM_CLK_CTL,Used to bypass the programmable clock controls for esm_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "HDMI_TX_CEC_CLK_CTL,Used to bypass the programmable clock controls for cec_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 8.--9. "HDMI_TX_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of HDMI TX" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "HDMI_TX_HPI_CLK_CTL,Used to bypass the programmable clock controls for hpi_clk input of HDMI TX" "0,1,2,3"
bitfld.long 0x00 4.--5. "FDCC_REF_CLK_CTL,Used to bypass the programmable clock controls for FDCC ref clock" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "FDCC_APB_CLK_CTL,Used to bypass the programmable clock controls for FDCC apb clock" "0,1,2,3"
bitfld.long 0x00 0.--1. "IRQS_CLK_CTL,Used to bypass the programmable clock controls for IRQ_STEER" "0,1,2,3"
group.long 0x70++0x03
line.long 0x00 "RTX_CLK_CTL3,RTX_CLK_CTL3"
bitfld.long 0x00 30.--31. "NOC_B_CLK_CTL,Used to bypass the programmable clock controls for bus clock input of the HDMI NOC" "0,1,2,3"
bitfld.long 0x00 28.--29. "NOC_HDCP_CLK_CTL,Used to bypass the programmable clock controls for hdcp clock input of the HDMI NOC" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "LCDIF_SPU_CLK_CTL,Used to bypass the programmable clock controls for spu_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 24.--25. "LCDIF_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of LCDIF" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "LCDIF_PDI_CLK_CTL,Used to bypass the programmable clock controls for pdi_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 20.--21. "LCDIF_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of LCDIF" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "LCDIF_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 16.--17. "VSFD_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of vsfd" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "VSFD_HTX_P_CLK_CTL,Used to bypass the programmable clock controls for the htx_p_clk input used in VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
bitfld.long 0x00 12.--13. "VSFD_HTX_APB_CLK_CTL,Used to bypass the programmable clock controls for the apb clk input of VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "HRV_MWR_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of HRV_MWR" "0,1,2,3"
bitfld.long 0x00 8.--9. "HRV_MWR_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of HRV_MWR" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "VID_SLV_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of video link slave" "0,1,2,3"
bitfld.long 0x00 4.--5. "VID_SLV_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of video link slave" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "TRNG_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of TRNG" "0,1,2,3"
bitfld.long 0x00 0.--1. "TRNG_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of TRNG" "0,1,2,3"
group.long 0x74++0x03
line.long 0x00 "RTX_CLK_CTL3_SET,RTX_CLK_CTL3"
bitfld.long 0x00 30.--31. "NOC_B_CLK_CTL,Used to bypass the programmable clock controls for bus clock input of the HDMI NOC" "0,1,2,3"
bitfld.long 0x00 28.--29. "NOC_HDCP_CLK_CTL,Used to bypass the programmable clock controls for hdcp clock input of the HDMI NOC" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "LCDIF_SPU_CLK_CTL,Used to bypass the programmable clock controls for spu_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 24.--25. "LCDIF_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of LCDIF" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "LCDIF_PDI_CLK_CTL,Used to bypass the programmable clock controls for pdi_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 20.--21. "LCDIF_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of LCDIF" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "LCDIF_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 16.--17. "VSFD_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of vsfd" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "VSFD_HTX_P_CLK_CTL,Used to bypass the programmable clock controls for the htx_p_clk input used in VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
bitfld.long 0x00 12.--13. "VSFD_HTX_APB_CLK_CTL,Used to bypass the programmable clock controls for the apb clk input of VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "HRV_MWR_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of HRV_MWR" "0,1,2,3"
bitfld.long 0x00 8.--9. "HRV_MWR_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of HRV_MWR" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "VID_SLV_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of video link slave" "0,1,2,3"
bitfld.long 0x00 4.--5. "VID_SLV_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of video link slave" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "TRNG_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of TRNG" "0,1,2,3"
bitfld.long 0x00 0.--1. "TRNG_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of TRNG" "0,1,2,3"
group.long 0x78++0x03
line.long 0x00 "RTX_CLK_CTL3_CLR,RTX_CLK_CTL3"
eventfld.long 0x00 30.--31. "NOC_B_CLK_CTL,Used to bypass the programmable clock controls for bus clock input of the HDMI NOC" "0,1,2,3"
eventfld.long 0x00 28.--29. "NOC_HDCP_CLK_CTL,Used to bypass the programmable clock controls for hdcp clock input of the HDMI NOC" "0,1,2,3"
newline
eventfld.long 0x00 26.--27. "LCDIF_SPU_CLK_CTL,Used to bypass the programmable clock controls for spu_clk input of LCDIF" "0,1,2,3"
eventfld.long 0x00 24.--25. "LCDIF_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of LCDIF" "0,1,2,3"
newline
eventfld.long 0x00 22.--23. "LCDIF_PDI_CLK_CTL,Used to bypass the programmable clock controls for pdi_clk input of LCDIF" "0,1,2,3"
eventfld.long 0x00 20.--21. "LCDIF_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of LCDIF" "0,1,2,3"
newline
eventfld.long 0x00 18.--19. "LCDIF_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of LCDIF" "0,1,2,3"
eventfld.long 0x00 16.--17. "VSFD_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of vsfd" "0,1,2,3"
newline
eventfld.long 0x00 14.--15. "VSFD_HTX_P_CLK_CTL,Used to bypass the programmable clock controls for the htx_p_clk input used in VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
eventfld.long 0x00 12.--13. "VSFD_HTX_APB_CLK_CTL,Used to bypass the programmable clock controls for the apb clk input of VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
newline
eventfld.long 0x00 10.--11. "HRV_MWR_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of HRV_MWR" "0,1,2,3"
eventfld.long 0x00 8.--9. "HRV_MWR_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of HRV_MWR" "0,1,2,3"
newline
eventfld.long 0x00 6.--7. "VID_SLV_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of video link slave" "0,1,2,3"
eventfld.long 0x00 4.--5. "VID_SLV_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of video link slave" "0,1,2,3"
newline
eventfld.long 0x00 2.--3. "TRNG_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of TRNG" "0,1,2,3"
eventfld.long 0x00 0.--1. "TRNG_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of TRNG" "0,1,2,3"
group.long 0x7C++0x03
line.long 0x00 "RTX_CLK_CTL3_TOG,RTX_CLK_CTL3"
bitfld.long 0x00 30.--31. "NOC_B_CLK_CTL,Used to bypass the programmable clock controls for bus clock input of the HDMI NOC" "0,1,2,3"
bitfld.long 0x00 28.--29. "NOC_HDCP_CLK_CTL,Used to bypass the programmable clock controls for hdcp clock input of the HDMI NOC" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "LCDIF_SPU_CLK_CTL,Used to bypass the programmable clock controls for spu_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 24.--25. "LCDIF_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of LCDIF" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "LCDIF_PDI_CLK_CTL,Used to bypass the programmable clock controls for pdi_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 20.--21. "LCDIF_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of LCDIF" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "LCDIF_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of LCDIF" "0,1,2,3"
bitfld.long 0x00 16.--17. "VSFD_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of vsfd" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "VSFD_HTX_P_CLK_CTL,Used to bypass the programmable clock controls for the htx_p_clk input used in VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
bitfld.long 0x00 12.--13. "VSFD_HTX_APB_CLK_CTL,Used to bypass the programmable clock controls for the apb clk input of VSFD (including portions of HRV_MWR logic)" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "HRV_MWR_CEA_CLK_CTL,Used to bypass the programmable clock controls for cea_clk input of HRV_MWR" "0,1,2,3"
bitfld.long 0x00 8.--9. "HRV_MWR_B_CLK_CTL,Used to bypass the programmable clock controls for b_clk input of HRV_MWR" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "VID_SLV_PIX_CLK_CTL,Used to bypass the programmable clock controls for pix_clk input of video link slave" "0,1,2,3"
bitfld.long 0x00 4.--5. "VID_SLV_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of video link slave" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "TRNG_SKP_CLK_CTL,Used to bypass the programmable clock controls for skp_clk input of TRNG" "0,1,2,3"
bitfld.long 0x00 0.--1. "TRNG_APB_CLK_CTL,Used to bypass the programmable clock controls for apb_clk input of TRNG" "0,1,2,3"
group.long 0x80++0x03
line.long 0x00 "RTX_CLK_CTL4,RTX_CLK_CTL4"
bitfld.long 0x00 2.--3. "TX_SEC_MEM_CLK_CTL,Used to bypass the request based clock gating on tx_sec_mem" "0,1,2,3"
bitfld.long 0x00 0.--1. "REVOCMEM_CLK_CTL,Used to bypass the request based clock gating on revocmem" "0,1,2,3"
group.long 0x84++0x03
line.long 0x00 "RTX_CLK_CTL4_SET,RTX_CLK_CTL4"
bitfld.long 0x00 2.--3. "TX_SEC_MEM_CLK_CTL,Used to bypass the request based clock gating on tx_sec_mem" "0,1,2,3"
bitfld.long 0x00 0.--1. "REVOCMEM_CLK_CTL,Used to bypass the request based clock gating on revocmem" "0,1,2,3"
group.long 0x88++0x03
line.long 0x00 "RTX_CLK_CTL4_CLR,RTX_CLK_CTL4"
eventfld.long 0x00 2.--3. "TX_SEC_MEM_CLK_CTL,Used to bypass the request based clock gating on tx_sec_mem" "0,1,2,3"
eventfld.long 0x00 0.--1. "REVOCMEM_CLK_CTL,Used to bypass the request based clock gating on revocmem" "0,1,2,3"
group.long 0x8C++0x03
line.long 0x00 "RTX_CLK_CTL4_TOG,RTX_CLK_CTL4"
bitfld.long 0x00 2.--3. "TX_SEC_MEM_CLK_CTL,Used to bypass the request based clock gating on tx_sec_mem" "0,1,2,3"
bitfld.long 0x00 0.--1. "REVOCMEM_CLK_CTL,Used to bypass the request based clock gating on revocmem" "0,1,2,3"
group.long 0x90++0x03
line.long 0x00 "RTX_IRQ_MASK,HDMI_RX_Control"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Interrupt Mask for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Interrupt Mask for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Interrupt Mask for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Interrupt Mask for TX_HPD_HIGH2LOW" "0,1"
group.long 0x94++0x03
line.long 0x00 "RTX_IRQ_MASK_SET,HDMI_RX_Control"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Interrupt Mask for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Interrupt Mask for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Interrupt Mask for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Interrupt Mask for TX_HPD_HIGH2LOW" "0,1"
group.long 0x98++0x03
line.long 0x00 "RTX_IRQ_MASK_CLR,HDMI_RX_Control"
eventfld.long 0x00 15. "TX_READY_LOW2HIGH,Interrupt Mask for TX_READY_LOW2HIGH" "0,1"
eventfld.long 0x00 14. "TX_READY_HIGH2LOW,Interrupt Mask for TX_READY_HIGH2LOW" "0,1"
newline
eventfld.long 0x00 13. "TX_HPD_LOW2HIGH,Interrupt Mask for TX_HPD_LOW2HIGH" "0,1"
eventfld.long 0x00 12. "TX_HPD_HIGH2LOW,Interrupt Mask for TX_HPD_HIGH2LOW" "0,1"
group.long 0x9C++0x03
line.long 0x00 "RTX_IRQ_MASK_TOG,HDMI_RX_Control"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Interrupt Mask for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Interrupt Mask for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Interrupt Mask for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Interrupt Mask for TX_HPD_HIGH2LOW" "0,1"
rgroup.long 0xA0++0x03
line.long 0x00 "RTX_IRQ_MASKED_STATUS,HDMI_TX Masked Interrupt status"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Masked Interrupt status for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Masked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Masked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Masked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
rgroup.long 0xA4++0x03
line.long 0x00 "RTX_IRQ_MASKED_STATUS_SET,HDMI_TX Masked Interrupt status"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Masked Interrupt status for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Masked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Masked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Masked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
rgroup.long 0xA8++0x03
line.long 0x00 "RTX_IRQ_MASKED_STATUS_CLR,HDMI_TX Masked Interrupt status"
eventfld.long 0x00 15. "TX_READY_LOW2HIGH,Masked Interrupt status for TX_READY_LOW2HIGH" "0,1"
eventfld.long 0x00 14. "TX_READY_HIGH2LOW,Masked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
eventfld.long 0x00 13. "TX_HPD_LOW2HIGH,Masked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
eventfld.long 0x00 12. "TX_HPD_HIGH2LOW,Masked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
rgroup.long 0xAC++0x03
line.long 0x00 "RTX_IRQ_MASKED_STATUS_TOG,HDMI_TX Masked Interrupt status"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Masked Interrupt status for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Masked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Masked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Masked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
group.long 0xB0++0x03
line.long 0x00 "RTX_IRQ_NONMASK_STATUS,HDMI_RX_Control"
eventfld.long 0x00 15. "TX_READY_LOW2HIGH,Unmasked Interrupt status for TX_READY_LOW2HIGH" "0,1"
eventfld.long 0x00 14. "TX_READY_HIGH2LOW,Unmasked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
eventfld.long 0x00 13. "TX_HPD_LOW2HIGH,Unmasked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
eventfld.long 0x00 12. "TX_HPD_HIGH2LOW,Unmasked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
group.long 0xB4++0x03
line.long 0x00 "RTX_IRQ_NONMASK_STATUS_SET,HDMI_RX_Control"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Unmasked Interrupt status for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Unmasked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Unmasked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Unmasked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
group.long 0xB8++0x03
line.long 0x00 "RTX_IRQ_NONMASK_STATUS_CLR,HDMI_RX_Control"
eventfld.long 0x00 15. "TX_READY_LOW2HIGH,Unmasked Interrupt status for TX_READY_LOW2HIGH" "0,1"
eventfld.long 0x00 14. "TX_READY_HIGH2LOW,Unmasked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
eventfld.long 0x00 13. "TX_HPD_LOW2HIGH,Unmasked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
eventfld.long 0x00 12. "TX_HPD_HIGH2LOW,Unmasked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
group.long 0xBC++0x03
line.long 0x00 "RTX_IRQ_NONMASK_STATUS_TOG,HDMI_RX_Control"
bitfld.long 0x00 15. "TX_READY_LOW2HIGH,Unmasked Interrupt status for TX_READY_LOW2HIGH" "0,1"
bitfld.long 0x00 14. "TX_READY_HIGH2LOW,Unmasked Interrupt status for TX_READY_HIGH2LOW" "0,1"
newline
bitfld.long 0x00 13. "TX_HPD_LOW2HIGH,Unmasked Interrupt status for TX_HPD_LOW2HIGH" "0,1"
bitfld.long 0x00 12. "TX_HPD_HIGH2LOW,Unmasked Interrupt status for TX_HPD_HIGH2LOW" "0,1"
group.long 0x200++0x03
line.long 0x00 "TX_CONTROL0,Miscellaneous Controls for the HDMI TX Controller"
bitfld.long 0x00 24. "TRNG_LOCK,TRNG_LOCK control" "0,1"
bitfld.long 0x00 23. "DDC_SDAIN_FILT_BYP,DDC_SDAIN_FILT_BYP" "0,1"
newline
bitfld.long 0x00 22. "DDC_SCLIN_FILT_BYP,DDC_SCLIN_FILT_BYP" "0,1"
bitfld.long 0x00 21. "CECIN_FILT_BYP,CECIN_FILT_BYP" "0,1"
newline
bitfld.long 0x00 20. "HPD_FILT_BYP,HPD_FILT_BYP" "0,1"
bitfld.long 0x00 16.--18. "HRV_MWR_NOC_HURRY,HRV_MWR_NOC_HURRY" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "LCDIF_NOC_HURRY,LCDIF_NOC_HURRY" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--8. "TX_CTL_CLK_DIV_CNT,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 3. "TX_PHY_PDOWN,TX_PHY_PDOWN control" "0,1"
bitfld.long 0x00 2. "TX_SKP_KEYS_VALID,RESERVED" "0,1"
newline
bitfld.long 0x00 1. "TX_CEC_EN,TX_CEC_EN control" "0,1"
bitfld.long 0x00 0. "TX_KEY_MEM_WR_LOCK,TX_KEY_MEM_WR_LOCK control" "0,1"
group.long 0x204++0x03
line.long 0x00 "TX_CONTROL0_SET,Miscellaneous Controls for the HDMI TX Controller"
bitfld.long 0x00 24. "TRNG_LOCK,TRNG_LOCK control" "0,1"
bitfld.long 0x00 23. "DDC_SDAIN_FILT_BYP,DDC_SDAIN_FILT_BYP" "0,1"
newline
bitfld.long 0x00 22. "DDC_SCLIN_FILT_BYP,DDC_SCLIN_FILT_BYP" "0,1"
bitfld.long 0x00 21. "CECIN_FILT_BYP,CECIN_FILT_BYP" "0,1"
newline
bitfld.long 0x00 20. "HPD_FILT_BYP,HPD_FILT_BYP" "0,1"
bitfld.long 0x00 16.--18. "HRV_MWR_NOC_HURRY,HRV_MWR_NOC_HURRY" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "LCDIF_NOC_HURRY,LCDIF_NOC_HURRY" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--8. "TX_CTL_CLK_DIV_CNT,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 3. "TX_PHY_PDOWN,TX_PHY_PDOWN control" "0,1"
bitfld.long 0x00 2. "TX_SKP_KEYS_VALID,RESERVED" "0,1"
newline
bitfld.long 0x00 1. "TX_CEC_EN,TX_CEC_EN control" "0,1"
bitfld.long 0x00 0. "TX_KEY_MEM_WR_LOCK,TX_KEY_MEM_WR_LOCK control" "0,1"
group.long 0x208++0x03
line.long 0x00 "TX_CONTROL0_CLR,Miscellaneous Controls for the HDMI TX Controller"
eventfld.long 0x00 24. "TRNG_LOCK,TRNG_LOCK control" "0,1"
eventfld.long 0x00 23. "DDC_SDAIN_FILT_BYP,DDC_SDAIN_FILT_BYP" "0,1"
newline
eventfld.long 0x00 22. "DDC_SCLIN_FILT_BYP,DDC_SCLIN_FILT_BYP" "0,1"
eventfld.long 0x00 21. "CECIN_FILT_BYP,CECIN_FILT_BYP" "0,1"
newline
eventfld.long 0x00 20. "HPD_FILT_BYP,HPD_FILT_BYP" "0,1"
eventfld.long 0x00 16.--18. "HRV_MWR_NOC_HURRY,HRV_MWR_NOC_HURRY" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 12.--14. "LCDIF_NOC_HURRY,LCDIF_NOC_HURRY" "0,1,2,3,4,5,6,7"
eventfld.long 0x00 4.--8. "TX_CTL_CLK_DIV_CNT,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
eventfld.long 0x00 3. "TX_PHY_PDOWN,TX_PHY_PDOWN control" "0,1"
eventfld.long 0x00 2. "TX_SKP_KEYS_VALID,RESERVED" "0,1"
newline
eventfld.long 0x00 1. "TX_CEC_EN,TX_CEC_EN control" "0,1"
eventfld.long 0x00 0. "TX_KEY_MEM_WR_LOCK,TX_KEY_MEM_WR_LOCK control" "0,1"
group.long 0x20C++0x03
line.long 0x00 "TX_CONTROL0_TOG,Miscellaneous Controls for the HDMI TX Controller"
bitfld.long 0x00 24. "TRNG_LOCK,TRNG_LOCK control" "0,1"
bitfld.long 0x00 23. "DDC_SDAIN_FILT_BYP,DDC_SDAIN_FILT_BYP" "0,1"
newline
bitfld.long 0x00 22. "DDC_SCLIN_FILT_BYP,DDC_SCLIN_FILT_BYP" "0,1"
bitfld.long 0x00 21. "CECIN_FILT_BYP,CECIN_FILT_BYP" "0,1"
newline
bitfld.long 0x00 20. "HPD_FILT_BYP,HPD_FILT_BYP" "0,1"
bitfld.long 0x00 16.--18. "HRV_MWR_NOC_HURRY,HRV_MWR_NOC_HURRY" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "LCDIF_NOC_HURRY,LCDIF_NOC_HURRY" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--8. "TX_CTL_CLK_DIV_CNT,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 3. "TX_PHY_PDOWN,TX_PHY_PDOWN control" "0,1"
bitfld.long 0x00 2. "TX_SKP_KEYS_VALID,RESERVED" "0,1"
newline
bitfld.long 0x00 1. "TX_CEC_EN,TX_CEC_EN control" "0,1"
bitfld.long 0x00 0. "TX_KEY_MEM_WR_LOCK,TX_KEY_MEM_WR_LOCK control" "0,1"
group.long 0x220++0x03
line.long 0x00 "TX_CONTROL2,TX Control"
hexmask.long.word 0x00 16.--25. 1. "TX_PREPCLK_ACTCYC_COUNT,TX_PREPCLK_ACTCYC_COUNT control"
hexmask.long.word 0x00 4.--13. 1. "TX_PREPCLK_TOT_COUNT,TX_PREPCLK_TOT_COUNT control"
group.long 0x224++0x03
line.long 0x00 "TX_CONTROL2_SET,TX Control"
hexmask.long.word 0x00 16.--25. 1. "TX_PREPCLK_ACTCYC_COUNT,TX_PREPCLK_ACTCYC_COUNT control"
hexmask.long.word 0x00 4.--13. 1. "TX_PREPCLK_TOT_COUNT,TX_PREPCLK_TOT_COUNT control"
group.long 0x228++0x03
line.long 0x00 "TX_CONTROL2_CLR,TX Control"
hexmask.long.word 0x00 16.--25. 1. "TX_PREPCLK_ACTCYC_COUNT,TX_PREPCLK_ACTCYC_COUNT control"
hexmask.long.word 0x00 4.--13. 1. "TX_PREPCLK_TOT_COUNT,TX_PREPCLK_TOT_COUNT control"
group.long 0x22C++0x03
line.long 0x00 "TX_CONTROL2_TOG,TX Control"
hexmask.long.word 0x00 16.--25. 1. "TX_PREPCLK_ACTCYC_COUNT,TX_PREPCLK_ACTCYC_COUNT control"
hexmask.long.word 0x00 4.--13. 1. "TX_PREPCLK_TOT_COUNT,TX_PREPCLK_TOT_COUNT control"
rgroup.long 0x230++0x03
line.long 0x00 "TX_STATUS0,Status"
bitfld.long 0x00 8. "TX_HPD_STATUS,TX_HPD_STATUS status" "0,1"
bitfld.long 0x00 7. "TX_PHY_PLL_LOCK,TX_PHY_PLL_LOCK status" "0,1"
newline
bitfld.long 0x00 6. "TX_PHY_RDY,TX_PHY_RDY status" "0,1"
bitfld.long 0x00 5. "TX_PHY_CLK_RDY,TX_PHY_CLK_RDY status" "0,1"
newline
bitfld.long 0x00 0.--4. "TX_PHY_AFC_CODE,TX_PHY_AFC_CODE status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x234++0x03
line.long 0x00 "TX_STATUS0_SET,Status"
bitfld.long 0x00 8. "TX_HPD_STATUS,TX_HPD_STATUS status" "0,1"
bitfld.long 0x00 7. "TX_PHY_PLL_LOCK,TX_PHY_PLL_LOCK status" "0,1"
newline
bitfld.long 0x00 6. "TX_PHY_RDY,TX_PHY_RDY status" "0,1"
bitfld.long 0x00 5. "TX_PHY_CLK_RDY,TX_PHY_CLK_RDY status" "0,1"
newline
bitfld.long 0x00 0.--4. "TX_PHY_AFC_CODE,TX_PHY_AFC_CODE status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x238++0x03
line.long 0x00 "TX_STATUS0_CLR,Status"
eventfld.long 0x00 8. "TX_HPD_STATUS,TX_HPD_STATUS status" "0,1"
eventfld.long 0x00 7. "TX_PHY_PLL_LOCK,TX_PHY_PLL_LOCK status" "0,1"
newline
eventfld.long 0x00 6. "TX_PHY_RDY,TX_PHY_RDY status" "0,1"
eventfld.long 0x00 5. "TX_PHY_CLK_RDY,TX_PHY_CLK_RDY status" "0,1"
newline
eventfld.long 0x00 0.--4. "TX_PHY_AFC_CODE,TX_PHY_AFC_CODE status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x23C++0x03
line.long 0x00 "TX_STATUS0_TOG,Status"
bitfld.long 0x00 8. "TX_HPD_STATUS,TX_HPD_STATUS status" "0,1"
bitfld.long 0x00 7. "TX_PHY_PLL_LOCK,TX_PHY_PLL_LOCK status" "0,1"
newline
bitfld.long 0x00 6. "TX_PHY_RDY,TX_PHY_RDY status" "0,1"
bitfld.long 0x00 5. "TX_PHY_CLK_RDY,TX_PHY_CLK_RDY status" "0,1"
newline
bitfld.long 0x00 0.--4. "TX_PHY_AFC_CODE,TX_PHY_AFC_CODE status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFC0++0x03
line.long 0x00 "SPARE_CONFIG0,Spare Config"
hexmask.long 0x00 0.--31. 1. "SPARE_CONFIG,TX decryption Seed"
group.long 0xFC4++0x03
line.long 0x00 "SPARE_CONFIG0_SET,Spare Config"
hexmask.long 0x00 0.--31. 1. "SPARE_CONFIG,TX decryption Seed"
group.long 0xFC8++0x03
line.long 0x00 "SPARE_CONFIG0_CLR,Spare Config"
hexmask.long 0x00 0.--31. 1. "SPARE_CONFIG,TX decryption Seed"
group.long 0xFCC++0x03
line.long 0x00 "SPARE_CONFIG0_TOG,Spare Config"
hexmask.long 0x00 0.--31. 1. "SPARE_CONFIG,TX decryption Seed"
rgroup.long 0xFF0++0x03
line.long 0x00 "SPARE_STATUS0,Spare Status0"
hexmask.long 0x00 0.--31. 1. "SPARE_STATUS,SPARE Control"
rgroup.long 0xFF4++0x03
line.long 0x00 "SPARE_STATUS0_SET,Spare Status0"
hexmask.long 0x00 0.--31. 1. "SPARE_STATUS,SPARE Control"
rgroup.long 0xFF8++0x03
line.long 0x00 "SPARE_STATUS0_CLR,Spare Status0"
hexmask.long 0x00 0.--31. 1. "SPARE_STATUS,SPARE Control"
rgroup.long 0xFFC++0x03
line.long 0x00 "SPARE_STATUS0_TOG,Spare Status0"
hexmask.long 0x00 0.--31. 1. "SPARE_STATUS,SPARE Control"
tree.end
tree "HSIO_BLK_CTRL"
base ad:0x32F10000
group.long 0x00++0x03
line.long 0x00 "GPR_REG0,Clock select reset and debug info select"
bitfld.long 0x00 8. "CRS_CLEAR,Clear CSR interrupt" "0,1"
bitfld.long 0x00 7. "CFG_READY,Configuration ready" "0,1"
newline
bitfld.long 0x00 6. "USB_PHY_REF_CLK_SEL,USB PHY ref clock selection" "0: 24Mhz exteral osc,1: 100Mhz high performace PLL"
bitfld.long 0x00 5. "PCIE_PHY_INIT_RESETN_INTERNAL,PCIE PHY init reset" "0,1"
newline
bitfld.long 0x00 4. "PCIE_PHY_APB_RESETN_INTERNAL,PCIE PHY APB interface reset" "0,1"
bitfld.long 0x00 2.--3. "PCIE_USB_DEBUG_INFO_SEL,PCIE USB debug information selection" "0,1,2,3"
newline
bitfld.long 0x00 1. "USB_CLOCK_MODULE_EN,USB related clock enable" "0,1"
bitfld.long 0x00 0. "PCIE_CLOCK_MODULE_EN,PCIE related clock enable" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "GPR_REG1,PCIE controller status"
bitfld.long 0x00 13. "PLL_LOCK,High performance PLL lock status" "0,1"
bitfld.long 0x00 10.--12. "PCIE_CTRL_PM_DSTATE,PCIE ctrl's pm dstate" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9. "PCIE_CTRL_PM_LINKST_IN_L0S,PCIE ctrl link in l0s state" "0,1"
bitfld.long 0x00 8. "PCIE_CTRL_PM_LINKST_IN_L1,PCIE ctrl link in l1 state" "0,1"
newline
bitfld.long 0x00 7. "PCIE_CTRL_PM_LINKST_IN_L1SUB,PCIE ctrl link in l1sub state" "0,1"
bitfld.long 0x00 1.--6. "SMLH_LTSSM_STATE,PCIE link state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "PM_EN_CORE_CLK,pm_en_core_clk pin status of pcie ctrl" "0,1"
group.long 0x08++0x03
line.long 0x00 "GPR_REG2,PLL configuration 0"
bitfld.long 0x00 31. "AFC_ENB_PLL,AFC_ENB input of high performance PLL" "0,1"
bitfld.long 0x00 29.--30. "LOCK_CON_REV_PLL,Lock con rev pin input of high performance PLL" "0,1,2,3"
newline
bitfld.long 0x00 27.--28. "LOCK_CON_DLY_PLL,Lock con delay input of high performance PLL" "0,1,2,3"
bitfld.long 0x00 25.--26. "LOCK_CON_OUT_PLL,Lock con input of high performance PLL" "0,1,2,3"
newline
bitfld.long 0x00 23.--24. "LOCK_CON_IN_PLL,Lock con in pin input of high performance PLL" "0,1,2,3"
bitfld.long 0x00 22. "LOCK_EN_PLL,locken pin input of high performance PLL" "0,1"
newline
bitfld.long 0x00 21. "BYPASS_PLL,Bypass pin input of high performance PLL" "0,1"
bitfld.long 0x00 19.--20. "ICP_PLL,ICP pin input of high performance PLL" "0,1,2,3"
newline
bitfld.long 0x00 16.--18. "S_PLL,S pin input of high performance PLL" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 6.--15. 1. "M_PLL,M pin input of high performance PLL"
newline
bitfld.long 0x00 0.--5. "P_PLL,P pin input of high performance PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "GPR_REG3,PLL configuration 1"
bitfld.long 0x00 31. "PLL_RESETB,reset pin input of high performance PLL" "0,1"
bitfld.long 0x00 18. "PLL_EXT_BYPASS,PLL ext bypass pin input of high performance PLL" "0,1"
newline
bitfld.long 0x00 17. "PLL_CKE,PLL cke pin input of high performance PLL" "0,1"
bitfld.long 0x00 13.--16. "RSEL_PLL,RSEL pin input of high performance PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "LRD_EN_PLL,LRD EN pin input of high performance PLL" "0,1"
bitfld.long 0x00 11. "PBIAS_CTRL_PLL,PBIAS CTRL pin input of high performance PLL" "0,1"
newline
bitfld.long 0x00 10. "PBIAS_CTRL_EN_PLL,PBIAS CTRL EN pin input of high performance PLL" "0,1"
bitfld.long 0x00 9. "VCO_BOOST_PLL,VCO BOOST pin input of high performance PLL" "0,1"
newline
bitfld.long 0x00 8. "FOUT_MASK_PLL,FOUT MASK pin input of high performance PLL" "0,1"
bitfld.long 0x00 7. "AFCINIT_SEL_PLL,AFCINT SEL input of high performance PLL" "0,1"
newline
bitfld.long 0x00 6. "FSEL_PLL,FSEL pin input of high performance PLL" "0,1"
bitfld.long 0x00 5. "FEED_EN_PLL,Feed en pin input of high performance PLL" "0,1"
newline
bitfld.long 0x00 0.--4. "EXTAFC_PLL,Extafc pin input of high performance PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10++0x03
line.long 0x00 "GPR_REG4,PCIE PME message and error detect register"
rbitfld.long 0x00 31. "INTM,Per PF dependent message interrupt is pending" "0,1"
rbitfld.long 0x00 30. "INTE,Per PF dependent error interrupt is pending" "0,1"
newline
eventfld.long 0x00 8. "ME,Indicates Multiple errors of same type" "0,1"
eventfld.long 0x00 7. "PCT,Indicates completion timeout" "0,1"
newline
eventfld.long 0x00 6. "PCAC,Completer abort was detected" "0,1"
eventfld.long 0x00 5. "CDNSC,Completion with data not succsessful was detected" "0,1"
newline
eventfld.long 0x00 4. "UREP,Indicates an unsupported request completion was detected" "0,1"
eventfld.long 0x00 3. "PTO,Indicates that PME turn off was detected" "0,1"
newline
eventfld.long 0x00 2. "HRD,Indicates a hot reset was detected" "0,1"
eventfld.long 0x00 1. "LDD,Indicates a link down was detected" "0,1"
newline
eventfld.long 0x00 0. "LUD,Indicates a link up was detected" "0,1"
group.long 0x14++0x03
line.long 0x00 "GPR_REG5,PCIE PME message and error detect interrupt enable register"
bitfld.long 0x00 7. "PCT_IE,completion timeout interrupt enable" "0,1"
bitfld.long 0x00 6. "PCAC_IE,Completer abort interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "CDNSC_IE,Completion with data not succsessful interrupt enable" "0,1"
bitfld.long 0x00 4. "UREP_IE,Unsupported request in EP mode interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "PTO_IE,PME turn off detect interrupt enable" "0,1"
bitfld.long 0x00 2. "HRD_IE,Hot reset detect interrupt enable" "0,1"
newline
bitfld.long 0x00 1. "LDD_IE,Link down detect interrupt enable" "0,1"
bitfld.long 0x00 0. "LUD_IE,Link up detect interrupt enable" "0,1"
group.long 0x18++0x03
line.long 0x00 "GPR_REG6,PCIE PME message and error detect interrupt detect disable register"
bitfld.long 0x00 8. "ME_DIS,Multiple errors of same type detection disable" "0,1"
bitfld.long 0x00 7. "PCT_DIS,completion detection disable" "0,1"
newline
bitfld.long 0x00 6. "PCAC_DIS,Completer abort detection disable" "0,1"
bitfld.long 0x00 5. "CDNSC_DIS,Completion with data not succsessful detection disable" "0,1"
newline
bitfld.long 0x00 4. "UREP_DIS,Unsupported request in EP mode detection disable" "0,1"
bitfld.long 0x00 3. "PTO_DIS,PME turn off detect disabled" "0,1"
newline
bitfld.long 0x00 2. "HRD_DIS,Hot reset detect disable" "0,1"
bitfld.long 0x00 1. "LDD_DIS,Link down detect disable" "0,1"
newline
bitfld.long 0x00 0. "LUD_DIS,Link up detect disable" "0,1"
group.long 0x1C++0x03
line.long 0x00 "GPR_REG7,USB1 beat limit and enable"
bitfld.long 0x00 16. "USB1_BEAT_LIMIT_EN,USB1 beat limit enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "USB1_BEAT_LIMIT,USB1 beat limit number"
group.long 0x20++0x03
line.long 0x00 "GPR_REG8,USB2 beat limit and enable"
bitfld.long 0x00 16. "USB2_BEAT_LIMIT_EN,USB2 beat limit enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "USB2_BEAT_LIMIT,USB2 beat limit number"
group.long 0x24++0x03
line.long 0x00 "GPR_REG9,PCIE beat limit and enable"
bitfld.long 0x00 16. "PCIE_BEAT_LIMIT_EN,PCIE beat limit enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "PCIE_BEAT_LIMIT,PCIE beat limit number"
group.long 0x100++0x03
line.long 0x00 "USB1_WAKEUP_CTRL,Register for USB1 wakeup"
bitfld.long 0x00 31. "OTG_WAKE_ENABLE,Global wakeup interrupt enable" "0,1"
bitfld.long 0x00 16. "PHY_BYPASSSEL,Transmitter Digital Bypass Select" "0,1"
newline
bitfld.long 0x00 15. "PHY_BYPASSDPEN,DP Transmitter Digital Bypass Enable" "0,1"
bitfld.long 0x00 14. "PHY_BYPASSDPDATA,Data for DP Transmitter Digital Bypass" "0,1"
newline
bitfld.long 0x00 13. "PHY_BYPASSDMEN,DM Transmitter Digital Bypass Enable" "0,1"
bitfld.long 0x00 12. "PHY_BYPASSDMDATA,Data for DM Transmitter Digital Bypass" "0,1"
newline
bitfld.long 0x00 11. "LOWSPEED_EN,Enable lowspeed autoresume feature" "0: FULL_HIGH_SPEED,1: LOWSPEED"
bitfld.long 0x00 10. "AUTORESUME_ENDLY,Tuning the timing between dp/dm data and enable signal when autoresume finish" "0,1"
newline
bitfld.long 0x00 9. "AUTORESUME_DATADLY,Please refer to the bitfield description for AUTORESUME_ENDLY" "0,1"
bitfld.long 0x00 8. "AUTORESUME_EN,Enable autoresume feature" "0: disable,1: enable"
newline
bitfld.long 0x00 5. "OTG_CONN_WAKEUP_EN,Enable signal for wakeup from connection or disconnection only for superspeed" "0,1"
bitfld.long 0x00 4. "OTG_VBUS_SOURCE_SEL,otg_vbus_source_sel" "0: select vbus_valid,1: select sessvld"
newline
bitfld.long 0x00 3. "OTG_U3_WAKE_EN,Enable signal for wake up from u3 state only for superspeed" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "OTG_ID_WAKEUP_EN,Enable signal for wake up from id change" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "OTG_VBUS_WAKE_EN,Enable signal for wake up from vbus valid or session valid changes" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "OTG_WKDPDMCHG_EN,Enable signal for wake up from dp/dm change" "0: DISABLE,1: ENABLE"
rgroup.long 0x104++0x03
line.long 0x00 "USB1_WAKEUP_STATUS,Status of USB1 wakeup"
bitfld.long 0x00 31. "OTG_WAKEUP_INTERRUPT,Same as WIR before it's OR of all wakeup interrupt then AND with otg_wakeup_enable" "0,1"
bitfld.long 0x00 13. "OTG_CONN_WAKEUP_INTERRUPT,Interrupt status of connection" "0,1"
newline
bitfld.long 0x00 11.--12. "PIPE3_POWERDOWN,Pipe powerdown" "0,1,2,3"
bitfld.long 0x00 10. "OTG_HOST_MODE,USB drd mode indicator" "0: DEVICE_MODE,1: HOST_MODE"
newline
bitfld.long 0x00 9. "PIPE_RXELECIDLE,pipe_rxelecidel wakeup source" "0,1"
bitfld.long 0x00 8. "OTG_PHY_OTGSESSVLD0,session valid wakeup source" "0,1"
newline
bitfld.long 0x00 7. "OTG_PHY_VBUSVALID0,vbus valid wakeup source" "0,1"
bitfld.long 0x00 6. "OTG_PHY_IDDIG0,ID status wakeup source" "0,1"
newline
bitfld.long 0x00 5. "OTG_PHY_LINESTATE0_1,linestate[1] wakeup source" "0,1"
bitfld.long 0x00 4. "OTG_PHY_LINESTATE0_0,linestate[0] wakeup source" "0,1"
newline
bitfld.long 0x00 3. "OTG_U3_WAKEUP_INTERRUP,Interrupt status of wakeup from u3 state" "0,1"
bitfld.long 0x00 2. "OTG_ID_WAKEUP_INTERRUPT,Interrupt status of wakeup from id" "0,1"
newline
bitfld.long 0x00 1. "OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT,Interrupt status of vbus or session valid signal" "0,1"
bitfld.long 0x00 0. "OTG_DP_DM_WAKEUP_INTERRUPT,Interrupt status of dm or dp otg_dp_wakeup_interrupt | otg_dm_wakeup_interrupt" "0,1"
group.long 0x108++0x03
line.long 0x00 "USB2_WAKEUP_CTRL,Register for USB2 wakeup"
bitfld.long 0x00 31. "OTG_WAKE_ENABLE,Global wakeup interrupt enable" "0,1"
bitfld.long 0x00 16. "PHY_BYPASSSEL,Transmitter Digital Bypass Select" "0,1"
newline
bitfld.long 0x00 15. "PHY_BYPASSDPEN,DP Transmitter Digital Bypass Enable" "0,1"
bitfld.long 0x00 14. "PHY_BYPASSDPDATA,Data for DP Transmitter Digital Bypass" "0,1"
newline
bitfld.long 0x00 13. "PHY_BYPASSDMEN,DM Transmitter Digital Bypass Enable" "0,1"
bitfld.long 0x00 12. "PHY_BYPASSDMDATA,Data for DM Transmitter Digital Bypass" "0,1"
newline
bitfld.long 0x00 11. "LOWSPEED_EN,Enable lowspeed autoresume feature" "0: FULL_HIGH_SPEED,1: LOWSPEED"
bitfld.long 0x00 10. "AUTORESUME_ENDLY,Tuning the timing between dp/dm data and enable signal when autoresume finish" "0,1"
newline
bitfld.long 0x00 9. "AUTORESUME_DATADLY,Please refer to the bitfield description for AUTORESUME_ENDLY" "0,1"
bitfld.long 0x00 8. "AUTORESUME_EN,Enable autoresume feature" "0: disable,1: enable"
newline
bitfld.long 0x00 5. "OTG_CONN_WAKEUP_EN,Enable signal for wakeup from connection or disconnection only for superspeed" "0,1"
bitfld.long 0x00 4. "OTG_VBUS_SOURCE_SEL,otg_vbus_source_sel" "0: select vbus_valid,1: select sessvld"
newline
bitfld.long 0x00 3. "OTG_U3_WAKE_EN,Enable signal for wake up from u3 state only for superspeed" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "OTG_ID_WAKEUP_EN,Enable signal for wake up from id change" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "OTG_VBUS_WAKE_EN,Enable signal for wake up from vbus valid or session valid changes" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "OTG_WKDPDMCHG_EN,Enable signal for wake up from dp/dm change" "0: DISABLE,1: ENABLE"
rgroup.long 0x10C++0x03
line.long 0x00 "USB2_WAKEUP_STATUS,Status of USB2 wakeup"
bitfld.long 0x00 31. "OTG_WAKEUP_INTERRUPT,Same as WIR before it's OR of all wakeup interrupt then AND with otg_wakeup_enable" "0,1"
bitfld.long 0x00 13. "OTG_CONN_WAKEUP_INTERRUPT,Interrupt status of connection" "0,1"
newline
bitfld.long 0x00 11.--12. "PIPE3_POWERDOWN,Pipe powerdown" "0,1,2,3"
bitfld.long 0x00 10. "OTG_HOST_MODE,USB drd mode indicator" "0: DEVICE_MODE,1: HOST_MODE"
newline
bitfld.long 0x00 9. "PIPE_RXELECIDLE,pipe_rxelecidel wakeup source" "0,1"
bitfld.long 0x00 8. "OTG_PHY_OTGSESSVLD0,session valid wakeup source" "0,1"
newline
bitfld.long 0x00 7. "OTG_PHY_VBUSVALID0,vbus valid wakeup source" "0,1"
bitfld.long 0x00 6. "OTG_PHY_IDDIG0,ID status wakeup source" "0,1"
newline
bitfld.long 0x00 5. "OTG_PHY_LINESTATE0_1,linestate[1] wakeup source" "0,1"
bitfld.long 0x00 4. "OTG_PHY_LINESTATE0_0,linestate[0] wakeup source" "0,1"
newline
bitfld.long 0x00 3. "OTG_U3_WAKEUP_INTERRUP,Interrupt status of wakeup from u3 state" "0,1"
bitfld.long 0x00 2. "OTG_ID_WAKEUP_INTERRUPT,Interrupt status of wakeup from id" "0,1"
newline
bitfld.long 0x00 1. "OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT,Interrupt status of vbus or session valid signal" "0,1"
bitfld.long 0x00 0. "OTG_DP_DM_WAKEUP_INTERRUPT,Interrupt status of dm or dp otg_dp_wakeup_interrupt | otg_dm_wakeup_interrupt" "0,1"
tree.end
tree "HTX_PAI (D_IP_HTX_PAI_SYN)"
base ad:0x32FC4800
group.long 0x00++0x03
line.long 0x00 "HTX_PAI_CTRL,HTX PAI Control"
bitfld.long 0x00 0. "ENABLE,HTX PAI Enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "HTX_PAI_CTRL_EXT,HTX PAI Control Extended"
hexmask.long.byte 0x00 24.--31. 1. "WTMK_HIGH,HTX PAI Watermark High"
hexmask.long.byte 0x00 16.--23. 1. "WTMK_LOW,HTX PAI Watermark Low"
newline
bitfld.long 0x00 11. "B_EXT,B-Field Extension" "0: Use default B-Preamble timing (from selected..,1: Extend B-Preamble timing to ensure it is set.."
bitfld.long 0x00 8.--10. "NUM_CH,Number of Channels Per Packet" "0: There is 1 channel per packet,1: There are 2 channels per packet,2: There are 3 channels per packet,3: There are 4 channels per packet,4: There are 5 channels per packet,5: There are 6 channels per packet,6: There are 7 channels per packet,7: There are 8 channels per packet"
newline
bitfld.long 0x00 0. "SOURCE,HTX PAI Source Select" "0: Normal operation,1: Low latency bypass mode"
group.long 0x08++0x03
line.long 0x00 "HTX_PAI_FIELD_CTRL,HTX PAI Field Control"
bitfld.long 0x00 31. "B_FILT,B-Detect Filter" "0,1"
bitfld.long 0x00 30. "PARITY_EN,Parity Enable" "0,1"
newline
bitfld.long 0x00 29. "END_SEL,Endianness Select" "0,1"
bitfld.long 0x00 24.--28. "PRE_SEL,IEC60958 Preamble Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 20.--23. "D_SEL,IEC60958 Data Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15.--19. "V_SEL,IEC60958 V Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--14. "U_SEL,IEC60958 U Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "C_SEL,IEC60958 C Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "P_SEL,IEC60958 P Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x0C++0x03
line.long 0x00 "HTX_PAI_STAT,HTX PAI Status"
bitfld.long 0x00 1. "WM_HIGH,Watermark High Flag" "0,1"
bitfld.long 0x00 0. "WM_LOW,Watermark Low Flag" "0,1"
group.long 0x10++0x03
line.long 0x00 "HTX_PAI_IRQ_NOMASK,HTX PAI Nonmasked Interrupt Flags"
eventfld.long 0x00 3. "WM_HIGH_IRQ,Watermark High IRQ" "0,1"
eventfld.long 0x00 2. "WM_LOW_IRQ,Watermark Low IRQ" "0,1"
newline
eventfld.long 0x00 1. "UND,HTX PAI Buffer Underflow" "0,1"
eventfld.long 0x00 0. "OVF,HTX PAI Buffer Overflow" "0,1"
group.long 0x14++0x03
line.long 0x00 "HTX_PAI_IRQ_MASKED,HTX PAI Masked Interrupt Flags"
eventfld.long 0x00 3. "WM_HIGH_IRQ,Watermark High IRQ Masked" "0,1"
eventfld.long 0x00 2. "WM_LOW_IRQ,Watermark Low IRQ Masked" "0,1"
newline
eventfld.long 0x00 1. "UND,HTX PAI Buffer Underflow" "0,1"
eventfld.long 0x00 0. "OVF,HTX PAI Buffer Overflow" "0,1"
group.long 0x18++0x03
line.long 0x00 "HTX_PAI_IRQ_MASK,HTX PAI IRQ Masks"
bitfld.long 0x00 3. "WM_HIGH_IRQ_MASK,Watermark High IRQ Mask" "0,1"
bitfld.long 0x00 2. "WM_LOW_IRQ_MASK,Watermark Low IRQ Mask" "0,1"
newline
bitfld.long 0x00 1. "UND_MASK,HTX PAI Buffer Underflow Mask" "0,1"
bitfld.long 0x00 0. "OVF_MASK,HTX PAI Buffer Overflow Mask" "0,1"
tree.end
tree "HTX_PVI"
base ad:0x32FC4000
group.long 0x00++0x03
line.long 0x00 "HTX_PVI_CTRL,HTX_PVI Control Reg"
bitfld.long 0x00 21. "EN_BG_INS_UNDRFLW,Enables the insertion of background color if the async FIFO underflows" "0,1"
bitfld.long 0x00 20. "EN_BG_INS_FDCC,Enables the insertion of background color if FDCC detects the HDMI Rx reference clock is out of specified video mode frequency range" "0,1"
newline
bitfld.long 0x00 18. "OP_VSYNC_POL,Controls the polarity of Vsync of the outgoing data" "0: OP_VSYNC_POL_0,1: OP_VSYNC_POL_1"
bitfld.long 0x00 17. "OP_HSYNC_POL,Controls the polarity of Hsync of the outgoing data" "0: OP_HSYNC_POL_0,1: OP_HSYNC_POL_1"
newline
bitfld.long 0x00 16. "OP_DE_POL,Controls the polarity of DataEnable of the outgoing data" "0: OP_DE_POL_0,1: OP_DE_POL_1"
bitfld.long 0x00 14. "INP_VSYNC_POL,Contains the information about the polarity of Vsync of the incoming data" "0: INP_VSYNC_POL_0,1: INP_VSYNC_POL_1"
newline
bitfld.long 0x00 13. "INP_HSYNC_POL,Contains the information about the polarity of Hsync of the incoming data" "0: INP_HSYNC_POL_0,1: INP_HSYNC_POL_1"
bitfld.long 0x00 12. "INP_DE_POL,Contains the information about the polarity of DataEnable of the incoming data" "0: INP_DE_POL_0,1: INP_DE_POL_1"
newline
bitfld.long 0x00 10. "INTRLC_EN,Enable interlaced HDMI timing" "0: INTRLC_EN_0,1: INTRLC_EN_1"
bitfld.long 0x00 9. "TMG_GEN_EN,Enable Timing Generator to insert the hsync and vsync" "0: TMG_GEN_EN_0,1: TMG_GEN_EN_1"
newline
bitfld.long 0x00 8. "VSYNC_SHIFT,VSYNC shift" "0: Run in general interlaced mode,1: Run in special interlaced format"
bitfld.long 0x00 6.--7. "PIPE_MODE,Sets the Timing Generator mode" "0: PIPE_MODE_0,1: 422 subsample,2: 420 subsample,3: PIPE_MODE_3"
newline
bitfld.long 0x00 5. "HTX_PLB_EN,Enables Data write to PLB from HDMI Tx" "0,1"
bitfld.long 0x00 4. "DCSS_YUV420_MODE,Indicates the data coming in from DCSS is in yuv 420 mode" "0,1"
newline
bitfld.long 0x00 3. "HTX_PVI_UPSMPL,Select the mode of upsample in case of 16bit output and 12bit input" "0: Fill LSB with 4'b0,1: Fill LSB with MSB 4 bits i.e"
bitfld.long 0x00 1.--2. "HTX_PVI_MODE,Selects the mode of operation in HTX PVI" "0: Select the DCSS Path,1: Select the Bypass path from HDMI Rx,2: Select the LCDIF Path,?..."
newline
bitfld.long 0x00 0. "HTX_PVI_EN,Enable to block to receive incoming data" "0,1"
group.long 0x04++0x03
line.long 0x00 "HTX_PVI_IRQ_MASK,Masks off the Interrupts"
bitfld.long 0x00 2.--5. "TMG_GEN_IRQ,4 IRQs that can be generated from Timing Generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "ASYNC_FIFO_UNDRFLW,Indicates the Async FIFO has underflow" "0,1"
newline
bitfld.long 0x00 0. "ASYNC_FIFO_OVRFLW,Indicates the Async FIFO has overflown" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "HTX_PVI_IRQ_STATUS,Interrupt Status"
bitfld.long 0x00 2.--5. "TMG_GEN_IRQ,4 IRQs that can be generated from Timing Generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "ASYNC_FIFO_UNDRFLW,Indicates the Async FIFO has underflow" "0,1"
newline
bitfld.long 0x00 0. "ASYNC_FIFO_OVRFLW,Indicates the Async FIFO has overflown" "0,1"
group.long 0x0C++0x03
line.long 0x00 "HTX_PVI_IRQ_CLR,Interrupts"
bitfld.long 0x00 2.--5. "TMG_GEN_IRQ,4 IRQs that can be generated from Timing Generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "ASYNC_FIFO_UNDRFLW,Indicates the Async FIFO has underflow" "0,1"
newline
bitfld.long 0x00 0. "ASYNC_FIFO_OVRFLW,Indicates the Async FIFO has overflown" "0,1"
group.long 0x10++0x03
line.long 0x00 "HTX_TMG_GEN_DISP_LRC,Display Coordinates"
hexmask.long.word 0x00 16.--31. 1. "POSX,Value of the Lower Right Corner X"
hexmask.long.word 0x00 0.--15. 1. "POSY,Value of the Lower Right Corner Y"
group.long 0x14++0x03
line.long 0x00 "HTX_TMG_GEN_DE_ULC,Data Enable Coordinates"
hexmask.long.word 0x00 16.--31. 1. "POSX,Value of the Upper Left Corner X"
hexmask.long.word 0x00 0.--15. 1. "POSY,Value of the Upper Left Corner Y"
group.long 0x18++0x03
line.long 0x00 "HTX_TMG_GEN_DE_LRC,Data Enable Coordinates"
hexmask.long.word 0x00 16.--31. 1. "POSX,Value of the Lower Right Corner X"
hexmask.long.word 0x00 0.--15. 1. "POSY,Value of the Lower Right Corner Y"
group.long 0x1C++0x03
line.long 0x00 "HTX_TMG_GEN_HSYNC,Hsync Start and End"
hexmask.long.word 0x00 16.--31. 1. "START,Value of the Lower Right Corner X"
hexmask.long.word 0x00 0.--15. 1. "END,Value of the Lower Right Corner Y"
group.long 0x20++0x03
line.long 0x00 "HTX_TMG_GEN_VSYNC,Vsync Start and End"
hexmask.long.word 0x00 16.--31. 1. "START,Value of the Lower Right Corner X"
hexmask.long.word 0x00 0.--15. 1. "END,Value of the Lower Right Corner Y"
group.long 0x24++0x03
line.long 0x00 "HTX_TMG_GEN_IRQ0,Controls the Position of first IRQ from Timing Generator"
hexmask.long.word 0x00 16.--31. 1. "POS_X,Xposition for the interrupt generation"
hexmask.long.word 0x00 0.--15. 1. "POS_Y,Yposition for the interrupt generation"
group.long 0x28++0x03
line.long 0x00 "HTX_TMG_GEN_IRQ1,Controls the Position of Second IRQ from Timing Generator"
hexmask.long.word 0x00 16.--31. 1. "POS_X,Xposition for the interrupt generation"
hexmask.long.word 0x00 0.--15. 1. "POS_Y,Yposition for the interrupt generation"
group.long 0x2C++0x03
line.long 0x00 "HTX_TMG_GEN_IRQ2,Controls the Position of Third IRQ from Timing Generator"
hexmask.long.word 0x00 16.--31. 1. "POS_X,Xposition for the interrupt generation"
hexmask.long.word 0x00 0.--15. 1. "POS_Y,Yposition for the interrupt generation"
group.long 0x30++0x03
line.long 0x00 "HTX_TMG_GEN_IRQ3,Controls the Position of Fourth IRQ from Timing Generator"
hexmask.long.word 0x00 16.--31. 1. "POS_X,Xposition for the interrupt generation"
hexmask.long.word 0x00 0.--15. 1. "POS_Y,Yposition for the interrupt generation"
group.long 0x34++0x03
line.long 0x00 "HTX_TMG_GEN_BG0,Background Color insertion for R or Y"
hexmask.long.word 0x00 0.--11. 1. "DEF_VAL,Default Value of the Background Color for R or Y"
group.long 0x38++0x03
line.long 0x00 "HTX_TMG_GEN_BG1,Background Color insertion for G or Cb"
hexmask.long.word 0x00 0.--11. 1. "DEF_VAL,Default Value of the Background color for G or Cb"
group.long 0x3C++0x03
line.long 0x00 "HTX_TMG_GEN_BG2,Background Color insertion for B or Cr"
hexmask.long.word 0x00 0.--11. 1. "DEF_VAL,Background Color Component for B or Cr"
group.long 0x40++0x03
line.long 0x00 "HTX_TMG_GEN_CFG,HStart and Vstart Delay Configuration"
bitfld.long 0x00 31. "EN_VS_DLY_STRT,Controls the Vsync Start Generation" "0,1"
bitfld.long 0x00 30. "EN_HS_DLY_STRT,Controls the Hsync Start Generation" "0,1"
newline
hexmask.long.word 0x00 16.--28. 1. "V_STRT_DLY,Starting position of VCount to enable Starting in VBack VSync or VFront"
hexmask.long.word 0x00 0.--12. 1. "H_STRT_DLY,Starting position of HCount to enable Starting in HBack HSync or HFront"
tree.end
tree "I2C (Inter-Integrated Circuit)"
repeat 6. (list 1. 2. 3. 4. 5. 6.) (list ad:0x30A20000 ad:0x30A30000 ad:0x30A40000 ad:0x30A50000 ad:0x30AD0000 ad:0x30AE0000)
tree "I2C$1"
base $2
group.word 0x00++0x01
line.word 0x00 "IADR,I2C Address Register"
hexmask.word.byte 0x00 1.--7. 1. "ADR,Slave address"
group.word 0x04++0x01
line.word 0x00 "IFDR,I2C Frequency Divider Register"
bitfld.word 0x00 0.--5. "IC,I2C clock rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x08++0x01
line.word 0x00 "I2CR,I2C Control Register"
bitfld.word 0x00 7. "IEN,I2C enable" "0: The block is disabled but registers can still..,1: The I2C is enabled"
bitfld.word 0x00 6. "IIEN,I2C interrupt enable" "0: I2C interrupts are disabled but the status..,1: I2C interrupts are enabled"
newline
bitfld.word 0x00 5. "MSTA,Master/Slave mode select bit" "0: Slave mode,1: Master mode"
bitfld.word 0x00 4. "MTX,Transmit/Receive mode select bit" "0: Receive.When a slave is addressed the..,1: Transmit.In Master mode MTX should be set.."
newline
bitfld.word 0x00 3. "TXAK,Transmit acknowledge enable" "0: An acknowledge signal is sent to the bus at..,1: No acknowledge signal response is sent (that.."
bitfld.word 0x00 2. "RSTA,Repeat start" "0: No repeat start,1: Generates a Repeated Start condition"
group.word 0x0C++0x01
line.word 0x00 "I2SR,I2C Status Register"
rbitfld.word 0x00 7. "ICF,Data transferring bit" "0: Transfer is in progress,1: Transfer is complete"
rbitfld.word 0x00 6. "IAAS,I2C addressed as a slave bit" "0: Not addressed,1: Addressed as a slave"
newline
rbitfld.word 0x00 5. "IBB,I2C bus busy bit" "0: Bus is idle,1: Bus is busy"
bitfld.word 0x00 4. "IAL,Arbitration lost" "0: No arbitration lost,1: Arbitration is lost"
newline
rbitfld.word 0x00 2. "SRW,Slave read/" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave"
bitfld.word 0x00 1. "IIF,I2C interrupt" "0: No I2C interrupt pending,1: An interrupt is pending.This causes a.."
newline
rbitfld.word 0x00 0. "RXAK,Received acknowledge" "0: An acknowledge signal was received after the..,1: A No acknowledge signal was detected at the.."
group.word 0x10++0x01
line.word 0x00 "I2DR,I2C Data I/O Register"
hexmask.word.byte 0x00 0.--7. 1. "DATA,Data Byte"
tree.end
repeat.end
tree.end
tree "I2S (Inter-Integrated Sound Bus Controller)"
repeat 6. (list 1. 2. 3. 5. 6. 7.) (list ad:0x30C10000 ad:0x30C20000 ad:0x30C30000 ad:0x30C50000 ad:0x30C60000 ad:0x30C80000)
tree "I2S$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "VERID,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
rgroup.long 0x04++0x03
line.long 0x00 "PARAM,Parameter Register"
bitfld.long 0x00 16.--19. "FRAME,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "FIFO,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DATALINE,Number of Datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "TCSR,SAI Transmit Control Register"
bitfld.long 0x00 31. "TE,Transmitter Enable" "0: Transmitter is disabled,1: Transmitter is enabled or transmitter has.."
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Transmitter disabled in Stop mode,1: Transmitter enabled in Stop mode"
newline
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Transmitter is disabled in Debug mode after..,1: Transmitter is enabled in Debug mode"
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Transmit bit clock is disabled,1: Transmit bit clock is enabled"
newline
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
newline
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
newline
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Transmit underrun not detected,1: Transmit underrun detected"
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled transmit FIFO is empty,1: Enabled transmit FIFO is empty"
newline
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Transmit FIFO watermark has not been reached,1: Transmit FIFO watermark has been reached"
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
newline
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
newline
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
newline
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
group.long 0x0C++0x03
line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register"
hexmask.long.byte 0x00 0.--6. 1. "TFW,Transmit FIFO Watermark"
group.long 0x10++0x03
line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register"
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with receiver,?..."
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
newline
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
newline
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs..,1: Bit clock is active low with drive outputs on.."
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
newline
bitfld.long 0x00 23. "BYP,Bit Clock Bypass" "0: Internal bit clock is generated from bit..,1: Internal bit clock is divide by one of the.."
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
group.long 0x14++0x03
line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register"
hexmask.long.byte 0x00 24.--31. 1. "CFR,Channel FIFO Reset"
hexmask.long.byte 0x00 16.--23. 1. "TCE,Transmit Channel Enable"
newline
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x03
line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register"
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO reads (from..,2: FIFO combine mode enabled on FIFO writes (by..,3: FIFO combine mode enabled on FIFO reads (from.."
newline
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
bitfld.long 0x00 16.--20. "FRSZ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "CHMOD,Channel Mode" "0: TDM mode transmit data pins are tri-stated..,1: Output mode transmit data pins are never.."
newline
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is transmitted first,1: MSB is transmitted first"
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
newline
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
newline
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame sync is generated externally in Slave..,1: Frame sync is generated internally in Master.."
group.long 0x1C++0x03
line.long 0x00 "TCR5,SAI Transmit Configuration 5 Register"
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0x20)++0x03
line.long 0x00 "TDR[$1],SAI Transmit Data Register $1"
hexmask.long 0x00 0.--31. 1. "TDR,Transmit Data Register"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x40)++0x03
line.long 0x00 "TFR[$1],SAI Transmit FIFO Register $1"
bitfld.long 0x00 31. "WCP,Write Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO writes and.."
hexmask.long.byte 0x00 16.--23. 1. "WFP,Write FIFO Pointer"
newline
hexmask.long.byte 0x00 0.--7. 1. "RFP,Read FIFO Pointer"
repeat.end
group.long 0x60++0x03
line.long 0x00 "TMR,SAI Transmit Mask Register"
hexmask.long 0x00 0.--31. 1. "TWM,Transmit Word Mask"
group.long 0x70++0x03
line.long 0x00 "TTCR,SAI Transmit Timestamp Control Register"
bitfld.long 0x00 9. "RBC,Reset Bit Counter" "0: Bit counter is not reset,1: Bit counter is reset"
bitfld.long 0x00 8. "RTSC,Reset Timestamp Counter" "0: Timestamp counter is not reset,1: Timestamp counter is reset"
newline
bitfld.long 0x00 1. "TSINC,Timestamp Increment" "0: Timestamp counter starts to increment when..,1: Timestamp counter starts to increment when.."
bitfld.long 0x00 0. "TSEN,Timestamp Enable" "0: Timestamp counter is disabled,1: Timestamp counter is enabled"
rgroup.long 0x74++0x03
line.long 0x00 "TTSR,SAI Transmit Timestamp Register"
hexmask.long 0x00 0.--31. 1. "TSC,Timestamp Counter"
rgroup.long 0x78++0x03
line.long 0x00 "TBCR,SAI Transmit Bit Count Register"
hexmask.long 0x00 0.--31. 1. "BCNT,Bit Counter"
rgroup.long 0x7C++0x03
line.long 0x00 "TBCTR,SAI Transmit Bit Count Timestamp Register"
hexmask.long 0x00 0.--31. 1. "BCTS,Bit Timestamp"
group.long 0x88++0x03
line.long 0x00 "RCSR,SAI Receive Control Register"
bitfld.long 0x00 31. "RE,Receiver Enable" "0: Receiver is disabled,1: Receiver is enabled or receiver has been.."
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Receiver disabled in Stop mode,1: Receiver enabled in Stop mode"
newline
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Receiver is disabled in Debug mode after..,1: Receiver is enabled in Debug mode"
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Receive bit clock is disabled,1: Receive bit clock is enabled"
newline
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
newline
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
newline
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Receive overflow not detected,1: Receive overflow detected"
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled receive FIFO is full,1: Enabled receive FIFO is full"
newline
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Receive FIFO watermark not reached,1: Receive FIFO watermark has been reached"
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
newline
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
newline
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
newline
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
group.long 0x8C++0x03
line.long 0x00 "RCR1,SAI Receive Configuration 1 Register"
hexmask.long.byte 0x00 0.--6. 1. "RFW,Receive FIFO Watermark"
group.long 0x90++0x03
line.long 0x00 "RCR2,SAI Receive Configuration 2 Register"
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with transmitter,?..."
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
newline
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
newline
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit Clock is active high with drive outputs..,1: Bit Clock is active low with drive outputs on.."
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
newline
bitfld.long 0x00 23. "BYP,Bit Clock Bypass" "0: Internal bit clock is generated from bit..,1: Internal bit clock is divide by one of the.."
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
group.long 0x94++0x03
line.long 0x00 "RCR3,SAI Receive Configuration 3 Register"
hexmask.long.byte 0x00 24.--31. 1. "CFR,Channel FIFO Reset"
hexmask.long.byte 0x00 16.--23. 1. "RCE,Receive Channel Enable"
newline
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x98++0x03
line.long 0x00 "RCR4,SAI Receive Configuration 4 Register"
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO writes..,2: FIFO combine mode enabled on FIFO reads (by..,3: FIFO combine mode enabled on FIFO writes.."
newline
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
bitfld.long 0x00 16.--20. "FRSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is received first,1: MSB is received first"
newline
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
newline
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame Sync is generated externally in Slave..,1: Frame Sync is generated internally in Master.."
group.long 0x9C++0x03
line.long 0x00 "RCR5,SAI Receive Configuration 5 Register"
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 8. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0xA0)++0x03
line.long 0x00 "RDR[$1],SAI Receive Data Register $1"
hexmask.long 0x00 0.--31. 1. "RDR,Receive Data Register"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0xC0)++0x03
line.long 0x00 "RFR[$1],SAI Receive FIFO Register $1"
hexmask.long.byte 0x00 16.--23. 1. "WFP,Write FIFO Pointer"
bitfld.long 0x00 15. "RCP,Receive Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO reads and.."
newline
hexmask.long.byte 0x00 0.--7. 1. "RFP,Read FIFO Pointer"
repeat.end
group.long 0xE0++0x03
line.long 0x00 "RMR,SAI Receive Mask Register"
hexmask.long 0x00 0.--31. 1. "RWM,Receive Word Mask"
group.long 0xF0++0x03
line.long 0x00 "RTCR,SAI Receive Timestamp Control Register"
bitfld.long 0x00 9. "RBC,Reset Bit Counter" "0: Bit counter is not reset,1: Bit counter is reset"
bitfld.long 0x00 8. "RTSC,Reset Timestamp Counter" "0: Timestamp counter is not reset,1: Timestamp counter is reset"
newline
bitfld.long 0x00 1. "TSINC,Timestamp Increment" "0: Timestamp counter starts to increment when..,1: Timestamp counter starts to increment when.."
bitfld.long 0x00 0. "TSEN,Timestamp Enable" "0: Timestamp counter is disabled,1: Timestamp counter is enabled"
rgroup.long 0xF4++0x03
line.long 0x00 "RTSR,SAI Receive Timestamp Register"
hexmask.long 0x00 0.--31. 1. "TSC,Timestamp Counter"
rgroup.long 0xF8++0x03
line.long 0x00 "RBCR,SAI Receive Bit Count Register"
hexmask.long 0x00 0.--31. 1. "BCNT,Bit Counter"
rgroup.long 0xFC++0x03
line.long 0x00 "RBCTR,SAI Receive Bit Count Timestamp Register"
hexmask.long 0x00 0.--31. 1. "BCTS,Bit Timestamp"
group.long 0x100++0x03
line.long 0x00 "MCR,SAI MCLK Control Register"
bitfld.long 0x00 30. "MOE,MCLK Output Enable" "0: MCLK signal pin is an input,1: MCLK signal pin is an output"
bitfld.long 0x00 23. "DIVEN,MCLK Post Divide Enable" "0: Output on MCLK signal pin is the audio master..,1: Output on MCLK signal pin is a post-divided.."
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,MCLK Post Divide"
tree.end
repeat.end
tree.end
tree "IDENTIFICATION (Identification)"
base ad:0x32FD8000
rgroup.byte 0x00++0x00
line.byte 0x00 "design_id,Design Identification Register"
hexmask.byte 0x00 0.--7. 1. "design_id,Design ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller"
rgroup.byte 0x01++0x00
line.byte 0x00 "revision_id,Revision Identification Register"
hexmask.byte 0x00 0.--7. 1. "revision_id,Revision ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller"
rgroup.byte 0x02++0x00
line.byte 0x00 "product_id0,Product Identification Register 0"
hexmask.byte 0x00 0.--7. 1. "product_id0,This one byte fixed code Identifies Synopsys's product line ( A0h for DWC_hdmi_tx products)"
rgroup.byte 0x03++0x00
line.byte 0x00 "product_id1,Product Identification Register 1"
bitfld.byte 0x00 6.--7. "product_id1_hdcp,These bits identify a Synopsys's HDMI Controller with HDCP encryption according to Synopsys product line" "0,1,2,3"
bitfld.byte 0x00 1. "product_id1_rx,This bit Identifies Synopsys's DWC_hdmi_rx Controller according to Synopsys product line" "0,1"
newline
bitfld.byte 0x00 0. "product_id1_tx,This bit Identifies Synopsys's DWC_hdmi_tx Controller according to Synopsys product line" "0,1"
rgroup.byte 0x04++0x00
line.byte 0x00 "config0_id,Configuration Identification Register 0"
bitfld.byte 0x00 7. "prepen,Indicates if it is possible to use internal pixel repetition" "0,1"
bitfld.byte 0x00 5. "audspdif,Indicates if the SPDIF audio interface is present" "0,1"
newline
bitfld.byte 0x00 4. "audi2s,Indicates if I2S interface is present" "0,1"
bitfld.byte 0x00 3. "hdmi14,Indicates if HDMI 1" "0,1"
newline
bitfld.byte 0x00 2. "csc,Indicates if Color Space Conversion block is present" "0,1"
bitfld.byte 0x00 1. "cec,Indicates if CEC is present" "0,1"
newline
bitfld.byte 0x00 0. "hdcp,Indicates if HDCP is present" "0,1"
rgroup.byte 0x05++0x00
line.byte 0x00 "config1_id,Configuration Identification Register 1"
bitfld.byte 0x00 6. "hdcp22_ext,Indicates if external HDCP 2" "0,1"
bitfld.byte 0x00 5. "hdmi20,Indicates if HDMI 2" "0,1"
newline
bitfld.byte 0x00 1. "confapb,Indicates that configuration interface is APB interface" "0,1"
rgroup.byte 0x06++0x00
line.byte 0x00 "config2_id,Configuration Identification Register 2"
abitfld.byte 0x00 0.--7. "phytype,Indicates the type of PHY interface selected" "0x00=0: Legacy PHY (HDMI TX PHY),0xC2=194: PHY MHL COMBO (MHL+HDMI 2,0xE2=226: PHY GEN2 (HDMI 3D TX PHY) + HEAC PHY,0xF2=242: PHY GEN2 (HDMI 3D TX PHY)"
rgroup.byte 0x07++0x00
line.byte 0x00 "config3_id,Configuration Identification Register 3"
bitfld.byte 0x00 1. "confahbauddma,Indicates that the audio interface is AHB AUD DMA" "0,1"
bitfld.byte 0x00 0. "confgpaud,Indicates that the audio interface is Generic Parallel Audio (GPAUD)" "0,1"
tree.end
tree "INTERRUPT (Interrupt)"
base ad:0x32FD8100
group.byte 0x00++0x00
line.byte 0x00 "ih_fc_stat0,Frame Composer Interrupt Status Register 0 (Packet Interrupts)"
eventfld.byte 0x00 7. "AUDI,Active after successful transmission of an Audio InfoFrame packet" "0,1"
eventfld.byte 0x00 6. "ACP,Active after successful transmission of an Audio Content Protection packet" "0,1"
newline
eventfld.byte 0x00 5. "HBR,Active after successful transmission of an Audio HBR packet" "0,1"
eventfld.byte 0x00 4. "MAS,Active after successful transmission of an MultiStream Audio packet" "0,1"
newline
eventfld.byte 0x00 3. "NVBI,Active after successful transmission of an NTSC VBI packet" "0,1"
eventfld.byte 0x00 2. "AUDS,Active after successful transmission of an Audio Sample packet" "0,1"
newline
eventfld.byte 0x00 1. "ACR,Active after successful transmission of an Audio Clock Regeneration (N/CTS transmission) packet" "0,1"
eventfld.byte 0x00 0. "NULL,Active after successful transmission of an Null packet" "0,1"
group.byte 0x01++0x00
line.byte 0x00 "ih_fc_stat1,Frame Composer Interrupt Status Register 1 (Packet Interrupts)"
eventfld.byte 0x00 7. "GMD,Active after successful transmission of an Gamut metadata packet" "0,1"
eventfld.byte 0x00 6. "ISCR1,Active after successful transmission of an International Standard Recording Code 1 packet" "0,1"
newline
eventfld.byte 0x00 5. "ISCR2,Active after successful transmission of an International Standard Recording Code 2 packet" "0,1"
eventfld.byte 0x00 4. "VSD,Active after successful transmission of an Vendor Specific Data InfoFrame packet" "0,1"
newline
eventfld.byte 0x00 3. "SPD,Active after successful transmission of an Source Product Descriptor InfoFrame packet" "0,1"
eventfld.byte 0x00 2. "AMP,Active after successful transmission of an Audio Metadata packet" "0,1"
newline
eventfld.byte 0x00 1. "AVI,Active after successful transmission of an AVI InfoFrame packet" "0,1"
eventfld.byte 0x00 0. "GCP,Active after successful transmission of an General Control Packet" "0,1"
group.byte 0x02++0x00
line.byte 0x00 "ih_fc_stat2,Frame Composer Interrupt Status Register 2 (Packet Interrupts)"
eventfld.byte 0x00 4. "DRM,Active after successful transmission of an DRM packet" "0,1"
eventfld.byte 0x00 1. "LowPriority_overflow,Frame Composer low priority packet queue descriptor overflow indication" "0,1"
newline
eventfld.byte 0x00 0. "HighPriority_overflow,Frame Composer high priority packet queue descriptor overflow indication" "0,1"
group.byte 0x03++0x00
line.byte 0x00 "ih_as_stat0,Audio Sampler Interrupt Status Register (FIFO Threshold Underflow and Overflow Interrupts)"
eventfld.byte 0x00 3. "fifo_overrun,Indicates an overrun on the audio FIFO" "0,1"
eventfld.byte 0x00 2. "Aud_fifo_underflow_thr,Audio Sampler audio FIFO empty threshold (four samples) indication for the legacy HBR audio interface" "0,1"
newline
eventfld.byte 0x00 1. "Aud_fifo_underflow,Audio Sampler audio FIFO empty indication" "0,1"
eventfld.byte 0x00 0. "Aud_fifo_overflow,Audio Sampler audio FIFO full indication" "0,1"
group.byte 0x04++0x00
line.byte 0x00 "ih_phy_stat0,PHY Interface Interrupt Status Register (RXSENSE PLL Lock and HPD Interrupts)"
eventfld.byte 0x00 5. "RX_SENSE_3,TX PHY RX_SENSE indication for driver 3" "0,1"
eventfld.byte 0x00 4. "RX_SENSE_2,TX PHY RX_SENSE indication for driver 2" "0,1"
newline
eventfld.byte 0x00 3. "RX_SENSE_1,TX PHY RX_SENSE indication for driver 1" "0,1"
eventfld.byte 0x00 2. "RX_SENSE_0,TX PHY RX_SENSE indication for driver 0" "0,1"
newline
eventfld.byte 0x00 1. "TX_PHY_LOCK,TX PHY PLL lock indication" "0,1"
eventfld.byte 0x00 0. "HPD,HDMI Hot Plug Detect indication" "0,1"
group.byte 0x05++0x00
line.byte 0x00 "ih_i2cm_stat0,E-DDC I2C Master Interrupt Status Register (Done and Error Interrupts)"
eventfld.byte 0x00 2. "scdc_readreq,I2C Master SCDC read request indication" "0,1"
eventfld.byte 0x00 1. "I2Cmasterdone,I2C Master done indication" "0,1"
newline
eventfld.byte 0x00 0. "I2Cmastererror,I2C Master error indication" "0,1"
group.byte 0x06++0x00
line.byte 0x00 "ih_cec_stat0,CEC Interrupt Status Register (Functional Operation Interrupts)"
eventfld.byte 0x00 6. "WAKEUP,CEC Wake-up indication" "0,1"
eventfld.byte 0x00 5. "ERROR_FOLLOW,CEC Error Follow indication" "0,1"
newline
eventfld.byte 0x00 4. "ERROR_INITIATOR,CEC Error Initiator indication" "0,1"
eventfld.byte 0x00 3. "ARB_LOST,CEC Arbitration Lost indication" "0,1"
newline
eventfld.byte 0x00 2. "NACK,CEC Not Acknowledge indication" "0,1"
eventfld.byte 0x00 1. "EOM,CEC End of Message Indication" "0,1"
newline
eventfld.byte 0x00 0. "DONE,CEC Done Indication" "0,1"
group.byte 0x07++0x00
line.byte 0x00 "ih_vp_stat0,Video Packetizer Interrupt Status Register (FIFO Full and Empty Interrupts)"
eventfld.byte 0x00 7. "fifofullrepet,Video Packetizer pixel repeater FIFO full interrupt" "0,1"
eventfld.byte 0x00 6. "fifoemptyrepet,Video Packetizer pixel repeater FIFO empty interrupt" "0,1"
newline
eventfld.byte 0x00 5. "fifofullpp,Video Packetizer pixel packing FIFO full interrupt" "0,1"
eventfld.byte 0x00 4. "fifoemptypp,Video Packetizer pixel packing FIFO empty interrupt" "0,1"
newline
eventfld.byte 0x00 3. "fifofullremap,Video Packetizer pixel YCbCr 422 re-mapper FIFO full interrupt" "0,1"
eventfld.byte 0x00 2. "fifoemptyremap,Video Packetizer pixel YCbCr 422 re-mapper FIFO empty interrupt" "0,1"
group.byte 0x08++0x00
line.byte 0x00 "ih_i2cmphy_stat0,PHY GEN2 I2C Master Interrupt Status Register (Done and Error Interrupts)"
eventfld.byte 0x00 1. "I2Cmphydone,I2C Master PHY done indication" "0,1"
eventfld.byte 0x00 0. "I2Cmphyerror,I2C Master PHY error indication" "0,1"
rgroup.byte 0x70++0x00
line.byte 0x00 "ih_decode,Interruption Handler Decode Assist Register"
bitfld.byte 0x00 7. "ih_fc_stat0,Interruption active at the ih_fc_stat0 register" "0,1"
bitfld.byte 0x00 6. "ih_fc_stat1,Interruption active at the ih_fc_stat1 register" "0,1"
newline
bitfld.byte 0x00 5. "ih_fc_stat2_vp,Interruption active at the ih_fc_stat2 or ih_vp_stat0 register" "0,1"
bitfld.byte 0x00 4. "ih_as_stat0,Interruption active at the ih_as_stat0 register" "0,1"
newline
bitfld.byte 0x00 3. "ih_phy,Interruption active at the ih_phy_stat0 or ih_i2cmphy_stat0 register" "0,1"
bitfld.byte 0x00 2. "ih_i2cm_stat0,Interruption active at the ih_i2cm_stat0 register" "0,1"
newline
bitfld.byte 0x00 1. "ih_cec_stat0,Interruption active at the ih_cec_stat0 register" "0,1"
bitfld.byte 0x00 0. "ih_ahbdmaaud_stat0,Interruption active at the ih_ahbdmaaud_stat0 register" "0,1"
group.byte 0x80++0x00
line.byte 0x00 "ih_mute_fc_stat0,Frame Composer Interrupt Mute Control Register 0"
bitfld.byte 0x00 7. "AUDI,When set to 1 mutes ih_fc_stat0[7]" "0,1"
bitfld.byte 0x00 6. "ACP,When set to 1 mutes ih_fc_stat0[6]" "0,1"
newline
bitfld.byte 0x00 5. "HBR,When set to 1 mutes ih_fc_stat0[5]" "0,1"
bitfld.byte 0x00 4. "MAS,When set to 1 mutes ih_fc_stat0[4]" "0,1"
newline
bitfld.byte 0x00 3. "NVBI,When set to 1 mutes ih_fc_stat0[3]" "0,1"
bitfld.byte 0x00 2. "AUDS,When set to 1 mutes ih_fc_stat0[2]" "0,1"
newline
bitfld.byte 0x00 1. "ACR,When set to 1 mutes ih_fc_stat0[1]" "0,1"
bitfld.byte 0x00 0. "NULL,When set to 1 mutes ih_fc_stat0[0]" "0,1"
group.byte 0x81++0x00
line.byte 0x00 "ih_mute_fc_stat1,Frame Composer Interrupt Mute Control Register 1"
bitfld.byte 0x00 7. "GMD,When set to 1 mutes ih_fc_stat1[7]" "0,1"
bitfld.byte 0x00 6. "ISCR1,When set to 1 mutes ih_fc_stat1[6]" "0,1"
newline
bitfld.byte 0x00 5. "ISCR2,When set to 1 mutes ih_fc_stat1[5]" "0,1"
bitfld.byte 0x00 4. "VSD,When set to 1 mutes ih_fc_stat1[4]" "0,1"
newline
bitfld.byte 0x00 3. "SPD,When set to 1 mutes ih_fc_stat1[3]" "0,1"
bitfld.byte 0x00 2. "AMP,When set to 1 mutes ih_fc_stat1[2]" "0,1"
newline
bitfld.byte 0x00 1. "AVI,When set to 1 mutes ih_fc_stat1[1]" "0,1"
bitfld.byte 0x00 0. "GCP,When set to 1 mutes ih_fc_stat1[0]" "0,1"
group.byte 0x82++0x00
line.byte 0x00 "ih_mute_fc_stat2,Frame Composer Interrupt Mute Control Register 2"
bitfld.byte 0x00 4. "DRM,When set to 1 mutes ih_fc_stat2[4]" "0,1"
bitfld.byte 0x00 1. "LowPriority_overflow,When set to 1 mutes ih_fc_stat2[1]" "0,1"
newline
bitfld.byte 0x00 0. "HighPriority_overflow,When set to 1 mutes ih_fc_stat2[0]" "0,1"
group.byte 0x83++0x00
line.byte 0x00 "ih_mute_as_stat0,Audio Sampler Interrupt Mute Control Register"
bitfld.byte 0x00 3. "fifo_overrun,When set to 1 mutes ih_as_stat0[3]" "0,1"
bitfld.byte 0x00 2. "Aud_fifo_underflow_thr,When set to 1 mutes ih_as_stat0[2]" "0,1"
newline
bitfld.byte 0x00 1. "Aud_fifo_underflow,When set to 1 mutes ih_as_stat0[1]" "0,1"
bitfld.byte 0x00 0. "Aud_fifo_overflow,When set to 1 mutes ih_as_stat0[0]" "0,1"
group.byte 0x84++0x00
line.byte 0x00 "ih_mute_phy_stat0,PHY Interface Interrupt Mute Control Register"
bitfld.byte 0x00 5. "RX_SENSE_3,When set to 1 mutes ih_phy_stat0[5]" "0,1"
bitfld.byte 0x00 4. "RX_SENSE_2,When set to 1 mutes ih_phy_stat0[4]" "0,1"
newline
bitfld.byte 0x00 3. "RX_SENSE_1,When set to 1 mutes ih_phy_stat0[3]" "0,1"
bitfld.byte 0x00 2. "RX_SENSE_0,When set to 1 mutes ih_phy_stat0[2]" "0,1"
newline
bitfld.byte 0x00 1. "TX_PHY_LOCK,When set to 1 mutes ih_phy_stat0[1]" "0,1"
bitfld.byte 0x00 0. "HPD,When set to 1 mutes ih_phy_stat0[0]" "0,1"
group.byte 0x85++0x00
line.byte 0x00 "ih_mute_i2cm_stat0,E-DDC I2C Master Interrupt Mute Control Register"
bitfld.byte 0x00 2. "scdc_readreq,When set to 1 mutes ih_i2cm_stat0[2]" "0,1"
bitfld.byte 0x00 1. "I2Cmasterdone,When set to 1 mutes ih_i2cm_stat0[1]" "0,1"
newline
bitfld.byte 0x00 0. "I2Cmastererror,When set to 1 mutes ih_i2cm_stat0[0]" "0,1"
group.byte 0x86++0x00
line.byte 0x00 "ih_mute_cec_stat0,CEC Interrupt Mute Control Register"
bitfld.byte 0x00 6. "WAKEUP,When set to 1 mutes ih_cec_stat0[6]" "0,1"
bitfld.byte 0x00 5. "ERROR_FOLLOW,When set to 1 mutes ih_cec_stat0[5]" "0,1"
newline
bitfld.byte 0x00 4. "ERROR_INITIATOR,When set to 1 mutes ih_cec_stat0[4]" "0,1"
bitfld.byte 0x00 3. "ARB_LOST,When set to 1 mutes ih_cec_stat0[3]" "0,1"
newline
bitfld.byte 0x00 2. "NACK,When set to 1 mutes ih_cec_stat0[2]" "0,1"
bitfld.byte 0x00 1. "EOM,When set to 1 mutes ih_cec_stat0[1]" "0,1"
newline
bitfld.byte 0x00 0. "DONE,When set to 1 mutes ih_cec_stat0[0]" "0,1"
group.byte 0x87++0x00
line.byte 0x00 "ih_mute_vp_stat0,Video Packetizer Interrupt Mute Control Register"
bitfld.byte 0x00 7. "fifofullrepet,When set to 1 mutes ih_vp_stat0[7]" "0,1"
bitfld.byte 0x00 6. "fifoemptyrepet,When set to 1 mutes ih_vp_stat0[6]" "0,1"
newline
bitfld.byte 0x00 5. "fifofullpp,When set to 1 mutes ih_vp_stat0[5]" "0,1"
bitfld.byte 0x00 4. "fifoemptypp,When set to 1 mutes ih_vp_stat0[4]" "0,1"
newline
bitfld.byte 0x00 3. "fifofullremap,When set to 1 mutes ih_vp_stat0[3]" "0,1"
bitfld.byte 0x00 2. "fifoemptyremap,When set to 1 mutes ih_vp_stat0[2]" "0,1"
newline
bitfld.byte 0x00 1. "spare_2,Reserved as spare bit with no associated functionality" "0,1"
bitfld.byte 0x00 0. "spare_1,Reserved as spare bit with no associated functionality" "0,1"
group.byte 0x88++0x00
line.byte 0x00 "ih_mute_i2cmphy_stat0,PHY GEN2 I2C Master Interrupt Mute Control Register"
bitfld.byte 0x00 1. "I2Cmphydone,When set to 1 mutes ih_i2cmphy_stat0[1]" "0,1"
bitfld.byte 0x00 0. "I2Cmphyerror,When set to 1 mutes ih_i2cmphy_stat0[0]" "0,1"
group.byte 0xFF++0x00
line.byte 0x00 "ih_mute,Global Interrupt Mute Control Register"
bitfld.byte 0x00 1. "mute_wakeup_interrupt,When set to 1 mutes the main interrupt output port" "0,1"
bitfld.byte 0x00 0. "mute_all_interrupt,When set to 1 mutes the main interrupt line (where all interrupts are ORed)" "0,1"
tree.end
tree "IOMUXC (IOMUX Controller)"
base ad:0x30330000
group.long 0x14++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO00,SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO00"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x18++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO01,SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO01"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO02,SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO02"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?,7: Select mux mode"
group.long 0x20++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO03,SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO03"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x24++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO04,SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO04"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x28++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO05,SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO05"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x2C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO06,SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO06"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x30++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO07,SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO07"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x34++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO08,SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO08"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x38++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO09,SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO09"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x3C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO10,SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO10"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?..."
group.long 0x40++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO11,SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO11"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x44++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO12,SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO12"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,?,?,5: Select mux mode,?..."
group.long 0x48++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO13,SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO13"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,?,?,5: Select mux mode,?..."
group.long 0x4C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO14,SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO14"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x50++0x03
line.long 0x00 "SW_MUX_CTL_PAD_GPIO1_IO15,SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad GPIO1_IO15"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x54++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_MDC,SW_MUX_CTL_PAD_ENET_MDC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_MDC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,?,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x58++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_MDIO,SW_MUX_CTL_PAD_ENET_MDIO SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_MDIO"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x5C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_TD3,SW_MUX_CTL_PAD_ENET_TD3 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_TD3"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x60++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_TD2,SW_MUX_CTL_PAD_ENET_TD2 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_TD2"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x64++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_TD1,SW_MUX_CTL_PAD_ENET_TD1 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_TD1"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x68++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_TD0,SW_MUX_CTL_PAD_ENET_TD0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_TD0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x6C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_TX_CTL,SW_MUX_CTL_PAD_ENET_TX_CTL SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_TX_CTL"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x70++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_TXC,SW_MUX_CTL_PAD_ENET_TXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_TXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x74++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_RX_CTL,SW_MUX_CTL_PAD_ENET_RX_CTL SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_RX_CTL"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x78++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_RXC,SW_MUX_CTL_PAD_ENET_RXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_RXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x7C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_RD0,SW_MUX_CTL_PAD_ENET_RD0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_RD0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x80++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_RD1,SW_MUX_CTL_PAD_ENET_RD1 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_RD1"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x84++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_RD2,SW_MUX_CTL_PAD_ENET_RD2 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_RD2"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x88++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ENET_RD3,SW_MUX_CTL_PAD_ENET_RD3 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ENET_RD3"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x8C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_CLK,SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_CLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x90++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_CMD,SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_CMD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x94++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA0,SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x98++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA1,SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA1"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x9C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA2,SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA2"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xA0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA3,SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA3"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xA4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA4,SW_MUX_CTL_PAD_SD1_DATA4 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA4"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xA8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA5,SW_MUX_CTL_PAD_SD1_DATA5 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA5"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xAC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA6,SW_MUX_CTL_PAD_SD1_DATA6 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA6"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xB0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_DATA7,SW_MUX_CTL_PAD_SD1_DATA7 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_DATA7"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xB4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_RESET_B,SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_RESET_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xB8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD1_STROBE,SW_MUX_CTL_PAD_SD1_STROBE SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD1_STROBE"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xBC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_CD_B,SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_CD_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,?,5: Select mux mode,?..."
group.long 0xC0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_CLK,SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_CLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0xC4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_CMD,SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_CMD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xC8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_DATA0,SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_DATA0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xCC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_DATA1,SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_DATA1"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xD0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_DATA2,SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_DATA2"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xD4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_DATA3,SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_DATA3"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0xD8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_RESET_B,SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_RESET_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,?,5: Select mux mode,?..."
group.long 0xDC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SD2_WP,SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SD2_WP"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0xE0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_ALE,SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_ALE"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0xE4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_CE0_B,SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_CE0_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0xE8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_CE1_B,SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_CE1_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0xEC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_CE2_B,SW_MUX_CTL_PAD_NAND_CE2_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_CE2_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0xF0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_CE3_B,SW_MUX_CTL_PAD_NAND_CE3_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_CE3_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0xF4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_CLE,SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_CLE"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0xF8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA00,SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA00"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0xFC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA01,SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA01"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x100++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA02,SW_MUX_CTL_PAD_NAND_DATA02 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA02"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x104++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA03,SW_MUX_CTL_PAD_NAND_DATA03 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA03"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x108++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA04,SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA04"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x10C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA05,SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA05"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x110++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA06,SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA06"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x114++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DATA07,SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DATA07"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x118++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_DQS,SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_DQS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x11C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_RE_B,SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_RE_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x120++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_READY_B,SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_READY_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x124++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_WE_B,SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_WE_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x128++0x03
line.long 0x00 "SW_MUX_CTL_PAD_NAND_WP_B,SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad NAND_WP_B"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x12C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI5_RXFS,SW_MUX_CTL_PAD_SAI5_RXFS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI5_RXFS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x130++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI5_RXC,SW_MUX_CTL_PAD_SAI5_RXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI5_RXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x134++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI5_RXD0,SW_MUX_CTL_PAD_SAI5_RXD0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI5_RXD0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x138++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI5_RXD1,SW_MUX_CTL_PAD_SAI5_RXD1 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI5_RXD1"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x13C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI5_RXD2,SW_MUX_CTL_PAD_SAI5_RXD2 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI5_RXD2"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x140++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI5_RXD3,SW_MUX_CTL_PAD_SAI5_RXD3 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI5_RXD3"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x144++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI5_MCLK,SW_MUX_CTL_PAD_SAI5_MCLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI5_MCLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x148++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXFS,SW_MUX_CTL_PAD_SAI1_RXFS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXFS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x14C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXC,SW_MUX_CTL_PAD_SAI1_RXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x150++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD0,SW_MUX_CTL_PAD_SAI1_RXD0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x154++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD1,SW_MUX_CTL_PAD_SAI1_RXD1 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD1"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x158++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD2,SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD2"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x15C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD3,SW_MUX_CTL_PAD_SAI1_RXD3 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD3"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x160++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD4,SW_MUX_CTL_PAD_SAI1_RXD4 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD4"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x164++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD5,SW_MUX_CTL_PAD_SAI1_RXD5 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD5"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x168++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD6,SW_MUX_CTL_PAD_SAI1_RXD6 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD6"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x16C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_RXD7,SW_MUX_CTL_PAD_SAI1_RXD7 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_RXD7"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x170++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXFS,SW_MUX_CTL_PAD_SAI1_TXFS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXFS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x174++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXC,SW_MUX_CTL_PAD_SAI1_TXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x178++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD0,SW_MUX_CTL_PAD_SAI1_TXD0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x17C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD1,SW_MUX_CTL_PAD_SAI1_TXD1 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD1"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x180++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD2,SW_MUX_CTL_PAD_SAI1_TXD2 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD2"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x184++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD3,SW_MUX_CTL_PAD_SAI1_TXD3 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD3"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x188++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD4,SW_MUX_CTL_PAD_SAI1_TXD4 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD4"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x18C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD5,SW_MUX_CTL_PAD_SAI1_TXD5 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD5"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x190++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD6,SW_MUX_CTL_PAD_SAI1_TXD6 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD6"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x194++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_TXD7,SW_MUX_CTL_PAD_SAI1_TXD7 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_TXD7"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x198++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI1_MCLK,SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI1_MCLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x19C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI2_RXFS,SW_MUX_CTL_PAD_SAI2_RXFS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI2_RXFS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1A0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI2_RXC,SW_MUX_CTL_PAD_SAI2_RXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI2_RXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1A4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI2_RXD0,SW_MUX_CTL_PAD_SAI2_RXD0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI2_RXD0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1A8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI2_TXFS,SW_MUX_CTL_PAD_SAI2_TXFS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI2_TXFS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1AC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI2_TXC,SW_MUX_CTL_PAD_SAI2_TXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI2_TXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1B0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI2_TXD0,SW_MUX_CTL_PAD_SAI2_TXD0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI2_TXD0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x1B4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI2_MCLK,SW_MUX_CTL_PAD_SAI2_MCLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI2_MCLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1B8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI3_RXFS,SW_MUX_CTL_PAD_SAI3_RXFS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI3_RXFS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1BC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI3_RXC,SW_MUX_CTL_PAD_SAI3_RXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI3_RXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1C0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI3_RXD,SW_MUX_CTL_PAD_SAI3_RXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI3_RXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1C4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI3_TXFS,SW_MUX_CTL_PAD_SAI3_TXFS SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI3_TXFS"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1C8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI3_TXC,SW_MUX_CTL_PAD_SAI3_TXC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI3_TXC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1CC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI3_TXD,SW_MUX_CTL_PAD_SAI3_TXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI3_TXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x1D0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SAI3_MCLK,SW_MUX_CTL_PAD_SAI3_MCLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SAI3_MCLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,6: Select mux mode,?..."
group.long 0x1D4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SPDIF_TX,SW_MUX_CTL_PAD_SPDIF_TX SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SPDIF_TX"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x1D8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SPDIF_RX,SW_MUX_CTL_PAD_SPDIF_RX SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SPDIF_RX"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x1DC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_SPDIF_EXT_CLK,SW_MUX_CTL_PAD_SPDIF_EXT_CLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad SPDIF_EXT_CLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x1E0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI1_SCLK,SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI1_SCLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x1E4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI1_MOSI,SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI1_MOSI"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x1E8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI1_MISO,SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI1_MISO"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x1EC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI1_SS0,SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI1_SS0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x1F0++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI2_SCLK,SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI2_SCLK"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x1F4++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI2_MOSI,SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI2_MOSI"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x1F8++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI2_MISO,SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI2_MISO"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x1FC++0x03
line.long 0x00 "SW_MUX_CTL_PAD_ECSPI2_SS0,SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad ECSPI2_SS0"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,?,4: Select mux mode,5: Select mux mode,?..."
group.long 0x200++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C1_SCL,SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C1_SCL"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x204++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C1_SDA,SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C1_SDA"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x208++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C2_SCL,SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C2_SCL"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x20C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C2_SDA,SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C2_SDA"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x210++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C3_SCL,SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C3_SCL"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x214++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C3_SDA,SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C3_SDA"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x218++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C4_SCL,SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C4_SCL"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x21C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_I2C4_SDA,SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad I2C4_SDA"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x220++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART1_RXD,SW_MUX_CTL_PAD_UART1_RXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART1_RXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,?,?,5: Select mux mode,?..."
group.long 0x224++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART1_TXD,SW_MUX_CTL_PAD_UART1_TXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART1_TXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,?,?,5: Select mux mode,?..."
group.long 0x228++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART2_RXD,SW_MUX_CTL_PAD_UART2_RXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART2_RXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x22C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART2_TXD,SW_MUX_CTL_PAD_UART2_TXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART2_TXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,?,5: Select mux mode,?..."
group.long 0x230++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART3_RXD,SW_MUX_CTL_PAD_UART3_RXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART3_RXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x234++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART3_TXD,SW_MUX_CTL_PAD_UART3_TXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART3_TXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x238++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART4_RXD,SW_MUX_CTL_PAD_UART4_RXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART4_RXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,2: Select mux mode,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x23C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_UART4_TXD,SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad UART4_TXD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x240++0x03
line.long 0x00 "SW_MUX_CTL_PAD_HDMI_DDC_SCL,SW_MUX_CTL_PAD_HDMI_DDC_SCL SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad HDMI_DDC_SCL"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x244++0x03
line.long 0x00 "SW_MUX_CTL_PAD_HDMI_DDC_SDA,SW_MUX_CTL_PAD_HDMI_DDC_SDA SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad HDMI_DDC_SDA"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x248++0x03
line.long 0x00 "SW_MUX_CTL_PAD_HDMI_CEC,SW_MUX_CTL_PAD_HDMI_CEC SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad HDMI_CEC"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,?,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x24C++0x03
line.long 0x00 "SW_MUX_CTL_PAD_HDMI_HPD,SW_MUX_CTL_PAD_HDMI_HPD SW MUX Control Register"
bitfld.long 0x00 4. "SION,Software Input On Field" "0: Input Path is determined by functionality,1: Force input path of pad HDMI_HPD"
bitfld.long 0x00 0.--2. "MUX_MODE,MUX Mode Select Field" "0: Select mux mode,1: Select mux mode,?,3: Select mux mode,4: Select mux mode,5: Select mux mode,?..."
group.long 0x250++0x03
line.long 0x00 "SW_PAD_CTL_PAD_BOOT_MODE0,SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x254++0x03
line.long 0x00 "SW_PAD_CTL_PAD_BOOT_MODE1,SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x258++0x03
line.long 0x00 "SW_PAD_CTL_PAD_BOOT_MODE2,SW_PAD_CTL_PAD_BOOT_MODE2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x25C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_BOOT_MODE3,SW_PAD_CTL_PAD_BOOT_MODE3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x260++0x03
line.long 0x00 "SW_PAD_CTL_PAD_JTAG_MOD,SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x264++0x03
line.long 0x00 "SW_PAD_CTL_PAD_JTAG_TDI,SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x268++0x03
line.long 0x00 "SW_PAD_CTL_PAD_JTAG_TMS,SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x26C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_JTAG_TCK,SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x270++0x03
line.long 0x00 "SW_PAD_CTL_PAD_JTAG_TDO,SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x274++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO00,SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x278++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO01,SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x27C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO02,SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x280++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO03,SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x284++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO04,SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x288++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO05,SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x28C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO06,SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x290++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO07,SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x294++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO08,SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x298++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO09,SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x29C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO10,SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2A0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO11,SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2A4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO12,SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2A8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO13,SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2AC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO14,SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2B0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_GPIO1_IO15,SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2B4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_MDC,SW_PAD_CTL_PAD_ENET_MDC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2B8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_MDIO,SW_PAD_CTL_PAD_ENET_MDIO SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2BC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_TD3,SW_PAD_CTL_PAD_ENET_TD3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2C0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_TD2,SW_PAD_CTL_PAD_ENET_TD2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2C4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_TD1,SW_PAD_CTL_PAD_ENET_TD1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2C8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_TD0,SW_PAD_CTL_PAD_ENET_TD0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2CC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_TX_CTL,SW_PAD_CTL_PAD_ENET_TX_CTL SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2D0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_TXC,SW_PAD_CTL_PAD_ENET_TXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2D4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_RX_CTL,SW_PAD_CTL_PAD_ENET_RX_CTL SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2D8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_RXC,SW_PAD_CTL_PAD_ENET_RXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2DC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_RD0,SW_PAD_CTL_PAD_ENET_RD0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2E0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_RD1,SW_PAD_CTL_PAD_ENET_RD1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2E4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_RD2,SW_PAD_CTL_PAD_ENET_RD2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2E8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ENET_RD3,SW_PAD_CTL_PAD_ENET_RD3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2EC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_CLK,SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2F0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_CMD,SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2F4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA0,SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2F8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA1,SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x2FC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA2,SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x300++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA3,SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x304++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA4,SW_PAD_CTL_PAD_SD1_DATA4 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x308++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA5,SW_PAD_CTL_PAD_SD1_DATA5 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x30C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA6,SW_PAD_CTL_PAD_SD1_DATA6 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x310++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_DATA7,SW_PAD_CTL_PAD_SD1_DATA7 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x314++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_RESET_B,SW_PAD_CTL_PAD_SD1_RESET_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x318++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD1_STROBE,SW_PAD_CTL_PAD_SD1_STROBE SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x31C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_CD_B,SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x320++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_CLK,SW_PAD_CTL_PAD_SD2_CLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x324++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_CMD,SW_PAD_CTL_PAD_SD2_CMD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x328++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_DATA0,SW_PAD_CTL_PAD_SD2_DATA0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x32C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_DATA1,SW_PAD_CTL_PAD_SD2_DATA1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x330++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_DATA2,SW_PAD_CTL_PAD_SD2_DATA2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x334++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_DATA3,SW_PAD_CTL_PAD_SD2_DATA3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x338++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_RESET_B,SW_PAD_CTL_PAD_SD2_RESET_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x33C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SD2_WP,SW_PAD_CTL_PAD_SD2_WP SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x340++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_ALE,SW_PAD_CTL_PAD_NAND_ALE SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x344++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_CE0_B,SW_PAD_CTL_PAD_NAND_CE0_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x348++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_CE1_B,SW_PAD_CTL_PAD_NAND_CE1_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x34C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_CE2_B,SW_PAD_CTL_PAD_NAND_CE2_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x350++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_CE3_B,SW_PAD_CTL_PAD_NAND_CE3_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x354++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_CLE,SW_PAD_CTL_PAD_NAND_CLE SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x358++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA00,SW_PAD_CTL_PAD_NAND_DATA00 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x35C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA01,SW_PAD_CTL_PAD_NAND_DATA01 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x360++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA02,SW_PAD_CTL_PAD_NAND_DATA02 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x364++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA03,SW_PAD_CTL_PAD_NAND_DATA03 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x368++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA04,SW_PAD_CTL_PAD_NAND_DATA04 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x36C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA05,SW_PAD_CTL_PAD_NAND_DATA05 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x370++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA06,SW_PAD_CTL_PAD_NAND_DATA06 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x374++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DATA07,SW_PAD_CTL_PAD_NAND_DATA07 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x378++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_DQS,SW_PAD_CTL_PAD_NAND_DQS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x37C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_RE_B,SW_PAD_CTL_PAD_NAND_RE_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x380++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_READY_B,SW_PAD_CTL_PAD_NAND_READY_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x384++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_WE_B,SW_PAD_CTL_PAD_NAND_WE_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x388++0x03
line.long 0x00 "SW_PAD_CTL_PAD_NAND_WP_B,SW_PAD_CTL_PAD_NAND_WP_B SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x38C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI5_RXFS,SW_PAD_CTL_PAD_SAI5_RXFS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x390++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI5_RXC,SW_PAD_CTL_PAD_SAI5_RXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x394++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI5_RXD0,SW_PAD_CTL_PAD_SAI5_RXD0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x398++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI5_RXD1,SW_PAD_CTL_PAD_SAI5_RXD1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x39C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI5_RXD2,SW_PAD_CTL_PAD_SAI5_RXD2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3A0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI5_RXD3,SW_PAD_CTL_PAD_SAI5_RXD3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3A4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI5_MCLK,SW_PAD_CTL_PAD_SAI5_MCLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3A8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXFS,SW_PAD_CTL_PAD_SAI1_RXFS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3AC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXC,SW_PAD_CTL_PAD_SAI1_RXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3B0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD0,SW_PAD_CTL_PAD_SAI1_RXD0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3B4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD1,SW_PAD_CTL_PAD_SAI1_RXD1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3B8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD2,SW_PAD_CTL_PAD_SAI1_RXD2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3BC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD3,SW_PAD_CTL_PAD_SAI1_RXD3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3C0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD4,SW_PAD_CTL_PAD_SAI1_RXD4 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3C4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD5,SW_PAD_CTL_PAD_SAI1_RXD5 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3C8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD6,SW_PAD_CTL_PAD_SAI1_RXD6 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3CC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_RXD7,SW_PAD_CTL_PAD_SAI1_RXD7 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3D0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXFS,SW_PAD_CTL_PAD_SAI1_TXFS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3D4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXC,SW_PAD_CTL_PAD_SAI1_TXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3D8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD0,SW_PAD_CTL_PAD_SAI1_TXD0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3DC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD1,SW_PAD_CTL_PAD_SAI1_TXD1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3E0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD2,SW_PAD_CTL_PAD_SAI1_TXD2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3E4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD3,SW_PAD_CTL_PAD_SAI1_TXD3 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3E8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD4,SW_PAD_CTL_PAD_SAI1_TXD4 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3EC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD5,SW_PAD_CTL_PAD_SAI1_TXD5 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3F0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD6,SW_PAD_CTL_PAD_SAI1_TXD6 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3F4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_TXD7,SW_PAD_CTL_PAD_SAI1_TXD7 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3F8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI1_MCLK,SW_PAD_CTL_PAD_SAI1_MCLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x3FC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI2_RXFS,SW_PAD_CTL_PAD_SAI2_RXFS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x400++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI2_RXC,SW_PAD_CTL_PAD_SAI2_RXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x404++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI2_RXD0,SW_PAD_CTL_PAD_SAI2_RXD0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x408++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI2_TXFS,SW_PAD_CTL_PAD_SAI2_TXFS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x40C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI2_TXC,SW_PAD_CTL_PAD_SAI2_TXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x410++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI2_TXD0,SW_PAD_CTL_PAD_SAI2_TXD0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x414++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI2_MCLK,SW_PAD_CTL_PAD_SAI2_MCLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x418++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI3_RXFS,SW_PAD_CTL_PAD_SAI3_RXFS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x41C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI3_RXC,SW_PAD_CTL_PAD_SAI3_RXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x420++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI3_RXD,SW_PAD_CTL_PAD_SAI3_RXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x424++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI3_TXFS,SW_PAD_CTL_PAD_SAI3_TXFS SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x428++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI3_TXC,SW_PAD_CTL_PAD_SAI3_TXC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x42C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI3_TXD,SW_PAD_CTL_PAD_SAI3_TXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x430++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SAI3_MCLK,SW_PAD_CTL_PAD_SAI3_MCLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x434++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SPDIF_TX,SW_PAD_CTL_PAD_SPDIF_TX SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x438++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SPDIF_RX,SW_PAD_CTL_PAD_SPDIF_RX SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x43C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_SPDIF_EXT_CLK,SW_PAD_CTL_PAD_SPDIF_EXT_CLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x440++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI1_SCLK,SW_PAD_CTL_PAD_ECSPI1_SCLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x444++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI1_MOSI,SW_PAD_CTL_PAD_ECSPI1_MOSI SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x448++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI1_MISO,SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x44C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI1_SS0,SW_PAD_CTL_PAD_ECSPI1_SS0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x450++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI2_SCLK,SW_PAD_CTL_PAD_ECSPI2_SCLK SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x454++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI2_MOSI,SW_PAD_CTL_PAD_ECSPI2_MOSI SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x458++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI2_MISO,SW_PAD_CTL_PAD_ECSPI2_MISO SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x45C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_ECSPI2_SS0,SW_PAD_CTL_PAD_ECSPI2_SS0 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x460++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C1_SCL,SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x464++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C1_SDA,SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x468++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C2_SCL,SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x46C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C2_SDA,SW_PAD_CTL_PAD_I2C2_SDA SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x470++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C3_SCL,SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x474++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C3_SDA,SW_PAD_CTL_PAD_I2C3_SDA SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x478++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C4_SCL,SW_PAD_CTL_PAD_I2C4_SCL SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x47C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_I2C4_SDA,SW_PAD_CTL_PAD_I2C4_SDA SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x480++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART1_RXD,SW_PAD_CTL_PAD_UART1_RXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x484++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART1_TXD,SW_PAD_CTL_PAD_UART1_TXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x488++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART2_RXD,SW_PAD_CTL_PAD_UART2_RXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x48C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART2_TXD,SW_PAD_CTL_PAD_UART2_TXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x490++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART3_RXD,SW_PAD_CTL_PAD_UART3_RXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x494++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART3_TXD,SW_PAD_CTL_PAD_UART3_TXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x498++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART4_RXD,SW_PAD_CTL_PAD_UART4_RXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x49C++0x03
line.long 0x00 "SW_PAD_CTL_PAD_UART4_TXD,SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4A0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_HDMI_DDC_SCL,SW_PAD_CTL_PAD_HDMI_DDC_SCL SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4A4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_HDMI_DDC_SDA,SW_PAD_CTL_PAD_HDMI_DDC_SDA SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4A8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_HDMI_CEC,SW_PAD_CTL_PAD_HDMI_CEC SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4AC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_HDMI_HPD,SW_PAD_CTL_PAD_HDMI_HPD SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4B0++0x03
line.long 0x00 "SW_PAD_CTL_PAD_CLKIN1,SW_PAD_CTL_PAD_CLKIN1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4B4++0x03
line.long 0x00 "SW_PAD_CTL_PAD_CLKIN2,SW_PAD_CTL_PAD_CLKIN2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4B8++0x03
line.long 0x00 "SW_PAD_CTL_PAD_CLKOUT1,SW_PAD_CTL_PAD_CLKOUT1 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4BC++0x03
line.long 0x00 "SW_PAD_CTL_PAD_CLKOUT2,SW_PAD_CTL_PAD_CLKOUT2 SW PAD Control Register"
bitfld.long 0x00 8. "PE,Pull Select Field" "0: PE_0_PULL_DISABLE,1: PE_1_PULL_ENABLE"
bitfld.long 0x00 7. "HYS,Input Select Field" "0: HYS_0_CMOS,1: HYS_1_SCHMITT"
newline
bitfld.long 0x00 6. "PUE,Pull Up / Down Config" "0: PUE_0_WEAK_PULL_DOWN,1: PUE_1_WEAK_PULL_UP"
bitfld.long 0x00 5. "ODE,Open Drain Field" "0: ODE_0_OPEN_DRAIN_DISABLE,1: ODE_1_OPEN_DRAIN_ENABLE"
newline
bitfld.long 0x00 4. "FSEL,Slew Rate Field" "0: FSEL_0_SLOW_SLEW_RATE,1: FSEL_1_FAST_SLEW_RATE"
bitfld.long 0x00 1.--2. "DSE,Drive Strength Field" "0: DSE_X1,1: DSE_X4,2: DSE_X2,3: DSE_X6"
group.long 0x4C0++0x03
line.long 0x00 "AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0,AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,?..."
group.long 0x4C4++0x03
line.long 0x00 "AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_1,AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_1 DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,6: Selecting Pad,7: Selecting Pad"
group.long 0x4C8++0x03
line.long 0x00 "AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_2,AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_2 DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,6: Selecting Pad,7: Selecting Pad"
group.long 0x4CC++0x03
line.long 0x00 "AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_3,AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_3 DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,6: Selecting Pad,?..."
group.long 0x4D0++0x03
line.long 0x00 "AUDIOMIX_SAI1_RXSYNC_SELECT_INPUT,AUDIOMIX_SAI1_RXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x4D4++0x03
line.long 0x00 "AUDIOMIX_SAI1_TXBCLK_SELECT_INPUT,AUDIOMIX_SAI1_TXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x4D8++0x03
line.long 0x00 "AUDIOMIX_SAI1_TXSYNC_SELECT_INPUT,AUDIOMIX_SAI1_TXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,?..."
group.long 0x4DC++0x03
line.long 0x00 "AUDIOMIX_SAI2_RXDATA_SELECT_INPUT_1,AUDIOMIX_SAI2_RXDATA_SELECT_INPUT_1 DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x4E0++0x03
line.long 0x00 "AUDIOMIX_SAI3_MCLK_SELECT_INPUT,AUDIOMIX_SAI3_MCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x4E4++0x03
line.long 0x00 "AUDIOMIX_SAI3_RXDATA_SELECT_INPUT_0,AUDIOMIX_SAI3_RXDATA_SELECT_INPUT_0 DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x4E8++0x03
line.long 0x00 "AUDIOMIX_SAI3_TXBCLK_SELECT_INPUT,AUDIOMIX_SAI3_TXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x4EC++0x03
line.long 0x00 "AUDIOMIX_SAI3_TXSYNC_SELECT_INPUT,AUDIOMIX_SAI3_TXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x4F0++0x03
line.long 0x00 "AUDIOMIX_SAI5_MCLK_SELECT_INPUT,AUDIOMIX_SAI5_MCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,3: Selecting Pad"
group.long 0x4F4++0x03
line.long 0x00 "AUDIOMIX_SAI5_RXBCLK_SELECT_INPUT,AUDIOMIX_SAI5_RXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x4F8++0x03
line.long 0x00 "AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_0,AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_0 DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x4FC++0x03
line.long 0x00 "AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_1,AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_1 DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x500++0x03
line.long 0x00 "AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_2,AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_2 DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x504++0x03
line.long 0x00 "AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_3,AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_3 DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x508++0x03
line.long 0x00 "AUDIOMIX_SAI5_RXSYNC_SELECT_INPUT,AUDIOMIX_SAI5_RXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x50C++0x03
line.long 0x00 "AUDIOMIX_SAI5_TXBCLK_SELECT_INPUT,AUDIOMIX_SAI5_TXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x510++0x03
line.long 0x00 "AUDIOMIX_SAI5_TXSYNC_SELECT_INPUT,AUDIOMIX_SAI5_TXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,?,2: Selecting Pad,?..."
group.long 0x514++0x03
line.long 0x00 "AUDIOMIX_SAI6_MCLK_SELECT_INPUT,AUDIOMIX_SAI6_MCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x518++0x03
line.long 0x00 "AUDIOMIX_SAI6_RXBCLK_SELECT_INPUT,AUDIOMIX_SAI6_RXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x51C++0x03
line.long 0x00 "AUDIOMIX_SAI6_RXDATA_SELECT_INPUT_0,AUDIOMIX_SAI6_RXDATA_SELECT_INPUT_0 DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x520++0x03
line.long 0x00 "AUDIOMIX_SAI6_RXSYNC_SELECT_INPUT,AUDIOMIX_SAI6_RXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x524++0x03
line.long 0x00 "AUDIOMIX_SAI6_TXBCLK_SELECT_INPUT,AUDIOMIX_SAI6_TXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x528++0x03
line.long 0x00 "AUDIOMIX_SAI6_TXSYNC_SELECT_INPUT,AUDIOMIX_SAI6_TXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x52C++0x03
line.long 0x00 "AUDIOMIX_SAI7_MCLK_SELECT_INPUT,AUDIOMIX_SAI7_MCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x530++0x03
line.long 0x00 "AUDIOMIX_SAI7_RXBCLK_SELECT_INPUT,AUDIOMIX_SAI7_RXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x534++0x03
line.long 0x00 "AUDIOMIX_SAI7_RXDATA_SELECT_INPUT_0,AUDIOMIX_SAI7_RXDATA_SELECT_INPUT_0 DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x538++0x03
line.long 0x00 "AUDIOMIX_SAI7_RXSYNC_SELECT_INPUT,AUDIOMIX_SAI7_RXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x53C++0x03
line.long 0x00 "AUDIOMIX_SAI7_TXBCLK_SELECT_INPUT,AUDIOMIX_SAI7_TXBCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x540++0x03
line.long 0x00 "AUDIOMIX_SAI7_TXSYNC_SELECT_INPUT,AUDIOMIX_SAI7_TXSYNC_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x544++0x03
line.long 0x00 "AUDIOMIX_EARC_PHY_SPDIF_IN_SELECT_INPUT,AUDIOMIX_EARC_PHY_SPDIF_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,?..."
group.long 0x548++0x03
line.long 0x00 "AUDIOMIX_SPDIF_EXTCLK_SELECT_INPUT,AUDIOMIX_SPDIF_EXTCLK_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x54C++0x03
line.long 0x00 "CAN1_CANRX_SELECT_INPUT,CAN1_CANRX_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x550++0x03
line.long 0x00 "CAN2_CANRX_SELECT_INPUT,CAN2_CANRX_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x554++0x03
line.long 0x00 "CCM_GPC_PMIC_VFUNCTIONAL_READY_SELECT_INPUT,CCM_GPC_PMIC_VFUNCTIONAL_READY_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x558++0x03
line.long 0x00 "ECSPI1_CSPI_CLK_IN_SELECT_INPUT,ECSPI1_CSPI_CLK_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x55C++0x03
line.long 0x00 "ECSPI1_MISO_SELECT_INPUT,ECSPI1_MISO_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x560++0x03
line.long 0x00 "ECSPI1_MOSI_SELECT_INPUT,ECSPI1_MOSI_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x564++0x03
line.long 0x00 "ECSPI1_SS_B_SELECT_INPUT_0,ECSPI1_SS_B_SELECT_INPUT_0 DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x568++0x03
line.long 0x00 "ECSPI2_CSPI_CLK_IN_SELECT_INPUT,ECSPI2_CSPI_CLK_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x56C++0x03
line.long 0x00 "ECSPI2_MISO_SELECT_INPUT,ECSPI2_MISO_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x570++0x03
line.long 0x00 "ECSPI2_MOSI_SELECT_INPUT,ECSPI2_MOSI_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x574++0x03
line.long 0x00 "ECSPI2_SS_B_SELECT_INPUT_0,ECSPI2_SS_B_SELECT_INPUT_0 DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x578++0x03
line.long 0x00 "ENET1_IPG_CLK_RMII_SELECT_INPUT,ENET1_IPG_CLK_RMII_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x57C++0x03
line.long 0x00 "ENET1_MDIO_SELECT_INPUT,ENET1_MDIO_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x580++0x03
line.long 0x00 "ENET1_RXDATA_0_SELECT_INPUT,ENET1_RXDATA_0_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x584++0x03
line.long 0x00 "ENET1_RXDATA_1_SELECT_INPUT,ENET1_RXDATA_1_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x588++0x03
line.long 0x00 "ENET1_RXEN_SELECT_INPUT,ENET1_RXEN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x58C++0x03
line.long 0x00 "ENET1_RXERR_SELECT_INPUT,ENET1_RXERR_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x590++0x03
line.long 0x00 "ENET_QOS_GMII_MDI_I_SELECT_INPUT,ENET_QOS_GMII_MDI_I_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x594++0x03
line.long 0x00 "GPT1_CAPIN1_SELECT_INPUT,GPT1_CAPIN1_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x598++0x03
line.long 0x00 "GPT1_CAPIN2_SELECT_INPUT,GPT1_CAPIN2_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x59C++0x03
line.long 0x00 "GPT1_CLKIN_SELECT_INPUT,GPT1_CLKIN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x5A0++0x03
line.long 0x00 "PCIE_CLKREQ_B_SELECT_INPUT,PCIE_CLKREQ_B_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x5A4++0x03
line.long 0x00 "I2C1_SCL_IN_SELECT_INPUT,I2C1_SCL_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x5A8++0x03
line.long 0x00 "I2C1_SDA_IN_SELECT_INPUT,I2C1_SDA_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x5AC++0x03
line.long 0x00 "I2C2_SCL_IN_SELECT_INPUT,I2C2_SCL_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x5B0++0x03
line.long 0x00 "I2C2_SDA_IN_SELECT_INPUT,I2C2_SDA_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,?..."
group.long 0x5B4++0x03
line.long 0x00 "I2C3_SCL_IN_SELECT_INPUT,I2C3_SCL_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,?..."
group.long 0x5B8++0x03
line.long 0x00 "I2C3_SDA_IN_SELECT_INPUT,I2C3_SDA_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,?..."
group.long 0x5BC++0x03
line.long 0x00 "I2C4_SCL_IN_SELECT_INPUT,I2C4_SCL_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,?..."
group.long 0x5C0++0x03
line.long 0x00 "I2C4_SDA_IN_SELECT_INPUT,I2C4_SDA_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,?..."
group.long 0x5C4++0x03
line.long 0x00 "I2C5_SCL_IN_SELECT_INPUT,I2C5_SCL_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x5C8++0x03
line.long 0x00 "I2C5_SDA_IN_SELECT_INPUT,I2C5_SDA_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x5CC++0x03
line.long 0x00 "I2C6_SCL_IN_SELECT_INPUT,I2C6_SCL_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x5D0++0x03
line.long 0x00 "I2C6_SDA_IN_SELECT_INPUT,I2C6_SDA_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x5D4++0x03
line.long 0x00 "ISP_FL_TRIG_0_SELECT_INPUT,ISP_FL_TRIG_0_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x5D8++0x03
line.long 0x00 "ISP_FL_TRIG_1_SELECT_INPUT,ISP_FL_TRIG_1_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x5DC++0x03
line.long 0x00 "ISP_SHUTTER_TRIG_0_SELECT_INPUT,ISP_SHUTTER_TRIG_0_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x5E0++0x03
line.long 0x00 "ISP_SHUTTER_TRIG_1_SELECT_INPUT,ISP_SHUTTER_TRIG_1_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x5E4++0x03
line.long 0x00 "UART1_UART_RTS_B_SELECT_INPUT,UART1_UART_RTS_B_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,?..."
group.long 0x5E8++0x03
line.long 0x00 "UART1_UART_RXD_MUX_SELECT_INPUT,UART1_UART_RXD_MUX_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,?..."
group.long 0x5EC++0x03
line.long 0x00 "UART2_UART_RTS_B_SELECT_INPUT,UART2_UART_RTS_B_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,?..."
group.long 0x5F0++0x03
line.long 0x00 "UART2_UART_RXD_MUX_SELECT_INPUT,UART2_UART_RXD_MUX_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,6: Selecting Pad,7: Selecting Pad"
group.long 0x5F4++0x03
line.long 0x00 "UART3_UART_RTS_B_SELECT_INPUT,UART3_UART_RTS_B_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x5F8++0x03
line.long 0x00 "UART3_UART_RXD_MUX_SELECT_INPUT,UART3_UART_RXD_MUX_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--2. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,6: Selecting Pad,7: Selecting Pad"
group.long 0x5FC++0x03
line.long 0x00 "UART4_UART_RTS_B_SELECT_INPUT,UART4_UART_RTS_B_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x600++0x03
line.long 0x00 "UART4_UART_RXD_MUX_SELECT_INPUT,UART4_UART_RXD_MUX_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--3. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad,4: Selecting Pad,5: Selecting Pad,6: Selecting Pad,7: Selecting Pad,8: Selecting Pad,9: Selecting Pad,?..."
group.long 0x604++0x03
line.long 0x00 "USDHC3_CARD_CLK_IN_SELECT_INPUT,USDHC3_CARD_CLK_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x608++0x03
line.long 0x00 "USDHC3_CARD_DET_SELECT_INPUT,USDHC3_CARD_DET_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
group.long 0x60C++0x03
line.long 0x00 "USDHC3_CMD_IN_SELECT_INPUT,USDHC3_CMD_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x610++0x03
line.long 0x00 "USDHC3_DAT0_IN_SELECT_INPUT,USDHC3_DAT0_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x614++0x03
line.long 0x00 "USDHC3_DAT1_IN_SELECT_INPUT,USDHC3_DAT1_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x618++0x03
line.long 0x00 "USDHC3_DAT2_IN_SELECT_INPUT,USDHC3_DAT2_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x61C++0x03
line.long 0x00 "USDHC3_DAT3_IN_SELECT_INPUT,USDHC3_DAT3_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x620++0x03
line.long 0x00 "USDHC3_DAT4_IN_SELECT_INPUT,USDHC3_DAT4_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x624++0x03
line.long 0x00 "USDHC3_DAT5_IN_SELECT_INPUT,USDHC3_DAT5_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x628++0x03
line.long 0x00 "USDHC3_DAT6_IN_SELECT_INPUT,USDHC3_DAT6_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x62C++0x03
line.long 0x00 "USDHC3_DAT7_IN_SELECT_INPUT,USDHC3_DAT7_IN_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x630++0x03
line.long 0x00 "USDHC3_STROBE_SELECT_INPUT,USDHC3_STROBE_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad"
group.long 0x634++0x03
line.long 0x00 "USDHC3_WP_ON_SELECT_INPUT,USDHC3_WP_ON_SELECT_INPUT DAISY Register"
bitfld.long 0x00 0.--1. "DAISY,Selecting Pads Involved in Daisy Chain" "0: Selecting Pad,1: Selecting Pad,2: Selecting Pad,3: Selecting Pad"
tree.end
tree "IOMUXC_GPR (IOMUX Controller General Purpose Registers)"
base ad:0x30340000
rgroup.long 0x00++0x03
line.long 0x00 "GPR0,General Purpose Register 0"
group.long 0x04++0x03
line.long 0x00 "GPR1,General Purpose Register 1"
bitfld.long 0x00 28.--31. "GPR_DBG_ACK_A53_MASK,mask debug ack from each ca53 core" "0: GPR_DBG_ACK_A53_MASK_0,1: GPR_DBG_ACK_A53_MASK_1,?..."
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bitfld.long 0x00 27. "GPR_DBG_ACK_M7_MASK,mask debug ack from each cm7" "0: GPR_DBG_ACK_M7_MASK_0,1: GPR_DBG_ACK_M7_MASK_1"
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bitfld.long 0x00 23. "GPR_TZASC1_SECURE_BOOT_LOCK,secure_boot_lock for TZASC" "0,1"
newline
bitfld.long 0x00 22. "IOMUXC_GPR_ENET1_RGMII_EN,ENET1 TX clock direction select for RGMII or MII" "0: IOMUXC_GPR_ENET1_RGMII_EN_0,1: IOMUXC_GPR_ENET1_RGMII_EN_1"
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bitfld.long 0x00 21. "IOMUXC_GPR_ENET_QOS_RGMII_EN,ENET QOS tx clock direction select for RGMII or MII" "0: IOMUXC_GPR_ENET_QOS_RGMII_EN_0,1: IOMUXC_GPR_ENET_QOS_RGMII_EN_1"
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bitfld.long 0x00 20. "IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL,SOI bit for the pad(iomuxc_sw_input_on_pad_enet_td2) should be set also" "0: ENET QOS RMII clock comes from external PHY..,1: ENET QOS RMII clock comes from.."
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bitfld.long 0x00 19. "GPR_ENET_QOS_CLK_GEN_EN,enable clk generate module for ENET QoS" "0: GPR_ENET_QOS_CLK_GEN_EN_0,1: GPR_ENET_QOS_CLK_GEN_EN_1"
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bitfld.long 0x00 16.--18. "GPR_ENET_QOS_INTF_SEL,select ENET QOS working mode" "0: GPR_ENET_QOS_INTF_SEL_0,1: GPR_ENET_QOS_INTF_SEL_1,?,?,4: GPR_ENET_QOS_INTF_SEL_4,?..."
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bitfld.long 0x00 15. "GPR_ANAMIX_IPT_MODE,mask ANAMIX ipt_mode" "0: GPR_ANAMIX_IPT_MODE_0,1: GPR_ANAMIX_IPT_MODE_1"
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bitfld.long 0x00 14. "GPR_ENET_QOS_DIS_CRC_CHK,disable CRC check feature" "0: GPR_ENET_QOS_DIS_CRC_CHK_0,1: GPR_ENET_QOS_DIS_CRC_CHK_1"
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bitfld.long 0x00 13. "IOMUXC_GPR_ENET1_TX_CLK_SEL,SOI bit for the pad(iomuxc_sw_input_on_pad_enet_td2) should be set also" "0: ENET1 RMII clock comes from external PHY or OSC,1: ENET1 RMII clock comes from ccm->pad->loopback"
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bitfld.long 0x00 12. "GPR_IRQ,Generate IRQ on IRQ0" "0,1"
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bitfld.long 0x00 7. "GPR_LVDS_TEST_DO_ON3,clock gate for LVDS TEST_DO[0] (ccm_ipp_do_clko1)" "0,1"
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bitfld.long 0x00 6. "GPR_LVDS_TEST_DO_ON2,clock gate for LVDS TEST_DO[1] (audio_pll1_clk)" "0,1"
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bitfld.long 0x00 5. "GPR_LVDS_TEST_DO_ON1,clock gate for LVDS TEST_DO[2] (sys_pll3_clk)" "0,1"
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bitfld.long 0x00 4. "GPR_LVDS_TEST_DO_ON0,clock gate for LVDS TEST_DO[3] (video_pll1_clk)" "0,1"
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bitfld.long 0x00 3. "GPR_GPT1_CAPIN2_SEL,Selector for GPT1 Capture in Channel 2" "0: GPR_GPT1_CAPIN2_SEL_0,1: ENET QOS TIMIER1 EVENT"
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bitfld.long 0x00 2. "GPR_GPT1_CAPIN1_SEL,Selector for GPT1 Capture in Channel 1" "0: GPR_GPT1_CAPIN1_SEL_0,1: GPR_GPT1_CAPIN1_SEL_1"
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bitfld.long 0x00 1. "GPR_ENET_QOS_EVENT0IN_SEL,Selector for ENET QoS EVENT0 IN" "0: GPR_ENET_QOS_EVENT0IN_SEL_0,1: GPR_ENET_QOS_EVENT0IN_SEL_1"
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bitfld.long 0x00 0. "GPR_ENET1_EVENT0IN_SEL,Selector for ENET1 EVENT0 IN" "0: GPR_ENET1_EVENT0IN_SEL_0,1: GPR_ENET1_EVENT0IN_SEL_1"
group.long 0x08++0x03
line.long 0x00 "GPR2,General Purpose Register 2"
bitfld.long 0x00 0.--1. "GPR_CORESIGHT_GPR_CTM_SEL,select for coresight master" "0,1,2,3"
rgroup.long 0x0C++0x03
line.long 0x00 "GPR3,General Purpose Register 3"
group.long 0x10++0x03
line.long 0x00 "GPR4,General Purpose Register 4"
rbitfld.long 0x00 28.--31. "CPU_STANDBYWFE,From CA53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "CPU_STANDBYWFI,From CA53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 21. "GPR_CAN2_IPG_STOP_ACK,can2 ipg stop ack" "0,1"
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rbitfld.long 0x00 20. "GPR_CAN1_IPG_STOP_ACK,can1 ipg stop ack" "0,1"
newline
rbitfld.long 0x00 19. "GPR_ENET1_IPG_STOP_ACK,enet1 ipg stop ack" "0,1"
newline
rbitfld.long 0x00 17. "GPR_FLEXSPI_O_IPG_STOP_ACK,flexspi ipg stop ack" "0,1"
newline
rbitfld.long 0x00 16. "GPR_SDAM1_IPG_STOP_ACK,sdma1 ipg stop ack" "0,1"
newline
bitfld.long 0x00 5. "GPR_CAN2_IPG_STOP,can2 ipg stop" "0,1"
newline
bitfld.long 0x00 4. "GPR_CAN1_IPG_STOP,can1 ipg stop" "0,1"
newline
bitfld.long 0x00 3. "GPR_ENET1_IPG_STOP,enet1 ipg stop" "0,1"
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bitfld.long 0x00 1. "GPR_FLEXSPI_I_IPG_STOP,flexspi ipg stop" "0,1"
newline
bitfld.long 0x00 0. "GPR_SDMA1_IPG_STOP,sdma1 ipg stop" "0,1"
group.long 0x14++0x03
line.long 0x00 "GPR5,General Purpose Register 5"
bitfld.long 0x00 20. "GPR_WDOG3_MASK,This bit is only used to mask the internal WDOG3 int signal for output of GPIO1_IO02" "0: wdog3 low will make the GPIO1_IO02.alt5_out low,1: wdog3 low will NOT impact the.."
newline
bitfld.long 0x00 7. "GPR_WDOG2_MASK,This bit is only used to mask the internal WDOG2 int signal for output of GPIO1_IO02" "0: wdog2 low will make the GPIO1_IO02.alt5_out low,1: wdog2 low will NOT impact the.."
newline
bitfld.long 0x00 6. "GPR_WDOG1_MASK,Normally WDOG1 output is in GPIO1_IO02" "0: wdog1 low will make the GPIO1_IO02.alt5_out low,1: wdog1 low will NOT impact the.."
newline
bitfld.long 0x00 2. "GPR_ENABLE_UPSIZER,enable to upsize 32bit SDMA1 burst transaction to 64bit" "0,1"
newline
bitfld.long 0x00 1. "GPR_RMW_S_WAIT_BVALID_CPL,If this bit set to 1 RMW will write back next data after bvalid_s is 1" "0,1"
newline
bitfld.long 0x00 0. "GPR_RMW_WAIT_BVALID_CPL,If this bit set to 1 RMW will write back next data after bvalid_s is 1" "0,1"
group.long 0x18++0x03
line.long 0x00 "GPR6,General Purpose Register 6"
hexmask.long 0x00 7.--31. 1. "GPR_M7_INITVTOR,decides where cm7 boot up out of reset"
repeat 3. (strings "7" "8" "9" )(list 0x0 0x4 0x8 )
rgroup.long ($2+0x1C)++0x03
line.long 0x00 "GPR$1,General Purpose Register $1"
repeat.end
group.long 0x28++0x03
line.long 0x00 "GPR10,General Purpose Register 10"
bitfld.long 0x00 19. "LOCK_GPR_EXC_ERR_RESP_EN,Lock bit for GPR_EXC_ERR_RESP_EN" "0,1"
newline
bitfld.long 0x00 18. "LOCK_GPR_SEC_ERR_RESP_EN,Lock bit for GPR_SEC_ERR_RESP_EN" "0,1"
newline
bitfld.long 0x00 17. "LOCK_GPR_TZASC_ID_SWAP_BYPASS,Lock bit for GPR_TZASC_ID_SWAP_BYPASS" "0,1"
newline
bitfld.long 0x00 16. "LOCK_GPR_TZASC_EN,Lock bit for GPR_TZASC_EN" "0,1"
newline
bitfld.long 0x00 5.--10. "GPR_OCRAM_A_TZ_START_ADDR,OCRAM Audio Trustzone start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "GPR_OCRAM_A_TZ_EN,OCRAM Audio Trustzone Enable" "0,1"
newline
bitfld.long 0x00 3. "GPR_EXC_ERR_RESP_EN,mem security gasket exclusive error response enable" "0,1"
newline
bitfld.long 0x00 2. "GPR_SEC_ERR_RESP_EN,mem security gasket security error response enable" "0,1"
newline
bitfld.long 0x00 1. "GPR_TZASC_ID_SWAP_BYPASS,Connect to id_swap_bypass input on tzasc_id_wrap" "0,1"
newline
bitfld.long 0x00 0. "GPR_TZASC_EN,Connect to tzasc_en input on tzasc_id_wrap" "0,1"
group.long 0x2C++0x03
line.long 0x00 "GPR11,General Purpose Register 11"
bitfld.long 0x00 27.--29. "LOCK_GPR_OCRAM_S_TZ_START_ADDR,Lock bit for GPR_OCRAM_S_TZ_START_ADDR[15:12]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 26. "LOCK_GPR_OCRAM_S_TZ_EN,Lock bit for GPR_OCRAM_S_TZ_EN" "0,1"
newline
bitfld.long 0x00 25. "LOCK_GPR_CAAM_CAAM_IPS_MANAGER,Lock bit for GPR_CAAM_CAAM_IPS_MANAGER[4]" "0,1"
newline
hexmask.long.byte 0x00 17.--24. 1. "LOCK_GPR_OCRAM_TZ_START_ADDR,Lock bit for GPR_OCRAM_TZ_START_ADDR[19:12]"
newline
bitfld.long 0x00 16. "LOCK_GPR_OCRAM_TZ_EN,Lock bit for GPR_OCRAM_TZ_EN" "0,1"
newline
bitfld.long 0x00 11.--14. "GPR_OCRAM_S_TZ_START_ADDR,OCRAM_S Trustzone start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10. "GPR_OCRAM_S_TZ_EN,OCRAM_S Trustzone Enable" "0,1"
newline
bitfld.long 0x00 9. "GPR_CAAM_CAAM_IPS_MANAGER,Used to control whether CAAM manager page and Job ring registers are controlled by CSU/RDC slot" "0: not controlled by CSU/RDC slot,1: GPR_CAAM_CAAM_IPS_MANAGER_1"
newline
hexmask.long.byte 0x00 1.--8. 1. "GPR_OCRAM_TZ_START_ADDR,OCRAM Trustzone start address"
newline
bitfld.long 0x00 0. "GPR_OCRAM_TZ_EN,OCRAM Trustzone Enable" "0,1"
group.long 0x30++0x03
line.long 0x00 "GPR12,General Purpose Register 12"
bitfld.long 0x00 31. "GPR_PCIE_DIAG_BUS_SEL,To PCIe CTRL" "0,1"
newline
bitfld.long 0x00 21.--22. "GPR_PCIE1_CTRL_DIAG_CTRL_BUS,To PCIe CTRL" "0,1,2,3"
newline
bitfld.long 0x00 17.--20. "GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT,To PCIe CTRL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "GPR_PCIE1_CTRL_DEVICE_TYPE,To PCIe CTRL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "GPR13,General Purpose Register 13"
bitfld.long 0x00 14. "GPR_AWCACHE_USB2,control the awcache[1] of usb master transaction" "0,1"
newline
bitfld.long 0x00 13. "GPR_ARCACHE_USB2,control the arcache[1] of usb master transaction" "0,1"
newline
bitfld.long 0x00 11. "GPR_AWCACHE_PCIE_EN,enable the GPR control of AWCACHE[1] of PCIE1 master transaction" "0,1"
newline
bitfld.long 0x00 10. "GPR_ARCACHE_PCIE_EN,enable the GPR control of ARCACHE[1] of PCIE1 master transaction" "0,1"
newline
bitfld.long 0x00 8. "GPR_AWCACHE_USB1,control the awcache[1] of usb master transaction" "0,1"
newline
bitfld.long 0x00 7. "GPR_ARCACHE_USB1,control the arcache[1] of usb master transaction" "0,1"
newline
bitfld.long 0x00 5. "GPR_AWCACHE_PCIE,control the awcache[1] of pcie master transaction" "0,1"
newline
bitfld.long 0x00 4. "GPR_ARCACHE_PCIE,control the arcache[1] of pcie master transaction" "0,1"
newline
bitfld.long 0x00 1. "GPR_AWCACHE_USDHC,sim_m.awcache_m_d_6/7/8[1]" "0,1"
newline
bitfld.long 0x00 0. "GPR_ARCACHE_USDHC,sim_m.arcache_m_d_6/7/8[1]" "0,1"
group.long 0x38++0x03
line.long 0x00 "GPR14,General Purpose Register 14"
bitfld.long 0x00 24.--25. "GPR_PCIE_PHY_PLL_REF_CLK_SEL,no description available" "0: GPR_PCIE_PHY_PLL_REF_CLK_SEL_0,1: Selects reference clock from XO..,2: Selects reference clock from IO..,3: Selects reference clock from SOC PLL.."
newline
bitfld.long 0x00 16.--19. "GPR_PCIE_PHY_CTRL_BUS,To PCIe CTRL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "GPR_PCIE_CLKREQ_B_OVERRIDE,Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller" "0,1"
newline
bitfld.long 0x00 10. "GPR_PCIE_CLKREQ_B_OVERRIDE_EN,Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller" "0,1"
newline
bitfld.long 0x00 9. "GPR_PCIE_REF_USE_PAD,To PCIe CTRL" "0,1"
newline
bitfld.long 0x00 8. "GPR_PCIE_APP_CLK_PM_EN,To PCIe CTRL" "0,1"
group.long 0x3C++0x03
line.long 0x00 "GPR15,General Purpose Register 15"
hexmask.long.word 0x00 16.--31. 1. "GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D,GPU2D AXI OTR limit beat limit"
newline
hexmask.long.word 0x00 0.--15. 1. "GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D,GPU3D AXI OTR limit beat limit"
group.long 0x40++0x03
line.long 0x00 "GPR16,General Purpose Register 16"
bitfld.long 0x00 1. "GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D,GPU2D AXI OTR limit gasket eanble" "0,1"
newline
bitfld.long 0x00 0. "GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D,GPU3D AXI OTR limit gasket eanble" "0,1"
repeat 2. (strings "17" "18" )(list 0x0 0x4 )
rgroup.long ($2+0x44)++0x03
line.long 0x00 "GPR$1,General Purpose Register $1"
repeat.end
rgroup.long 0x4C++0x03
line.long 0x00 "GPR19,General Purpose Register 19"
hexmask.long 0x00 0.--31. 1. "PCIE_DIAG_STATUS,From PCIE"
group.long 0x50++0x03
line.long 0x00 "GPR20,General Purpose Register 20"
bitfld.long 0x00 31. "GPR_APBHDMA_M_D_4_HADDR32,haddr bit 32 of apbhdma" "0,1"
newline
bitfld.long 0x00 30. "GPR_APBHDMA_M_D_4_HADDR33,haddr bit 33 of apbhdma" "0,1"
newline
bitfld.long 0x00 29. "GPR_CORESIGHT_M_A_0_ARADDR32,araddr bit 32 of coresight" "0,1"
newline
bitfld.long 0x00 28. "GPR_CORESIGHT_M_A_0_ARADDR33,araddr bit 33 of coresight" "0,1"
newline
bitfld.long 0x00 27. "GPR_CORESIGHT_M_A_0_AWADDR32,awaddr bit 32 of coresight" "0,1"
newline
bitfld.long 0x00 26. "GPR_CORESIGHT_M_A_0_AWADDR33,awaddr bit 33 of coresight" "0,1"
newline
bitfld.long 0x00 25. "GPR_DAP_M_D_0_HADDR32,AHB address bit 32 of DAP" "0,1"
newline
bitfld.long 0x00 24. "GPR_DAP_M_D_0_HADDR33,AHB address bit 33 of DAP" "0,1"
newline
bitfld.long 0x00 23. "GPR_ENET1_M_E_0_ARADDR32,AXI read in fabric m_e_0 address bit 32 of ENET1" "0,1"
newline
bitfld.long 0x00 22. "GPR_ENET1_M_E_0_ARADDR33,AXI read in fabric m_e_0 address bit 33 of ENET1" "0,1"
newline
bitfld.long 0x00 21. "GPR_ENET1_M_E_0_AWADDR32,AXI write in fabric m_e_0 address bit 32 of ENET1" "0,1"
newline
bitfld.long 0x00 20. "GPR_ENET1_M_E_0_AWADDR33,AXI write in fabric m_e_0 address bit 33 of ENET1" "0,1"
newline
bitfld.long 0x00 19. "GPR_ENET1_M_E_1_ARADDR32,AXI read in fabric m_e_1 address bit 32 of ENET1" "0,1"
newline
bitfld.long 0x00 18. "GPR_ENET1_M_E_1_ARADDR33,AXI read in fabric m_e_1 address bit 33 of ENET1" "0,1"
newline
bitfld.long 0x00 17. "GPR_ENET1_M_E_1_AWADDR32,AXI write in fabric m_e_1 address bit 32 of ENET1" "0,1"
newline
bitfld.long 0x00 16. "GPR_ENET1_M_E_1_AWADDR33,AXI write in fabric m_e_1 address bit 33 of ENET1" "0,1"
newline
bitfld.long 0x00 15. "GPR_RAWNAND_M_D_5_ARADDR32,AXI read address bit 32 of RAWNAND" "0,1"
newline
bitfld.long 0x00 14. "GPR_RAWNAND_M_D_5_ARADDR33,AXI read address bit 33 of RAWNAND" "0,1"
newline
bitfld.long 0x00 13. "GPR_RAWNAND_M_D_5_AWADDR32,AXI write address bit 32 of RAWNAND" "0,1"
newline
bitfld.long 0x00 12. "GPR_RAWNAND_M_D_5_AWADDR33,AXI write address bit 33 of RAWNAND" "0,1"
newline
bitfld.long 0x00 11. "GPR_USDHC1_M_D_6_ARADDR32,AXI read address bit 32 of USDHC1" "0,1"
newline
bitfld.long 0x00 10. "GPR_USDHC1_M_D_6_ARADDR33,AXI read address bit 33 of USDHC1" "0,1"
newline
bitfld.long 0x00 9. "GPR_USDHC1_M_D_6_AWADDR32,AXI write address bit 32 of USDHC1" "0,1"
newline
bitfld.long 0x00 8. "GPR_USDHC1_M_D_6_AWADDR33,AXI write address bit 33 of USDHC1" "0,1"
newline
bitfld.long 0x00 7. "GPR_USDHC2_M_D_7_ARADDR32,AXI read address bit 32 of USDHC2" "0,1"
newline
bitfld.long 0x00 6. "GPR_USDHC2_M_D_7_ARADDR33,AXI read address bit 33 of USDHC2" "0,1"
newline
bitfld.long 0x00 5. "GPR_USDHC2_M_D_7_AWADDR32,AXI write address bit 32 of USDHC2" "0,1"
newline
bitfld.long 0x00 4. "GPR_USDHC2_M_D_7_AWADDR33,AXI write address bit 33 of USDHC2" "0,1"
newline
bitfld.long 0x00 3. "GPR_USDHC3_M_D_8_ARADDR32,AXI read address bit 32 of USDHC3" "0,1"
newline
bitfld.long 0x00 2. "GPR_USDHC3_M_D_8_ARADDR33,AXI read address bit 33 of USDHC3" "0,1"
newline
bitfld.long 0x00 1. "GPR_USDHC3_M_D_8_AWADDR32,AXI write address bit 32 of USDHC3" "0,1"
newline
bitfld.long 0x00 0. "GPR_USDHC3_M_D_8_AWADDR33,AXI write address bit 33 of USDHC3" "0,1"
group.long 0x54++0x03
line.long 0x00 "GPR21,General Purpose Register 21"
bitfld.long 0x00 31. "GPR_SDMA1_M_D_2_HADDR32,AHB address bit 32 of SDMA1" "0,1"
newline
bitfld.long 0x00 30. "GPR_SDMA1_M_D_2_HADDR33,AHB address bit 33 of SDMA1" "0,1"
newline
bitfld.long 0x00 29. "GPR_SDMA1_M_D_3_ARADDR32,AXI read address bit 32 of SDMA1" "0,1"
newline
bitfld.long 0x00 28. "GPR_SDMA1_M_D_3_ARADDR33,AXI read address bit 33 of SDMA1" "0,1"
newline
bitfld.long 0x00 27. "GPR_SDMA1_M_D_3_AWADDR32,AXI write address bit 32 of SDMA1" "0,1"
newline
bitfld.long 0x00 26. "GPR_SDMA1_M_D_3_AWADDR33,AXI write address bit 33 of SDMA1" "0,1"
group.long 0x58++0x03
line.long 0x00 "GPR22,General Purpose Register 22"
rbitfld.long 0x00 16. "SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL,SJC challenge response authentication fail" "0,1"
newline
bitfld.long 0x00 3. "GPR_M7_HCLK_GATE_EN,gate off cm7 hclk" "0: GPR_M7_HCLK_GATE_EN_0,1: GPR_M7_HCLK_GATE_EN_1"
newline
bitfld.long 0x00 2. "GPR_M7_HCLK_AUTO_GATE_EN,gate cm7 hclk automatically" "0: depends on the value of GPR_M7_HCLK_GATE_EN,1: ignore the value of GPR_M7_HCLK_GATE_EN"
newline
bitfld.long 0x00 0. "GPR_M7_CPUWAIT,m7 in wait mode" "0: do not let CM7 enter wait mode,1: let CM7 enter wait mode"
rgroup.long 0x5C++0x03
line.long 0x00 "GPR23,General Purpose Register 23"
rgroup.long 0x60++0x03
line.long 0x00 "GPR24,General Purpose Register 24"
hexmask.long.byte 0x00 16.--23. 1. "GPR_MLMIX_DEBUG_OUT,debug out for mlmix"
newline
hexmask.long.byte 0x00 8.--15. 1. "GPR_GPU3D_DEBUG_OUT,debug out for gpu3d"
newline
hexmask.long.byte 0x00 0.--7. 1. "GPR_GPU2D_DEBUG_OUT,debug out for gpu2d"
tree.end
tree "IRQSTEER"
tree "IRQ_STEER_AUDIO_PROCESSOR"
base ad:0x30A80000
repeat 5. (increment 0 1) (increment 0 0x4)
group.long ($2+0x04)++0x03
line.long 0x00 "CHn_MASK[$1],Channel n Interrupt Mask Register $1"
hexmask.long 0x00 0.--31. 1. "MASKFLD,Mask bits"
repeat.end
repeat 5. (increment 0 1) (increment 0 0x4)
group.long ($2+0x18)++0x03
line.long 0x00 "CHn_SET[$1],Channel n Interrupt Set Register $1"
hexmask.long 0x00 0.--31. 1. "FORCEFLD,Force interrupt"
repeat.end
repeat 5. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x2C)++0x03
line.long 0x00 "CHn_STATUS[$1],Channel n Interrupt Status Register $1"
hexmask.long 0x00 0.--31. 1. "STATUS,Status of an interrupt"
repeat.end
group.long 0x40++0x03
line.long 0x00 "CHn_MINTDIS,Channel n Master Interrupt Disable Register"
bitfld.long 0x00 0.--2. "DISABLE,Each bit of this field disables the corresponding interrupts in table above" "0: Enable interrupts,1: Disable interrupts,?..."
rgroup.long 0x44++0x03
line.long 0x00 "CHn_MSTRSTAT,Channel n Master Status Register"
bitfld.long 0x00 0. "STATUS,Status of all interrupts" "0: No interrupts are asserted,1: At least one interrupt is asserted"
tree.end
tree "IRQ_STEER_HDMI"
base ad:0x32FC2000
repeat 5. (increment 0 1) (increment 0 0x4)
group.long ($2+0x04)++0x03
line.long 0x00 "CHn_MASK[$1],Channel n Interrupt Mask Register $1"
hexmask.long 0x00 0.--31. 1. "MASKFLD,Mask bits"
repeat.end
repeat 5. (increment 0 1) (increment 0 0x4)
group.long ($2+0x18)++0x03
line.long 0x00 "CHn_SET[$1],Channel n Interrupt Set Register $1"
hexmask.long 0x00 0.--31. 1. "FORCEFLD,Force interrupt"
repeat.end
repeat 5. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x2C)++0x03
line.long 0x00 "CHn_STATUS[$1],Channel n Interrupt Status Register $1"
hexmask.long 0x00 0.--31. 1. "STATUS,Status of an interrupt"
repeat.end
group.long 0x40++0x03
line.long 0x00 "CHn_MINTDIS,Channel n Master Interrupt Disable Register"
bitfld.long 0x00 0.--2. "DISABLE,Each bit of this field disables the corresponding interrupts in table above" "0: Enable interrupts,1: Disable interrupts,?..."
rgroup.long 0x44++0x03
line.long 0x00 "CHn_MSTRSTAT,Channel n Master Status Register"
bitfld.long 0x00 0. "STATUS,Status of all interrupts" "0: No interrupts are asserted,1: At least one interrupt is asserted"
tree.end
tree.end
tree "ISI (ISI Memory Map)"
base ad:0x32E00000
group.long 0x00++0x03
line.long 0x00 "CHNL_CTRL,Channel Control Register"
bitfld.long 0x00 31. "CHNL_EN,Enable channel processing" "0: Processing channel is disabled,1: Processing channel is enabled"
bitfld.long 0x00 30. "CLK_EN,Channel clock enable" "0: Channel processing clock is disabled,1: Channel processing clock is enabled"
newline
bitfld.long 0x00 29. "CHNL_BYPASS,Channel bypass enable" "0: Channel is not bypassed,1: Channel is bypassed"
bitfld.long 0x00 25.--26. "CHAIN_BUF,Chain line buffer control" "0: No line buffers chained (supports 2048 or..,1: 2 line buffers chained (supports 4096..,2: 4 line buffers chained (supports 8192..,?..."
newline
bitfld.long 0x00 24. "SW_RST,Software reset bit" "0: SW_RST_0,1: Channel pipeline is under software reset"
bitfld.long 0x00 8.--10. "SEC_LB_SRC,Secondary line buffer source" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SRC_TYPE,Type of selected input image source" "0: Image input source is Pixel Link,1: Image input source is Memory"
bitfld.long 0x00 0. "SRC,Input image source port selection" "0: Image will be sourced from input port 0 of..,1: Image will be sourced from input port 1 of.."
group.long 0x04++0x03
line.long 0x00 "CHNL_IMG_CTRL,Channel Image Control Register"
bitfld.long 0x00 24.--29. "FORMAT,Output image format" "0: FORMAT_0,1: FORMAT_1,2: FORMAT_2,3: FORMAT_3,4: FORMAT_4,5: FORMAT_5,6: FORMAT_6,7: FORMAT_7,8: FORMAT_8,9: FORMAT_9,10: FORMAT_10,11: FORMAT_11,12: FORMAT_12,13: FORMAT_13,14: FORMAT_14,15: FORMAT_15,16: FORMAT_16,17: FORMAT_17,18: FORMAT_18,19: FORMAT_19,20: FORMAT_20,21: FORMAT_21,22: FORMAT_22,?,24: FORMAT_24,25: FORMAT_25,26: FORMAT_26,?,28: FORMAT_28,29: FORMAT_29,30: FORMAT_30,?,32: FORMAT_32,33: FORMAT_33,34: FORMAT_34,?,36: FORMAT_36,37: FORMAT_37,38: FORMAT_38,?,40: FORMAT_40,41: FORMAT_41,42: FORMAT_42,?,44: FORMAT_44,45: FORMAT_45,46: FORMAT_46,?,?,49: FORMAT_49,50: FORMAT_50,?,?,53: FORMAT_53,54: FORMAT_54,?,?,57: FORMAT_57,58: FORMAT_58,?,?,61: FORMAT_61,62: FORMAT_62,?..."
hexmask.long.byte 0x00 16.--23. 1. "GBL_ALPHA_VAL,Global alpha value"
newline
bitfld.long 0x00 15. "GBL_ALPHA_EN,Global alpha value insertion enable" "0: Global Alpha value insertion is disabled,1: Global Alpha value insertion is enabled"
bitfld.long 0x00 12.--14. "DEINT,De-interlace control" "0: No de-interlacing done,1: No de-interlacing done,2: Weave de-interlacing (Odd Even) method used,3: Weave de-interlacing (Even Odd) method used,4: Blending or linear interpolation (Odd + Even)..,5: Blending or linear interpolation (Even + Odd)..,6: Line doubling de-interlacing method used,7: Line doubling de-interlacing method used"
newline
bitfld.long 0x00 10.--11. "DEC_X,Horizontal pre-decimation control" "0: Pre-decimation filter is disabled,1: Decimate by 2,2: Decimate by 4,3: Decimate by 8"
bitfld.long 0x00 8.--9. "DEC_Y,Vertical pre-decimation control" "0: Pre-decimation filter is disabled,1: Decimate by 2,2: Decimate by 4,3: Decimate by 8"
newline
bitfld.long 0x00 7. "CROP_EN,Output image cropping enable" "0: Image cropping is disabled,1: Image cropping is enabled"
bitfld.long 0x00 6. "VFLIP_EN,Veritical flip control" "0: Vertical image flip disabled,1: Vertical image flip enabled"
newline
bitfld.long 0x00 5. "HFLIP_EN,Horizontal flip control" "0: Horizantal image flip disabled,1: Horizontal image flip enabled"
bitfld.long 0x00 3. "YCBCR_MODE,YCbCr Mode" "0: YCbCr mode is disabled,1: YCbCr mode is enabled"
newline
bitfld.long 0x00 1.--2. "CSC_MODE,Color Space Conversion operating mode" "0: Convert from YUV to RGB,1: Convert from YCbCr to RGB,2: Convert from RGB to YUV,3: Convert from RGB to YCbCr"
bitfld.long 0x00 0. "CSC_BYP,Color Space Conversion bypass control" "0: CSC is operational,1: CSC is bypassed"
group.long 0x08++0x03
line.long 0x00 "CHNL_OUT_BUF_CTRL,Channel Output Buffer Control Register"
bitfld.long 0x00 31. "MAX_WR_BEATS_Y,Maximum AXI write beats for Y-buffer" "0: Maximum write beats per write request are 8..,1: Maximum write beats per write request are 16.."
bitfld.long 0x00 30. "MAX_WR_BEATS_UV,Maximum AXI write beats for U and V-buffers" "0: Maximum write beats per write request are 8..,1: Maximum write beats per write request are 16.."
newline
bitfld.long 0x00 16.--19. "PANIC_SET_THD_V,Overflow panic set threshold value for V output buffer" "0: No panic alert will be asserted,1: Panic will assert when buffer is n * 6.25%..,2: Panic will assert when buffer is n * 6.25%..,3: Panic will assert when buffer is n * 6.25%..,4: Panic will assert when buffer is n * 6.25%..,5: Panic will assert when buffer is n * 6.25%..,6: Panic will assert when buffer is n * 6.25%..,7: Panic will assert when buffer is n * 6.25%..,8: Panic will assert when buffer is n * 6.25%..,9: Panic will assert when buffer is n * 6.25%..,?..."
bitfld.long 0x00 15. "LOAD_BUF2_ADDR,Load Buffer 2 Address from CHNLOUT_BUF2_ADDR_* registers" "0,1"
newline
bitfld.long 0x00 14. "LOAD_BUF1_ADDR,Load Buffer 1 Address from CHNLOUT_BUF1_ADDR_* registers" "0,1"
bitfld.long 0x00 8.--11. "PANIC_SET_THD_U,Overflow panic set threshold value for U output buffer" "0: No panic alert will be asserted,1: Panic will assert when buffer is n * 6.25%..,2: Panic will assert when buffer is n * 6.25%..,3: Panic will assert when buffer is n * 6.25%..,4: Panic will assert when buffer is n * 6.25%..,5: Panic will assert when buffer is n * 6.25%..,6: Panic will assert when buffer is n * 6.25%..,7: Panic will assert when buffer is n * 6.25%..,8: Panic will assert when buffer is n * 6.25%..,9: Panic will assert when buffer is n * 6.25%..,?..."
newline
bitfld.long 0x00 0.--3. "PANIC_SET_THD_Y,Overflow panic set threshold value for Y/RGB output buffer" "0: No panic alert will be asserted,1: Panic will assert when buffer is n * 6.25%..,2: Panic will assert when buffer is n * 6.25%..,3: Panic will assert when buffer is n * 6.25%..,4: Panic will assert when buffer is n * 6.25%..,5: Panic will assert when buffer is n * 6.25%..,6: Panic will assert when buffer is n * 6.25%..,7: Panic will assert when buffer is n * 6.25%..,8: Panic will assert when buffer is n * 6.25%..,9: Panic will assert when buffer is n * 6.25%..,?..."
group.long 0x0C++0x03
line.long 0x00 "CHNL_IMG_CFG,Channel Image Configuration"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,Input image height (lines)"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,Input image width (pixels)"
group.long 0x10++0x03
line.long 0x00 "CHNL_IER,Channel Interrupt Enable Register"
bitfld.long 0x00 31. "MEM_RD_DONE_EN,Memory read complete interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 30. "LINE_RCVD_EN,Line received interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
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bitfld.long 0x00 29. "FRM_RCVD_EN,Frame received interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 28. "AXI_WR_ERR_V_EN,AXI bus read error interrupt enable bit for V data buffer" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 27. "AXI_WR_ERR_U_EN,AXI bus read error interrupt enable bit for U data buffer" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 26. "AXI_WR_ERR_Y_EN,AXI bus read error interrupt enable bit for Y/RGB data buffer" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 25. "AXI_RD_ERR_EN,AXI bus read error interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 23. "PANIC_V_BUF_EN,V output buffer potential overflow panic interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 22. "OFLW_V_BUF_EN,V output buffer overflow interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 21. "PANIC_U_BUF_EN,U output buffer potential overflow panic interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 20. "OFLW_U_BUF_EN,U output buffer overflow interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 19. "PANIC_Y_BUF_EN,Y output buffer potential overflow panic interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 18. "OFLW_Y_BUF_EN,Y output buffer overflow interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 17. "EARLY_VSYNC_ERR_EN,VSYNC timing (Early) error interrupt enable bit" "0: Interrupt is disabled,1: EARLY_VSYNC_ERR_EN_1"
newline
bitfld.long 0x00 16. "LATE_VSYNC_ERR_EN,VSYNC timing (Late) error interrupt enable bit" "0: Interrupt is disabled,1: Interrupt is enabled"
group.long 0x14++0x03
line.long 0x00 "CHNL_STS,Channel Status Register"
eventfld.long 0x00 31. "MEM_RD_DONE,Memory read complete interrupt flag" "0: Image read from memory not complete or not..,1: Image read from memory completed"
eventfld.long 0x00 30. "LINE_STRD,Line received and stored interrupt flag" "0: No new line received,1: New line received and stored into memory"
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eventfld.long 0x00 29. "FRM_STRD,Frame stored successfully interrupt flag" "0: No frame being received or in progress,1: One full frame has been received and stored.."
eventfld.long 0x00 28. "AXI_WR_ERR_V,AXI Bus write error interrupt flag for V data buffer" "0: AXI_WR_ERR_V_0,1: Error occured during"
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eventfld.long 0x00 27. "AXI_WR_ERR_U,AXI Bus write error interrupt flag for U data buffer" "0: AXI_WR_ERR_U_0,1: Error occured during"
eventfld.long 0x00 26. "AXI_WR_ERR_Y,AXI Bus write error interrupt flag for Y/RGB data buffer" "0: AXI_WR_ERR_Y_0,1: Error occured during"
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eventfld.long 0x00 25. "AXI_RD_ERR,AXI Bus read error interrupt flag" "0: AXI_RD_ERR_0,1: Error occured during"
eventfld.long 0x00 23. "PANIC_V_BUF,V output buffer potential overflow panic alert interrupt flag" "0: Buffer has not crossed the panic threshold..,1: Panic threshold limit crossed"
newline
eventfld.long 0x00 22. "OFLW_V_BUF,Overflow in U output buffer interrupt flag" "0: OFLW_V_BUF_0,1: Overflow has occured in the channel"
eventfld.long 0x00 21. "PANIC_U_BUF,U output buffer potential overflow panic alert interrupt flag" "0: Buffer has not crossed the panic threshold..,1: Panic threshold limit crossed"
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eventfld.long 0x00 20. "OFLW_U_BUF,Overflow in U output buffer interrupt flag" "0: OFLW_U_BUF_0,1: Overflow has occured in the channel"
eventfld.long 0x00 19. "PANIC_Y_BUF,Y/RGB output buffer potential overflow panic alert interrupt flag" "0: Buffer has not crossed the panic threshold..,1: Panic threshold limit crossed"
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eventfld.long 0x00 18. "OFLW_Y_BUF,Overflow in Y/RGB output buffer interrupt flag" "0: OFLW_Y_BUF_0,1: Overflow has occured in the channel"
eventfld.long 0x00 17. "EARLY_VSYNC_ERR,VSYNC timing (Early) error interrupt flag" "0: EARLY_VSYNC_ERR_0,1: VSYNC detected earlier than expected"
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eventfld.long 0x00 16. "LATE_VSYNC_ERR,VSYNC timing (Late) error interrupt flag" "0: LATE_VSYNC_ERR_0,1: VSYNC detected later than expected"
rbitfld.long 0x00 10. "MEM_RD_OFLOW,Memory read FIFO overflow error status" "0: No overflow occurred during memory,1: FIFO overflow occurred during memory"
newline
rbitfld.long 0x00 9. "BUF2_ACTIVE,Current frame being stored in Buffer 2 Address" "0: Buffer 2 Address inactive,1: Buffer 2 Address in use"
rbitfld.long 0x00 8. "BUF1_ACTIVE,Current frame being stored in Buffer 1 Address" "0: Buffer 1 Address inactive,1: Buffer 1 Address in use"
group.long 0x18++0x03
line.long 0x00 "CHNL_SCALE_FACTOR,Channel Scale Factor Register"
hexmask.long.word 0x00 16.--29. 1. "Y_SCALE,Vertical scaling factor"
hexmask.long.word 0x00 0.--13. 1. "X_SCALE,Horizontal scaling factor"
group.long 0x1C++0x03
line.long 0x00 "CHNL_SCALE_OFFSET,Channel Scale Offset Register"
hexmask.long.word 0x00 16.--27. 1. "Y_OFFSET,Vertical scaling offset"
hexmask.long.word 0x00 0.--11. 1. "X_OFFSET,Horizontal scaling offset"
group.long 0x20++0x03
line.long 0x00 "CHNL_CROP_ULC,Channel Crop Upper Left Corner Coordinate Register"
hexmask.long.word 0x00 16.--27. 1. "X,Upper Left X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Upper Left Y-coordinate"
group.long 0x24++0x03
line.long 0x00 "CHNL_CROP_LRC,Channel Crop Lower Right Corner Coordinate Register"
hexmask.long.word 0x00 16.--27. 1. "X,Lower Right X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Lower Right Y-coordinate"
group.long 0x28++0x03
line.long 0x00 "CHNL_CSC_COEFF0,Channel Color Space Conversion Coefficient Register 0"
hexmask.long.word 0x00 16.--26. 1. "A2,CSC Coefficient A2 value"
hexmask.long.word 0x00 0.--10. 1. "A1,CSC Coefficient A1 value"
group.long 0x2C++0x03
line.long 0x00 "CHNL_CSC_COEFF1,Channel Color Space Conversion Coefficient Register 1"
hexmask.long.word 0x00 16.--26. 1. "B1,CSC Coefficient B1 value"
hexmask.long.word 0x00 0.--10. 1. "A3,CSC Coefficient A3 value"
group.long 0x30++0x03
line.long 0x00 "CHNL_CSC_COEFF2,Channel Color Space Conversion Coefficient Register 2"
hexmask.long.word 0x00 16.--26. 1. "B3,CSC Coefficient B3 value"
hexmask.long.word 0x00 0.--10. 1. "B2,CSC Coefficient B2 value"
group.long 0x34++0x03
line.long 0x00 "CHNL_CSC_COEFF3,Channel Color Space Conversion Coefficient Register 3"
hexmask.long.word 0x00 16.--26. 1. "C2,CSC Coefficient C2 value"
hexmask.long.word 0x00 0.--10. 1. "C1,CSC Coefficient C1 value"
group.long 0x38++0x03
line.long 0x00 "CHNL_CSC_COEFF4,Channel Color Space Conversion Coefficient Register 4"
hexmask.long.word 0x00 16.--24. 1. "D1,CSC Coefficient D1 value"
hexmask.long.word 0x00 0.--10. 1. "C3,CSC Coefficient C3 value"
group.long 0x3C++0x03
line.long 0x00 "CHNL_CSC_COEFF5,Channel Color Space Conversion Coefficient Register 5"
hexmask.long.word 0x00 16.--24. 1. "D3,CSC Coefficient D3 value"
hexmask.long.word 0x00 0.--8. 1. "D2,CSC Coefficient D2 value"
group.long 0x40++0x03
line.long 0x00 "CHNL_ROI_0_ALPHA,Channel Alpha Value Register for Region of Interest 0"
hexmask.long.byte 0x00 24.--31. 1. "ALPHA,Alpha Value to be inserted with image"
bitfld.long 0x00 16. "ALPHA_EN,Alpha value insertion enable" "0: Alpha value insertion is disabled,1: Alpha value insertion is enabled"
group.long 0x44++0x03
line.long 0x00 "CHNL_ROI_0_ULC,Channel Upper Left Coordinate Register for Region of Interest 0"
hexmask.long.word 0x00 16.--27. 1. "X,Upper Left X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Upper Left Y-coordinate"
group.long 0x48++0x03
line.long 0x00 "CHNL_ROI_0_LRC,Channel Lower Right Coordinate Register for Region of Interest 0"
hexmask.long.word 0x00 16.--27. 1. "X,Lower Right X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Lower Right Y-coordinate"
group.long 0x4C++0x03
line.long 0x00 "CHNL_ROI_1_ALPHA,Channel Alpha Value Register for Region of Interest 1"
hexmask.long.byte 0x00 24.--31. 1. "ALPHA,Alpha Value to be inserted with image"
bitfld.long 0x00 16. "ALPHA_EN,Alpha value insertion enable" "0: Alpha value insertion is disabled,1: Alpha value insertion is enabled"
group.long 0x50++0x03
line.long 0x00 "CHNL_ROI_1_ULC,Channel Upper Left Coordinate Register for Region of Interest 1"
hexmask.long.word 0x00 16.--27. 1. "X,Upper Left X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Upper Left Y-coordinate"
group.long 0x54++0x03
line.long 0x00 "CHNL_ROI_1_LRC,Channel Lower Right Coordinate Register for Region of Interest 1"
hexmask.long.word 0x00 16.--27. 1. "X,Lower Right X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Lower Right Y-coordinate"
group.long 0x58++0x03
line.long 0x00 "CHNL_ROI_2_ALPHA,Channel Alpha Value Register for Region of Interest 2"
hexmask.long.byte 0x00 24.--31. 1. "ALPHA,Alpha Value to be inserted with image"
bitfld.long 0x00 16. "ALPHA_EN,Alpha value insertion enable" "0: Alpha value insertion is disabled,1: Alpha value insertion is enabled"
group.long 0x5C++0x03
line.long 0x00 "CHNL_ROI_2_ULC,Channel Upper Left Coordinate Register for Region of Interest 2"
hexmask.long.word 0x00 16.--27. 1. "X,Upper Left X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Upper Left Y-coordinate"
group.long 0x60++0x03
line.long 0x00 "CHNL_ROI_2_LRC,Channel Lower Right Coordinate Register for Region of Interest 2"
hexmask.long.word 0x00 16.--27. 1. "X,Lower Right X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Lower Right Y-coordinate"
group.long 0x64++0x03
line.long 0x00 "CHNL_ROI_3_ALPHA,Channel Alpha Value Register for Region of Interest 3"
hexmask.long.byte 0x00 24.--31. 1. "ALPHA,Alpha Value to be inserted with image"
bitfld.long 0x00 16. "ALPHA_EN,Alpha value insertion enable" "0: Alpha value insertion is disabled,1: Alpha value insertion is enabled"
group.long 0x68++0x03
line.long 0x00 "CHNL_ROI_3_ULC,Channel Upper Left Coordinate Register for Region of Interest 3"
hexmask.long.word 0x00 16.--27. 1. "X,Upper Left X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Upper Left Y-coordinate"
group.long 0x6C++0x03
line.long 0x00 "CHNL_ROI_3_LRC,Channel Lower Right Coordinate Register for Region of Interest 3"
hexmask.long.word 0x00 16.--27. 1. "X,Lower Right X-coordinate"
hexmask.long.word 0x00 0.--11. 1. "Y,Lower Right Y-coordinate"
group.long 0x70++0x03
line.long 0x00 "CHNL_OUT_BUF1_ADDR_Y,Channel RGB or Luma (Y) Output Buffer 1 Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Starting address for the RGB or Y (luma) memory location"
group.long 0x74++0x03
line.long 0x00 "CHNL_OUT_BUF1_ADDR_U,Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location"
group.long 0x78++0x03
line.long 0x00 "CHNL_OUT_BUF1_ADDR_V,Channel Chroma (V/Cr) Output Buffer 1 Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Starting address for the V/Cr memory location"
group.long 0x7C++0x03
line.long 0x00 "CHNL_OUT_BUF_PITCH,Channel Output Buffer Pitch"
hexmask.long.word 0x00 0.--15. 1. "LINE_PITCH,Output Buffer Line Pitch"
group.long 0x80++0x03
line.long 0x00 "CHNL_IN_BUF_ADDR,Channel Input Buffer Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Starting Address from where the input image is read in from"
group.long 0x84++0x03
line.long 0x00 "CHNL_IN_BUF_PITCH,Channel Input Buffer Pitch"
hexmask.long.word 0x00 16.--31. 1. "FRM_PITCH,Frame Pitch"
hexmask.long.word 0x00 0.--15. 1. "LINE_PITCH,Line Pitch"
group.long 0x88++0x03
line.long 0x00 "CHNL_MEM_RD_CTRL,Channel Memory Read Control"
bitfld.long 0x00 28.--31. "IMG_TYPE,Input image format" "0: BGR8P - BGR format with 8-bits per color..,1: RGB8P - RGB format with 8-bits per color..,2: XRGB8 - RGB format with 8-bits per color..,3: RGBX8 - RGB format with 8-bits per color..,4: XBGR8 - BGR format with 8-bits per color..,5: RGB565 - RGB format with 5-bits of R B 6-bits..,6: A2BGR10 - BGR format with 2-bits alpha in MSB..,7: A2RGB10 - RGB format with 2-bits alpha in MSB..,8: YUV444_1P8P with 8-bits per color component..,9: YUV444_1P10 with 10-bits per color component..,10: YUV444_1P10P with 10-bits per color..,11: YUV444_1P12 with 12-bits per color component..,12: YUV444_1P8 with 8-bits per color component..,13: YUV422_1P8P with 8-bits per color component..,14: YUV422_1P10 with 10-bits per color component..,15: YUV422_1P12 with 12-bits per color component.."
bitfld.long 0x00 0. "READ_MEM,Initiate read from memory" "0: No reads from memory done,1: Reads from memory initiated"
group.long 0x8C++0x03
line.long 0x00 "CHNL_OUT_BUF2_ADDR_Y,Channel RGB or Luma (Y) Output Buffer 2 Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Starting address for the RGB or Y (luma) memory location"
group.long 0x90++0x03
line.long 0x00 "CHNL_OUT_BUF2_ADDR_U,Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location"
group.long 0x94++0x03
line.long 0x00 "CHNL_OUT_BUF2_ADDR_V,Channel Chroma (V/Cr) Output Buffer 2 Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Starting address for the V/Cr memory location"
group.long 0x98++0x03
line.long 0x00 "CHNL_SCL_IMG_CFG,Channel Scaled Image Configuration"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,Scaled image height (lines)"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,Scaled image width (pixels)"
group.long 0x9C++0x03
line.long 0x00 "CHNL_FLOW_CTRL,Channel Flow Control Register"
hexmask.long.byte 0x00 16.--23. 1. "FC_NUMER,Numertor value of fraction of usable bandwidth"
hexmask.long.byte 0x00 0.--7. 1. "FC_DENOM,Denominator value of fraction of usable bandwidth"
group.long 0xA0++0x03
line.long 0x00 "CHNL_Y_BUF1_XTND_ADDR,Channel Output Y-Buffer 1 Extended Address Bits Register"
bitfld.long 0x00 0.--3. "Y1ADDR_MSB,Extended Address Most Significant Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA4++0x03
line.long 0x00 "CHNL_U_BUF1_XTND_ADDR,Channel Output U-Buffer 1 Extended Address Bits Register"
bitfld.long 0x00 0.--3. "U1ADDR_MSB,Extended Address Most Significant Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA8++0x03
line.long 0x00 "CHNL_V_BUF1_XTND_ADDR,Channel Output V-Buffer 1 Extended Address Bits Register"
bitfld.long 0x00 0.--3. "V1ADDR_MSB,Extended Address Most Significant Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC++0x03
line.long 0x00 "CHNL_Y_BUF2_XTND_ADDR,Channel Output Y-Buffer 2 Extended Address Bits Register"
bitfld.long 0x00 0.--3. "Y2ADDR_MSB,Extended Address Most Significant Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x03
line.long 0x00 "CHNL_U_BUF2_XTND_ADDR,Channel Output U-Buffer 2 Extended Address Bits Register"
bitfld.long 0x00 0.--3. "U2ADDR_MSB,Extended Address Most Significant Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB4++0x03
line.long 0x00 "CHNL_V_BUF2_XTND_ADDR,Channel Output V-Buffer 2 Extended Address Bits Register"
bitfld.long 0x00 0.--3. "V2ADDR_MSB,Extended Address Most Significant Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB8++0x03
line.long 0x00 "CHNL_IN_BUF_XTND_ADDR,Channel Input Buffer Extended Address Bits Register"
bitfld.long 0x00 0.--3. "XADDR_MSB,Extended Address Most Significant Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "LCDIF (LCD Interface)"
repeat 3. (list 1. 2. 3.) (list ad:0x32E80000 ad:0x32E90000 ad:0x32FC6000)
tree "LCDIF$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTRL,LCDIF display control Register"
bitfld.long 0x00 31. "SW_RESET,SW_RESET" "0: SW_RESET_0,1: All LCDIF internal registers are forced into.."
bitfld.long 0x00 8.--9. "fetch_start_option,Indicates when to start fetching for new frame" "0: fetch start as soon as FPV begins(as the end..,1: fetch start as soon as PWV begins,2: fetch start as soon as BPV begins,3: fetch start as soon as RESV begins(still have.."
newline
bitfld.long 0x00 4. "NEG,Indicates if value at the output (pixel data output) needs to be negated" "0: Output is to remain same,1: Output to be negated"
bitfld.long 0x00 3. "INV_PXCK,Polarity change of Pixel Clock" "0: Display samples data on the falling edge,1: Display samples data on the rising edge"
newline
bitfld.long 0x00 2. "INV_DE,Invert Data Enable polarity" "0: Data enable is active high,1: Data enable is active low"
bitfld.long 0x00 1. "INV_VS,Invert Vertical synchronization signal" "0: VSYNC signal not inverted (active HIGH),1: Invert VSYNC signal (active LOW)"
newline
bitfld.long 0x00 0. "INV_HS,Invert Horizontal synchronization signal" "0: HSYNC signal not inverted (active HIGH),1: Invert HSYNC signal (active LOW)"
group.long 0x04++0x03
line.long 0x00 "CTRL_SET,LCDIF display control Register"
bitfld.long 0x00 31. "SW_RESET,SW_RESET" "0: SW_RESET_0,1: All LCDIF internal registers are forced into.."
bitfld.long 0x00 8.--9. "fetch_start_option,Indicates when to start fetching for new frame" "0: fetch start as soon as FPV begins(as the end..,1: fetch start as soon as PWV begins,2: fetch start as soon as BPV begins,3: fetch start as soon as RESV begins(still have.."
newline
bitfld.long 0x00 4. "NEG,Indicates if value at the output (pixel data output) needs to be negated" "0: Output is to remain same,1: Output to be negated"
bitfld.long 0x00 3. "INV_PXCK,Polarity change of Pixel Clock" "0: Display samples data on the falling edge,1: Display samples data on the rising edge"
newline
bitfld.long 0x00 2. "INV_DE,Invert Data Enable polarity" "0: Data enable is active high,1: Data enable is active low"
bitfld.long 0x00 1. "INV_VS,Invert Vertical synchronization signal" "0: VSYNC signal not inverted (active HIGH),1: Invert VSYNC signal (active LOW)"
newline
bitfld.long 0x00 0. "INV_HS,Invert Horizontal synchronization signal" "0: HSYNC signal not inverted (active HIGH),1: Invert HSYNC signal (active LOW)"
group.long 0x08++0x03
line.long 0x00 "CTRL_CLR,LCDIF display control Register"
bitfld.long 0x00 31. "SW_RESET,SW_RESET" "0: SW_RESET_0,1: All LCDIF internal registers are forced into.."
bitfld.long 0x00 8.--9. "fetch_start_option,Indicates when to start fetching for new frame" "0: fetch start as soon as FPV begins(as the end..,1: fetch start as soon as PWV begins,2: fetch start as soon as BPV begins,3: fetch start as soon as RESV begins(still have.."
newline
bitfld.long 0x00 4. "NEG,Indicates if value at the output (pixel data output) needs to be negated" "0: Output is to remain same,1: Output to be negated"
bitfld.long 0x00 3. "INV_PXCK,Polarity change of Pixel Clock" "0: Display samples data on the falling edge,1: Display samples data on the rising edge"
newline
bitfld.long 0x00 2. "INV_DE,Invert Data Enable polarity" "0: Data enable is active high,1: Data enable is active low"
bitfld.long 0x00 1. "INV_VS,Invert Vertical synchronization signal" "0: VSYNC signal not inverted (active HIGH),1: Invert VSYNC signal (active LOW)"
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bitfld.long 0x00 0. "INV_HS,Invert Horizontal synchronization signal" "0: HSYNC signal not inverted (active HIGH),1: Invert HSYNC signal (active LOW)"
group.long 0x0C++0x03
line.long 0x00 "CTRL_TOG,LCDIF display control Register"
bitfld.long 0x00 31. "SW_RESET,SW_RESET" "0: SW_RESET_0,1: All LCDIF internal registers are forced into.."
bitfld.long 0x00 8.--9. "fetch_start_option,Indicates when to start fetching for new frame" "0: fetch start as soon as FPV begins(as the end..,1: fetch start as soon as PWV begins,2: fetch start as soon as BPV begins,3: fetch start as soon as RESV begins(still have.."
newline
bitfld.long 0x00 4. "NEG,Indicates if value at the output (pixel data output) needs to be negated" "0: Output is to remain same,1: Output to be negated"
bitfld.long 0x00 3. "INV_PXCK,Polarity change of Pixel Clock" "0: Display samples data on the falling edge,1: Display samples data on the rising edge"
newline
bitfld.long 0x00 2. "INV_DE,Invert Data Enable polarity" "0: Data enable is active high,1: Data enable is active low"
bitfld.long 0x00 1. "INV_VS,Invert Vertical synchronization signal" "0: VSYNC signal not inverted (active HIGH),1: Invert VSYNC signal (active LOW)"
newline
bitfld.long 0x00 0. "INV_HS,Invert Horizontal synchronization signal" "0: HSYNC signal not inverted (active HIGH),1: Invert HSYNC signal (active LOW)"
group.long 0x10++0x03
line.long 0x00 "DISP_PARA,Display Parameter Register"
bitfld.long 0x00 31. "DISP_ON,Display panel On/Off mode" "0: Display Off,1: Display On"
bitfld.long 0x00 30. "SWAP_EN,output data swap enable" "0: swap disable,1: swap enbale output data will swap the high.."
newline
bitfld.long 0x00 26.--29. "LINE_PATTERN,LCDIF line output order" "0: LINE_PATTERN_0,1: LINE_PATTERN_1,2: LINE_PATTERN_2,3: LINE_PATTERN_3,4: LINE_PATTERN_4,5: LINE_PATTERN_5,6: LINE_PATTERN_6,7: LINE_PATTERN_7,8: YUYV at [16:0],9: UYVY at [16:0],10: LINE_PATTERN_10,11: LINE_PATTERN_11,12: LINE_PATTERN_12,13: LINE_PATTERN_13,14: LINE_PATTERN_14,15: LINE_PATTERN_15"
bitfld.long 0x00 24.--25. "DISP_MODE,LCDIF operating mode" "0: Normal mode,1: Test Mode1.(BGND Color Display),2: Test Mode2.(Column Color Bar),3: Test Mode3.(Row Color Bar)"
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hexmask.long.byte 0x00 16.--23. 1. "BGND_R,Red component of the default color displayed in the sectors where no layer is active"
hexmask.long.byte 0x00 8.--15. 1. "BGND_G,Green component of the default color displayed in the sectors where no layer is active"
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hexmask.long.byte 0x00 0.--7. 1. "BGND_B,Blue component of the default color displayed in the sectors where no layer is active"
group.long 0x14++0x03
line.long 0x00 "DISP_SIZE,Display Size Register"
hexmask.long.word 0x00 16.--31. 1. "DELTA_Y,Sets the display size vertical resolution in pixels"
hexmask.long.word 0x00 0.--15. 1. "DELTA_X,Sets the display size horizontal resolution in pixels"
group.long 0x18++0x03
line.long 0x00 "HSYN_PARA,Horizontal Sync Parameter Register"
hexmask.long.word 0x00 16.--31. 1. "BP_H,HSYNC back-porch pulse width (in pixel clock cycles)"
hexmask.long.word 0x00 0.--15. 1. "FP_H,HSYNC front-porch pulse width (in pixel clock cycles)"
group.long 0x1C++0x03
line.long 0x00 "VSYN_PARA,Vertical Sync Parameter Register"
hexmask.long.word 0x00 16.--31. 1. "BP_V,VSYNC back-porch pulse width (in horizontal line cycles)"
hexmask.long.word 0x00 0.--15. 1. "FP_V,VSYNC front-porch pulse width (in horizontal line cycles)"
group.long 0x20++0x03
line.long 0x00 "VSYN_HSYN_WIDTH,Vertical and Horizontal Pulse Width Parameter Register"
hexmask.long.word 0x00 16.--31. 1. "PW_V,VSYNC active pulse width (in horizontal line cycles)"
hexmask.long.word 0x00 0.--15. 1. "PW_H,HSYNC active pulse width (in pixel clock cycles)"
group.long 0x24++0x03
line.long 0x00 "INT_STATUS_D0,Interrupt Status Register for domain 0"
eventfld.long 0x00 24. "FIFO_EMPTY,Interrupt flag to indicate that which FIFO in the pixel blending underflowed" "0,1"
eventfld.long 0x00 16. "DMA_DONE,Interrupt flag to indicate that which PLANE has fetched the last pixel from memory" "0,1"
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eventfld.long 0x00 8. "DMA_ERR,Interrupt flag to indicate that which PLANE has Read Error on the AXI interface" "0,1"
eventfld.long 0x00 2. "VS_BLANK,Interrupt flag to indicate vertical blanking period" "0,1"
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eventfld.long 0x00 1. "UNDERRUN,Interrupt flag to indicate the output buffer underrun condition" "0,1"
eventfld.long 0x00 0. "VSYNC,Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)" "0,1"
group.long 0x28++0x03
line.long 0x00 "INT_ENABLE_D0,Interrupt Enable Register for domain 0"
bitfld.long 0x00 24. "FIFO_EMPTY_EN,Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed" "0,1"
bitfld.long 0x00 16. "DMA_DONE_EN,Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory" "0,1"
newline
bitfld.long 0x00 8. "DMA_ERR_EN,Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface" "0,1"
bitfld.long 0x00 2. "VS_BLANK_EN,Enable Interrupt flag to indicate vertical blanking period" "0,1"
newline
bitfld.long 0x00 1. "UNDERRUN_EN,Enable Interrupt flag to indicate the output buffer underrun condition" "0,1"
bitfld.long 0x00 0. "VSYNC_EN,Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)" "0,1"
group.long 0x30++0x03
line.long 0x00 "INT_STATUS_D1,Interrupt Status Register for domain 0"
eventfld.long 0x00 0. "PLANE_PANIC,plane panic to indicate that which FIFO reaches the panic threshold" "0,1"
group.long 0x34++0x03
line.long 0x00 "INT_ENABLE_D1,Interrupt Enable Register for domain 0"
bitfld.long 0x00 0. "PLANE_PANIC_EN,Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed" "0,1"
group.long 0x200++0x03
line.long 0x00 "CTRLDESCL0_1,Control Descriptor Layer Register 1"
hexmask.long.word 0x00 16.--31. 1. "HEIGHT,Height of the layer in pixels"
hexmask.long.word 0x00 0.--15. 1. "WIDTH,Width of the layer in pixels"
group.long 0x208++0x03
line.long 0x00 "CTRLDESCL0_3,Control Descriptor Layer Register 3"
hexmask.long.word 0x00 0.--15. 1. "PITCH,Number of bytes between 2 vertically adjacent pixels in system memory"
group.long 0x20C++0x03
line.long 0x00 "CTRLDESCL_LOW0_4,Control Descriptor Layer Register 4"
hexmask.long 0x00 0.--31. 1. "ADDR_LOW,Address of layer data in the memory"
group.long 0x210++0x03
line.long 0x00 "CTRLDESCL_HIGH0_4,Control Descriptor Layer Register 4"
bitfld.long 0x00 0.--3. "ADDR_HIGH,Address of layer data in the memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x214++0x03
line.long 0x00 "CTRLDESCL0_5,Control Descriptor Layer Register 5"
bitfld.long 0x00 31. "EN,Enable the layer for DMA" "0: EN_0,1: EN_1"
bitfld.long 0x00 30. "SHADOW_LOAD_EN,Shadow Load Enable" "0,1"
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bitfld.long 0x00 24.--27. "BPP,Layer encoding format (bit per pixel)" "?,?,?,?,4: 16 bpp (RGB565),5: 16 bpp (ARGB1555),6: 16 bpp (ARGB4444),7: YCbCr422,8: 24 bpp (RGB888),9: 32 bpp (ARGB8888),10: 32 bpp (ABGR8888),?..."
bitfld.long 0x00 14.--15. "YUV_FORMAT,The YUV422 input format selection" "0: The YUV422 32bit memory is {Y2 V1 Y1 U1},1: The YUV422 32bit memory is {Y2 U1 Y1 V1},2: The YUV422 32bit memory is {V1 Y2 U1 Y1},3: The YUV422 32bit memory is {U1 Y2 V1 Y1}"
group.long 0x21C++0x03
line.long 0x00 "CSC0_CTRL,Color Space Conversion Ctrl Register"
bitfld.long 0x00 1.--2. "CSC_MODE,This field controls how the CSC unit operates on pixels when the CSC is not bypassed" "0,1,2,3"
bitfld.long 0x00 0. "BYPASS,This bit controls whether the pixels entering the CSC2 unit get converted or not" "0,1"
group.long 0x220++0x03
line.long 0x00 "CSC0_COEF0,Color Space Conversion Coefficient Register 0"
hexmask.long.word 0x00 16.--26. 1. "A2,Two's complement coefficient offset"
hexmask.long.word 0x00 0.--10. 1. "A1,Two's complement coefficient offset"
group.long 0x224++0x03
line.long 0x00 "CSC0_COEF1,Color Space Conversion Coefficient Register 1"
hexmask.long.word 0x00 16.--26. 1. "B1,Two's complement coefficient offset"
hexmask.long.word 0x00 0.--10. 1. "A3,Two's complement coefficient offset"
group.long 0x228++0x03
line.long 0x00 "CSC0_COEF2,Color Space Conversion Coefficient Register 2"
hexmask.long.word 0x00 16.--26. 1. "B3,Two's complement coefficient offset"
hexmask.long.word 0x00 0.--10. 1. "B2,Two's complement coefficient offset"
group.long 0x22C++0x03
line.long 0x00 "CSC0_COEF3,Color Space Conversion Coefficient Register 3"
hexmask.long.word 0x00 16.--26. 1. "C2,Two's complement coefficient offset"
hexmask.long.word 0x00 0.--10. 1. "C1,Two's complement coefficient offset"
group.long 0x230++0x03
line.long 0x00 "CSC0_COEF4,Color Space Conversion Coefficient Register 4"
hexmask.long.word 0x00 16.--24. 1. "D1,Two's complement D1 coefficient integer offset to be added"
hexmask.long.word 0x00 0.--10. 1. "C3,Two's complement coefficient offset"
group.long 0x234++0x03
line.long 0x00 "CSC0_COEF5,Color Space Conversion Coefficient Register 0"
hexmask.long.word 0x00 16.--24. 1. "D3,Two's complement D3 coefficient integer offset to be added"
hexmask.long.word 0x00 0.--8. 1. "D2,Two's complement D2 coefficient integer offset to be added"
group.long 0x238++0x03
line.long 0x00 "PANIC0_THRES,Memory request priority threshold register"
hexmask.long.word 0x00 16.--24. 1. "PANIC_THRES_LOW,This value should be set to a value of pixels from (0+1)*128bits to (511+1)*128bits"
hexmask.long.word 0x00 0.--8. 1. "PANIC_THRES_HIGH,This value should be set to a value of pixels from (0+1)*128bits to (511+1)*128bits"
tree.end
repeat.end
tree.end
tree "MAINCONTROLLER (MainController)"
base ad:0x32FDC000
group.byte 0x01++0x00
line.byte 0x00 "mc_clkdis,Main Controller Synchronous Clock Domain Disable Register"
bitfld.byte 0x00 6. "hdcpclk_disable,HDCP clock synchronous disable signal" "0,1"
bitfld.byte 0x00 5. "cecclk_disable,CEC Engine clock synchronous disable signal" "0,1"
newline
bitfld.byte 0x00 4. "cscclk_disable,Color Space Converter clock synchronous disable signal" "0,1"
bitfld.byte 0x00 3. "audclk_disable,Audio Sampler clock synchronous disable signal" "0,1"
newline
bitfld.byte 0x00 2. "prepclk_disable,Pixel Repetition clock synchronous disable signal" "0,1"
bitfld.byte 0x00 1. "tmdsclk_disable,TMDS clock synchronous disable signal" "0,1"
newline
bitfld.byte 0x00 0. "pixelclk_disable,Pixel clock synchronous disable signal" "0,1"
group.byte 0x02++0x00
line.byte 0x00 "mc_swrstzreq_1,Main Controller Software Reset Register Main controller software reset request per clock domain"
bitfld.byte 0x00 7. "igpaswrst_req,GPAUD interface soft reset request" "0,1"
bitfld.byte 0x00 6. "cecswrst_req,CEC software reset request" "0,1"
newline
bitfld.byte 0x00 4. "ispdifswrst_req,SPDIF audio software reset request" "0,1"
bitfld.byte 0x00 3. "ii2sswrst_req,I2S audio software reset request" "0,1"
newline
bitfld.byte 0x00 2. "prepswrst_req,Pixel Repetition software reset request" "0,1"
bitfld.byte 0x00 1. "tmdsswrst_req,TMDS software reset request" "0,1"
newline
bitfld.byte 0x00 0. "pixelswrst_req,Pixel software reset request" "0,1"
group.byte 0x03++0x00
line.byte 0x00 "mc_opctrl,Main Controller HDCP Bypass Control Register"
bitfld.byte 0x00 0. "hdcp_block_byp,Block HDCP bypass mechanism" "0,1"
group.byte 0x04++0x00
line.byte 0x00 "mc_flowctrl,Main Controller Feed Through Control Register"
bitfld.byte 0x00 0. "Feed_through_off,Video path Feed Through enable bit" "0,1"
group.byte 0x05++0x00
line.byte 0x00 "mc_phyrstz,Main Controller PHY Reset Register"
bitfld.byte 0x00 0. "phyrstz,HDMI Source PHY active low reset control for PHY GEN1 active high reset control for PHY GEN2" "0,1"
group.byte 0x06++0x00
line.byte 0x00 "mc_lockonclock_1,Main Controller Clock Present Register"
eventfld.byte 0x00 7. "igpaclk,GPAUD interface clock status" "0,1"
eventfld.byte 0x00 6. "pclk,Pixel clock status" "0,1"
newline
eventfld.byte 0x00 5. "tclk,TMDS clock status" "0,1"
eventfld.byte 0x00 4. "prepclk,Pixel Repetition clock status" "0,1"
newline
eventfld.byte 0x00 3. "i2sclk,I2S clock status" "0,1"
eventfld.byte 0x00 2. "audiospdifclk,SPDIF clock status" "0,1"
newline
eventfld.byte 0x00 0. "cecclk,CEC clock status" "0,1"
tree.end
tree "MEDIA_BLK_CTRL (MEDIAMIX)"
base ad:0x32EC0000
group.long 0x00++0x03
line.long 0x00 "SFT_RSTN,Media Mix Software Reset Register"
bitfld.long 0x00 24. "SFT_EN_LCDIF2_AXI_CLK_RESETN,sft_en_lcdif2_axi_clk_resetn" "0: software reset enable for lcdif2_axi_clk,1: software reset disable for lcdif2_axi_clk"
newline
bitfld.long 0x00 23. "SFT_EN_LCDIF_AXI_CLK_RESETN,sft_en_lcdif_axi_clk_resetn" "0: software reset enable for lcdif_axi_clk,1: software reset disable for lcdif_axi_clk"
newline
bitfld.long 0x00 22. "SFT_EN_MIPI_DSI2_CLKREF_RESETN,sft_en_mipi_dsi2_CLKREF_resetn" "0: software reset enable for mipi_dsi2_CLKREF,1: software reset disable for mipi_dsi2_CLKREF"
newline
bitfld.long 0x00 21. "SFT_EN_DWE_AHB_CLK_RESETN,sft_en_dwe_ahb_clk_resetn" "0: software reset enable for dwe_ahb_clk,1: software reset disable for dwe_ahb_clk"
newline
bitfld.long 0x00 20. "SFT_EN_DWE_AXI_CLK_RESETN,sft_en_dwe_axi_clk_resetn" "0: software reset enable for dwe_axi_clk,1: software reset disable for dwe_axi_clk"
newline
bitfld.long 0x00 19. "SFT_EN_DWE_COR_CLK_RESETN,sft_en_dwe_cor_clk_resetn" "0: software reset enable for dwe_cor_clk,1: software reset disable for dwe_cor_clk"
newline
bitfld.long 0x00 18. "SFT_EN_ISP_AHB_CLK_RESETN,sft_en_isp_ahb_clk_resetn" "0: software reset enable for isp_ahb_clk,1: software reset disable for isp_ahb_clk"
newline
bitfld.long 0x00 17. "SFT_EN_ISP_AXI_CLK_RESETN,sft_en_isp_axi_clk_resetn" "0: software reset enable for isp_axi_clk,1: software reset disable for isp_axi_clk"
newline
bitfld.long 0x00 16. "SFT_EN_ISP_COR_CLK_RESETN,sft_en_isp_cor_clk_resetn" "0: software reset enable for isp_cor_clk,1: software reset disable for isp_cor_clk"
newline
bitfld.long 0x00 12. "SFT_EN_LCDIF2_APB_CLK_RESETN,sft_en_lcdif2_apb_clk_resetn" "0: software reset enable for lcdif2_apb_clk,1: software reset disable for lcdif2_apb_clk"
newline
bitfld.long 0x00 11. "SFT_EN_LCDIF2_PIXEL_CLK_RESETN,sft_en_lcdif2_pixel_clk_resetn" "0: software reset enable for lcdif2_pixel_clk,1: software reset disable for lcdif2_pixel_clk"
newline
bitfld.long 0x00 10. "SFT_EN_MIPI_CSI2_ACLK_RESETN,sft_en_mipi_csi2_aclk_resetn" "0: software reset enable for mipi_csi2_aclk,1: software reset disable for mipi_csi2_aclk"
newline
bitfld.long 0x00 9. "SFT_EN_MIPI_CSI2_PCLK_RESETN,sft_en_mipi_csi2_pclk_resetn" "0: software reset enable for mipi_csi2_pclk,1: software reset disable for mipi_csi2_pclk"
newline
bitfld.long 0x00 8. "SFT_EN_BUS_BLK_CLK_RESETN,sft_en_bus_blk_clk_resetn" "0: software reset enable for bus_blk_clk,1: software reset disable for bus_blk_clk"
newline
bitfld.long 0x00 7. "SFT_EN_ISI_APB_CLK_RESETN,sft_en_isi_apb_clk_resetn" "0: software reset enable for isi_apb_clk,1: software reset disable for isi_apb_clk"
newline
bitfld.long 0x00 6. "SFT_EN_ISI_PROC_CLK_RESETN,sft_en_isi_proc_clk_resetn" "0: software reset enable for isi_proc_clk,1: software reset disable for isi_proc_clk"
newline
bitfld.long 0x00 5. "SFT_EN_LCDIF_APB_CLK_RESETN,sft_en_lcdif_apb_clk_resetn" "0: software reset enable for lcdif_apb_clk,1: software reset disable for lcdif_apb_clk"
newline
bitfld.long 0x00 4. "SFT_EN_LCDIF_PIXEL_CLK_RESETN,sft_en_lcdif_pixel_clk_resetn" "0: software reset enable for lcdif_pixel_clk,1: software reset disable for lcdif_pixel_clk"
newline
bitfld.long 0x00 3. "SFT_EN_MIPI_CSI_ACLK_RESETN,sft_en_mipi_csi_aclk_resetn" "0: software reset enable for mipi_csi_aclk,1: software reset disable for mipi_csi_aclk"
newline
bitfld.long 0x00 2. "SFT_EN_MIPI_CSI_PCLK_RESETN,sft_en_mipi_csi_pclk_resetn" "0: software reset enable for mipi_csi_pclk,1: software reset disable for mipi_csi_pclk"
newline
bitfld.long 0x00 1. "SFT_EN_MIPI_DSI_CLKREF_RESETN,sft_en_mipi_dsi_CLKREF_resetn" "0: software reset enable for mipi_dsi_CLKREF,1: software reset disable for mipi_dsi_CLKREF"
newline
bitfld.long 0x00 0. "SFT_EN_MIPI_DSI_PCLK_RESETN,sft_en_mipi_dsi_pclk_resetn" "0: software reset enable for mipi_dsi_pclk,1: software reset disable for mipi_dsi_pclk"
group.long 0x04++0x03
line.long 0x00 "CLK_EN,Media Mix Clock Enable Register"
bitfld.long 0x00 24. "SFT_EN_LCDIF2_AXI_CLK,sft_en_lcdif2_axi_clk" "0: clock disable (gated) for lcdif2_axi_clk,1: clock enable for lcdif2_axi_clk"
newline
bitfld.long 0x00 23. "SFT_EN_LCDIF_AXI_CLK,sft_en_lcdif_axi_clk" "0: clock disable (gated) for lcdif_axi_clk,1: clock enable for lcdif_axi_clk"
newline
bitfld.long 0x00 22. "SFT_EN_MIPI_DSI2_CLKREF,sft_en_mipi_dsi2_CLKREF" "0: clock disable (gated) for mipi_dsi2_CLKREF,1: clock enable for mipi_dsi2_CLKREF"
newline
bitfld.long 0x00 21. "SFT_EN_DWE_AHB_CLK,sft_en_dwe_ahb_clk" "0: clock disable (gated) for dwe_ahb_clk,1: clock enable for dwe_ahb_clk"
newline
bitfld.long 0x00 20. "SFT_EN_DWE_AXI_CLK,sft_en_dwe_axi_clk" "0: clock disable (gated) for dwe_axi_clk,1: clock enable for dwe_axi_clk"
newline
bitfld.long 0x00 19. "SFT_EN_DWE_COR_CLK,sft_en_dwe_cor_clk" "0: clock disable (gated) for dwe_cor_clk,1: clock enable for dwe_cor_clk"
newline
bitfld.long 0x00 18. "SFT_EN_ISP_AHB_CLK,sft_en_isp_ahb_clk" "0: clock disable (gated) for isp_ahb_clk,1: clock enable for isp_ahb_clk"
newline
bitfld.long 0x00 17. "SFT_EN_ISP_AXI_CLK,sft_en_isp_axi_clk" "0: clock disable (gated) for isp_axi_clk,1: clock enable for isp_axi_clk"
newline
bitfld.long 0x00 16. "SFT_EN_ISP_COR_CLK,sft_en_isp_cor_clk" "0: clock disable (gated) for isp_cor_clk,1: clock enable for isp_cor_clk"
newline
bitfld.long 0x00 12. "SFT_EN_LCDIF2_APB_CLK,sft_en_lcdif2_apb_clk" "0: clock disable (gated) for lcdif2_apb_clk,1: clock enable for lcdif2_apb_clk"
newline
bitfld.long 0x00 11. "SFT_EN_LCDIF2_PIXEL_CLK,sft_en_lcdif2_pixel_clk" "0: clock disable (gated) for lcdif2_pixel_clk,1: clock enable for lcdif2_pixel_clk"
newline
bitfld.long 0x00 10. "SFT_EN_MIPI_CSI2_ACLK,sft_en_mipi_csi2_aclk" "0: clock disable (gated) for mipi_csi2_aclk,1: clock enable for mipi_csi2_aclk"
newline
bitfld.long 0x00 9. "SFT_EN_MIPI_CSI2_PCLK,sft_en_mipi_csi2_pclk" "0: clock disable (gated) for mipi_csi2_pclk,1: clock enable for mipi_csi2_pclk"
newline
bitfld.long 0x00 8. "SFT_EN_BUS_BLK_CLK,sft_en_bus_blk_clk" "0: clock disable (gated) for bus_blk_clk,1: clock enable for bus_blk_clk"
newline
bitfld.long 0x00 7. "SFT_EN_ISI_APB_CLK,sft_en_isi_apb_clk" "0: clock disable (gated) for isi_apb_clk,1: clock enable for isi_apb_clk"
newline
bitfld.long 0x00 6. "SFT_EN_ISI_PROC_CLK,sft_en_isi_proc_clk" "0: clock disable (gated) for isi_proc_clk,1: clock enable for isi_proc_clk"
newline
bitfld.long 0x00 5. "SFT_EN_LCDIF_APB_CLK,sft_en_lcdif_apb_clk" "0: clock disable (gated) for lcdif_apb_clk,1: clock enable for lcdif_apb_clk"
newline
bitfld.long 0x00 4. "SFT_EN_LCDIF_PIXEL_CLK,sft_en_lcdif_pixel_clk" "0: clock disable (gated) for lcdif_pixel_clk,1: clock enable for lcdif_pixel_clk"
newline
bitfld.long 0x00 3. "SFT_EN_MIPI_CSI_ACLK,sft_en_mipi_csi_aclk" "0: clock disable (gated) for mipi_csi_aclk,1: clock enable for mipi_csi_aclk"
newline
bitfld.long 0x00 2. "SFT_EN_MIPI_CSI_PCLK,sft_en_mipi_csi_pclk" "0: clock disable (gated) for mipi_csi_pclk,1: clock enable for mipi_csi_pclk"
newline
bitfld.long 0x00 1. "SFT_EN_MIPI_DSI_CLKREF,sft_en_mipi_dsi_CLKREF" "0: clock disable (gated) for mipi_dsi_CLKREF,1: clock enable for mipi_dsi_CLKREF"
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bitfld.long 0x00 0. "SFT_EN_MIPI_DSI_PCLK,sft_en_mipi_dsi_pclk" "0: clock disable (gated) for mipi_dsi_pclk,1: clock enable for mipi_dsi_pclk"
group.long 0x08++0x03
line.long 0x00 "MIPI_RESET_DIV,MIPI PHY Control Register"
bitfld.long 0x00 30. "GPR_MIPI_S2_RESETN,GPR_MIPI_S2_RESETN" "0: MIPI DPHY S2_RESETN reset enable,1: MIPI DPHY S2_RESETN reset disable"
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bitfld.long 0x00 29. "GPR_MIPI_M2_RESETN,GPR_MIPI_M2_RESETN" "0: MIPI DPHY M2_RESETN reset enable,1: MIPI DPHY M2_RESETN reset disable"
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bitfld.long 0x00 26. "GPR_MIPI_M_DPDN_SWAP_CLK,GPR_MIPI_M_DPDN_SWAP_CLK" "0: Master DPHY clock lane DP and DN swap disable,1: Master DPHY clock lane DP and DN swap enable"
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bitfld.long 0x00 25. "GPR_MIPI_M_DPDN_SWAP_DAT,GPR_MIPI_M_DPDN_SWAP_DAT" "0: Master DPHY data lane DP and DN swap disable,1: Master DPHY data lane DP and DN swap enable"
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bitfld.long 0x00 24. "GPR_MIPI_S_DPDN_SWAP_CLK,GPR_MIPI_S_DPDN_SWAP_CLK" "0: Slave DPHY clock lane DP and DN swap disable,1: Slave DPHY clock lane DP and DN swap enable"
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bitfld.long 0x00 23. "GPR_MIPI_S_DPDN_SWAP_DAT,GPR_MIPI_S_DPDN_SWAP_DAT" "0: Master DPHY data lane DP and DN swap disable,1: Master DPHY data lane DP and DN swap enable"
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bitfld.long 0x00 22. "GPR_CTRL_M1_BIASEN,GPR_CTRL_M1_BIASEN" "0: GPR_CTRL_M1_BIASEN_0,1: GPR_CTRL_M1_BIASEN_1"
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bitfld.long 0x00 21. "GPR_CTRL_M2_BIASEN,GPR_CTRL_M2_BIASEN" "0: GPR_CTRL_M2_BIASEN_0,1: GPR_CTRL_M2_BIASEN_1"
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bitfld.long 0x00 20. "GPR_CTRL_S1_BIASEN,GPR_CTRL_S1_BIASEN" "0: GPR_CTRL_S1_BIASEN_0,1: GPR_CTRL_S1_BIASEN_1"
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bitfld.long 0x00 19. "GPR_CTRL_S2_BIASEN,GPR_CTRL_S2_BIASEN" "0: GPR_CTRL_S2_BIASEN_0,1: GPR_CTRL_S2_BIASEN_1"
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bitfld.long 0x00 18. "GPR_CTRL_S3_BIASEN,GPR_CTRL_S3_BIASEN" "0: GPR_CTRL_S3_BIASEN_0,1: GPR_CTRL_S3_BIASEN_1"
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bitfld.long 0x00 17. "GPR_MIPI_M_RESETN,GPR_MIPI_M_RESETN" "0: MIPI DPHY M_RESETN reset enable,1: MIPI DPHY M_RESETN reset disable"
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bitfld.long 0x00 16. "GPR_MIPI_S_RESETN,GPR_MIPI_S_RESETN" "0: MIPI DPHY S_RESETN reset enable,1: MIPI DPHY S_RESETN reset disable"
group.long 0x0C++0x03
line.long 0x00 "MIPI_M_PLLPMS,Master PLL PMS Value setting Register"
bitfld.long 0x00 13.--18. "PMS_P,PMS_P" "0: Do not program can cause malfunction,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Divide by 30,31: Divide by 31,32: Divide by 32,33: Divide by 33,?..."
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hexmask.long.word 0x00 4.--12. 1. "PMS_M,PMS_M"
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bitfld.long 0x00 1.--2. "PMS_S,PMS_S" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8"
group.long 0x10++0x03
line.long 0x00 "MIPI_M_PLLCTL_LOW,Master PLL Control Low Register"
bitfld.long 0x00 31. "SSCG_EN,Enable pin for dithered mode" "0,1"
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bitfld.long 0x00 30. "AFC_SEL,AFC operation mode select pin" "0,1"
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bitfld.long 0x00 29. "FEED_EN,FEED_OUT enable pin (active-high)" "0,1"
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bitfld.long 0x00 28. "PBIAS_CTRL,PBIAS pull-down initial voltage control pin" "0,1"
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bitfld.long 0x00 27. "PBIAS_CTRL_EN,PBIAS voltage pull-down enable pin (active-high)" "0,1"
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bitfld.long 0x00 23. "FSEL,Monitoring frequency select pin" "0,1"
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bitfld.long 0x00 22. "BYPASS,BYPASS" "0,1"
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bitfld.long 0x00 20.--21. "ICP,Controls the charge-pump current" "0,1,2,3"
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bitfld.long 0x00 6. "AFCINIT_SEL,AFC initial delay select pin" "0,1"
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bitfld.long 0x00 1.--5. "EXTAFC,EXTAFC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "AFC_ENB,Automatic Frequency Control Enable/Disable" "0: AFC is enabled,1: AFC is disabled"
group.long 0x14++0x03
line.long 0x00 "MIPI_M_PLLCTL_HIGH,Master PLL Control High Register"
hexmask.long.word 0x00 16.--31. 1. "K,Value of 16-bit Delta-Sigma Modulator (DSM)"
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bitfld.long 0x00 14.--15. "SEL_PF,Value of 2-bit modulation method control" "0,1,2,3"
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bitfld.long 0x00 8.--13. "MRR,Value of 6-bit Modulation Rate (MR) control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 0.--7. 1. "MFR,Value of 8-bit Modulation Frequency (MF) control"
group.long 0x18++0x03
line.long 0x00 "MIPI_B_DPHYCTL_LOW,Master and Slave DPHY Control Low Register"
bitfld.long 0x00 30.--31. "USER_DATA_HS,User Data Pattern for HS Loopback mode" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BIAS_REF_VOLT_CTL,BIAS_REF_VOLT_CTL" "0: BIAS_REF_VOLT_CTL_0,1: BIAS_REF_VOLT_CTL_1,2: BIAS_REF_VOLT_CTL_2,3: BIAS_REF_VOLT_CTL_3"
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bitfld.long 0x00 27. "BGR_CHOPPER_FREQ_CTL,BGR_CHOPPER_FREQ_CTL" "0: BGR_CHOPPER_FREQ_CTL_0,1: BGR_CHOPPER_FREQ_CTL_1"
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bitfld.long 0x00 26. "REG_VALID_CTL_1_2,REG_VALID_CTL_1_2" "0: Internal 1.2V regulator,1: REG_VALID_CTL_1_2_1"
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bitfld.long 0x00 24.--25. "REG_LVL_CTL_1_2,REG_LVL_CTL_1_2" "0: REG_LVL_CTL_1_2_0,1: REG_LVL_CTL_1_2_1,2: REG_LVL_CTL_1_2_2,3: REG_LVL_CTL_1_2_3"
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bitfld.long 0x00 23. "REG_VALID_1_2,REG_VALID_1_2" "0: Use ulps_en signal,1: Use valid signal from 1.2V regulator"
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bitfld.long 0x00 21.--22. "LP_RX_HYS_CTL,LP_RX_HYS_CTL" "0: LP_RX_HYS_CTL_0,1: LP_RX_HYS_CTL_1,2: LP_RX_HYS_CTL_2,3: LP_RX_HYS_CTL_3"
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bitfld.long 0x00 20. "VREF_SRC_SEL,VREF_SRC_SEL" "0: Generated from the BGR,1: Generated from the current mirror"
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bitfld.long 0x00 18.--19. "LP_RX_VREF_LVL,LP_RX_VREF_LVL" "0: LP_RX_VREF_LVL_0,1: LP_RX_VREF_LVL_1,2: LP_RX_VREF_LVL_2,3: LP_RX_VREF_LVL_3"
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bitfld.long 0x00 17. "LP_RX_PULSE_REJ,LP_RX_PULSE_REJ" "0: LP_RX_PULSE_REJ_0,1: LP_RX_PULSE_REJ_1"
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bitfld.long 0x00 15.--16. "MSTR_CLK_SLEW_RATE_DOWN,MSTR_CLK_SLEW_RATE_DOWN" "0: MSTR_CLK_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 14. "MSTR_CLK_SLEW_RATE_UP,MSTR_CLK_SLEW_RATE_UP" "0: MSTR_CLK_SLEW_RATE_UP_0,1: MSTR_CLK_SLEW_RATE_UP_1"
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bitfld.long 0x00 13. "LP_CD_HYS,LP_CD_HYS" "0: LP_CD_HYS_0,1: LP_CD_HYS_1"
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bitfld.long 0x00 12. "BGR_CHOPPER_EN,BGR_CHOPPER_EN" "0: BGR_CHOPPER_EN_0,1: BGR_CHOPPER_EN_1"
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bitfld.long 0x00 11. "ERR_CONT_LP_EN,ERR_CONT_LP_EN" "0: ERR_CONT_LP_EN_0,1: ERR_CONT_LP_EN_1"
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bitfld.long 0x00 10. "TX_TRIGGER_CLK_EN,TX_TRIGGER_CLK_EN" "0: TX_TRIGGER_CLK_EN_0,1: TX_TRIGGER_CLK_EN_1"
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hexmask.long.word 0x00 0.--9. 1. "ULPS_EXIT_COUNTER,ULPS_EXIT_COUNTER"
group.long 0x1C++0x03
line.long 0x00 "MIPI_B_DPHYCTL_HIGH,Master and Slave DPHY Control High Register"
bitfld.long 0x00 30.--31. "MSTR_DATA3_SLEW_RATE_DOWN,MSTR_DATA3_SLEW_RATE_DOWN" "0: MSTR_DATA3_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 29. "MSTR_DATA3_SLEW_RATE_UP,MSTR_DATA3_SLEW_RATE_UP" "0: MSTR_DATA3_SLEW_RATE_UP_0,1: MSTR_DATA3_SLEW_RATE_UP_1"
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bitfld.long 0x00 27.--28. "MSTR_DATA2_SLEW_RATE_DOWN,MSTR_DATA2_SLEW_RATE_DOWN" "0: MSTR_DATA2_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 26. "MSTR_DATA2_SLEW_RATE_UP,MSTR_DATA2_SLEW_RATE_UP" "0: MSTR_DATA2_SLEW_RATE_UP_0,1: MSTR_DATA2_SLEW_RATE_UP_1"
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bitfld.long 0x00 24.--25. "MSTR_DATA1_SLEW_RATE_DOWN,MSTR_DATA1_SLEW_RATE_DOWN" "0: MSTR_DATA1_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 23. "MSTR_DATA1_SLEW_RATE_UP,MSTR_DATA1_SLEW_RATE_UP" "0: MSTR_DATA1_SLEW_RATE_UP_0,1: MSTR_DATA1_SLEW_RATE_UP_1"
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bitfld.long 0x00 21.--22. "MSTR_DATA0_SLEW_RATE_DOWN,MSTR_DATA0_SLEW_RATE_DOWN" "0: MSTR_DATA0_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 20. "MSTR_DATA0_SLEW_RATE_UP,MSTR_DATA0_SLEW_RATE_UP" "0: MSTR_DATA0_SLEW_RATE_UP_0,1: MSTR_DATA0_SLEW_RATE_UP_1"
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bitfld.long 0x00 14. "LP_VREF_REG_SRC_SEL,LP_VREF_REG_SRC_SEL" "0: LP_VREF_REG_SRC_SEL_0,1: Generated from Current Mirror"
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bitfld.long 0x00 13. "RX_SKEW_CALIB_FIX_CODE_EN,RX_SKEW_CALIB_FIX_CODE_EN" "0: RX_SKEW_CALIB_FIX_CODE_EN_0,1: RX_SKEW_CALIB_FIX_CODE_EN_1"
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bitfld.long 0x00 11. "DCC_DONE_CTL,DCC_DONE_CTL" "0: DONE from DCC block,1: U DONE is always 1"
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bitfld.long 0x00 8.--9. "BGR_VOLT_TUNING_CTL,BGR_VOLT_TUNING_CTL" "0: BGR_VOLT_TUNING_CTL_0,1: BGR_VOLT_TUNING_CTL_1,2: BGR_VOLT_TUNING_CTL_2,3: BGR_VOLT_TUNING_CTL_3"
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bitfld.long 0x00 6.--7. "HS_MODE_CTL,HS_MODE_CTL" "0: Designated Pattern,1: HS_MODE_CTL_1,2: HS_MODE_CTL_2,3: User Data Pattern"
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bitfld.long 0x00 0.--5. "USER_DATA_HS,User Data Pattern for HS Loopback mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x20++0x03
line.long 0x00 "MIPI_M_DPHYCTL_LOW,Master and Slave DPHY Control Low Register"
bitfld.long 0x00 31. "HS_REG_VREF_SRC_SEL,HS_REG_VREF_SRC_SEL" "0: HS_REG_VREF_SRC_SEL_0,1: Generated from Current Mirror"
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bitfld.long 0x00 30. "CLK_BUFFER_EN_CTL,CLK_BUFFER_EN_CTL" "0: CLK_BUFFER_EN_CTL_0,1: CLK_BUFFER_EN_CTL_1"
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bitfld.long 0x00 27.--29. "HS_TX_RISE_FALL_TIME_CTL,HS_TX_RISE_FALL_TIME_CTL" "0: HS_TX_RISE_FALL_TIME_CTL_0,1: HS_TX_RISE_FALL_TIME_CTL_1,2: HS_TX_RISE_FALL_TIME_CTL_2,3: HS_TX_RISE_FALL_TIME_CTL_3,4: HS_TX_RISE_FALL_TIME_CTL_4,5: HS_TX_RISE_FALL_TIME_CTL_5,6: HS_TX_RISE_FALL_TIME_CTL_6,7: HS_TX_RISE_FALL_TIME_CTL_7"
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bitfld.long 0x00 24.--26. "HS_TX_REG_OUT_CTL,HS_TX_REG_OUT_CTL" "0: HS_TX_REG_OUT_CTL_0,1: HS_TX_REG_OUT_CTL_1,2: HS_TX_REG_OUT_CTL_2,3: HS_TX_REG_OUT_CTL_3,4: HS_TX_REG_OUT_CTL_4,5: HS_TX_REG_OUT_CTL_5,6: HS_TX_REG_OUT_CTL_6,7: HS_TX_REG_OUT_CTL_7"
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bitfld.long 0x00 23. "HS_TX_REG_CURRENT_CTL,HS_TX_REG_CURRENT_CTL" "0: HS_TX_REG_CURRENT_CTL_0,1: HS_TX_REG_CURRENT_CTL_1"
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bitfld.long 0x00 20.--22. "HS_TX_TERM_IMP_DOWN_CTL,HS_TX_TERM_IMP_DOWN_CTL" "0: HS_TX_TERM_IMP_DOWN_CTL_0,1: HS_TX_TERM_IMP_DOWN_CTL_1,2: HS_TX_TERM_IMP_DOWN_CTL_2,3: HS_TX_TERM_IMP_DOWN_CTL_3,4: HS_TX_TERM_IMP_DOWN_CTL_4,5: HS_TX_TERM_IMP_DOWN_CTL_5,6: HS_TX_TERM_IMP_DOWN_CTL_6,7: HS_TX_TERM_IMP_DOWN_CTL_7"
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bitfld.long 0x00 17.--19. "HS_TX_TERM_IMP_UP_CTL,HS_TX_TERM_IMP_UP_CTL" "0: HS_TX_TERM_IMP_UP_CTL_0,1: HS_TX_TERM_IMP_UP_CTL_1,2: HS_TX_TERM_IMP_UP_CTL_2,3: HS_TX_TERM_IMP_UP_CTL_3,4: HS_TX_TERM_IMP_UP_CTL_4,5: HS_TX_TERM_IMP_UP_CTL_5,6: HS_TX_TERM_IMP_UP_CTL_6,7: HS_TX_TERM_IMP_UP_CTL_7"
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bitfld.long 0x00 15.--16. "ANA_TIMER_HYS_CTL,ANA_TIMER_HYS_CTL" "0: ANA_TIMER_HYS_CTL_0,1: ANA_TIMER_HYS_CTL_1,2: ANA_TIMER_HYS_CTL_2,3: ANA_TIMER_HYS_CTL_3"
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bitfld.long 0x00 13.--14. "DATA_LANE_CAP_CTL,DATA_LANE_CAP_CTL" "0: DATA_LANE_CAP_CTL_0,1: DATA_LANE_CAP_CTL_1,2: DATA_LANE_CAP_CTL_2,3: DATA_LANE_CAP_CTL_3"
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bitfld.long 0x00 11.--12. "CLK_LANE_CAP_CTL,CLK_LANE_CAP_CTL" "0: CLK_LANE_CAP_CTL_0,1: CLK_LANE_CAP_CTL_1,2: CLK_LANE_CAP_CTL_2,3: CLK_LANE_CAP_CTL_3"
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bitfld.long 0x00 10. "HS_TX_SLEW_RATE_EN,HS_TX_SLEW_RATE_EN" "0: HS_TX_SLEW_RATE_EN_0,1: HS_TX_SLEW_RATE_EN_1"
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bitfld.long 0x00 7.--9. "HS_TX_SLEW_RATE_CTL,HS_TX_SLEW_RATE_CTL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--6. "CLK_HS_TX_DELAY_CTL,CLK_HS_TX_DELAY_CTL" "0: CLK_HS_TX_DELAY_CTL_0,1: CLK_HS_TX_DELAY_CTL_1,2: CLK_HS_TX_DELAY_CTL_2,3: CLK_HS_TX_DELAY_CTL_3"
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bitfld.long 0x00 4. "HS_TX_REG_TURN_ON_CTL,HS_TX_REG_TURN_ON_CTL" "0: HS_TX_REG_TURN_ON_CTL_0,1: Always Turn-On the HS Regulator"
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bitfld.long 0x00 2.--3. "HS_TX_REG_AMP_CTL,HS_TX_REG_AMP_CTL" "0: HS_TX_REG_AMP_CTL_0,1: HS_TX_REG_AMP_CTL_1,2: HS_TX_REG_AMP_CTL_2,3: HS_TX_REG_AMP_CTL_3"
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bitfld.long 0x00 0.--1. "DATA_HS_TX_DELAY_CTL,DATA_HS_TX_DELAY_CTL" "0: DATA_HS_TX_DELAY_CTL_0,1: DATA_HS_TX_DELAY_CTL_1,2: DATA_HS_TX_DELAY_CTL_2,3: DATA_HS_TX_DELAY_CTL_3"
group.long 0x24++0x03
line.long 0x00 "MIPI_M_DPHYCTL_HIGH,Master and Slave DPHY Control High Register"
bitfld.long 0x00 28. "PLL_CLK_OUT_SEL,PLL_CLK_OUT_SEL" "0: Disable OUT to Other lane,1: Enable OUT to Other lane"
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bitfld.long 0x00 16.--19. "TXSKEWCALHS_WAIT_CTL,TXSKEWCALHS_WAIT_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "TXSKEWCALHS_INIT_CTL,TXSKEWCALHS_INIT_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "TXSKEWCALHS_CTL,TXSKEWCALHS_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "CLK_SEL_CTL,CLK_SEL_CTL" "0: Generated from Internal PLL,1: Generated from External PLL"
group.long 0x28++0x03
line.long 0x00 "MIPI_S_DPHYCTL_LOW,Master and Slave DPHY Control Low Register"
bitfld.long 0x00 31. "DCC_STABLE_CTL,DCC_STABLE_CTL" "0: 1 number counter running,1: 2 number counter running"
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bitfld.long 0x00 28.--30. "DCC_INIT_TOLERANCE,DCC_INIT_TOLERANCE" "0: DCC_INIT_TOLERANCE_0,1: DCC_INIT_TOLERANCE_1,2: DCC_INIT_TOLERANCE_2,3: DCC_INIT_TOLERANCE_3,4: DCC_INIT_TOLERANCE_4,5: DCC_INIT_TOLERANCE_5,6: DCC_INIT_TOLERANCE_6,7: DCC_INIT_TOLERANCE_7"
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bitfld.long 0x00 23.--27. "DCC_BYPASS_UP_CODE_CTL_DBG2,DCC_BYPASS_UP_CODE_CTL_DBG2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 18.--22. "DCC_BYPASS_UP_CODE_CTL_DBG1,DCC_BYPASS_UP_CODE_CTL_DBG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--17. "DCC_CCO_GAIN_CTL,DCC_CCO_GAIN_CTL" "0: DCC_CCO_GAIN_CTL_0,1: DCC_CCO_GAIN_CTL_1,2: DCC_CCO_GAIN_CTL_2,3: DCC_CCO_GAIN_CTL_3"
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bitfld.long 0x00 13.--14. "ANA_TIMER_HYS_CTL,ANA_TIMER_HYS_CTL" "0: ANA_TIMER_HYS_CTL_0,1: ANA_TIMER_HYS_CTL_1,2: ANA_TIMER_HYS_CTL_2,3: ANA_TIMER_HYS_CTL_3"
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bitfld.long 0x00 12. "CLK_MISS_EN,CLK_MISS_EN" "0: CLK_MISS_EN_0,1: CLK_MISS_EN_1"
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bitfld.long 0x00 10.--11. "CLK_LANE_CAP_CTL_TCLK_MISS,CLK_LANE_CAP_CTL_TCLK_MISS" "0: CLK_LANE_CAP_CTL_TCLK_MISS_0,1: CLK_LANE_CAP_CTL_TCLK_MISS_1,2: CLK_LANE_CAP_CTL_TCLK_MISS_2,3: CLK_LANE_CAP_CTL_TCLK_MISS_3"
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bitfld.long 0x00 8.--9. "CLK_LANE_CAP_CTL_TCLK_SETTLE,CLK_LANE_CAP_CTL_TCLK_SETTLE" "0: CLK_LANE_CAP_CTL_TCLK_SETTLE_0,1: CLK_LANE_CAP_CTL_TCLK_SETTLE_1,2: CLK_LANE_CAP_CTL_TCLK_SETTLE_2,3: CLK_LANE_CAP_CTL_TCLK_SETTLE_3"
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bitfld.long 0x00 6.--7. "HS_RX_TERM_IMP_CTL,HS_RX_TERM_IMP_CTL" "0: HS_RX_TERM_IMP_CTL_0,1: HS_RX_TERM_IMP_CTL_1,2: HS_RX_TERM_IMP_CTL_2,3: HS_RX_TERM_IMP_CTL_3"
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bitfld.long 0x00 4.--5. "XXX,xxx" "0: XXX_0,1: XXX_1,2: XXX_2,3: XXX_3"
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bitfld.long 0x00 2.--3. "HS_RX_DELAY_CTRL,HS_RX_DELAY_CTRL" "0: HS_RX_DELAY_CTRL_0,1: HS_RX_DELAY_CTRL_1,2: HS_RX_DELAY_CTRL_2,3: HS_RX_DELAY_CTRL_3"
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bitfld.long 0x00 0.--1. "HS_RX_BIAS_CTL,HS_RX_BIAS_CTL" "0: HS_RX_BIAS_CTL_0,1: HS_RX_BIAS_CTL_1,2: HS_RX_BIAS_CTL_2,3: HS_RX_BIAS_CTL_3"
group.long 0x2C++0x03
line.long 0x00 "MIPI_S_DPHYCTL_HIGH,Master and Slave DPHY Control High Register"
bitfld.long 0x00 28.--31. "SKEW_CALIB_CMP_RUN_TIME_CTL,SKEW_CALIB_CMP_RUN_TIME_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 26.--27. "SKEW_CALIB_CMP_WAIT_TIME_CTL,SKEW_CALIB_CMP_WAIT_TIME_CTL" "0: SKEW_CALIB_CMP_WAIT_TIME_CTL_0,?,?,3: SKEW_CALIB_CMP_WAIT_TIME_CTL_3"
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bitfld.long 0x00 24.--25. "SKEW_CALIB_FAIL_TOL_CTL,SKEW_CALIB_FAIL_TOL_CTL" "0: Recognizes the pass although fail appears 3..,1: Recognizes the pass although fail appears 2..,2: Recognizes the pass although fail appears 1..,?..."
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bitfld.long 0x00 16.--21. "SKEW_CALIB_PASS_MIN_CTL,SKEW_CALIB_PASS_MIN_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SKEW_CALIB_FAIL_MIN_CTL,SKEW_CALIB_FAIL_MIN_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 2.--7. "SKEW_CALIB_MAX_CODE_CTL,SKEW_CALIB_MAX_CODE_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "SKEW_CALIB_EN,SKEW_CALIB_EN" "0: Skew Calibration Disable,1: Skew Calibration Enable"
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bitfld.long 0x00 0. "DCC_EN,DCC_EN" "0: DCC Disable,1: DCC Enable"
group.long 0x4C++0x03
line.long 0x00 "LCDIF_ARCACHE_CTRL,LCDIF ARCACHE Control Register"
bitfld.long 0x00 13.--15. "GPR_LCDIF_1_RD_HURRY,GPR_lcdif_1_rd_hurry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 10.--12. "GPR_LCDIF_0_RD_HURRY,GPR_lcdif_0_rd_hurry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--9. "GPR_ARCACHE_LCDIF2,Control LCDIF2 AXI master ARCACHE type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 5. "GPR_ARCACHE_LCDIF2_EN,AXI master ARCACHE control enable" "0: disable LCDIF2 AXI master ARCACHE control,1: enable LCDIF2 AXI master ARCACHE control"
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bitfld.long 0x00 1.--4. "GPR_ARCACHE_LCDIF,Control LCDIF AXI master ARCACHE type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "GPR_ARCACHE_LCDIF_EN,AXI master ARCACHE control enable" "0: disable LCDIF AXI master ARCACHE control,1: enable LCDIF AXI master ARCACHE control"
group.long 0x50++0x03
line.long 0x00 "ISI_CACHE_CTRL,ISI CACHE Control Register"
bitfld.long 0x00 26.--28. "GPR_ISI_V_WR_HURRY,GPR_ISI_v_wr_hurry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 23.--25. "GPR_ISI_U_WR_HURRY,GPR_ISI_u_wr_hurry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. "GPR_ISI_Y_WR_HURRY,GPR_ISI_y_wr_hurry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "GPR_AWCACHE_ISI_V,Control ISI V channel AXI master AWCACHE type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "GPR_AWCACHE_ISI_V_EN,ISI V channel AXI master AWCACHE control enable" "0: GPR_AWCACHE_ISI_V_EN_0,1: GPR_AWCACHE_ISI_V_EN_1"
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bitfld.long 0x00 11.--14. "GPR_AWCACHE_ISI_U,Control ISI U channel AXI master AWCACHE type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "GPR_AWCACHE_ISI_U_EN,ISI U channel AXI master AWCACHE control enable" "0: GPR_AWCACHE_ISI_U_EN_0,1: GPR_AWCACHE_ISI_U_EN_1"
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bitfld.long 0x00 6.--9. "GPR_AWCACHE_ISI_Y,Control ISI Y channel AXI master AWCACHE type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 5. "GPR_AWCACHE_ISI_Y_EN,ISI Y channel AXI master AWCACHE control enable" "0: GPR_AWCACHE_ISI_Y_EN_0,1: GPR_AWCACHE_ISI_Y_EN_1"
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bitfld.long 0x00 1.--4. "GPR_ARCACHE_ISI_Y,Control ISI Y channel AXI master ARCACHE type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "GPR_ARCACHE_ISI_Y_EN,ISI Y channel AXI master ARCACHE control enable" "0: GPR_ARCACHE_ISI_Y_EN_0,1: GPR_ARCACHE_ISI_Y_EN_1"
group.long 0x54++0x03
line.long 0x00 "LDO_CTRL,LDO Control Register"
bitfld.long 0x00 0.--4. "MIPI_DPHY_LDO_VOUT_CTRL,LDO output control port(high level 0.8v low level 0v)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x58++0x03
line.long 0x00 "LDO_TRIM,LDO Trim Register"
bitfld.long 0x00 0.--4. "MIPI_DPHY_LDO_VOUT_TRIM,LDO output trimming port(high level 0.8v low level 0v)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "LDB_CTRL,LDB Control Register"
bitfld.long 0x00 12. "REG_CH1_FIFO_RESET,reg_ch1_fifo_reset" "0,1"
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bitfld.long 0x00 11. "REG_CH0_FIFO_RESET,reg_ch0_fifo_reset" "0,1"
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bitfld.long 0x00 10. "DI1_VSYNC_POLARITY,di1 VSYNC polarity select" "0: DI1_VSYNC_POLARITY_0,1: DI1_VSYNC_POLARITY_1"
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bitfld.long 0x00 9. "DI0_VSYNC_POLARITY,di0 VSYNC polarity select" "0: DI0_VSYNC_POLARITY_0,1: DI0_VSYNC_POLARITY_1"
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bitfld.long 0x00 8. "CH1_BIT_MAPPING,ch1_bit_mapping" "0: CH1_BIT_MAPPING_0,1: CH1_BIT_MAPPING_1"
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bitfld.long 0x00 7. "CH1_DATA_WIDTH,ch1_data_width" "0,1"
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bitfld.long 0x00 6. "CH0_BIT_MAPPING,ch0_bit_mapping" "0: CH0_BIT_MAPPING_0,1: CH0_BIT_MAPPING_1"
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bitfld.long 0x00 5. "CH0_DATA_WIDTH,ch0_data_width" "0: CH0_DATA_WIDTH_0,1: CH0_DATA_WIDTH_1"
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bitfld.long 0x00 4. "SPLIT_MODE,split_mode" "0,1"
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bitfld.long 0x00 3. "CH1_DI_SELECT,ch1_di_select" "0: LDB data from source 0,1: LDB data from source 1"
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bitfld.long 0x00 2. "CH1_ENABLE,ch1_enable" "0,1"
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bitfld.long 0x00 1. "CH0_DI_SELECT,ch0_di_select" "0: LDB data from source 0,1: LDB data from source 1"
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bitfld.long 0x00 0. "CH0_ENABLE,ch0_enable" "0,1"
group.long 0x60++0x03
line.long 0x00 "GASKET_0_CTRL,Gasket 0 Control Register"
bitfld.long 0x00 20. "MIPI_CSI_HS_POLARITY,mipi_csi_hs_polarity" "0,1"
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bitfld.long 0x00 18.--19. "MIPI_CSI_VS_SEL,mipi_csi_vs_sel" "0,1,2,3"
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bitfld.long 0x00 17. "MIPI_ISP_LEFT_JUST_MODE,mipi_isp_left_just_mode" "0,1"
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bitfld.long 0x00 16. "GASKET_0_LINE_DOUBLING_EN,Gasket 0 output for ISI de-interlace line_doubling mode enable" "0: Gasket 0 not output for ISI de-interlace..,1: Gasket 0 output for ISI de-interlace.."
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bitfld.long 0x00 14.--15. "GASKET_0_SRC_SEL,Gasket 0 source when support ISI de-interlace line_doubling mode" "0: source from mipi_csi channel 0,1: source from mipi_csi channel 1,2: source from mipi_csi channel 2,3: source from mipi_csi channel 3"
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bitfld.long 0x00 8.--13. "GASKET_0_DATA_TYPE,Gasket 0 data type" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: GASKET_0_DATA_TYPE_24,25: GASKET_0_DATA_TYPE_25,26: GASKET_0_DATA_TYPE_26,?,28: YUV420 8-bit(Chroma Shifted Pixel Sampling),29: YUV420 10-bit(Chroma Shifted Pixel Sampling),30: GASKET_0_DATA_TYPE_30,31: GASKET_0_DATA_TYPE_31,?,?,34: GASKET_0_DATA_TYPE_34,35: GASKET_0_DATA_TYPE_35,36: GASKET_0_DATA_TYPE_36,?,?,?,40: GASKET_0_DATA_TYPE_40,41: GASKET_0_DATA_TYPE_41,42: GASKET_0_DATA_TYPE_42,43: GASKET_0_DATA_TYPE_43,44: GASKET_0_DATA_TYPE_44,45: GASKET_0_DATA_TYPE_45,?..."
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bitfld.long 0x00 6.--7. "GASKET_0_INTER_MODE,Gasket 0 interlace mode" "0: GASKET_0_INTER_MODE_0,1: GASKET_0_INTER_MODE_1,2: GASKET_0_INTER_MODE_2,?..."
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bitfld.long 0x00 4.--5. "GASKET_0_VC_ID,Gasket 0 Virtual channel identifier" "0,1,2,3"
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bitfld.long 0x00 3. "GASKET_0_YUV420_LINE_SEL,Gasket 0 YUV420 ODD/EVEN line first select" "0: Gasket 0 ODD line first for YUV420 data type,1: Gasket 0 EVEN line first for YUV420 data type"
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bitfld.long 0x00 2. "GASKET_0_LEFT_JUST_MODE,Gasket 0 Left justified mode" "0: unused LSB equal lease significant bit of..,1: unused LSB equal most significant bit of.."
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bitfld.long 0x00 1. "GASKET_0_DOUBLE_COMP,Gasket 0 double component enable" "0: Gasket 0 input single component per pixel..,1: Gasket 0 input double component per pixel.."
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bitfld.long 0x00 0. "GASKET_0_ENABLE,Gasket 0 enable" "0: Gasket output disable,1: Gasket 0 output enable"
group.long 0x64++0x03
line.long 0x00 "GASKET_0_HSIZE,Gasket 0 Video Horizontal Size Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_HSIZE,Gasket 0 video Horizontal size(count in pixel)"
group.long 0x68++0x03
line.long 0x00 "GASKET_0_VSIZE,Gasket 0 Video Vertical Size Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_VSIZE,Gasket 0 video Vertical size(count in line)"
group.long 0x6C++0x03
line.long 0x00 "GASKET_0_HFP,Gasket 0 Video Horizontal Front Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_HFP,Gasket 0 video Horizontal front porch(count in pixel)"
group.long 0x70++0x03
line.long 0x00 "GASKET_0_HBP,Gasket 0 Video Horizontal Back Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_HBP,Gasket 0 video Horizontal back porch(count in pixel)"
group.long 0x74++0x03
line.long 0x00 "GASKET_0_VFP,Gasket 0 Video Vertical Front Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_VFP,Gasket 0 video Vertical front porch(count in line)"
group.long 0x78++0x03
line.long 0x00 "GASKET_0_VBP,Gasket 0 Video Vertical Back Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_VBP,Gasket 0 video Vertical back porch(count in line)"
group.long 0x7C++0x03
line.long 0x00 "GASKET_0_ISI_PIXEL_CNT,Gasket 0 ISI Pixel Count Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_ISI_PIXEL_CNT,Gasket 0 output to ISI pixel count status"
group.long 0x80++0x03
line.long 0x00 "GASKET_0_ISI_LINE_CNT,Gasket 0 ISI Line Count Register"
hexmask.long 0x00 0.--31. 1. "GASKET_0_ISI_LINE_CNT,Gasket 0 output to ISI line count status"
group.long 0x84++0x03
line.long 0x00 "GASKET_0_ISI_PIXEL_CTRL,Gasket 0 ISI Pixel Control Information Register"
hexmask.long.word 0x00 0.--11. 1. "GASKET_0_ISI_PIXEL_CTRL,Gasket 0 output to ISI pixel control information status"
group.long 0x90++0x03
line.long 0x00 "GASKET_1_CTRL,Gasket 1 Control Register"
bitfld.long 0x00 20. "MIPI_CSI2_HS_POLARITY,mipi_csi2_hs_polarity" "0,1"
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bitfld.long 0x00 18.--19. "MIPI_CSI2_VS_SEL,mipi_csi2_vs_sel" "0,1,2,3"
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bitfld.long 0x00 17. "MIPI_ISP2_LEFT_JUST_MODE,mipi_isp2_left_just_mode" "0,1"
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bitfld.long 0x00 16. "GASKET_1_LINE_DOUBLING_EN,Gasket 1 output for ISI de-interlace line_doubling mode enable" "0: Gasket 0 not output for ISI de-interlace..,1: Gasket 1 output for ISI de-interlace.."
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bitfld.long 0x00 14.--15. "GASKET_1_SRC_SEL,Gasket 1 source when support ISI de-interlace line_doubling mode" "0: source from mipi_csi channel 0,1: source from mipi_csi channel 1,2: source from mipi_csi channel 2,3: source from mipi_csi channel 3"
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bitfld.long 0x00 8.--13. "GASKET_1_DATA_TYPE,Gasket 1 data type" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: GASKET_1_DATA_TYPE_24,25: GASKET_1_DATA_TYPE_25,26: GASKET_1_DATA_TYPE_26,?,28: YUV420 8-bit(Chroma Shifted Pixel Sampling),29: YUV420 10-bit(Chroma Shifted Pixel Sampling),30: GASKET_1_DATA_TYPE_30,31: GASKET_1_DATA_TYPE_31,?,?,34: GASKET_1_DATA_TYPE_34,35: GASKET_1_DATA_TYPE_35,36: GASKET_1_DATA_TYPE_36,?,?,?,40: GASKET_1_DATA_TYPE_40,41: GASKET_1_DATA_TYPE_41,42: GASKET_1_DATA_TYPE_42,43: GASKET_1_DATA_TYPE_43,44: GASKET_1_DATA_TYPE_44,45: GASKET_1_DATA_TYPE_45,?..."
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bitfld.long 0x00 6.--7. "GASKET_1_INTER_MODE,Gasket 1 interlace mode" "0: GASKET_1_INTER_MODE_0,1: GASKET_1_INTER_MODE_1,2: GASKET_1_INTER_MODE_2,?..."
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bitfld.long 0x00 4.--5. "GASKET_1_VC_ID,Gasket 1 Virtual channel identifier" "0,1,2,3"
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bitfld.long 0x00 3. "GASKET_1_YUV420_LINE_SEL,Gasket 1 YUV420 ODD/EVEN line first select" "0: Gasket 1 ODD line first for YUV420 data type,1: Gasket 1 EVEN line first for YUV420 data type"
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bitfld.long 0x00 2. "GASKET_1_LEFT_JUST_MODE,Gasket 1 Left justified mode" "0: unused LSB equal lease significant bit of..,1: unused LSB equal most significant bit of.."
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bitfld.long 0x00 1. "GASKET_1_DOUBLE_COMP,Gasket 1 double component enable" "0: Gasket 1 input single component per pixel..,1: Gasket 1 input double component per pixel.."
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bitfld.long 0x00 0. "GASKET_1_ENABLE,Gasket 1 enable" "0: Gasket output disable,1: Gasket 1 output enable"
group.long 0x94++0x03
line.long 0x00 "GASKET_1_HSIZE,Gasket 1 Video Horizontal Size Register"
hexmask.long 0x00 0.--31. 1. "GP0,Gasket 1 video Horizontal size(count in pixel)"
group.long 0x98++0x03
line.long 0x00 "GASKET_1_VSIZE,Gasket 1 Video Vertical Size Register"
hexmask.long 0x00 0.--31. 1. "GASKET_1_VSIZE,Gasket 1 video Vertical size(count in line)"
group.long 0x9C++0x03
line.long 0x00 "GASKET_1_HFP,Gasket 1 Video Horizontal Front Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_1_HFP,Gasket 1 video Horizontal front porch(count in pixel)"
group.long 0xA0++0x03
line.long 0x00 "GASKET_1_HBP,Gasket 1 Video Horizontal Back Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_1_HBP,Gasket 1 video Horizontal back porch(count in pixel)"
group.long 0xA4++0x03
line.long 0x00 "GASKET_1_VFP,Gasket 1 Video Vertical Front Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_1_VFP,Gasket 1 video Vertical front porch(count in line)"
group.long 0xA8++0x03
line.long 0x00 "GASKET_1_VBP,Gasket 1 Video Vertical Back Porch Register"
hexmask.long 0x00 0.--31. 1. "GASKET_1_VBP,Gasket 1 video Vertical back porch(count in line)"
group.long 0xAC++0x03
line.long 0x00 "GASKET_1_ISI_PIXEL_CNT,Gasket 1 ISI Pixel Count Register"
hexmask.long 0x00 0.--31. 1. "GASKET_1_ISI_PIXEL_CNT,Gasket 1 output to ISI pixel count status"
group.long 0xB0++0x03
line.long 0x00 "GASKET_1_ISI_LINE_CNT,Gasket 1 ISI Line Count Register"
hexmask.long 0x00 0.--31. 1. "GASKET_1_ISI_LINE_CNT,Gasket 1 output to ISI line count status"
group.long 0xB4++0x03
line.long 0x00 "GASKET_1_ISI_PIXEL_CTRL,Gasket 1 ISI Pixel Control Information Register"
hexmask.long.word 0x00 0.--11. 1. "GASKET_1_ISI_PIXEL_CTRL,Gasket 1 output to ISI pixel control information status"
group.long 0x120++0x03
line.long 0x00 "MIPI_B2_DPHYCTL_LOW,Master and Slave DPHY Control Low Register"
bitfld.long 0x00 30.--31. "USER_DATA_HS,User Data Pattern for HS Loopback mode" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BIAS_REF_VOLT_CTL,BIAS_REF_VOLT_CTL" "0: BIAS_REF_VOLT_CTL_0,1: BIAS_REF_VOLT_CTL_1,2: BIAS_REF_VOLT_CTL_2,3: BIAS_REF_VOLT_CTL_3"
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bitfld.long 0x00 27. "BGR_CHOPPER_FREQ_CTL,BGR_CHOPPER_FREQ_CTL" "0: BGR_CHOPPER_FREQ_CTL_0,1: BGR_CHOPPER_FREQ_CTL_1"
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bitfld.long 0x00 26. "REG_VALID_CTL_1_2,REG_VALID_CTL_1_2" "0: Internal 1.2V regulator,1: REG_VALID_CTL_1_2_1"
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bitfld.long 0x00 24.--25. "REG_LVL_CTL_1_2,REG_LVL_CTL_1_2" "0: REG_LVL_CTL_1_2_0,1: REG_LVL_CTL_1_2_1,2: REG_LVL_CTL_1_2_2,3: REG_LVL_CTL_1_2_3"
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bitfld.long 0x00 23. "REG_VALID_1_2,REG_VALID_1_2" "0: Use ulps_en signal,1: Use valid signal from 1.2V regulator"
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bitfld.long 0x00 21.--22. "LP_RX_HYS_CTL,LP_RX_HYS_CTL" "0: LP_RX_HYS_CTL_0,1: LP_RX_HYS_CTL_1,2: LP_RX_HYS_CTL_2,3: LP_RX_HYS_CTL_3"
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bitfld.long 0x00 20. "VREF_SRC_SEL,VREF_SRC_SEL" "0: Generated from the BGR,1: Generated from the current mirror"
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bitfld.long 0x00 18.--19. "LP_RX_VREF_LVL,LP_RX_VREF_LVL" "0: LP_RX_VREF_LVL_0,1: LP_RX_VREF_LVL_1,2: LP_RX_VREF_LVL_2,3: LP_RX_VREF_LVL_3"
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bitfld.long 0x00 17. "LP_RX_PULSE_REJ,LP_RX_PULSE_REJ" "0: LP_RX_PULSE_REJ_0,1: LP_RX_PULSE_REJ_1"
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bitfld.long 0x00 15.--16. "MSTR_CLK_SLEW_RATE_DOWN,MSTR_CLK_SLEW_RATE_DOWN" "0: MSTR_CLK_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 14. "MSTR_CLK_SLEW_RATE_UP,MSTR_CLK_SLEW_RATE_UP" "0: MSTR_CLK_SLEW_RATE_UP_0,1: MSTR_CLK_SLEW_RATE_UP_1"
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bitfld.long 0x00 13. "LP_CD_HYS,LP_CD_HYS" "0: LP_CD_HYS_0,1: LP_CD_HYS_1"
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bitfld.long 0x00 12. "BGR_CHOPPER_EN,BGR_CHOPPER_EN" "0: BGR_CHOPPER_EN_0,1: BGR_CHOPPER_EN_1"
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bitfld.long 0x00 11. "ERR_CONT_LP_EN,ERR_CONT_LP_EN" "0: ERR_CONT_LP_EN_0,1: ERR_CONT_LP_EN_1"
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bitfld.long 0x00 10. "TX_TRIGGER_CLK_EN,TX_TRIGGER_CLK_EN" "0: TX_TRIGGER_CLK_EN_0,1: TX_TRIGGER_CLK_EN_1"
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hexmask.long.word 0x00 0.--9. 1. "ULPS_EXIT_COUNTER,ULPS_EXIT_COUNTER"
group.long 0x124++0x03
line.long 0x00 "MIPI_B2_DPHYCTL_HIGH,Master and Slave DPHY Control High Register"
bitfld.long 0x00 30.--31. "MSTR_DATA3_SLEW_RATE_DOWN,MSTR_DATA3_SLEW_RATE_DOWN" "0: MSTR_DATA3_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 29. "MSTR_DATA3_SLEW_RATE_UP,MSTR_DATA3_SLEW_RATE_UP" "0: MSTR_DATA3_SLEW_RATE_UP_0,1: MSTR_DATA3_SLEW_RATE_UP_1"
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bitfld.long 0x00 27.--28. "MSTR_DATA2_SLEW_RATE_DOWN,MSTR_DATA2_SLEW_RATE_DOWN" "0: MSTR_DATA2_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 26. "MSTR_DATA2_SLEW_RATE_UP,MSTR_DATA2_SLEW_RATE_UP" "0: MSTR_DATA2_SLEW_RATE_UP_0,1: MSTR_DATA2_SLEW_RATE_UP_1"
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bitfld.long 0x00 24.--25. "MSTR_DATA1_SLEW_RATE_DOWN,MSTR_DATA1_SLEW_RATE_DOWN" "0: MSTR_DATA1_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 23. "MSTR_DATA1_SLEW_RATE_UP,MSTR_DATA1_SLEW_RATE_UP" "0: MSTR_DATA1_SLEW_RATE_UP_0,1: MSTR_DATA1_SLEW_RATE_UP_1"
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bitfld.long 0x00 21.--22. "MSTR_DATA0_SLEW_RATE_DOWN,MSTR_DATA0_SLEW_RATE_DOWN" "0: MSTR_DATA0_SLEW_RATE_DOWN_0,1: Decrease the slew rate by about 15%,2: Decrease the slew rate by about 15%,3: Decrease the slew rate by about 30%"
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bitfld.long 0x00 20. "MSTR_DATA0_SLEW_RATE_UP,MSTR_DATA0_SLEW_RATE_UP" "0: MSTR_DATA0_SLEW_RATE_UP_0,1: MSTR_DATA0_SLEW_RATE_UP_1"
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bitfld.long 0x00 14. "LP_VREF_REG_SRC_SEL,LP_VREF_REG_SRC_SEL" "0: LP_VREF_REG_SRC_SEL_0,1: Generated from Current Mirror"
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bitfld.long 0x00 13. "RX_SKEW_CALIB_FIX_CODE_EN,RX_SKEW_CALIB_FIX_CODE_EN" "0: RX_SKEW_CALIB_FIX_CODE_EN_0,1: RX_SKEW_CALIB_FIX_CODE_EN_1"
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bitfld.long 0x00 11. "DCC_DONE_CTL,DCC_DONE_CTL" "0: DONE from DCC block,1: U DONE is always 1"
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bitfld.long 0x00 8.--9. "BGR_VOLT_TUNING_CTL,BGR_VOLT_TUNING_CTL" "0: BGR_VOLT_TUNING_CTL_0,1: BGR_VOLT_TUNING_CTL_1,2: BGR_VOLT_TUNING_CTL_2,3: BGR_VOLT_TUNING_CTL_3"
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bitfld.long 0x00 6.--7. "HS_MODE_CTL,HS_MODE_CTL" "0: Designated Pattern,1: HS_MODE_CTL_1,2: HS_MODE_CTL_2,3: User Data Pattern"
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bitfld.long 0x00 0.--5. "USER_DATA_HS,User Data Pattern for HS Loopback mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "LVDS_CTRL,LVDS Control Register"
bitfld.long 0x00 17.--19. "VBG_ADJ,Bandgap adjustment" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 14.--16. "SLEW_ADJ,Output transition time adjustment" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 11.--13. "CC_ADJ,Output current adjustment" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "CM_ADJ,Output common mode(Vos) adjustment" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. "PRE_EMPH_ADJ,Pre-emphasis adjustment" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "PRE_EMPH_EN,Enable pre-emphasis" "0,1"
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bitfld.long 0x00 3. "HS_EN,hs_en" "?,1: enable the 100 Ohm terminated resistor in the.."
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bitfld.long 0x00 2. "VBG_EN,Bandgap enable" "0,1"
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bitfld.long 0x00 1. "CH1_EN,channel1 enable" "0,1"
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bitfld.long 0x00 0. "CH0_EN,channel0 enable" "0,1"
group.long 0x12C++0x03
line.long 0x00 "AXI_LIMIT_CONTROL,AXI Limit Control Register"
bitfld.long 0x00 3. "GPR_AXI_LIMIT_DEWARP_EN,gpr_axi_limit_dewarp_en" "0,1"
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bitfld.long 0x00 2. "GPR_AXI_LIMIT_ISI_EN,gpr_axi_limit_isi_en" "0,1"
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bitfld.long 0x00 1. "GPR_AXI_LIMIT_LCDIF1_EN,gpr_axi_limit_lcdif1_en" "0,1"
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bitfld.long 0x00 0. "GPR_AXI_LIMIT_LCDIF0_EN,gpr_axi_limit_lcdif0_en" "0,1"
group.long 0x130++0x03
line.long 0x00 "AXI_LIMIT_THRESH0,AXI Limit Threshold Register 0"
hexmask.long.word 0x00 16.--31. 1. "GPR_AXI_LIMIT_LCDIF1_THRESH,gpr_axi_limit_lcdif1_thresh"
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hexmask.long.word 0x00 0.--15. 1. "GPR_AXI_LIMIT_LCDIF0_THRESH,gpr_axi_limit_lcdif0_thresh"
group.long 0x134++0x03
line.long 0x00 "AXI_LIMIT_THRESH1,AXI Limit Threshold Register 1"
hexmask.long.word 0x00 16.--31. 1. "GPR_AXI_LIMIT_DEWARP_THRESH,gpr_axi_limit_dewarp_thresh"
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hexmask.long.word 0x00 0.--15. 1. "GPR_AXI_LIMIT_ISI_THRESH,gpr_axi_limit_isi_thresh"
group.long 0x138++0x03
line.long 0x00 "ISP_DEWARP_CONTROL,ISP Dewarp Control Register"
bitfld.long 0x00 23.--24. "ISP_ID_MODE,isp_id_mode" "0: vc_id_disable ID will not toggle during no..,1: vc_id_012 toggle 0 2 during no data transmit,2: vc_id_01 toggle 0 1 during no data transmit,3: vc_id_02 toggle 0 1 2 during no data transmit"
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bitfld.long 0x00 19. "MIPI_ISP2_LEFT_JUST_MODE,mipi_isp2_left_just_mode" "0,1"
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bitfld.long 0x00 13.--18. "MIPI_ISP2_DATA_TYPE,mipi_isp2_data_type" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,40: MIPI_ISP2_DATA_TYPE_40,41: MIPI_ISP2_DATA_TYPE_41,42: MIPI_ISP2_DATA_TYPE_42,43: MIPI_ISP2_DATA_TYPE_43,44: MIPI_ISP2_DATA_TYPE_44,45: MIPI_ISP2_DATA_TYPE_45,?..."
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bitfld.long 0x00 9. "MIPI_ISP_LEFT_JUST_MODE,mipi_isp_left_just_mode" "0,1"
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bitfld.long 0x00 3.--8. "MIPI_ISP_DATA_TYPE,mipi_isp_data_type" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,40: MIPI_ISP_DATA_TYPE_40,41: MIPI_ISP_DATA_TYPE_41,42: MIPI_ISP_DATA_TYPE_42,43: MIPI_ISP_DATA_TYPE_43,44: MIPI_ISP_DATA_TYPE_44,45: MIPI_ISP_DATA_TYPE_45,?..."
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bitfld.long 0x00 1. "GPR_ISP_1_DISABLE,gpr_isp_1_disable" "0,1"
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bitfld.long 0x00 0. "GPR_ISP_0_DISABLE,gpr_isp_0_disable" "0,1"
tree.end
tree "MIPI_CSI (MIPI CSI Host Controller)"
repeat 2. (list 1. 2.) (list ad:0x32E40000 ad:0x32E50000)
tree "MIPI_CSI$1"
base $2
group.long 0x04++0x03
line.long 0x00 "CSIS_COMMON_CTRL,CSIS Common Control Register"
bitfld.long 0x00 16. "UPDATE_SHADOW,Strobe of updating shadow registers" "0,1"
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bitfld.long 0x00 10.--11. "INTERLEAVE_MODE,Select Interleave mode" "0: CH0 only no data interleave,1: DT (Data type) only,?..."
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bitfld.long 0x00 8.--9. "LANE_NUMBER,Number of data lane" "0: LANE_NUMBER_0,1: LANE_NUMBER_1,2: LANE_NUMBER_2,3: LANE_NUMBER_3"
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bitfld.long 0x00 1. "SW_RESET,Software reset" "0: SW_RESET_0,1: SW_RESET_1"
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bitfld.long 0x00 0. "CSI_EN,MIPI CSI2 system enable" "0: CSI_EN_0,1: CSI_EN_1"
group.long 0x08++0x03
line.long 0x00 "CSIS_CLOCK_CTRL,CSIS Clock Control Register"
bitfld.long 0x00 16.--19. "CLKGATE_TRAIL,0 ~ 3 (1~4 Trailing clocks)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4. "CLKGATE_EN,no description available" "0: Pixel clock is always alive,1: Pixel clock is alive during the interval of.."
group.long 0x10++0x03
line.long 0x00 "INTERRUPT_MASK_0,Interrupt mask register 0"
bitfld.long 0x00 24. "MSK_FRAMESTART,FS packet is received CH0" "0: MSK_FRAMESTART_0,1: Enable (unmasked)"
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bitfld.long 0x00 20. "MSK_FRAMEEND,FE packet is received CH0" "0: Disable (masked),1: Enable (unmasked)"
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bitfld.long 0x00 16.--19. "MSK_ERR_SOT_HS,Start of transmission error [Lane3 Lane2 Lane1 Lane0]" "0: MSK_ERR_SOT_HS_0,1: Enable (unmasked),?..."
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bitfld.long 0x00 12. "MSK_ERR_LOST_FS,Lost of Frame Start packet CH0" "0: MSK_ERR_LOST_FS_0,1: MSK_ERR_LOST_FS_1"
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bitfld.long 0x00 8. "MSK_ERR_LOST_FE,Lost of Frame End packet CH0" "0: MSK_ERR_LOST_FE_0,1: MSK_ERR_LOST_FE_1"
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bitfld.long 0x00 4. "MSK_ERR_OVER,Image FIFO overflow interrupt" "0: Disable (masked),1: Enable (unmasked)"
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bitfld.long 0x00 3. "MSK_ERR_WRONG_CFG,Wrong configuration" "0: MSK_ERR_WRONG_CFG_0,1: MSK_ERR_WRONG_CFG_1"
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bitfld.long 0x00 2. "MSK_ERR_ECC,ECC error" "0: Disable (masked),1: Enable (unmasked)"
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bitfld.long 0x00 1. "MSK_ERR_CRC,CRC error" "0: Disable (masked),1: Enable (unmasked)"
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bitfld.long 0x00 0. "MSK_ERR_ID,Unknown ID error" "0: Disable (masked),1: Enable (unmasked)"
group.long 0x14++0x03
line.long 0x00 "INTERRUPT_SOURCE_0,Interrupt source register 0"
eventfld.long 0x00 24. "FRAME_START,FS packet is received CH0" "0,1"
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eventfld.long 0x00 20. "FRAME_END,FE packet is received CH0" "0,1"
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eventfld.long 0x00 16.--19. "ERR_SOT_HS,Start of transmission error [Lane3 Lane2 Lane1 Lane0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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eventfld.long 0x00 12. "ERR_LOST_FS,Indication of lost of Frame Start packet CH0" "0,1"
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eventfld.long 0x00 8. "ERR_LOST_FE,Indication of lost of Frame End packet CH0" "0,1"
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eventfld.long 0x00 4. "ERR_OVER,Overflow is caused in image FIFO" "0,1"
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eventfld.long 0x00 3. "ERR_WRONG_CFG,Wrong configuration" "0,1"
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eventfld.long 0x00 2. "ERR_ECC,ECC error" "0,1"
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eventfld.long 0x00 1. "ERR_CRC,CRC error" "0,1"
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eventfld.long 0x00 0. "ERR_ID,Unknown ID error" "0,1"
group.long 0x18++0x03
line.long 0x00 "INTERRUPT_MASK_1,Interrupt mask register 1"
eventfld.long 0x00 0. "MSK_LINE_END,End of specific line CH0" "0,1"
group.long 0x1C++0x03
line.long 0x00 "INTERRUPT_SOURCE_1,Interrupt source register 1"
eventfld.long 0x00 0. "LINE_END,End of specific line CH0" "0,1"
group.long 0x20++0x03
line.long 0x00 "DPHY_STATUS,D-PHY status register"
eventfld.long 0x00 8.--11. "ULPSDAT,Data lane [3:0] is in ULPS" "0: ULPSDAT_0,1: ULPSDAT_1,?..."
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rbitfld.long 0x00 4.--7. "STOPSTATEDAT,Data lane [3:0] is in Stop State" "0: STOPSTATEDAT_0,1: STOPSTATEDAT_1,?..."
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rbitfld.long 0x00 1. "ULPSCLK,no description available" "0: ULPSCLK_0,1: ULPSCLK_1"
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rbitfld.long 0x00 0. "STOPSTATECLK,Clock lane is in Stop State" "0: STOPSTATECLK_0,1: STOPSTATECLK_1"
group.long 0x24++0x03
line.long 0x00 "DPHY_COMMON_CTRL,D-PHY common control register"
hexmask.long.byte 0x00 24.--31. 1. "HSSETTLE,HS-RX settle time control"
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bitfld.long 0x00 22.--23. "S_CLKSETTLECTL,Slave clock lane control for Tclk-settle" "0,1,2,3"
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bitfld.long 0x00 6. "S_DPDN_SWAP_CLK,Swapping Dp and Dn channel of clock lane" "0: S_DPDN_SWAP_CLK_0,1: S_DPDN_SWAP_CLK_1"
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bitfld.long 0x00 5. "S_DPDN_SWAP_DAT,Swapping Dp and Dn channel of data lanes" "0: S_DPDN_SWAP_DAT_0,1: S_DPDN_SWAP_DAT_1"
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bitfld.long 0x00 1.--4. "ENABLE_DAT,D-PHY enable" "0: ENABLE_DAT_0,1: ENABLE_DAT_1,?..."
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bitfld.long 0x00 0. "ENABLE_CLK,D-PHY clock lane enable" "0: ENABLE_CLK_0,1: ENABLE_CLK_1"
group.long 0x30++0x03
line.long 0x00 "DPHY_MASTER_SLAVE_CTRL_LOW,D-PHY Master and Slave Control register Low"
bitfld.long 0x00 30.--31. "USER_DATA_PATTERN_LOW,User Data Pattern for HS Loopback mode" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BIAS_REF_VOLT,Bias Reference Voltage 710m Control" "0,1,2,3"
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bitfld.long 0x00 27. "BGR_CHOPPER_FREQ,BGR Chopper Frequency Control" "0,1"
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bitfld.long 0x00 26. "VREG12_EXTPWR_EN_CTL,VREG12_EXTPWR Enable Control (No regulator in JF)" "0,1"
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bitfld.long 0x00 24.--25. "REG_1P2_LVL_CTL,1.2V Regulator Level Control (No regulator in JF)" "0,1,2,3"
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bitfld.long 0x00 23. "REG_1P2_LVL_SEL,1.2V Regulator Valid Level Selection" "0,1"
newline
bitfld.long 0x00 21.--22. "LP_RX_HYS_LVL,LP-RX Hysteresis Level Control" "0,1,2,3"
newline
bitfld.long 0x00 20. "VREF_SRC_SEL,Vref Source Selection" "0,1"
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bitfld.long 0x00 18.--19. "LP_RX_VREF_LVL,LP-RX Vref Level Control" "0,1,2,3"
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bitfld.long 0x00 17. "LP_RX_PULSE_REJECT,LP-RX Pulse Rejection Control" "0,1"
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bitfld.long 0x00 15.--16. "MSTRCLK_LP_SLEW_RATE_DOWN,Master Clock Lane's LP-TX Driver Slew Rate Down Control" "0,1,2,3"
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bitfld.long 0x00 14. "MSTRCLK_LP_SLEW_RATE_UP,Master Clock Lane's LP-TX Driver Slew Rate Up Control" "0,1"
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bitfld.long 0x00 13. "LP_CD_HYS,LP-CD Hysteresis Level Control" "0,1"
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bitfld.long 0x00 12. "BGR_CHOPPER_EN,BGR Chopper Function Enable" "0,1"
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bitfld.long 0x00 11. "ERRCONTENTION_LP_EN,ErrContention LP Enable" "0,1"
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bitfld.long 0x00 10. "TXTRIGGER_CLK_EN,TxTrigger_Clk Enable" "0,1"
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hexmask.long.word 0x00 0.--9. 1. "B_DPHYCTRL,ULPS EXIT Counter Value Control"
group.long 0x34++0x03
line.long 0x00 "DPHY_MASTER_SLAVE_CTRL_HIGH,D-PHY Master and Slave Control register HIGH"
bitfld.long 0x00 30.--31. "MST_DATA3_TX_SLEW_DOWN,Master Data3 Lane's LP-TX Driver Slew Rate Down Control" "0,1,2,3"
newline
bitfld.long 0x00 29. "MST_DATA3_TX_SLEW_UP,Master Data3 Lane's LP-TX Driver Slew Rate Up Control" "0,1"
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bitfld.long 0x00 27.--28. "MST_DATA2_TX_SLEW_DOWN,Master Data2 Lane's LP-TX Driver Slew Rate Down Control" "0,1,2,3"
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bitfld.long 0x00 26. "MST_DATA2_TX_SLEW_UP,Master Data2 Lane's LP-TX Driver Slew Rate Up Control" "0,1"
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bitfld.long 0x00 24.--25. "MST_DATA1_TX_SLEW_DOWN,Master Data1 Lane's LP-TX Driver Slew Rate Down Control" "0,1,2,3"
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bitfld.long 0x00 23. "MST_DATA1_TX_SLEW_UP,Master Data1 Lane's LP-TX Driver Slew Rate Up Control" "0,1"
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bitfld.long 0x00 21.--22. "MST_DATA0_TX_SLEW_DOWN,Master Data0 Lane's LP-TX Driver Slew Rate Down Control" "0,1,2,3"
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bitfld.long 0x00 20. "MST_DATA0_TX_SLEW_UP,Master Data0 Lane's LP-TX Driver Slew Rate Up Control" "0,1"
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bitfld.long 0x00 14. "LP_REG_VREF_SRC_SEL,LP Regulator Vref Source Selection (No regulator in JF)" "0,1"
newline
bitfld.long 0x00 13. "RX_SKEW_CALIB_FIX_EN,RX Skew Calibration Fixing Code Enable/Disable Control" "0,1"
newline
bitfld.long 0x00 11. "DCC_DONE,DCC DONE Signal Control" "0,1"
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bitfld.long 0x00 8.--9. "BGR_VOLT_TUNE,BGR voltage tuning control" "0,1,2,3"
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bitfld.long 0x00 6.--7. "HS_LOOPBACK_MODE_CTL,HS Loopback Mode Control" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "USER_DATA_PATTERN_HIGH,User Data Pattern for HS Loopback mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "DPHY_SLAVE_CTRL_LOW,D-PHY Slave Control register Low"
bitfld.long 0x00 31. "DCC_STABLE,DCC Stable Control" "0,1"
newline
bitfld.long 0x00 28.--30. "DCC_INIT_TOLERANCE,DCC Initial Tolerance" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--17. "DCC_CCO_GAIN,DCC CCO Gain Control" "0,1,2,3"
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bitfld.long 0x00 13.--14. "ANA_TIMER_HYS,Analog Timer Hysteresis Control" "0,1,2,3"
newline
bitfld.long 0x00 12. "CLK_MISS_EN,Clock Miss Function Enable/Disable Control" "0,1"
newline
bitfld.long 0x00 10.--11. "CLOCK_LANE_CAP_TCLK_MISS,Clock Lane Cap" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "CLOCK_LANE_CAP_TCLK_SETTLE,Clock Lane Cap" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "HS_RX_TERMINATION_IMPEDENCE,HS-RX Termination Impedance Control" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "DATA_LANE_HS_RX_DELAY,Data Lane HS RX Delay Control" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "CLK_LANE_HS_RX_DELAY,Clock Lane HS RX Delay Control" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "HS_RX_BIAS,HS RX Bias Control" "0,1,2,3"
group.long 0x3C++0x03
line.long 0x00 "DPHY_SLAVE_CTRL_HIGH,D-PHY Slave Control register HIGH"
bitfld.long 0x00 28.--31. "RX_SKEW_CALIB_COMPARE_RUN_TIME,RX Skew Calibration Compare-run time Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 26.--27. "RX_SKEW_CALIB_COMPARE_WAIT_TIME,RX Skew Calibration Compare-wait time Control" "0,1,2,3"
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bitfld.long 0x00 24.--25. "RX_SKEW_CALIB_FAIL_TOLERANCE,RX Skew Calibration Fail-tolerance Control" "0,1,2,3"
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bitfld.long 0x00 16.--21. "RX_SKEW_CALIB_PASS_MIN,RX Skew Calibration Pass-min Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "RX_SKEW_CALIB_FAIL_MIN,RX Skew Calibration Fail-min Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 2.--7. "RX_SKEW_CALIB_MAX,RX Skew Calibration Max Code Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "SKEW_CALIB_EN,Skew Calibration Function Enable/Disable Control" "0,1"
newline
bitfld.long 0x00 0. "DCC_EN,DCC Function Enable/Disable Control" "0,1"
group.long 0x40++0x03
line.long 0x00 "ISP_CONFIG,ISP Configuration Register"
bitfld.long 0x00 12.--13. "PIXEL_MODE,Pixel mode selection" "0,1,2,3"
newline
bitfld.long 0x00 11. "PARALLEL,Output bus width of CH0 is 32 bits" "0: Normal output,1: 32bit data alignment"
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bitfld.long 0x00 10. "RGB_SWAP,Swapping RGB sequence" "0: MSB is R and LSB is B,1: MSB is B and LSB is R (swapped)"
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bitfld.long 0x00 2.--7. "DATAFORMAT,Image Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x44++0x03
line.long 0x00 "ISP_RESOLUTION,ISP Resolution Register"
hexmask.long.word 0x00 16.--31. 1. "VRESOL,Vertical Image resolution"
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hexmask.long.word 0x00 0.--15. 1. "HRESOL,Horizontal Image resolution"
group.long 0x48++0x03
line.long 0x00 "ISP_SYNC,ISP SYNC Register"
bitfld.long 0x00 18.--23. "HSYNC_LINTV,Interval between last falling of DVALID and falling of HSync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x80++0x03
line.long 0x00 "SHADOW_CONFIG,Shadow Configuration Register"
bitfld.long 0x00 12.--13. "PIXEL_MODE,Current pixel_mode" "0,1,2,3"
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bitfld.long 0x00 11. "PARALLEL_SDW,Current Parallel" "0,1"
newline
bitfld.long 0x00 10. "RGB_SWAP_SDW,Current RGB_SWAP" "0,1"
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bitfld.long 0x00 2.--7. "DATAFORMAT,Current Image Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x84++0x03
line.long 0x00 "SHADOW_RESOLUTION,Shadow Resolution Register"
hexmask.long.word 0x00 16.--31. 1. "VRESOL_SDW,Current Vertical Image resolution"
newline
hexmask.long.word 0x00 0.--15. 1. "HRESOL_SDW,Current Horizontal Image resolution"
rgroup.long 0x88++0x03
line.long 0x00 "SHADOW_SYNC,Shadow SYNC Register"
bitfld.long 0x00 18.--23. "HSYNC_LINTV_SDW,Current interval between Hsync falling and Hsync rising (Line interval)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x100++0x03
line.long 0x00 "FRAME_COUNTER,Frame Counter"
hexmask.long 0x00 0.--31. 1. "FRM_CNT,Number of input frames"
group.long 0x110++0x03
line.long 0x00 "LINE_INTERRUPT_RATIO,Line Interrupt Ratio"
hexmask.long 0x00 0.--31. 1. "LINE_INTR,The line number that user wants to set the line_end interrupt"
tree.end
repeat.end
tree.end
tree "MIPI_DSI (MIPI DSI Host Controller)"
base ad:0x32E10000
rgroup.long 0x00++0x03
line.long 0x00 "DSI_VERSION,Specifies the DSI version register"
hexmask.long 0x00 0.--31. 1. "Version,Specifies the DSI version information"
rgroup.long 0x04++0x03
line.long 0x00 "DSI_STATUS,Specifies the status register"
bitfld.long 0x00 31. "PllStable,D-phy pll generates stable byteclk" "0,1"
bitfld.long 0x00 20. "SwRstRls,Specifies the software reset status" "0: Reset state,1: Release state"
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bitfld.long 0x00 16. "Direction,Specifies the data direction indicator" "0: Forward direction,1: Backward direction"
bitfld.long 0x00 10. "TxReadyHsClk,Specifies the HS clock ready at clock lane" "0,1"
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bitfld.long 0x00 9. "UlpsClk,Specifies the ULPS indicator at clock lane" "0: No ULPS in clock lane,1: ULSP in clock lane"
bitfld.long 0x00 8. "StopstateClk,Specifies the stop state indicator at clock lane" "0,1"
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bitfld.long 0x00 4.--7. "UlpsDat,Specifies the ULPS indicator at data lanes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "StopstateDat,Specifies the stop state indicator at data lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x08++0x03
line.long 0x00 "DSI_RGB_STATUS,Specifies the RGB FSM status register"
bitfld.long 0x00 31. "CmdMode_InSel,Specifies the command mode input selection" "0: using RGB video interface,1: using S-i80 interface"
hexmask.long.word 0x00 0.--12. 1. "RGBstate,Specifies the RGB packetize FSM status"
group.long 0x0C++0x03
line.long 0x00 "DSI_SWRST,Specifies the software reset register"
bitfld.long 0x00 16. "FuncRst,Specifies the software reset (High active)" "0,1"
bitfld.long 0x00 0. "SwRst,Specifies the software reset (High active)" "0,1"
group.long 0x10++0x03
line.long 0x00 "DSI_CLKCTRL,Specifies the clock control register"
bitfld.long 0x00 31. "TxRequestHsClk,Specifies the HS clock request for HS transfer at clock lane (Turn on HS clock)" "0,1"
bitfld.long 0x00 29. "Dphy_sel,D-PHY select" "0: 1.5Gbps D-PHY (default),1: 1Gbps D-PHY"
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bitfld.long 0x00 28. "EscClkEn,Enables the escape clock generating prescaler" "0: Disables,1: Enables"
bitfld.long 0x00 27. "PLLBypass,Sets the PLLBypass signal connected to D-PHY module input for selecting clock source bit" "0,1"
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bitfld.long 0x00 25.--26. "ByteClkSrc,Selects byte clock source" "0,1,2,3"
bitfld.long 0x00 24. "ByteClkEn,Enables byte clock" "0: Disables,1: Enables"
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bitfld.long 0x00 19.--23. "LaneEscClkEn,Enables escape clock for D-phy lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "EscPrescaler,Specifies the escape clock prescaler value"
group.long 0x14++0x03
line.long 0x00 "DSI_TIMEOUT,Specifies the time out register"
hexmask.long.byte 0x00 16.--23. 1. "BtaTout,Specifies the timer for BTA"
hexmask.long.word 0x00 0.--15. 1. "LpdrTout,Specifies the timer for LP Rx mode timeout"
group.long 0x18++0x03
line.long 0x00 "DSI_CONFIG,Specifies the configuration register"
bitfld.long 0x00 31. "Non_Continuous_clock_lane,Non-continuous clock mode" "0,1"
bitfld.long 0x00 30. "Clklane_Stop_Start,PHY clock lane On/Off for ESD" "0,1"
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bitfld.long 0x00 29. "Mflush_VS,Auto flush of MD FIFO using Vsync pulse" "0,1"
bitfld.long 0x00 28. "EoT_r03,Disables EoT packet in HS mode" "0,1"
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bitfld.long 0x00 27. "SyncInform,Selects Sync Pulse or Event mode in Video mode" "0,1"
bitfld.long 0x00 26. "BurstMode,Selects Burst mode in Video mode In Non-burst mode RGB data area is filled with RGB data and Null packets according to input bandwidth of RGB interface" "0,1"
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bitfld.long 0x00 25. "VideoMode,Specifies display configuration" "0: Command mode,1: Video mode"
bitfld.long 0x00 24. "AutoMode,Specifies auto vertical count mode" "0,1"
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bitfld.long 0x00 23. "HseDisableMode,In Vsync pulse and Vporch area MIPI DSI master transfers only Hsync start packet to MIPI DSI slave at MIPI DSI spec 1" "0,1"
bitfld.long 0x00 22. "HfpDisableMode,Specifies HFP disable mode" "0,1"
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bitfld.long 0x00 21. "HbpDisableMode,Specifies HBP disable mode" "0,1"
bitfld.long 0x00 20. "HsaDisableMode,Specifies HSA disable mode" "0,1"
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bitfld.long 0x00 18.--19. "MainVc,Specifies virtual channel number for main display" "0,1,2,3"
bitfld.long 0x00 16.--17. "SubVc,Specifies virtual channel number for sub display" "0,1,2,3"
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bitfld.long 0x00 12.--14. "MainPixFormat,Specifies pixel stream format for main display" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "SubPixFormat,Specifies pixel stream format for sub display" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--6. "NumOfDatLane,Sets the data lane number" "0,1,2,3"
bitfld.long 0x00 0.--4. "LaneEn,Enables the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x03
line.long 0x00 "DSI_ESCMODE,Specifies the escape mode register"
hexmask.long.word 0x00 21.--31. 1. "STOPstate_Cnt,After transmitting read packet or write set_tear_on command BTA requests to D-phy automatically"
bitfld.long 0x00 20. "ForceStopstate_,Forces Stopstate for D-PHY" "0,1"
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bitfld.long 0x00 16. "ForceBta,Forces Bus Turn Around" "0,1"
bitfld.long 0x00 7. "CmdLpdt,Specifies LPDT transfers command in SFR FIFO" "0: HS Mode,1: LP Mode"
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bitfld.long 0x00 6. "TxLpdt,Specifies data transmission in LP mode (all data transfer in LPDT)" "0: HS Mode,1: LP Mode"
bitfld.long 0x00 4. "TxTriggerRst,Specifies remote reset trigger function" "0,1"
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bitfld.long 0x00 3. "TxUlpsDat,Specifies ULPS request for data lane" "0,1"
bitfld.long 0x00 2. "TxUlpsExit,Specifies ULPS exit request for data lane" "0,1"
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bitfld.long 0x00 1. "TxUlpsClk,Specifies ULPS request for clock lane" "0,1"
bitfld.long 0x00 0. "TxUlpsClkExit,Specifies ULPS exit request for clock lane" "0,1"
group.long 0x20++0x03
line.long 0x00 "DSI_MDRESOL,Specifies the main display image resolution register"
bitfld.long 0x00 31. "MainStandby,Specifies standby for receiving DISPCON output in Command mode after setting all configuration" "0,1"
hexmask.long.word 0x00 16.--27. 1. "MainVResol,Specifies Vertical resolution (1 ~ 2047)"
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hexmask.long.word 0x00 0.--11. 1. "MainHResol,Specifies Horizontal resolution (1 ~ 2047)"
group.long 0x24++0x03
line.long 0x00 "DSI_MVPORCH,Specifies the main display Vporch register"
bitfld.long 0x00 28.--31. "CmdAllow,Specifies the number of horizontal lines where command packet transmission is allowed after Stable VFP period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--26. 1. "StableVfp,Specifies the number of horizontal lines where command packet transmission is not allowed after end of active region"
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hexmask.long.word 0x00 0.--10. 1. "MainVbp,Specifies vertical back porch width for Video mode (line count)"
group.long 0x28++0x03
line.long 0x00 "DSI_MHPORCH,Specifies the main display Hporch register"
hexmask.long.word 0x00 16.--31. 1. "MainHfp,Specifies the horizontal front porch width for Video mode"
hexmask.long.word 0x00 0.--15. 1. "MainHbp,Specifies the horizontal back porch width for Video mode"
group.long 0x2C++0x03
line.long 0x00 "DSI_MSYNC,Specifies the main display Sync Area register"
hexmask.long.word 0x00 22.--31. 1. "MainVsa,Specifies the vertical sync pulse width for Video mode (Line count)"
hexmask.long.word 0x00 0.--15. 1. "MainHsa,Specifies the horizontal sync pulse width for Video mode"
group.long 0x30++0x03
line.long 0x00 "DSI_SDRESOL,Specifies the sub display image resolution register"
bitfld.long 0x00 31. "SubStandby,Specifies standby for receiving DISPCON output in Command mode after setting all configuration" "0,1"
hexmask.long.word 0x00 16.--26. 1. "SubVResol,Specifies the Vertical resolution (1 ~ 1024)"
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hexmask.long.word 0x00 0.--10. 1. "SubHResol,Specifies the Horizontal resolution (1 ~ 1024)"
group.long 0x34++0x03
line.long 0x00 "DSI_INTSRC,Specifies the interrupt source register"
bitfld.long 0x00 31. "PllStable,Indicates that D-phy PLL is stable" "0,1"
bitfld.long 0x00 30. "SwRstRelease,Releases the software reset" "0,1"
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bitfld.long 0x00 29. "SFRPLFifoEmpty,Specifies the SFR payload FIFO empty" "0,1"
bitfld.long 0x00 28. "SFRPHFifoEmpty,Specifies the SFR Packet Header FIFO empty" "0,1"
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bitfld.long 0x00 27. "SyncOverride,Indicates that other DSI command transfer have overridden sync timing" "0,1"
bitfld.long 0x00 25. "BusTurnOver,Indicates when bus grant turns over from DSI slave to DSI master" "0,1"
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bitfld.long 0x00 24. "FrameDone,Indicates when MIPI DSI transfers the whole image frame" "0,1"
bitfld.long 0x00 21. "LpdrTout,Specifies the LP Rx timeout" "0,1"
newline
bitfld.long 0x00 20. "TaTout,Turns around Acknowledge Timeout" "0,1"
bitfld.long 0x00 18. "RxDatDone,Completes receiving data" "0,1"
newline
bitfld.long 0x00 17. "RxTE,Receives TE Rx trigger" "0,1"
bitfld.long 0x00 16. "RxAck,Receives ACK Rx trigger" "0,1"
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bitfld.long 0x00 15. "ErrRxECC,Specifies the ECC multi bit error in LPDR" "0,1"
bitfld.long 0x00 14. "ErrRxCRC,Specifies the CRC error in LPDR" "0,1"
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bitfld.long 0x00 13. "ErrEsc3,Specifies the escape mode entry error lane 3" "0,1"
bitfld.long 0x00 12. "ErrEsc2,Specifies the escape mode entry error lane 2" "0,1"
newline
bitfld.long 0x00 11. "ErrEsc1,Specifies the escape mode entry error lane 1" "0,1"
bitfld.long 0x00 10. "ErrEsc0,Specifies the escape mode entry error lane 0" "0,1"
newline
bitfld.long 0x00 9. "ErrSync3,Specifies the LPDT sync error lane 3" "0,1"
bitfld.long 0x00 8. "ErrSync2,Specifies the LPDT Sync Error lane2" "0,1"
newline
bitfld.long 0x00 7. "ErrSync1,Specifies the LPDT Sync Error lane1" "0,1"
bitfld.long 0x00 6. "ErrSync0,Specifies the LPDT Sync Error lane0" "0,1"
newline
bitfld.long 0x00 5. "ErrControl3,Controls Error lane3" "0,1"
bitfld.long 0x00 4. "ErrControl2,Controls Error lane2" "0,1"
newline
bitfld.long 0x00 3. "ErrControl1,Controls Error lane1" "0,1"
bitfld.long 0x00 2. "ErrControl0,Controls Error lane0" "0,1"
newline
bitfld.long 0x00 1. "ErrContentLP0,Specifies the LP0 Contention Error (only lane0 because BTA occurs at lane0 only)" "0,1"
bitfld.long 0x00 0. "ErrContentLP1,Specifies the LP1 Contention Error (only lane0 because BTA occurs at lane0 only)" "0,1"
group.long 0x38++0x03
line.long 0x00 "DSI_INTMSK,Specifies the interrupt mask register"
bitfld.long 0x00 31. "MskPllStable,Indicates that D-PHY PLL is stable" "0,1"
bitfld.long 0x00 30. "MskSwRstRelease,Releases software reset" "0,1"
newline
bitfld.long 0x00 29. "MskSFRPLFifoEmpty,Empties SFR payload FIFO" "0,1"
bitfld.long 0x00 28. "MskSFRPHFifoEmpty,Interrupt Mask for SFR packet header FIFO empty" "0,1"
newline
bitfld.long 0x00 27. "MskSyncOverride,Indicates that other DSI command transfer have overridden sync timing" "0,1"
bitfld.long 0x00 25. "MskBusTurnOver,Indicates when bus grant turns over from DSI slave to DSI master" "0,1"
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bitfld.long 0x00 24. "MskFrameDone,Indicates when MIPI DSI transfers whole image frame" "0,1"
bitfld.long 0x00 21. "MskLpdrTout,Specifies LP Rx timeout" "0,1"
newline
bitfld.long 0x00 20. "MskTaTout,Specifies turnaround acknowledge timeout" "0,1"
bitfld.long 0x00 18. "MskRxDatDone,Specifies completion of data receiving" "0,1"
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bitfld.long 0x00 17. "MskRxTE,Specifies receipt of TE Rx trigger" "0,1"
bitfld.long 0x00 16. "MskRxAck,Specifies receipt of ACK Rx trigger" "0,1"
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bitfld.long 0x00 15. "MskRxECC,Specifies ECC multibit error in LPDR" "0,1"
bitfld.long 0x00 14. "MskRxCRC,Specifies CRC error in LPDR" "0,1"
newline
bitfld.long 0x00 13. "MskEsc3,Specifies escape mode entry error in lane3" "0,1"
bitfld.long 0x00 12. "MskEsc2,Specifies escape mode entry error in lane2" "0,1"
newline
bitfld.long 0x00 11. "MskEsc1,Specifies escape mode entry error in lane1" "0,1"
bitfld.long 0x00 10. "MskEsc0,Specifies escape mode entry error in lane0" "0,1"
newline
bitfld.long 0x00 9. "MskSync3,Specifies LPDT sync error in lane3" "0,1"
bitfld.long 0x00 8. "MskSync2,Specifies LPDT sync error in lane2" "0,1"
newline
bitfld.long 0x00 7. "MskSync1,Specifies LPDT sync error in lane1" "0,1"
bitfld.long 0x00 6. "MskSync0,Specifies LPDT sync error in lane0" "0,1"
newline
bitfld.long 0x00 5. "MskControl3,Controls error in lane3" "0,1"
bitfld.long 0x00 4. "MskControl2,Controls error in lane2" "0,1"
newline
bitfld.long 0x00 3. "MskControl1,Controls error in lane1" "0,1"
bitfld.long 0x00 2. "MskControl0,Controls error in lane0" "0,1"
newline
bitfld.long 0x00 1. "MskContentLP0,Specifies LP0 contention error" "0,1"
bitfld.long 0x00 0. "MskContentLP1,Specifies LP1 contention error" "0,1"
wgroup.long 0x3C++0x03
line.long 0x00 "DSI_PKTHDR,Specifies the packet header FIFO register"
hexmask.long.tbyte 0x00 0.--23. 1. "PacketHeader,Writes the packet header of Tx packet"
wgroup.long 0x40++0x03
line.long 0x00 "DSI_PAYLOAD,Specifies the payload FIFO register"
hexmask.long 0x00 0.--31. 1. "Payload,Writes the Payload of Tx packet"
rgroup.long 0x44++0x03
line.long 0x00 "DSI_RXFIFO,Specifies the read FIFO register"
hexmask.long 0x00 0.--31. 1. "RxDat,In the Rx mode you can read Rx data through this register"
group.long 0x48++0x03
line.long 0x00 "DSI_FIFOTHLD,Specifies the FIFO threshold level register"
hexmask.long.word 0x00 0.--8. 1. "WfullLevelSfr,Almost full level of SFR payload FIFO"
group.long 0x4C++0x03
line.long 0x00 "DSI_FIFOCTRL,Specifies the FIFO status and control register"
rbitfld.long 0x00 25. "FullRx,Rx FIFO full" "0,1"
rbitfld.long 0x00 24. "EmptyRx,Rx FIFO empty" "0,1"
newline
rbitfld.long 0x00 23. "FullHSfr,SFR packet header FIFO full" "0,1"
rbitfld.long 0x00 22. "EmptyHSfr,SFR packet header FIFO empty" "0,1"
newline
rbitfld.long 0x00 21. "FullLSfr,SFR payload FIFO full" "0,1"
rbitfld.long 0x00 20. "EmptyLSfr,SFR payload FIFO empty" "0,1"
newline
rbitfld.long 0x00 19. "FullHI80,S-i80 packet header FIFO full" "0,1"
rbitfld.long 0x00 18. "EmptyHI80,S-i80 packet header FIFO empty" "0,1"
newline
rbitfld.long 0x00 17. "FullLI80,S-i80 payload FIFO full" "0,1"
rbitfld.long 0x00 16. "EmptyLI80,S-i80 payload FIFO empty" "0,1"
newline
rbitfld.long 0x00 15. "FullHSub,Sub display packet header FIFO full" "0,1"
rbitfld.long 0x00 14. "EmptyHSub,Sub display packet header FIFO empty" "0,1"
newline
rbitfld.long 0x00 13. "FullLSub,Sub display payload FIFO full" "0,1"
rbitfld.long 0x00 12. "EmptyLSub,Sub display payload FIFO empty" "0,1"
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rbitfld.long 0x00 11. "FullHMain,Main display packet header FIFO full" "0,1"
rbitfld.long 0x00 10. "EmptyHMain,Main display packet header FIFO empty" "0,1"
newline
rbitfld.long 0x00 9. "FullLMain,Main display payload FIFO full" "0,1"
rbitfld.long 0x00 8. "EmptyLMain,Main display payload FIFO empty" "0,1"
newline
bitfld.long 0x00 4. "nInitRx,MD FIFO read point initialize" "0,1"
bitfld.long 0x00 3. "nInitSfr,SFR FIFO write point initialize" "0,1"
newline
bitfld.long 0x00 2. "nInitI80,S-i80 FIFO write point initialize" "0,1"
bitfld.long 0x00 1. "nInitSub,SD FIFO write point initialize" "0,1"
newline
bitfld.long 0x00 0. "nInitMain,MD FIFO write point initialize" "0,1"
group.long 0x50++0x03
line.long 0x00 "DSI_MEMACCHR,Specifies the FIFO memory AC characteristic register"
bitfld.long 0x00 15. "PGEN_SD,Sub display FIFO memory power gating" "0,1"
bitfld.long 0x00 14. "RETN_SD,Sub display FIFO memory Retention" "0,1"
newline
bitfld.long 0x00 11.--13. "EMAB_SD,Sub display FIFO memory B port margin adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "EMAA_SD,Sub display FIFO memory A port margin adjustment" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "PGEN_MD,Main display FIFO memory power gating" "0,1"
bitfld.long 0x00 6. "RETN_MD,Main display FIFO memory Retention" "0,1"
newline
bitfld.long 0x00 3.--5. "EMAB_MD,Main display FIFO memory B port margin adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "EMAA_MD,Main display FIFO memory A port margin adjustment" "0,1,2,3,4,5,6,7"
group.long 0x78++0x03
line.long 0x00 "DSI_MULTI_PKT,Specifies the Multi Packet Packet Go register"
bitfld.long 0x00 30. "Multi_PKT_EN,Specifies the send multi command packets on single transmission" "0,1"
bitfld.long 0x00 29. "PKT_Go_EN,Specifies the send command packet(s) per frame enable Packet go can transfer by only HS mode" "0,1"
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bitfld.long 0x00 28. "PKT_Go_Rdy,Specifies the send command packet(s) on this frame VFP" "0,1"
hexmask.long.word 0x00 16.--27. 1. "PKT_Send_Cnt_Ref,Specifies the command packet(s) send point indicator"
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hexmask.long.word 0x00 0.--15. 1. "Multi_PKT_Cnt_Ref,Specifies the number of packets on single transmission"
group.long 0x90++0x03
line.long 0x00 "DSI_PLLCTRL_1G,Specifies the 1Gbps D-PHY PLL control register"
bitfld.long 0x00 12.--15. "HSzeroCtl,1Gbps D-PHY HS-Zero driving timing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "Freq_Band,1Gbps D-PHY Timing control for D-PHY global operation timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--6. "PREPRCtl,1Gbps D-PHY PLL Tclk-prepare and Ths-prepare driving control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PRPRCtlClk,1Gbps D-PHY PLL Ths-prepare driving time control" "0,1,2,3,4,5,6,7"
group.long 0x94++0x03
line.long 0x00 "DSI_PLLCTRL,Specifies the PLL control register"
bitfld.long 0x00 25. "DpDnSwap_CLK,Swaps Dp/Dn channel of clock lane" "0,1"
bitfld.long 0x00 24. "DpDnSwap_DAT,Swaps Dp/Dn channel of Data lanes" "0,1"
newline
bitfld.long 0x00 23. "PllEn,Enables PLL" "0,1"
hexmask.long.tbyte 0x00 1.--19. 1. "PMS,Specifies the PLL PMS value"
group.long 0x98++0x03
line.long 0x00 "DSI_PLLCTRL1,Specifies the PLL control register 1"
hexmask.long 0x00 0.--31. 1. "M_PLLCTL0,M_PLLCTL[31:0] to D-PHY"
group.long 0x9C++0x03
line.long 0x00 "DSI_PLLCTRL2,Specifies the PLL control register 2"
hexmask.long.byte 0x00 0.--7. 1. "M_PLLCTL1,M_PLLCTL[39:32] to D-PHY"
group.long 0xA0++0x03
line.long 0x00 "DSI_PLLTMR,Specifies the PLL timer register"
hexmask.long 0x00 0.--31. 1. "PllTimer,Specifies the PLL Timer for stability of the generated clock (System clock cycle base)"
group.long 0xA4++0x03
line.long 0x00 "DSI_PHYCTRL_B1,Specifies the D-PHY control register 1"
hexmask.long 0x00 0.--31. 1. "B_DPHYCTL0,B_DPHYCTL[31:0] to D-PHY"
group.long 0xA8++0x03
line.long 0x00 "DSI_PHYCTRL_B2,Specifies the D-PHY control register 2"
hexmask.long 0x00 0.--31. 1. "B_DPHYCTL1,B_DPHYCTL[63:32] to D-PHY"
group.long 0xAC++0x03
line.long 0x00 "DSI_PHYCTRL_M1,Specifies the D-PHY control register 1"
hexmask.long 0x00 0.--31. 1. "M_DPHYCTL0,M_DPHYCTL[31:0] to D-PHY"
group.long 0xB0++0x03
line.long 0x00 "DSI_PHYCTRL_M2,Specifies the D-PHY control register 2"
hexmask.long 0x00 0.--31. 1. "M_DPHYCTL1,M_DPHYCTL[63:32] to D-PHY"
group.long 0xB4++0x03
line.long 0x00 "DSI_PHYTIMING,Specifies the D-PHY timing register"
hexmask.long.byte 0x00 8.--15. 1. "M_TLPXCTL,M_TLPXCTL[7:0] to D-PHY"
hexmask.long.byte 0x00 0.--7. 1. "M_THSEXITCTL,M_THSEXITCTL[7:0] to D-PHY"
group.long 0xB8++0x03
line.long 0x00 "DSI_PHYTIMING1,Specifies the D-PHY timing register 1"
hexmask.long.byte 0x00 24.--31. 1. "M_TCLKPRPRCTL,M_TCLKPRPRCTL[7:0] to D-PHY"
hexmask.long.byte 0x00 16.--23. 1. "M_TCLKZEROCTL,M_TCLKZEROCTL[7:0] to D-PHY"
newline
hexmask.long.byte 0x00 8.--15. 1. "M_TCLKPOSTCTL,M_TCLKPOSTCTL[7:0] to D-PHY"
hexmask.long.byte 0x00 0.--7. 1. "M_TCLKTRAILCTL,M_TCLKTRAILCTL[7:0] to D-PHY"
group.long 0xBC++0x03
line.long 0x00 "DSI_PHYTIMING2,Specifies the D-PHY timing register 2"
hexmask.long.byte 0x00 16.--23. 1. "M_THSPRPRCTL,M_THSPRPRCTL[7:0] to D-PHY"
hexmask.long.byte 0x00 8.--15. 1. "M_THSZEROCTL,M_THSZEROCTL[7:0] to D-PHY"
newline
hexmask.long.byte 0x00 0.--7. 1. "M_THSTRAILCTL,M_THSTRAILCTL[7:0] to D-PHY"
tree.end
tree "MUB (Messaging Unit Processor B-side)"
base ad:0x30AB0000
group.long 0x00++0x03
line.long 0x00 "BTR0,Processor B Transmit Register 0"
hexmask.long 0x00 0.--31. 1. "BTR0,Processor B Transmit Register 0"
group.long 0x04++0x03
line.long 0x00 "BTR1,Processor B Transmit Register 1"
hexmask.long 0x00 0.--31. 1. "BTR1,Processor B Transmit Register 1"
group.long 0x08++0x03
line.long 0x00 "BTR2,Processor B Transmit Register 2"
hexmask.long 0x00 0.--31. 1. "BTR2,Processor B Transmit Register 2"
group.long 0x0C++0x03
line.long 0x00 "BTR3,Processor B Transmit Register 3"
hexmask.long 0x00 0.--31. 1. "BTR3,Processor B Transmit Register 3"
rgroup.long 0x10++0x03
line.long 0x00 "BRR0,Processor B Receive Register 0"
hexmask.long 0x00 0.--31. 1. "BRR0,Processor B Receive Register 0"
rgroup.long 0x14++0x03
line.long 0x00 "BRR1,Processor B Receive Register 1"
hexmask.long 0x00 0.--31. 1. "BRR1,Processor B Receive Register 1"
rgroup.long 0x18++0x03
line.long 0x00 "BRR2,Processor B Receive Register 2"
hexmask.long 0x00 0.--31. 1. "BRR2,Processor B Receive Register 2"
rgroup.long 0x1C++0x03
line.long 0x00 "BRR3,Processor B Receive Register 3"
hexmask.long 0x00 0.--31. 1. "BRR3,Processor B Receive Register 3"
group.long 0x20++0x03
line.long 0x00 "BSR,Processor B Status Register"
bitfld.long 0x00 28.--31. "GIPn,For n = {0 1 2 3} Processor B General Interrupt Request n Pending" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
bitfld.long 0x00 24.--27. "RFn,For n = {0 1 2 3} Processor B Receive Register n Full" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
newline
bitfld.long 0x00 20.--23. "TEn,For n = {0 1 2 3} Processor B Transmit Register n Empty" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
bitfld.long 0x00 8. "FUP,Processor B Flags Update Pending" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
newline
bitfld.long 0x00 7. "ARS,Processor A Reset State" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
bitfld.long 0x00 5.--6. "APM,Processor A Power Mode" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
newline
bitfld.long 0x00 4. "EP,Processor B-Side Event Pending" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
bitfld.long 0x00 0.--2. "Fn,For n = {0 1 2} Processor B-Side Flag n" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
group.long 0x24++0x03
line.long 0x00 "BCR,Processor B Control Register"
bitfld.long 0x00 28.--31. "GIEn,For n = {0 1 2 3} Processor B General Purpose Interrupt Enable n" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
bitfld.long 0x00 24.--27. "RIEn,For n = {0 1 2 3} Processor B Receive Interrupt Enable n" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
newline
bitfld.long 0x00 20.--23. "TIEn,For n = {0 1 2 3} Processor B Transmit Interrupt Enable n" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
bitfld.long 0x00 16.--19. "GIRn,For n = {0 1 2 3} Processor B General Purpose Interrupt Request n" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
newline
bitfld.long 0x00 4. "HRM,Processor B Hardware Reset Mask" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
bitfld.long 0x00 0.--2. "BAFn,For n = {0 1 2} Processor B to Processor A Flag n" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
tree.end
tree "NPU"
base ad:0x38500000
group.long 0x00++0x03
line.long 0x00 "AQHiClockControl,Clock Control Register"
bitfld.long 0x00 20.--23. "MULTI_PIPE_REG_SEL,Multiple Pipe Register Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19. "ISOLATE_GPU,Isolate GPU" "0,1"
newline
rbitfld.long 0x00 16. "IDLE3_D,3D pipe is idle" "0,1"
bitfld.long 0x00 13. "DIS_RAM_PWR_OPT,Disable RAM power optimization" "0,1"
newline
bitfld.long 0x00 10. "DIS_RAM_CLK_GATING,Disable clock gating for RAMs" "0,1"
bitfld.long 0x00 9. "FSCALE_CMD_LOAD,Core clock frequency scale value enable" "?,1: The frequency scale factor is updated with.."
newline
hexmask.long.byte 0x00 2.--8. 1. "FSCALE_VAL,Core clock frequency scale value"
bitfld.long 0x00 1. "CLK2D_DIS,Disable 2D clock" "0,1"
newline
bitfld.long 0x00 0. "CLK3D_DIS,Disable 3D clock" "?,1: The clock is frozen"
rgroup.long 0x04++0x03
line.long 0x00 "AQHiIdle,Idle Status Register"
bitfld.long 0x00 31. "AXI_LP,AXI is in low power mode" "0,1"
bitfld.long 0x00 3. "IDLE_SH,SH is idle" "0,1"
newline
bitfld.long 0x00 0. "IDLE_FE,FE is idle" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "AQAxiStatus,AXI Status Register"
bitfld.long 0x00 9. "DET_RD_ERR,Detect Read Error" "?,1: Detect read error"
bitfld.long 0x00 8. "DET_WR_ERR,Detect Write Error" "?,1: Detect write error"
newline
bitfld.long 0x00 4.--7. "RD_ERR_ID,Read Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "WR_ERR_ID,Write Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x10++0x03
line.long 0x00 "AQIntrAcknowledge,Interrupt Acknowledge Register"
hexmask.long 0x00 0.--31. 1. "INTR_VEC,Interrupt Vector"
group.long 0x14++0x03
line.long 0x00 "AQIntrEnbl,Interrupt Enable Register"
hexmask.long 0x00 0.--31. 1. "INTR_ENBL_VEC,Interrupt Vector Enable"
group.long 0x78++0x03
line.long 0x00 "gcTotalCycles,Total Cycles Register"
hexmask.long 0x00 0.--31. 1. "CYCLES,Cycles"
group.long 0x100++0x03
line.long 0x00 "gcModulePowerControls,Module Power Level Control Register"
hexmask.long.word 0x00 16.--31. 1. "TURN_OFF_COUNTER,Counter value for clock gating the module if the module is idle for this amount of clock cycles"
bitfld.long 0x00 4.--7. "TURN_ON_COUNTER,Number of clock cycles to wait after turning on the clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "DIS_STARVE_MOD_CLK_GATING,Disables module level clock gating for starve/idle condition" "0,1"
bitfld.long 0x00 1. "DIS_STALL_MOD_CLK_GATING,Disables module level clock gating for stall condition" "0,1"
newline
bitfld.long 0x00 0. "EN_MOD_CLK_GATING,Enables module level clock gating" "0,1"
group.long 0x10C++0x03
line.long 0x00 "gcPulseEater,Pulse eater Control Register"
hexmask.long.byte 0x00 1.--7. 1. "FSCALE_VAL_SH,Fscale value for shader"
bitfld.long 0x00 0. "FSCALE_CMD_LOAD_SH,Fscale_cmd_load for shader" "0,1"
group.long 0x388++0x03
line.long 0x00 "gcregMMUAHBControl,MMU Control Register"
bitfld.long 0x00 0. "MMU,Enable the MMU" "0: DISABLE,1: ENABLE"
group.long 0x38C++0x03
line.long 0x00 "gcregMMUAHBTableArrayBaseAddressLow,MMU Table Array Base Lower 32-bit Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address"
group.long 0x390++0x03
line.long 0x00 "gcregMMUAHBTableArrayBaseAddressHigh,MMU Table Array Base Higher 32-bit Address Register"
bitfld.long 0x00 9. "MASTER_TLB_SHAREABLE,Bit that defines whether the master TLB address is shareable or not" "0,1"
bitfld.long 0x00 8. "MASTER_TLB_SECURE,Bit that defines whether the master TLB address is secure or not" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "MASTER_TLB,Upper 8-bits of the master TLB address to form a true 40-bit address"
group.long 0x394++0x03
line.long 0x00 "gcregMMUAHBTableArraySize,MMU Table Array Size Control Register"
hexmask.long.word 0x00 0.--15. 1. "SIZE,Size"
group.long 0x398++0x03
line.long 0x00 "gcregMMUAHBSafeNonSecureAddress,MMU NonSecure Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address"
group.long 0x39C++0x03
line.long 0x00 "gcregMMUAHBSafeSecureAddress,MMU Secure Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address"
wgroup.long 0x3A4++0x03
line.long 0x00 "gcregCmdBufferAHBCtrl,Command Buffer Control Register"
bitfld.long 0x00 16. "ENABLE,Enable the command parser" "0: DISABLE,1: ENABLE"
hexmask.long.word 0x00 0.--15. 1. "PREFETCH,Prefetch"
group.long 0x3A8++0x03
line.long 0x00 "gcregHiAHBControl,MMU Host Interface Control Register"
bitfld.long 0x00 1. "DEBUG_MODE,Debug Mode" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "SOFT_RESET,Soft Reset" "0: DISABLE,1: ENABLE"
group.long 0x3AC++0x03
line.long 0x00 "gcregAxiAHBConfig,MMU AXI Configuration Register"
bitfld.long 0x00 20.--23. "AXCACHE_OVERRIDE_SHARED,Ax Cache value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18.--19. "AXDOMAIN_NON_SHARED,Ax Domain value" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "AXDOMAIN_SHARED,Ax Domain value" "0,1,2,3"
bitfld.long 0x00 12.--15. "ARCACHE,AR Cache value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "AWCACHE,AW Cache value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ARID,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "AWID,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x414++0x03
line.long 0x00 "AQMemoryDebug,Memory Debug Register"
hexmask.long.byte 0x00 0.--7. 1. "MAX_OUTSTANDING_READS,Maximum Outstanding Reads"
group.long 0x42C++0x03
line.long 0x00 "AQRegisterTimingControl,Register Timing Control Register"
bitfld.long 0x00 22. "LIGHT_SLEEP,Light sleep" "0,1"
bitfld.long 0x00 21. "DEEP_SLEEP,Deep sleep" "0,1"
newline
bitfld.long 0x00 20. "POWER_DOWN,Power Down Memory" "0,1"
bitfld.long 0x00 18.--19. "FAST_WTC,WTC for fast RAM" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "FAST_RTC,RTC for fast RAM" "0,1,2,3"
hexmask.long.byte 0x00 8.--15. 1. "FOR_RF2P,For 2 port RAM"
newline
hexmask.long.byte 0x00 0.--7. 1. "FOR_RF1P,For 1 port RAM"
wgroup.long 0x654++0x03
line.long 0x00 "AQCmdBufferAddr,Command Buffer Base Address Register"
bitfld.long 0x00 31. "TYPE,Type" "0: System,1: Virtual System"
hexmask.long 0x00 0.--30. 1. "ADDRESS,Address"
rgroup.long 0x664++0x03
line.long 0x00 "AQFEDebugCurCmdAdr,Command Decoder Address Register"
hexmask.long 0x00 3.--31. 1. "CUR_CMD_ADR,Command decoder Address"
tree.end
tree "OCOTP (OCOTP Register Reference Index)"
base ad:0x30350000
group.long 0x00++0x03
line.long 0x00 "HW_CTRL,OTP Controller Control Register"
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
bitfld.long 0x00 11. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
newline
bitfld.long 0x00 10. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
rbitfld.long 0x00 9. "BUSY,OTP controller status bit" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "ADDR,OTP write and read access address register"
group.long 0x04++0x03
line.long 0x00 "HW_CTRL_SET,OTP Controller Control Register"
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
bitfld.long 0x00 10. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
newline
bitfld.long 0x00 9. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
rbitfld.long 0x00 8. "BUSY,OTP controller status bit" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "ADDR,OTP write and read access address register"
group.long 0x08++0x03
line.long 0x00 "HW_CTRL_CLR,OTP Controller Control Register"
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
bitfld.long 0x00 10. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
newline
bitfld.long 0x00 9. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
rbitfld.long 0x00 8. "BUSY,OTP controller status bit" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "ADDR,OTP write and read access address register"
group.long 0x0C++0x03
line.long 0x00 "HW_CTRL_TOG,OTP Controller Control Register"
hexmask.long.word 0x00 16.--31. 1. "WR_UNLOCK,Write 0x3E77 to enable OTP write accesses"
bitfld.long 0x00 10. "RELOAD_SHADOWS,Set to force re-loading the shadow registers (HW/SW capability and LOCK)" "0,1"
newline
bitfld.long 0x00 9. "ERROR,Set by the controller when an access to a locked region(OTP or shadow register) is requested" "0,1"
rbitfld.long 0x00 8. "BUSY,OTP controller status bit" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "ADDR,OTP write and read access address register"
group.long 0x10++0x03
line.long 0x00 "HW_TIMING,OTP Controller Timing Register"
bitfld.long 0x00 22.--27. "WAIT,This count value specifies time interval between auto read and write access in one time program" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "STROBE_READ,This count value specifies the strobe period in one time read OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--15. "RELAX,This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "STROBE_PROG,This count value specifies the strobe period in one time write OTP"
group.long 0x20++0x03
line.long 0x00 "HW_DATA,OTP Controller Write Data Register"
hexmask.long 0x00 0.--31. 1. "DATA,Used to initiate a write to OTP"
group.long 0x30++0x03
line.long 0x00 "HW_READ_CTRL,OTP Controller Write Data Register"
bitfld.long 0x00 0. "READ_FUSE,Used to initiate a read to OTP" "0,1"
group.long 0x40++0x03
line.long 0x00 "HW_READ_FUSE_DATA,OTP Controller Read Data Register"
hexmask.long 0x00 0.--31. 1. "DATA,The data read from OTP"
group.long 0x60++0x03
line.long 0x00 "HW_SCS,Software Controllable Signals Register"
bitfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
newline
bitfld.long 0x00 0. "HAB_JDE,HAB JTAG Debug Enable" "0,1"
group.long 0x64++0x03
line.long 0x00 "HW_SCS_SET,Software Controllable Signals Register"
bitfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
group.long 0x68++0x03
line.long 0x00 "HW_SCS_CLR,Software Controllable Signals Register"
bitfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
group.long 0x6C++0x03
line.long 0x00 "HW_SCS_TOG,Software Controllable Signals Register"
bitfld.long 0x00 31. "LOCK,When set all of the bits in this register are locked and can not be changed through SW programming" "0,1"
hexmask.long 0x00 1.--30. 1. "SPARE,Unallocated read/write bits for implementation specific software use"
rgroup.long 0x90++0x03
line.long 0x00 "HW_VERSION,OTP Controller Version Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value reflecting the MAJOR field of the RTL version"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value reflecting the MINOR field of the RTL version"
newline
hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the RTL version"
rgroup.long 0x400++0x03
line.long 0x00 "HW_LOCK,Value of OTP Bank0 Word0 (Lock controls)"
bitfld.long 0x00 22.--23. "GP2,Status of shadow register and OTP write lock for gp2 region" "0,1,2,3"
bitfld.long 0x00 20.--21. "GP1,Status of shadow register and OTP write lock for gp1 region" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "MAC_ADDR,Status of shadow register and OTP write lock for mac_addr region" "0,1,2,3"
bitfld.long 0x00 12.--13. "USB_ID,Status of shadow register and OTP write lock for usb_id region" "0,1,2,3"
newline
bitfld.long 0x00 10. "SJC_RESP,Status of shadow register read and write OTP read and write lock for sjc_resp region" "0,1"
bitfld.long 0x00 2.--3. "BOOT_CFG,Status of shadow register and OTP write lock for boot_cfg region" "0,1,2,3"
group.long 0x470++0x03
line.long 0x00 "HW_BOOT_CFG0,Value of OTP Bank1 Word3 (Boot Configuration Info.)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 1 word 3"
group.long 0x480++0x03
line.long 0x00 "HW_BOOT_CFG1,Value of OTP Bank2 Word0 (Boot Configuration Info.)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 2 word 0"
group.long 0x490++0x03
line.long 0x00 "HW_BOOT_CFG2,Value of OTP Bank2 Word1 (Boot Configuration Info.)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 2 word 1"
group.long 0x4A0++0x03
line.long 0x00 "HW_BOOT_CFG3,Value of OTP Bank2 Word2 (Boot Configuration Info.)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 2 word 2"
group.long 0x4B0++0x03
line.long 0x00 "HW_BOOT_CFG4,Value of OTP Bank2 Word3 (BOOT Configuration Info.)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP bank 2 word 3"
group.long 0x600++0x03
line.long 0x00 "HW_SJC_RESP0,Value of OTP Bank8 Word0 (Secure JTAG Response Field)"
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 8 word 0)"
group.long 0x610++0x03
line.long 0x00 "HW_SJC_RESP1,Value of OTP Bank8 Word1 (Secure JTAG Response Field)"
hexmask.long 0x00 0.--31. 1. "BITS,Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 8 word 1)"
group.long 0x620++0x03
line.long 0x00 "HW_USB_ID,Value of OTP Bank8 Word2 (USB ID info)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 8 word 2"
group.long 0x640++0x03
line.long 0x00 "HW_MAC_ADDR0,Value of OTP Bank9 Word0 (MAC Address)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 9 word 0"
group.long 0x650++0x03
line.long 0x00 "HW_MAC_ADDR1,Value of OTP Bank9 Word1 (MAC Address)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 9 word 1"
group.long 0x660++0x03
line.long 0x00 "HW_MAC_ADDR2,Value of OTP Bank9 Word2 (MAC Address)"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 9 word 2"
group.long 0x780++0x03
line.long 0x00 "HW_GP10,Value of OTP Bank14 Word0 ()"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 14 word 0"
group.long 0x790++0x03
line.long 0x00 "HW_GP11,Value of OTP Bank14 Word1 ()"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 14 word 1"
group.long 0x7A0++0x03
line.long 0x00 "HW_GP20,Value of OTP Bank14 Word2 ()"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 14 word 2"
group.long 0x7B0++0x03
line.long 0x00 "HW_GP21,Value of OTP Bank14 Word3 ()"
hexmask.long 0x00 0.--31. 1. "BITS,Reflects value of OTP Bank 14 word 3"
tree.end
tree "PCIE (PCI Express Interface)"
base ad:0x33800000
group.long 0x00++0x03
line.long 0x00 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register"
hexmask.long.word 0x00 16.--31. 1. "DEVICE_ID,Device ID"
newline
hexmask.long.word 0x00 0.--15. 1. "VENDOR_ID,Vendor ID"
group.long 0x04++0x03
line.long 0x00 "TYPE1_STATUS_COMMAND_REG,Status and Command Register"
eventfld.long 0x00 31. "DETECTED_PARITY_ERROR,Detected Parity Error" "0,1"
newline
eventfld.long 0x00 30. "SIGNALED_SYS_ERROR,Signaled System Error" "0,1"
newline
eventfld.long 0x00 29. "RCVD_MASTER_ABORT,Received Master Abort" "0,1"
newline
eventfld.long 0x00 28. "RCVD_TARGET_ABORT,Received Target Abort" "0,1"
newline
eventfld.long 0x00 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort" "0,1"
newline
rbitfld.long 0x00 25.--26. "DEV_SEL_TIMING,DEVSEL Timing" "0,1,2,3"
newline
eventfld.long 0x00 24. "MASTER_DPE,Master Data Parity Error" "0,1"
newline
rbitfld.long 0x00 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable" "0,1"
newline
rbitfld.long 0x00 22. "RSVDP_22,Reserved for future use" "0,1"
newline
rbitfld.long 0x00 21. "FAST_66MHZ_CAP,66 MHz Capable" "0,1"
newline
rbitfld.long 0x00 20. "CAP_LIST,Capabilities List" "0,1"
newline
rbitfld.long 0x00 19. "INT_STATUS,Interrupt Status" "0,1"
newline
rbitfld.long 0x00 17.--18. "RSVDP_17,Reserved for future use" "0,1,2,3"
newline
rbitfld.long 0x00 11.--15. "RESERV,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10. "INT_EN,Interrupt Disable" "0,1"
newline
rbitfld.long 0x00 9. "RSVDP_9,Reserved for future use" "0,1"
newline
bitfld.long 0x00 8. "SERREN,SERR# Enable" "0,1"
newline
rbitfld.long 0x00 7. "IDSEL,IDSEL Stepping/Wait Cycle Control" "0,1"
newline
bitfld.long 0x00 6. "PERREN,Parity Error Response" "0,1"
newline
rbitfld.long 0x00 5. "VGAPS,VGA Palette Snoop" "0,1"
newline
rbitfld.long 0x00 4. "MWI_EN,Memory Write and Invalidate" "0,1"
newline
rbitfld.long 0x00 3. "SCO,Special Cycle Enable" "0,1"
newline
bitfld.long 0x00 2. "BME,Bus Master Enable" "0,1"
newline
bitfld.long 0x00 1. "MSE,Memory Space Enable" "0,1"
newline
bitfld.long 0x00 0. "IO_EN,IO Space Enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register"
hexmask.long.byte 0x00 24.--31. 1. "BASE_CLASS_CODE,Base Class Code"
newline
hexmask.long.byte 0x00 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code"
newline
hexmask.long.byte 0x00 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface"
newline
hexmask.long.byte 0x00 0.--7. 1. "REVISION_ID,Revision ID"
group.long 0x0C++0x03
line.long 0x00 "TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,Header Type Latency Timer and Cache Line Size Register"
hexmask.long.byte 0x00 24.--31. 1. "BIST,BIST"
newline
rbitfld.long 0x00 23. "MULTI_FUNC,Multi-Function Device" "0,1"
newline
hexmask.long.byte 0x00 16.--22. 1. "HEADER_TYPE,Header Layout"
newline
hexmask.long.byte 0x00 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer"
newline
hexmask.long.byte 0x00 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size"
group.long 0x18++0x03
line.long 0x00 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer Subordinate Bus Number Secondary Bus Number and Primary Bus Number Register"
hexmask.long.byte 0x00 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer"
newline
hexmask.long.byte 0x00 16.--23. 1. "SUB_BUS,Subordinate Bus Number"
newline
hexmask.long.byte 0x00 8.--15. 1. "SEC_BUS,Secondary Bus Number"
newline
hexmask.long.byte 0x00 0.--7. 1. "PRIM_BUS,Primary Bus Number"
group.long 0x1C++0x03
line.long 0x00 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status and I/O Limit and Base Register"
eventfld.long 0x00 31. "SEC_STAT_DPE,Detected Parity Error" "0,1"
newline
eventfld.long 0x00 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error" "0,1"
newline
eventfld.long 0x00 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort" "0,1"
newline
eventfld.long 0x00 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort" "0,1"
newline
eventfld.long 0x00 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort" "0,1"
newline
rbitfld.long 0x00 25.--26. "RSVDP_25,Reserved for future use" "0,1,2,3"
newline
eventfld.long 0x00 24. "SEC_STAT_MDPE,Master Data Parity Error" "0,1"
newline
rbitfld.long 0x00 23. "RSVDP_23,Reserved for future use" "0,1"
newline
hexmask.long.byte 0x00 16.--22. 1. "SEC_STAT_RESERV,Reserved"
newline
bitfld.long 0x00 12.--15. "IO_LIMIT,I/O Limit Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 9.--11. "IO_RESERV1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address)" "0: The bridge supports only 16-bit I/O addressing,1: The bridge supports 32-bit I/O address decoding"
newline
bitfld.long 0x00 4.--7. "IO_BASE,I/O Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 1.--3. "IO_RESERV,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge" "0: The bridge supports only 16-bit I/O addressing,1: The bridge supports 32-bit I/O address decoding"
group.long 0x20++0x03
line.long 0x00 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register"
hexmask.long.word 0x00 20.--31. 1. "MEM_LIMIT,Memory Limit Address"
newline
rbitfld.long 0x00 16.--19. "MEM_LIMIT_RESERV,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 4.--15. 1. "MEM_BASE,Memory Base Address"
newline
rbitfld.long 0x00 0.--3. "MEM_BASE_RESERV,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register"
hexmask.long.word 0x00 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address"
newline
rbitfld.long 0x00 17.--19. "PREF_RESERV1,Reserved" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode" "0: Indicates that the bridge supports only 32 bit,1: Indicates that the bridge supports 64 bit"
newline
hexmask.long.word 0x00 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address"
newline
rbitfld.long 0x00 1.--3. "PREF_RESERV,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode" "0: Indicates that the bridge supports only 32 bit,1: Indicates that the bridge supports 64 bit"
rgroup.long 0x28++0x03
line.long 0x00 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register"
hexmask.long 0x00 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit"
rgroup.long 0x2C++0x03
line.long 0x00 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register"
hexmask.long 0x00 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit"
rgroup.long 0x30++0x03
line.long 0x00 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register"
hexmask.long.word 0x00 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits"
newline
hexmask.long.word 0x00 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits"
group.long 0x34++0x03
line.long 0x00 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RSVDP_8,Reserved for future use"
newline
hexmask.long.byte 0x00 0.--7. 1. "CAP_POINTER,Capabilities Pointer"
group.long 0x38++0x03
line.long 0x00 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register"
hexmask.long.tbyte 0x00 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address"
newline
hexmask.long.word 0x00 1.--10. 1. "RSVDP_1,Reserved for future use"
newline
bitfld.long 0x00 0. "ROM_BAR_ENABLE,Expansion ROM Enable" "0,1"
group.long 0x3C++0x03
line.long 0x00 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control Interrupt Pin and Interrupt Line Register"
hexmask.long.word 0x00 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved"
newline
bitfld.long 0x00 22. "SBR,Secondary Bus Reset" "0,1"
newline
rbitfld.long 0x00 21. "MSTR_ABORT_MODE,Master Abort Mode" "0,1"
newline
rbitfld.long 0x00 20. "VGA_16B_DEC,VGA 16 bit decode" "0: Execute 10-bit address decodes on VGA I/O..,1: Execute 16-bit address decodes on VGA I/O"
newline
rbitfld.long 0x00 19. "VGA_EN,VGA Enable" "0: Do not forward VGA compatible memory and I/O,1: Forward VGA compatible memory and I/O addresses"
newline
bitfld.long 0x00 18. "ISA_EN,ISA Enable" "0: Forward downstream all I/O addresses in the,1: Forward upstream ISA I/O addresses in the"
newline
bitfld.long 0x00 17. "SERR_EN,SERR# Enable" "0,1"
newline
bitfld.long 0x00 16. "PERE,Parity Error Response Enable" "0,1"
newline
abitfld.long 0x00 8.--15. "INT_PIN,Interrupt PIN" "0x00=0: indicates that the Function uses no legacy,0x04=4: map to legacy interrupt Messages for..,0xFF=255: Reserved"
newline
hexmask.long.byte 0x00 0.--7. 1. "INT_LINE,Interrupt Line"
group.long 0x40++0x03
line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register"
bitfld.long 0x00 27.--31. "PME_SUPPORT,Power Management Event Support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 26. "D2_SUPPORT,D2 State Support" "0,1"
newline
bitfld.long 0x00 25. "D1_SUPPORT,D1 State Support" "0,1"
newline
bitfld.long 0x00 22.--24. "AUX_CURR,Auxiliary Current Requirements" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21. "DSI,Device Specific Initialization Bit" "0,1"
newline
rbitfld.long 0x00 19. "PME_CLK,PCI Clock Requirement" "0,1"
newline
bitfld.long 0x00 16.--18. "PM_SPEC_VER,Power Management Spec Version" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer"
newline
hexmask.long.byte 0x00 0.--7. 1. "PM_CAP_ID,Power Management Capability ID"
group.long 0x44++0x03
line.long 0x00 "CON_STATUS_REG,Power Management Control and Status Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_REG_ADD_INFO,Power Data Information Register"
newline
rbitfld.long 0x00 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable" "0,1"
newline
rbitfld.long 0x00 22. "B2_B3_SUPPORT,B2B3 Support for D3hot" "0,1"
newline
rbitfld.long 0x00 16.--21. "RSVDP_16,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 15. "PME_STATUS,PME Status" "0,1"
newline
rbitfld.long 0x00 13.--14. "DATA_SCALE,Data Scaling Factor" "0,1,2,3"
newline
rbitfld.long 0x00 9.--12. "DATA_SELECT,Data Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "PME_ENABLE,PME Enable" "0,1"
newline
rbitfld.long 0x00 4.--7. "RSVDP_4,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "NO_SOFT_RST,No soft Reset" "0,1"
newline
rbitfld.long 0x00 2. "RSVDP_2,Reserved for future use" "0,1"
newline
bitfld.long 0x00 0.--1. "POWER_STATE,Power State" "0,1,2,3"
group.long 0x50++0x03
line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID Next Pointer Capability/Control Registers"
rbitfld.long 0x00 27.--31. "RSVDP_27,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable" "0,1"
newline
bitfld.long 0x00 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable" "0,1"
newline
rbitfld.long 0x00 24. "PCI_PVM_SUPPORT,MSI Per Vector Masking Capable" "0,1"
newline
bitfld.long 0x00 23. "PCI_MSI_64_BIT_ADDR_CAP,MSI 64-bit Address Capable" "0,1"
newline
bitfld.long 0x00 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,MSI Multiple Message Enable" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,MSI Multiple Message Capable" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "PCI_MSI_ENABLE,MSI Enable" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,MSI Capability Next Pointer"
newline
hexmask.long.byte 0x00 0.--7. 1. "PCI_MSI_CAP_ID,MSI Capability ID"
group.long 0x54++0x03
line.long 0x00 "MSI_CAP_OFF_04H_REG,MSI Message Lower Address Register"
hexmask.long 0x00 2.--31. 1. "PCI_MSI_CAP_OFF_04H,MSI Message Lower Address Field"
newline
rbitfld.long 0x00 0.--1. "RSVDP_0,Reserved for future use" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "MSI_CAP_OFF_08H_REG,For a 32 bit MSI Message this register contains Data"
hexmask.long.word 0x00 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a 32 bit MSI Message this field contains Ext MSI Data"
newline
hexmask.long.word 0x00 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a 32-bit MSI Message this field contains Data"
group.long 0x5C++0x03
line.long 0x00 "MSI_CAP_OFF_0CH_REG,For a 64 bit MSI Message this register contains Data"
hexmask.long.word 0x00 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a 64-bit MSI Message this field contains Data"
newline
hexmask.long.word 0x00 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a 64-bit MSI Message this field contains Data"
group.long 0x60++0x03
line.long 0x00 "MSI_CAP_OFF_10H_REG,Used for MSI when Vector Masking Capable"
hexmask.long 0x00 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when Vector Masking Capable"
rgroup.long 0x64++0x03
line.long 0x00 "MSI_CAP_OFF_14H_REG,Used for MSI 64 bit messaging when Vector Masking Capable"
hexmask.long 0x00 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Used for MSI 64-bit messaging when Vector Masking Capable"
group.long 0x70++0x03
line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities ID Next Pointer Register"
rbitfld.long 0x00 31. "RSVDP_31,Reserved for future use" "0,1"
newline
rbitfld.long 0x00 30. "RSVD,Reserved" "0,1"
newline
bitfld.long 0x00 25.--29. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 24. "PCIE_SLOT_IMP,PCIe Slot Implemented Valid" "0,1"
newline
rbitfld.long 0x00 20.--23. "PCIE_DEV_PORT_TYPE,PCIE Device/PortType" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "PCIE_CAP_REG,PCIE Capability Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "PCIE_CAP_NEXT_PTR,PCIE Next Capability Pointer"
newline
hexmask.long.byte 0x00 0.--7. 1. "PCIE_CAP_ID,PCIE Capability ID"
group.long 0x74++0x03
line.long 0x00 "DEVICE_CAPABILITIES_REG,Device Capabilities Register"
hexmask.long.word 0x00 16.--31. 1. "RSVDP_16,Reserved for future use"
newline
bitfld.long 0x00 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-based Error Reporting Implemented" "0,1"
newline
hexmask.long.word 0x00 6.--14. 1. "RSVDP_6,Reserved for future use"
newline
bitfld.long 0x00 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported" "0,1"
newline
bitfld.long 0x00 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported" "0,1,2,3"
newline
bitfld.long 0x00 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max Payload Size Supported" "0,1,2,3,4,5,6,7"
group.long 0x78++0x03
line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register"
hexmask.long.word 0x00 22.--31. 1. "RSVDP_22,Reserved for future use"
newline
rbitfld.long 0x00 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending Status" "0,1"
newline
rbitfld.long 0x00 20. "PCIE_CAP_AUX_POWER_DETECTED,Aux Power Detected Status" "0,1"
newline
eventfld.long 0x00 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected Status" "0,1"
newline
eventfld.long 0x00 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected Status" "0,1"
newline
eventfld.long 0x00 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected Status" "0,1"
newline
eventfld.long 0x00 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected Status" "0,1"
newline
bitfld.long 0x00 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (for endpoints)" "0,1"
newline
bitfld.long 0x00 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max Read Request Size" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop" "0,1"
newline
bitfld.long 0x00 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable" "0,1"
newline
rbitfld.long 0x00 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable" "0,1"
newline
rbitfld.long 0x00 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable" "0,1"
newline
bitfld.long 0x00 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max Payload Size" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering" "0,1"
newline
bitfld.long 0x00 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable" "0,1"
newline
bitfld.long 0x00 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable" "0,1"
newline
bitfld.long 0x00 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-fatal Error Reporting Enable" "0,1"
newline
bitfld.long 0x00 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "LINK_CAPABILITIES_REG,Link Capabilities Register"
hexmask.long.byte 0x00 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number"
newline
rbitfld.long 0x00 23. "RSVDP_23,Reserved for future use" "0,1"
newline
bitfld.long 0x00 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance" "0,1"
newline
bitfld.long 0x00 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capable" "0,1"
newline
rbitfld.long 0x00 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable" "0,1"
newline
bitfld.long 0x00 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable" "0,1"
newline
rbitfld.long 0x00 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management" "0,1"
newline
rbitfld.long 0x00 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,LOs Exit Latency" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Level of ASPM (Active State Power Management) Support" "0,1,2,3"
newline
bitfld.long 0x00 4.--9. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--3. "PCIE_CAP_MAX_LINK_SPEED,Maximum Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register"
eventfld.long 0x00 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status" "0,1"
newline
eventfld.long 0x00 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status" "0,1"
newline
rbitfld.long 0x00 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Active" "0,1"
newline
bitfld.long 0x00 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration" "0,1"
newline
rbitfld.long 0x00 27. "PCIE_CAP_LINK_TRAINING,LTSSM is in Configuration or Recovery State" "0,1"
newline
rbitfld.long 0x00 26. "RSVDP_26,Reserved for future use" "0,1"
newline
rbitfld.long 0x00 20.--25. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 16.--19. "PCIE_CAP_LINK_SPEED,Current Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control" "0,1,2,3"
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rbitfld.long 0x00 12.--13. "RSVDP_12,Reserved for future use" "0,1,2,3"
newline
bitfld.long 0x00 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable" "0,1"
newline
bitfld.long 0x00 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable" "0,1"
newline
bitfld.long 0x00 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable" "0,1"
newline
bitfld.long 0x00 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management" "0,1"
newline
bitfld.long 0x00 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch" "0,1"
newline
bitfld.long 0x00 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration" "0,1"
newline
bitfld.long 0x00 5. "PCIE_CAP_RETRAIN_LINK,Initiate Link Retrain" "0,1"
newline
bitfld.long 0x00 4. "PCIE_CAP_LINK_DISABLE,Initiate Link Disable" "0,1"
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bitfld.long 0x00 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB)" "0,1"
newline
rbitfld.long 0x00 2. "RSVDP_2,Reserved for future use" "0,1"
newline
bitfld.long 0x00 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control" "0,1,2,3"
group.long 0x84++0x03
line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register"
hexmask.long.word 0x00 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number"
newline
bitfld.long 0x00 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support" "0,1"
newline
bitfld.long 0x00 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present" "0,1"
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bitfld.long 0x00 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale" "0,1,2,3"
newline
hexmask.long.byte 0x00 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value"
newline
bitfld.long 0x00 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot Plug Capable" "0,1"
newline
bitfld.long 0x00 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot Plug Surprise possible" "0,1"
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bitfld.long 0x00 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present" "0,1"
newline
bitfld.long 0x00 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present" "0,1"
newline
bitfld.long 0x00 2. "PCIE_CAP_MRL_SENSOR,MRL Present" "0,1"
newline
bitfld.long 0x00 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present" "0,1"
newline
bitfld.long 0x00 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present" "0,1"
group.long 0x88++0x03
line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register"
hexmask.long.byte 0x00 25.--31. 1. "RSVDP_25,Reserved for future use"
newline
eventfld.long 0x00 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed" "0,1"
newline
rbitfld.long 0x00 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status" "0,1"
newline
rbitfld.long 0x00 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State" "0,1"
newline
rbitfld.long 0x00 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State" "0,1"
newline
eventfld.long 0x00 20. "PCIE_CAP_CMD_CPLD,Command Completed" "0,1"
newline
eventfld.long 0x00 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed" "0,1"
newline
eventfld.long 0x00 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed" "0,1"
newline
eventfld.long 0x00 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected" "0,1"
newline
eventfld.long 0x00 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed" "0,1"
newline
rbitfld.long 0x00 13.--15. "RSVDP_13,Reserved for future use" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable" "0,1"
newline
bitfld.long 0x00 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control" "0,1"
newline
bitfld.long 0x00 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control" "0,1"
newline
bitfld.long 0x00 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control" "0,1,2,3"
newline
bitfld.long 0x00 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot Plug Interrupt Enable" "0,1"
newline
bitfld.long 0x00 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable" "0,1"
newline
bitfld.long 0x00 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable" "0,1"
newline
bitfld.long 0x00 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable" "0,1"
newline
bitfld.long 0x00 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable" "0,1"
newline
bitfld.long 0x00 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable" "0,1"
group.long 0x8C++0x03
line.long 0x00 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register"
hexmask.long.word 0x00 17.--31. 1. "RSVDP_17,Reserved for future use"
newline
bitfld.long 0x00 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable" "0,1"
newline
hexmask.long.word 0x00 5.--15. 1. "RSVDP_5,Reserved for future use"
newline
bitfld.long 0x00 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,Configuration Request Retry Status (CRS) Software Visibility Enable" "0,1"
newline
bitfld.long 0x00 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable" "0,1"
newline
bitfld.long 0x00 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable" "0,1"
newline
bitfld.long 0x00 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-fatal Error Enable" "0,1"
newline
bitfld.long 0x00 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable" "0,1"
group.long 0x90++0x03
line.long 0x00 "ROOT_STATUS_REG,Root Status Register"
hexmask.long.word 0x00 18.--31. 1. "RSVDP_18,Reserved for future use"
newline
rbitfld.long 0x00 17. "PCIE_CAP_PME_PENDING,PME Pending" "0,1"
newline
eventfld.long 0x00 16. "PCIE_CAP_PME_STATUS,PME Status" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID"
rgroup.long 0x94++0x03
line.long 0x00 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register"
hexmask.long.byte 0x00 24.--30. 1. "RSVDP_24,Reserved for future use"
newline
bitfld.long 0x00 18.--19. "PCIE_CAP_OBFF_SUPPORT,(OBFF) Optimized Buffer Flush/fill Supported" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported" "0,1"
newline
bitfld.long 0x00 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported" "0,1"
newline
bitfld.long 0x00 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1" "0,1"
newline
bitfld.long 0x00 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0" "0,1"
newline
bitfld.long 0x00 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported" "0,1"
newline
bitfld.long 0x00 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No Relaxed Ordering Enabled PR-PR Passing" "0,1"
newline
bitfld.long 0x00 9. "PCIE_CAP_128_CAS_CPL_SUPP,128 Bit CAS Completer Supported" "0,1"
newline
bitfld.long 0x00 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64 Bit AtomicOp Completer Supported" "0,1"
newline
bitfld.long 0x00 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32 Bit AtomicOp Completer Supported" "0,1"
newline
bitfld.long 0x00 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,Atomic Operation Routing Supported" "0,1"
newline
bitfld.long 0x00 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported" "0,1"
newline
bitfld.long 0x00 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported" "0,1"
newline
bitfld.long 0x00 0.--3. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x98++0x03
line.long 0x00 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register"
rbitfld.long 0x00 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable" "0,1"
newline
bitfld.long 0x00 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable" "0,1"
newline
bitfld.long 0x00 0.--3. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x9C++0x03
line.long 0x00 "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register"
bitfld.long 0x00 25.--30. "RSVDP_25,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 9.--22. 1. "RSVDP_9,Reserved for future use"
newline
bitfld.long 0x00 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Cross Link Supported" "0,1"
newline
abitfld.long 0x00 1.--7. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector" "0x0B=11: 0000001 where PCIE_CAP_MAX_LINK_SPEED..,0x0F=15: (PCIE_CAP_MAX_LINK_SPEED == 0011) ?,0x6F=111: (PCIE_CAP_MAX_LINK_SPEED == 0010) ?"
newline
bitfld.long 0x00 0. "RSVDP_0,Reserved for future use" "0,1"
group.long 0xA0++0x03
line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register"
rbitfld.long 0x00 31. "DRS_MESSAGE_RECEIVED,DRS Message Received" "0,1"
newline
rbitfld.long 0x00 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 26.--27. "RSVDP_26,Reserved for future use" "0,1,2,3"
newline
rbitfld.long 0x00 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level" "0,1"
newline
bitfld.long 0x00 12.--15. "PCIE_CAP_COMPLIANCE_PRESET,Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "PCIE_CAP_COMPLIANCE_SOS,Sets Compliance Skip Ordered Sets transmission" "0,1"
newline
bitfld.long 0x00 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance" "0,1"
newline
bitfld.long 0x00 7.--9. "PCIE_CAP_TX_MARGIN,Controls Transmit Margin for Debug or Compliance" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6. "PCIE_CAP_SEL_DEEMPHASIS,Controls Selectable De-emphasis for 5 GT/s" "0,1"
newline
bitfld.long 0x00 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable" "0,1"
newline
bitfld.long 0x00 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance Mode" "0,1"
newline
bitfld.long 0x00 0.--3. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x100++0x03
line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header"
hexmask.long.word 0x00 20.--31. 1. "NEXT_OFFSET,Next Capability Offset"
newline
bitfld.long 0x00 16.--19. "CAP_VERSION,Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "CAP_ID,AER Extended Capability ID"
group.long 0x104++0x03
line.long 0x00 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register"
rbitfld.long 0x00 26.--31. "RSVDP_26,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status" "0,1"
newline
rbitfld.long 0x00 23. "RSVDP_23,Reserved for future use" "0,1"
newline
eventfld.long 0x00 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status" "0,1"
newline
eventfld.long 0x00 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status" "0,1"
newline
eventfld.long 0x00 19. "ECRC_ERR_STATUS,ECRC Error Status" "0,1"
newline
eventfld.long 0x00 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status" "0,1"
newline
eventfld.long 0x00 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status" "0,1"
newline
eventfld.long 0x00 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status" "0,1"
newline
eventfld.long 0x00 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status" "0,1"
newline
eventfld.long 0x00 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status" "0,1"
newline
eventfld.long 0x00 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status" "0,1"
newline
eventfld.long 0x00 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status" "0,1"
newline
rbitfld.long 0x00 6.--11. "RSVDP_6,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional)" "0,1"
newline
eventfld.long 0x00 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status" "0,1"
newline
rbitfld.long 0x00 0.--3. "RSVDP_0,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x108++0x03
line.long 0x00 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register"
rbitfld.long 0x00 26.--31. "RSVDP_26,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask" "0,1"
newline
rbitfld.long 0x00 24. "ATOMIC_EGRESS_BLOCKED_ERR_MASK,AtomicOp Egress Block Mask (Optional)" "0,1"
newline
rbitfld.long 0x00 23. "RSVDP_23,Reserved for future use" "0,1"
newline
bitfld.long 0x00 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional)" "0,1"
newline
bitfld.long 0x00 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask" "0,1"
newline
bitfld.long 0x00 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional)" "0,1"
newline
bitfld.long 0x00 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask" "0,1"
newline
bitfld.long 0x00 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional)" "0,1"
newline
bitfld.long 0x00 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask" "0,1"
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bitfld.long 0x00 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional)" "0,1"
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bitfld.long 0x00 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask" "0,1"
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bitfld.long 0x00 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask" "0,1"
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bitfld.long 0x00 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask" "0,1"
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rbitfld.long 0x00 6.--11. "RSVDP_6,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask" "0,1"
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bitfld.long 0x00 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask" "0,1"
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rbitfld.long 0x00 0.--3. "RSVDP_0,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x03
line.long 0x00 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register"
rbitfld.long 0x00 26.--31. "RSVDP_26,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional)" "0,1"
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rbitfld.long 0x00 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional)" "0,1"
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rbitfld.long 0x00 23. "RSVDP_23,Reserved for future use" "0,1"
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bitfld.long 0x00 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional)" "0,1"
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bitfld.long 0x00 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity" "0,1"
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bitfld.long 0x00 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional)" "0,1"
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bitfld.long 0x00 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity" "0,1"
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bitfld.long 0x00 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional)" "0,1"
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bitfld.long 0x00 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity" "0,1"
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bitfld.long 0x00 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional)" "0,1"
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bitfld.long 0x00 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity" "0,1"
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bitfld.long 0x00 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional)" "0,1"
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bitfld.long 0x00 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity" "0,1"
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rbitfld.long 0x00 6.--11. "RSVDP_6,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional)" "0,1"
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bitfld.long 0x00 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity" "0,1"
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rbitfld.long 0x00 0.--3. "RSVDP_0,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110++0x03
line.long 0x00 "CORR_ERR_STATUS_OFF,Correctable Error Status Register"
hexmask.long.word 0x00 16.--31. 1. "RSVDP_16,Reserved for future use"
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eventfld.long 0x00 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional)" "0,1"
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eventfld.long 0x00 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional)" "0,1"
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eventfld.long 0x00 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status" "0,1"
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eventfld.long 0x00 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status" "0,1"
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rbitfld.long 0x00 9.--11. "RSVDP_9,Reserved for future use" "0,1,2,3,4,5,6,7"
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eventfld.long 0x00 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status" "0,1"
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eventfld.long 0x00 7. "BAD_DLLP_STATUS,Bad DLLP Status" "0,1"
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eventfld.long 0x00 6. "BAD_TLP_STATUS,Bad TLP Status" "0,1"
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rbitfld.long 0x00 1.--5. "RSVDP_1,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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eventfld.long 0x00 0. "RX_ERR_STATUS,Receiver Error Status (Optional)" "0,1"
group.long 0x114++0x03
line.long 0x00 "CORR_ERR_MASK_OFF,Correctable Error Mask Register"
hexmask.long.word 0x00 16.--31. 1. "RSVDP_16,Reserved for future use"
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bitfld.long 0x00 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional)" "0,1"
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bitfld.long 0x00 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional)" "0,1"
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bitfld.long 0x00 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask" "0,1"
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bitfld.long 0x00 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask" "0,1"
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rbitfld.long 0x00 9.--11. "RSVDP_9,Reserved for future use" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask" "0,1"
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bitfld.long 0x00 7. "BAD_DLLP_MASK,Bad DLLP Mask" "0,1"
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bitfld.long 0x00 6. "BAD_TLP_MASK,Bad TLP Mask" "0,1"
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rbitfld.long 0x00 1.--5. "RSVDP_1,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "RX_ERR_MASK,Receiver Error Mask (Optional)" "0,1"
group.long 0x118++0x03
line.long 0x00 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register"
hexmask.long.tbyte 0x00 12.--31. 1. "RSVDP_12,Reserved for future use"
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rbitfld.long 0x00 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable" "0,1"
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rbitfld.long 0x00 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable" "0,1"
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bitfld.long 0x00 8. "ECRC_CHECK_EN,ECRC Check Enable" "0,1"
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rbitfld.long 0x00 7. "ECRC_CHECK_CAP,ECRC Check Capable" "0,1"
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bitfld.long 0x00 6. "ECRC_GEN_EN,ECRC Generation Enable" "0,1"
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rbitfld.long 0x00 5. "ECRC_GEN_CAP,ECRC Generation Capable" "0,1"
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rbitfld.long 0x00 0.--4. "FIRST_ERR_POINTER,First Error Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x11C++0x03
line.long 0x00 "HDR_LOG_0_OFF,Header Log Register 0"
hexmask.long.byte 0x00 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word"
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hexmask.long.byte 0x00 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word"
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hexmask.long.byte 0x00 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word"
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hexmask.long.byte 0x00 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word"
rgroup.long 0x120++0x03
line.long 0x00 "HDR_LOG_1_OFF,Header Log Register 1"
hexmask.long.byte 0x00 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word"
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hexmask.long.byte 0x00 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word"
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hexmask.long.byte 0x00 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word"
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hexmask.long.byte 0x00 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word"
rgroup.long 0x124++0x03
line.long 0x00 "HDR_LOG_2_OFF,Header Log Register 2"
hexmask.long.byte 0x00 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word"
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hexmask.long.byte 0x00 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word"
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hexmask.long.byte 0x00 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word"
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hexmask.long.byte 0x00 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word"
rgroup.long 0x128++0x03
line.long 0x00 "HDR_LOG_3_OFF,Header Log Register 3"
hexmask.long.byte 0x00 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word"
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hexmask.long.byte 0x00 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word"
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hexmask.long.byte 0x00 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word"
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hexmask.long.byte 0x00 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word"
group.long 0x12C++0x03
line.long 0x00 "ROOT_ERR_CMD_OFF,Root Error Command Register"
hexmask.long 0x00 3.--31. 1. "RSVDP_3,Reserved for future use"
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bitfld.long 0x00 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable" "0,1"
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bitfld.long 0x00 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable" "0,1"
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bitfld.long 0x00 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable" "0,1"
group.long 0x130++0x03
line.long 0x00 "ROOT_ERR_STATUS_OFF,Root Error Status Register"
bitfld.long 0x00 27.--31. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.tbyte 0x00 7.--26. 1. "RSVDP_7,Reserved for future use"
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eventfld.long 0x00 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received" "0,1"
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eventfld.long 0x00 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received" "0,1"
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eventfld.long 0x00 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal" "0,1"
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eventfld.long 0x00 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received" "0,1"
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eventfld.long 0x00 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received" "0,1"
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eventfld.long 0x00 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received" "0,1"
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eventfld.long 0x00 0. "ERR_COR_RX,Correctable Error Received" "0,1"
rgroup.long 0x134++0x03
line.long 0x00 "ERR_SRC_ID_OFF,Error Source Identification Register"
hexmask.long.word 0x00 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error"
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hexmask.long.word 0x00 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error"
rgroup.long 0x138++0x03
line.long 0x00 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1"
hexmask.long.byte 0x00 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1"
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hexmask.long.byte 0x00 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1"
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hexmask.long.byte 0x00 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1"
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hexmask.long.byte 0x00 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1"
rgroup.long 0x13C++0x03
line.long 0x00 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2"
hexmask.long.byte 0x00 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2"
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hexmask.long.byte 0x00 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2"
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hexmask.long.byte 0x00 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2"
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hexmask.long.byte 0x00 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2"
rgroup.long 0x140++0x03
line.long 0x00 "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3"
hexmask.long.byte 0x00 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3"
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hexmask.long.byte 0x00 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3"
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hexmask.long.byte 0x00 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3"
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hexmask.long.byte 0x00 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3"
rgroup.long 0x144++0x03
line.long 0x00 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4"
hexmask.long.byte 0x00 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4"
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hexmask.long.byte 0x00 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4"
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hexmask.long.byte 0x00 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4"
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hexmask.long.byte 0x00 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4"
group.long 0x158++0x03
line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header"
hexmask.long.word 0x00 20.--31. 1. "NEXT_OFFSET,Next Capability Offset"
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bitfld.long 0x00 16.--19. "CAP_VERSION,Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID"
group.long 0x15C++0x03
line.long 0x00 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
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bitfld.long 0x00 19.--23. "PWR_ON_VALUE_SUPPORT,Port T Power On Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 18. "RSVDP_18,Reserved for future use" "0,1"
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bitfld.long 0x00 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale" "0,1,2,3"
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hexmask.long.byte 0x00 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time"
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rbitfld.long 0x00 5.--7. "RSVDP_5,Reserved for future use" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported" "0,1"
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bitfld.long 0x00 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported" "0,1"
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bitfld.long 0x00 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported" "0,1"
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bitfld.long 0x00 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported" "0,1"
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bitfld.long 0x00 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported" "0,1"
group.long 0x160++0x03
line.long 0x00 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register"
bitfld.long 0x00 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 26.--28. "RSVDP_26,Reserved for future use" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value"
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hexmask.long.byte 0x00 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time"
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rbitfld.long 0x00 4.--7. "RSVDP_4,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "L1_1_ASPM_EN,ASPM L11 Enable" "0,1"
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bitfld.long 0x00 2. "L1_2_ASPM_EN,ASPM L12 Enable" "0,1"
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bitfld.long 0x00 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable" "0,1"
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bitfld.long 0x00 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable" "0,1"
group.long 0x164++0x03
line.long 0x00 "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RSVDP_8,Reserved for future use"
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bitfld.long 0x00 3.--7. "T_POWER_ON_VALUE,T Power On Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 2. "RSVDP_2,Reserved for future use" "0,1"
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bitfld.long 0x00 0.--1. "T_POWER_ON_SCALE,T Power On Scale" "0,1,2,3"
group.long 0x700++0x03
line.long 0x00 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register"
hexmask.long.word 0x00 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit"
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hexmask.long.word 0x00 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit"
group.long 0x704++0x03
line.long 0x00 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register"
hexmask.long 0x00 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register"
group.long 0x708++0x03
line.long 0x00 "PORT_FORCE_OFF,Port Force Link Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
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bitfld.long 0x00 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew for SRIS instead of using received SKP OS if DO_DESKEW_FOR_SRIS is set to 1" "0,1"
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rbitfld.long 0x00 22. "RSVDP_22,Reserved for future use" "0,1"
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bitfld.long 0x00 16.--21. "LINK_STATE,Forced LTSSM State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 15. "FORCE_EN,Force Link" "0,1"
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rbitfld.long 0x00 12.--14. "RSVDP_12,Reserved for future use" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "FORCED_LTSSM,Forced Link Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "LINK_NUM,Link Number"
group.long 0x70C++0x03
line.long 0x00 "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register"
rbitfld.long 0x00 31. "RSVDP_31,Reserved for future use" "0,1"
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bitfld.long 0x00 30. "ENTER_ASPM,ASPM L1 Entry Control" "0: Core enters ASPM L1 only after idle period,1: Core enters ASPM L1 after a period in which it"
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bitfld.long 0x00 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency" "0: 1 us,1: 2 us,2: 4 us,3: 8 us,4: 16 us,5: 32 us - 110 or,?,7: 64 us"
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bitfld.long 0x00 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency" "0: 1 us,1: 2 us,2: 3 us,3: 4 us,4: 5 us,5: 6 us - 110 or,?,7: 7 us This field is"
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hexmask.long.byte 0x00 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS"
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hexmask.long.byte 0x00 8.--15. 1. "ACK_N_FTS,N_FTS"
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hexmask.long.byte 0x00 0.--7. 1. "ACK_FREQ,Ack Frequency"
group.long 0x710++0x03
line.long 0x00 "PORT_LINK_CTRL_OFF,Port Link Control Register"
rbitfld.long 0x00 28.--31. "RSVDP_28,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field" "0,1"
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bitfld.long 0x00 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field" "0,1"
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bitfld.long 0x00 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field" "0,1"
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bitfld.long 0x00 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field" "0,1"
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bitfld.long 0x00 16.--21. "LINK_CAPABLE,Link Mode Enable" "?,1: x1,?,3: x2,?,?,?,7: x4,?,?,?,?,?,?,?,15: x8,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: x16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: x32 (not"
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rbitfld.long 0x00 12.--15. "RSVDP_12,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "LINK_RATE,LINK_RATE is an internally reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "FAST_LINK_MODE,Fast Link Mode" "0,1"
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bitfld.long 0x00 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field" "0,1"
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bitfld.long 0x00 5. "DLL_LINK_EN,DLL Link Enable" "0,1"
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rbitfld.long 0x00 4. "RSVDP_4,Reserved for future use" "0,1"
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bitfld.long 0x00 3. "RESET_ASSERT,Reset Assert" "0,1"
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bitfld.long 0x00 2. "LOOPBACK_ENABLE,Loopback Enable" "0,1"
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bitfld.long 0x00 1. "SCRAMBLE_DISABLE,Scramble Disable" "0,1"
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eventfld.long 0x00 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request" "0,1"
group.long 0x714++0x03
line.long 0x00 "LANE_SKEW_OFF,Lane Skew Register"
bitfld.long 0x00 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew" "0,1"
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bitfld.long 0x00 27.--30. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes" "0: 1 lane,1: 2 lanes,?,3: 4 lanes,?,?,?,7: 8 lanes,?,?,?,?,?,?,?,15: 16 lanes The number of"
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bitfld.long 0x00 26. "GEN34_ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate" "0: Nominal Half Full Buffer mode,1: Nominal Empty Buffer Mode This register bit.."
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bitfld.long 0x00 25. "ACK_NAK_DISABLE,Ack/Nak Disable" "0,1"
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bitfld.long 0x00 24. "FLOW_CTRL_DISABLE,Flow Control Disable" "0,1"
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hexmask.long.tbyte 0x00 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field"
group.long 0x718++0x03
line.long 0x00 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register"
rbitfld.long 0x00 31. "RSVDP_31,Reserved for future use" "0,1"
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bitfld.long 0x00 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor" "0: Scaling Factor is 1024 (1ms is 1us),1: Scaling Factor is 256 (1ms is 4us),2: Scaling Factor is 64 (1ms is 16us),3: Scaling Factor is 16 (1ms is 64us) Default is"
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bitfld.long 0x00 24.--28. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 19.--23. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--18. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 8.--13. "RSVDP_8,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request"
group.long 0x71C++0x03
line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register"
abitfld.long 0x00 16.--31. "MASK_RADM_1,Filter Mask 1" "0x0000=0: Treat Function MisMatched TLPs as UR,0x0001=1: Do not treat Function MisMatched TLPs.."
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bitfld.long 0x00 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer" "0,1"
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bitfld.long 0x00 11.--14. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--10. 1. "SKP_INT_VAL,SKP Interval Value"
group.long 0x720++0x03
line.long 0x00 "FILTER_MASK_2_OFF,Filter Mask 2 Register"
abitfld.long 0x00 0.--31. "MASK_RADM_2,Filter Mask 2" "0x00000000=0: Vendor MSG Type 0 dropped with UR..,0x00000001=1: Vendor MSG Type 0 not dropped"
group.long 0x724++0x03
line.long 0x00 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register"
hexmask.long 0x00 1.--31. 1. "RSVDP_1,Reserved for future use"
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bitfld.long 0x00 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests" "0,1"
rgroup.long 0x728++0x03
line.long 0x00 "PL_DEBUG0_OFF,Debug Register 0"
hexmask.long 0x00 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]"
rgroup.long 0x72C++0x03
line.long 0x00 "PL_DEBUG1_OFF,Debug Register 1"
hexmask.long 0x00 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]"
rgroup.long 0x730++0x03
line.long 0x00 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. "RSVDP_20,Reserved for future use"
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hexmask.long.byte 0x00 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits"
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hexmask.long.word 0x00 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits"
rgroup.long 0x734++0x03
line.long 0x00 "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. "RSVDP_20,Reserved for future use"
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hexmask.long.byte 0x00 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits"
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hexmask.long.word 0x00 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits"
rgroup.long 0x738++0x03
line.long 0x00 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. "RSVDP_20,Reserved for future use"
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hexmask.long.byte 0x00 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits"
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hexmask.long.word 0x00 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits"
group.long 0x73C++0x03
line.long 0x00 "QUEUE_STATUS_OFF,Queue Status"
bitfld.long 0x00 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable" "0,1"
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rbitfld.long 0x00 29.--30. "RSVDP_29,Reserved for future use" "0,1,2,3"
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hexmask.long.word 0x00 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value"
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eventfld.long 0x00 15. "RX_SERIALIZATION_Q_READ_ERR,Receive Serialization Read Error" "0,1"
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eventfld.long 0x00 14. "RX_SERIALIZATION_Q_WRITE_ERR,Receive Serialization Queue Write Error" "0,1"
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rbitfld.long 0x00 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty" "0,1"
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hexmask.long.word 0x00 4.--12. 1. "RSVDP_4,Reserved for future use"
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eventfld.long 0x00 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow" "0,1"
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rbitfld.long 0x00 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty" "0,1"
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rbitfld.long 0x00 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty" "0,1"
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rbitfld.long 0x00 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned" "0,1"
rgroup.long 0x740++0x03
line.long 0x00 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1"
hexmask.long.byte 0x00 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0"
group.long 0x748++0x03
line.long 0x00 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control"
bitfld.long 0x00 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues" "0: Round robin,1: Strict ordering higher numbered VCs have higher"
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bitfld.long 0x00 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0" "0: Strict ordering,1: PCIe ordering rules (recommended)"
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bitfld.long 0x00 28.--29. "RESERVED5,Reserved" "0,1,2,3"
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bitfld.long 0x00 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites" "0,1,2,3"
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bitfld.long 0x00 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites" "0,1,2,3"
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bitfld.long 0x00 21.--23. "VC0_P_TLP_Q_MODE,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "RESERVED4,Reserved" "0,1"
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hexmask.long.byte 0x00 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits"
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hexmask.long.word 0x00 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits"
group.long 0x74C++0x03
line.long 0x00 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control"
bitfld.long 0x00 28.--31. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites" "0,1,2,3"
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bitfld.long 0x00 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites" "0,1,2,3"
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bitfld.long 0x00 21.--23. "VC0_NP_TLP_Q_MODE,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "RESERVED6,Reserved" "0,1"
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hexmask.long.byte 0x00 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits"
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hexmask.long.word 0x00 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits"
group.long 0x750++0x03
line.long 0x00 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control"
bitfld.long 0x00 28.--31. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites" "0,1,2,3"
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bitfld.long 0x00 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites" "0,1,2,3"
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bitfld.long 0x00 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "RESERVED8,Reserved" "0,1"
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hexmask.long.byte 0x00 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits"
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hexmask.long.word 0x00 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits"
group.long 0x80C++0x03
line.long 0x00 "GEN2_CTRL_OFF,Link Width and Speed Change Control Register"
hexmask.long.word 0x00 22.--31. 1. "RSVDP_22,Reserved for future use"
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bitfld.long 0x00 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate" "0: Use RxElecIdle signal to infer Electrical Idle,1: Use RxValid signal to infer Electrical Idle"
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bitfld.long 0x00 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports" "0: -6 dB,1: -3.5 dB This field"
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bitfld.long 0x00 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit" "0,1"
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bitfld.long 0x00 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing" "0: Full Swing,1: Low Swing This field is reserved"
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bitfld.long 0x00 17. "DIRECT_SPEED_CHANGE,Directed Speed Change" "0,1"
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bitfld.long 0x00 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes" "0,1"
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bitfld.long 0x00 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip" "0: Connect logical Lane0 to physical lane 0 or,1: Connect logical Lane0 to physical lane,2: Connect logical Lane0 to physical lane,3: Connect logical Lane0 to physical lane,4: Connect logical Lane0 to physical lane 15 This,?..."
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bitfld.long 0x00 8.--12. "NUM_OF_LANES,Predetermined Number of Lanes" "?,1: 1 lane,2: 2 lanes,3: 3 lanes,?..."
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hexmask.long.byte 0x00 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training"
rgroup.long 0x810++0x03
line.long 0x00 "PHY_STATUS_OFF,PHY Status Register"
hexmask.long 0x00 0.--31. 1. "PHY_STATUS,PHY Status"
group.long 0x814++0x03
line.long 0x00 "PHY_CONTROL_OFF,PHY Control Register"
hexmask.long 0x00 0.--31. 1. "PHY_CONTROL,PHY Control"
group.long 0x81C++0x03
line.long 0x00 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register"
hexmask.long.word 0x00 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved"
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bitfld.long 0x00 16.--20. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number" "0,1"
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bitfld.long 0x00 0.--5. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x820++0x03
line.long 0x00 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address"
group.long 0x824++0x03
line.long 0x00 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address"
group.long 0x828++0x03
line.long 0x00 "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable"
group.long 0x82C++0x03
line.long 0x00 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask"
group.long 0x830++0x03
line.long 0x00 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status"
group.long 0x834++0x03
line.long 0x00 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable"
group.long 0x838++0x03
line.long 0x00 "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask"
group.long 0x83C++0x03
line.long 0x00 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status"
group.long 0x840++0x03
line.long 0x00 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable"
group.long 0x844++0x03
line.long 0x00 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask"
group.long 0x848++0x03
line.long 0x00 "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status"
group.long 0x84C++0x03
line.long 0x00 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable"
group.long 0x850++0x03
line.long 0x00 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask"
group.long 0x854++0x03
line.long 0x00 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status"
group.long 0x858++0x03
line.long 0x00 "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable"
group.long 0x85C++0x03
line.long 0x00 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask"
group.long 0x860++0x03
line.long 0x00 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status"
group.long 0x864++0x03
line.long 0x00 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable"
group.long 0x868++0x03
line.long 0x00 "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask"
group.long 0x86C++0x03
line.long 0x00 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status"
group.long 0x870++0x03
line.long 0x00 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable"
group.long 0x874++0x03
line.long 0x00 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask"
group.long 0x878++0x03
line.long 0x00 "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status"
group.long 0x87C++0x03
line.long 0x00 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable"
group.long 0x880++0x03
line.long 0x00 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask"
group.long 0x884++0x03
line.long 0x00 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register"
hexmask.long 0x00 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status"
group.long 0x888++0x03
line.long 0x00 "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register"
hexmask.long 0x00 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register"
group.long 0x88C++0x03
line.long 0x00 "CLOCK_GATING_CTRL_OFF,RADM clock gating enable control register"
hexmask.long 0x00 1.--31. 1. "RSVDP_1,Reserved for future use"
newline
bitfld.long 0x00 0. "RADM_CLK_GATING_EN,Enable Radm clock gating feature" "0: Disable,1: Enable(default)"
group.long 0x8B4++0x03
line.long 0x00 "ORDER_RULE_CTRL_OFF,Order Rule Control Register"
hexmask.long.word 0x00 16.--31. 1. "RSVDP_16,Reserved for future use"
newline
abitfld.long 0x00 8.--15. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control" "0x00=0: CPL can not pass P (recommended),0x01=1: CPL can pass P"
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abitfld.long 0x00 0.--7. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control" "0x00=0: NP can not pass P (recommended),0x01=1: NP can pass P"
group.long 0x8B8++0x03
line.long 0x00 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register"
bitfld.long 0x00 31. "PIPE_LOOPBACK,PIPE Loopback Enable" "0,1"
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rbitfld.long 0x00 27.--30. "RSVDP_27,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 22.--23. "RSVDP_22,Reserved for future use" "0,1,2,3"
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bitfld.long 0x00 16.--21. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field"
group.long 0x8BC++0x03
line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register"
hexmask.long 0x00 6.--31. 1. "RSVDP_6,Reserved for future use"
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bitfld.long 0x00 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID" "0,1"
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bitfld.long 0x00 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4)" "0,1"
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bitfld.long 0x00 2. "UR_CA_MASK_4_TRGT1,This field only applies to request TLPs (with UR filtering status) that you have chosen to forward to the application (when you set DEFAULT_TARGET in this register)" "0,1"
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bitfld.long 0x00 1. "DEFAULT_TARGET,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller" "0: The controller drops all incoming I/O or MEM,1: The controller forwards all incoming I/O or MEM"
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bitfld.long 0x00 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI" "0,1"
group.long 0x8C0++0x03
line.long 0x00 "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RSVDP_8,Reserved for future use"
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bitfld.long 0x00 7. "UPCONFIGURE_SUPPORT,Upconfigure Support" "0,1"
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bitfld.long 0x00 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change" "0,1"
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bitfld.long 0x00 0.--5. "TARGET_LINK_WIDTH,Target Link Width" "0: Core does not start upconfigure or,1: x1,2: x2,?,4: x4,?,?,?,8: x8,?,?,?,?,?,?,?,16: x16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: x32 This field is reserved (fixed,?..."
group.long 0x8C4++0x03
line.long 0x00 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register"
hexmask.long.tbyte 0x00 11.--31. 1. "RSVDP_11,Reserved for future use"
newline
bitfld.long 0x00 10. "L1_CLK_SEL,L1 Clock control bit" "0: Controller requests aux_clk switch and core_clk,1: Controller does not request aux_clk switch and"
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rbitfld.long 0x00 9. "L1_NOWAIT_P1,L1 entry control bit" "0: Core waits for the PHY to acknowledge..,1: Core does not wait for PHY to acknowledge"
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bitfld.long 0x00 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n" "0: Core waits for the PHY to assert,1: Core exits L1 without waiting for the PHY to"
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rbitfld.long 0x00 7. "RSVDP_7,Reserved for future use" "0,1"
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hexmask.long.byte 0x00 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control"
group.long 0x8C8++0x03
line.long 0x00 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register"
eventfld.long 0x00 31. "DELETE_EN,This is a one-shot bit" "0,1"
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hexmask.long 0x00 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT"
group.long 0x8CC++0x03
line.long 0x00 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVD_I_8,This is an internally reserved field"
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hexmask.long.tbyte 0x00 1.--23. 1. "RSVDP_1,Reserved for future use"
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bitfld.long 0x00 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge" "0,1"
group.long 0x8D0++0x03
line.long 0x00 "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register"
hexmask.long.word 0x00 16.--31. 1. "RSVDP_16,Reserved for future use"
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bitfld.long 0x00 10.--15. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map" "0: Completion Timeout -> DECERR,1: Completion Timeout -> SLVERR The AXI bridge,?..."
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rbitfld.long 0x00 5.--9. "RSVDP_5,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping" "0: OKAY,1: OKAY with all FFFF_FFFF data for all CRS,2: OKAY with FFFF_0001 data for CRS completions to,3: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field"
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bitfld.long 0x00 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping" "0: OKAY (with FFFF data),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field"
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rbitfld.long 0x00 1. "RSVDP_1,Reserved for future use" "0,1"
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bitfld.long 0x00 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping" "0: OKAY (with FFFF data for non-posted requests),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field"
group.long 0x8D4++0x03
line.long 0x00 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RSVDP_9,Reserved for future use"
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bitfld.long 0x00 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms)"
group.long 0x8D8++0x03
line.long 0x00 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control"
hexmask.long.tbyte 0x00 8.--31. 1. "RSVDP_8,Reserved for future use"
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bitfld.long 0x00 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application" "0: The zero length Read is terminated at the DW,1: The zero length Read is forward to the.."
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rbitfld.long 0x00 5.--6. "RSVDP_5,Reserved for future use" "0,1,2,3"
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bitfld.long 0x00 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector" "0: B'last event,1: AW'last event,2: This setting will not affect,3: Reserved"
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rbitfld.long 0x00 2. "RSVDP_2,Reserved for future use" "0,1"
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bitfld.long 0x00 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable" "0,1"
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rbitfld.long 0x00 0. "RSVDP_0,Reserved for future use" "0,1"
group.long 0x8F0++0x03
line.long 0x00 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to"
hexmask.long.tbyte 0x00 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages"
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hexmask.long.word 0x00 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use"
group.long 0x8F4++0x03
line.long 0x00 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to"
hexmask.long 0x00 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages"
rgroup.long 0x8F8++0x03
line.long 0x00 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number"
hexmask.long 0x00 0.--31. 1. "VERSION_NUMBER,Version Number"
rgroup.long 0x8FC++0x03
line.long 0x00 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type"
hexmask.long 0x00 0.--31. 1. "VERSION_TYPE,Version Type"
group.long 0xB40++0x03
line.long 0x00 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register"
hexmask.long.tbyte 0x00 10.--31. 1. "RSVDP_10,Reserved for future use"
newline
hexmask.long.word 0x00 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz"
group.long 0xB44++0x03
line.long 0x00 "L1_SUBSTATES_OFF,L1 Substates Timing Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RSVDP_8,Reserved for future use"
newline
bitfld.long 0x00 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n" "0,1,2,3"
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bitfld.long 0x00 2.--5. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry" "0,1,2,3"
group.long 0x300000++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3"
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bitfld.long 0x00 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1"
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bitfld.long 0x00 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--4. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300004++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
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bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
newline
bitfld.long 0x00 27. "DMA_BYPASS,DMA Bypass Mode" "0,1"
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bitfld.long 0x00 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable" "0: LWR_TARGET_RW in the,1: LWR_TARGET_RW in the"
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bitfld.long 0x00 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data" "0: Fmt[1] =0/1 so that TLPs with or without data,1: Fmt[1] =0 so that only TLP type without data is"
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bitfld.long 0x00 20. "SNP,Serialize Non-Posted Requests" "0,1"
newline
bitfld.long 0x00 19. "FUNC_BYPASS,Function Number Translation Bypass" "0,1"
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bitfld.long 0x00 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "TAG,TAG"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code)"
group.long 0x300008++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
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hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30000C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300010++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
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hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300014++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address Register"
hexmask.long 0x00 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used"
group.long 0x300018++0x03
line.long 0x00 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region"
group.long 0x300100++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3"
newline
bitfld.long 0x00 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1"
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bitfld.long 0x00 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--4. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300104++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
newline
bitfld.long 0x00 30. "MATCH_MODE,Match Mode" "0: Address Match Mode,1: Vendor ID Match Mode"
newline
bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
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bitfld.long 0x00 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode" "0,1"
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bitfld.long 0x00 24.--25. "RESPONSE_CODE,Response Code" "0: Normal RADM filter response is used,1: Unsupported request (UR),2: Completer abort (CA),3: Not used / undefined / reserved"
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bitfld.long 0x00 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable" "0,1"
newline
bitfld.long 0x00 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS)" "0,1"
newline
bitfld.long 0x00 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable" "0,1"
newline
bitfld.long 0x00 16. "ATTR_MATCH_EN,ATTR Match Enable" "0,1"
newline
bitfld.long 0x00 15. "TD_MATCH_EN,TD Match Enable" "0,1"
newline
bitfld.long 0x00 14. "TC_MATCH_EN,TC Match Enable" "0,1"
newline
bitfld.long 0x00 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode" "0,1"
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bitfld.long 0x00 8.--10. "BAR_NUM,BAR Number" "0: BAR0,1: BAR1,2: BAR2,3: BAR3,4: BAR4,5: BAR5,6: ROM,7: reserved - IO"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code)"
group.long 0x300108++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
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hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30010C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300110++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
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hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300114++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region"
group.long 0x300200++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3"
newline
bitfld.long 0x00 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1"
newline
bitfld.long 0x00 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300204++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
newline
bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
newline
bitfld.long 0x00 27. "DMA_BYPASS,DMA Bypass Mode" "0,1"
newline
bitfld.long 0x00 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable" "0: LWR_TARGET_RW in the,1: LWR_TARGET_RW in the"
newline
bitfld.long 0x00 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data" "0: Fmt[1] =0/1 so that TLPs with or without data,1: Fmt[1] =0 so that only TLP type without data is"
newline
bitfld.long 0x00 20. "SNP,Serialize Non-Posted Requests" "0,1"
newline
bitfld.long 0x00 19. "FUNC_BYPASS,Function Number Translation Bypass" "0,1"
newline
bitfld.long 0x00 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "TAG,TAG"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code)"
group.long 0x300208++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30020C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300210++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300214++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address Register"
hexmask.long 0x00 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used"
group.long 0x300218++0x03
line.long 0x00 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region"
group.long 0x300300++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3"
newline
bitfld.long 0x00 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1"
newline
bitfld.long 0x00 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300304++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
newline
bitfld.long 0x00 30. "MATCH_MODE,Match Mode" "0: Address Match Mode,1: Vendor ID Match Mode"
newline
bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
newline
bitfld.long 0x00 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode" "0,1"
newline
bitfld.long 0x00 24.--25. "RESPONSE_CODE,Response Code" "0: Normal RADM filter response is used,1: Unsupported request (UR),2: Completer abort (CA),3: Not used / undefined / reserved"
newline
bitfld.long 0x00 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable" "0,1"
newline
bitfld.long 0x00 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS)" "0,1"
newline
bitfld.long 0x00 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable" "0,1"
newline
bitfld.long 0x00 16. "ATTR_MATCH_EN,ATTR Match Enable" "0,1"
newline
bitfld.long 0x00 15. "TD_MATCH_EN,TD Match Enable" "0,1"
newline
bitfld.long 0x00 14. "TC_MATCH_EN,TC Match Enable" "0,1"
newline
bitfld.long 0x00 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode" "0,1"
newline
bitfld.long 0x00 8.--10. "BAR_NUM,BAR Number" "0: BAR0,1: BAR1,2: BAR2,3: BAR3,4: BAR4,5: BAR5,6: ROM,7: reserved - IO"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code)"
group.long 0x300308++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30030C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300310++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300314++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region"
group.long 0x300400++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3"
newline
bitfld.long 0x00 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1"
newline
bitfld.long 0x00 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300404++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
newline
bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
newline
bitfld.long 0x00 27. "DMA_BYPASS,DMA Bypass Mode" "0,1"
newline
bitfld.long 0x00 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable" "0: LWR_TARGET_RW in the,1: LWR_TARGET_RW in the"
newline
bitfld.long 0x00 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data" "0: Fmt[1] =0/1 so that TLPs with or without data,1: Fmt[1] =0 so that only TLP type without data is"
newline
bitfld.long 0x00 20. "SNP,Serialize Non-Posted Requests" "0,1"
newline
bitfld.long 0x00 19. "FUNC_BYPASS,Function Number Translation Bypass" "0,1"
newline
bitfld.long 0x00 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "TAG,TAG"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code)"
group.long 0x300408++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30040C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300410++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300414++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address Register"
hexmask.long 0x00 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used"
group.long 0x300418++0x03
line.long 0x00 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region"
group.long 0x300500++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3"
newline
bitfld.long 0x00 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1"
newline
bitfld.long 0x00 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300504++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
newline
bitfld.long 0x00 30. "MATCH_MODE,Match Mode" "0: Address Match Mode,1: Vendor ID Match Mode"
newline
bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
newline
bitfld.long 0x00 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode" "0,1"
newline
bitfld.long 0x00 24.--25. "RESPONSE_CODE,Response Code" "0: Normal RADM filter response is used,1: Unsupported request (UR),2: Completer abort (CA),3: Not used / undefined / reserved"
newline
bitfld.long 0x00 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable" "0,1"
newline
bitfld.long 0x00 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS)" "0,1"
newline
bitfld.long 0x00 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable" "0,1"
newline
bitfld.long 0x00 16. "ATTR_MATCH_EN,ATTR Match Enable" "0,1"
newline
bitfld.long 0x00 15. "TD_MATCH_EN,TD Match Enable" "0,1"
newline
bitfld.long 0x00 14. "TC_MATCH_EN,TC Match Enable" "0,1"
newline
bitfld.long 0x00 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode" "0,1"
newline
bitfld.long 0x00 8.--10. "BAR_NUM,BAR Number" "0: BAR0,1: BAR1,2: BAR2,3: BAR3,4: BAR4,5: BAR5,6: ROM,7: reserved - IO"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code)"
group.long 0x300508++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30050C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300510++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300514++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region"
group.long 0x300600++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3"
newline
bitfld.long 0x00 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1"
newline
bitfld.long 0x00 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300604++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
newline
bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
newline
bitfld.long 0x00 27. "DMA_BYPASS,DMA Bypass Mode" "0,1"
newline
bitfld.long 0x00 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable" "0: LWR_TARGET_RW in the,1: LWR_TARGET_RW in the"
newline
bitfld.long 0x00 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data" "0: Fmt[1] =0/1 so that TLPs with or without data,1: Fmt[1] =0 so that only TLP type without data is"
newline
bitfld.long 0x00 20. "SNP,Serialize Non-Posted Requests" "0,1"
newline
bitfld.long 0x00 19. "FUNC_BYPASS,Function Number Translation Bypass" "0,1"
newline
bitfld.long 0x00 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "TAG,TAG"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code)"
group.long 0x300608++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30060C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300610++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300614++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address Register"
hexmask.long 0x00 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used"
group.long 0x300618++0x03
line.long 0x00 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region"
group.long 0x300700++0x03
line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1 Register"
bitfld.long 0x00 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size" "0,1"
newline
bitfld.long 0x00 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3"
newline
bitfld.long 0x00 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1"
newline
bitfld.long 0x00 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300704++0x03
line.long 0x00 "IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2 Register"
bitfld.long 0x00 31. "REGION_EN,Region Enable" "0,1"
newline
bitfld.long 0x00 30. "MATCH_MODE,Match Mode" "0: Address Match Mode,1: Vendor ID Match Mode"
newline
bitfld.long 0x00 29. "INVERT_MODE,Invert Mode" "0,1"
newline
bitfld.long 0x00 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1"
newline
bitfld.long 0x00 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode" "0,1"
newline
bitfld.long 0x00 24.--25. "RESPONSE_CODE,Response Code" "0: Normal RADM filter response is used,1: Unsupported request (UR),2: Completer abort (CA),3: Not used / undefined / reserved"
newline
bitfld.long 0x00 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable" "0,1"
newline
bitfld.long 0x00 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS)" "0,1"
newline
bitfld.long 0x00 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable" "0,1"
newline
bitfld.long 0x00 16. "ATTR_MATCH_EN,ATTR Match Enable" "0,1"
newline
bitfld.long 0x00 15. "TD_MATCH_EN,TD Match Enable" "0,1"
newline
bitfld.long 0x00 14. "TC_MATCH_EN,TC Match Enable" "0,1"
newline
bitfld.long 0x00 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode" "0,1"
newline
bitfld.long 0x00 8.--10. "BAR_NUM,BAR Number" "0: BAR0,1: BAR1,2: BAR2,3: BAR3,4: BAR4,5: BAR5,6: ROM,7: reserved - IO"
newline
hexmask.long.byte 0x00 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code)"
group.long 0x300708++0x03
line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated"
group.long 0x30070C++0x03
line.long 0x00 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address Register"
hexmask.long 0x00 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated"
group.long 0x300710++0x03
line.long 0x00 "IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address Register"
hexmask.long.word 0x00 16.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated"
group.long 0x300714++0x03
line.long 0x00 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address Register"
hexmask.long.word 0x00 16.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region"
newline
hexmask.long.word 0x00 0.--15. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region"
group.long 0x380000++0x03
line.long 0x00 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface"
hexmask.long.tbyte 0x00 12.--31. 1. "RSVDP_12,Reserved for future use"
newline
bitfld.long 0x00 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests" "0,1,2,3,4,5,6,7"
group.long 0x380008++0x03
line.long 0x00 "DMA_CTRL_OFF,DMA Number of Channels Register"
rbitfld.long 0x00 26.--31. "RSVDP_26,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels completion to memory write context cache pre-fetch function" "0,1"
newline
bitfld.long 0x00 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels completion to memory write context cache pre-fetch function" "0,1"
newline
rbitfld.long 0x00 20.--23. "RSVDP_20,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "NUM_DMA_RD_CHAN,Number of Read Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 4.--15. 1. "RSVDP_4,Reserved for future use"
newline
rbitfld.long 0x00 0.--3. "NUM_DMA_WR_CHAN,Number of Write Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38000C++0x03
line.long 0x00 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
hexmask.long.word 0x00 1.--15. 1. "RSVDP_1,Reserved for future use"
newline
bitfld.long 0x00 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable" "0: Disable (Soft Reset),1: Enable"
group.long 0x380010++0x03
line.long 0x00 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register"
bitfld.long 0x00 31. "WR_STOP,Stop" "0,1"
newline
hexmask.long 0x00 3.--30. 1. "RSVDP_3,Reserved for future use"
newline
bitfld.long 0x00 0.--2. "WR_DOORBELL_NUM,Doorbell Number" "0,1,2,3,4,5,6,7"
group.long 0x380018++0x03
line.long 0x00 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register"
hexmask.long.word 0x00 20.--31. 1. "RSVDP_20,Reserved for future use"
newline
bitfld.long 0x00 15.--19. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--14. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38001C++0x03
line.long 0x00 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register"
hexmask.long.word 0x00 20.--31. 1. "RSVDP_20,Reserved for future use"
newline
bitfld.long 0x00 15.--19. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--14. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38002C++0x03
line.long 0x00 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
hexmask.long.word 0x00 1.--15. 1. "RSVDP_1,Reserved for future use"
newline
bitfld.long 0x00 0. "DMA_READ_ENGINE,DMA Read Engine Enable" "0: Disable (Soft Reset),1: Enable"
group.long 0x380030++0x03
line.long 0x00 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register"
bitfld.long 0x00 31. "RD_STOP,Stop" "0,1"
newline
hexmask.long 0x00 3.--30. 1. "RSVDP_3,Reserved for future use"
newline
bitfld.long 0x00 0.--2. "RD_DOORBELL_NUM,Doorbell Number" "0,1,2,3,4,5,6,7"
group.long 0x380038++0x03
line.long 0x00 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register"
hexmask.long.word 0x00 20.--31. 1. "RSVDP_20,Reserved for future use"
newline
bitfld.long 0x00 15.--19. "READ_CHANNEL3_WEIGHT,Channel 3 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--14. "READ_CHANNEL2_WEIGHT,Channel 2 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "READ_CHANNEL1_WEIGHT,Channel 1 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "READ_CHANNEL0_WEIGHT,Channel 0 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38003C++0x03
line.long 0x00 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register"
hexmask.long.word 0x00 20.--31. 1. "RSVDP_20,Reserved for future use"
newline
bitfld.long 0x00 15.--19. "READ_CHANNEL7_WEIGHT,Channel 7 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--14. "READ_CHANNEL6_WEIGHT,Channel 6 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "READ_CHANNEL5_WEIGHT,Channel 5 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "READ_CHANNEL4_WEIGHT,Channel 4 Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38004C++0x03
line.long 0x00 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
hexmask.long.byte 0x00 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
hexmask.long.byte 0x00 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status"
group.long 0x380054++0x03
line.long 0x00 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
bitfld.long 0x00 16. "WR_ABORT_INT_MASK,Abort Interrupt Mask" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
bitfld.long 0x00 0. "WR_DONE_INT_MASK,Done Interrupt Mask" "0,1"
group.long 0x380058++0x03
line.long 0x00 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
eventfld.long 0x00 16. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
eventfld.long 0x00 0. "WR_DONE_INT_CLEAR,Done Interrupt Clear" "0,1"
rgroup.long 0x38005C++0x03
line.long 0x00 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
hexmask.long.byte 0x00 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
hexmask.long.byte 0x00 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected"
group.long 0x380060++0x03
line.long 0x00 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register"
hexmask.long 0x00 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP"
group.long 0x380064++0x03
line.long 0x00 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register"
hexmask.long 0x00 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP"
group.long 0x380068++0x03
line.long 0x00 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register"
hexmask.long 0x00 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates"
group.long 0x38006C++0x03
line.long 0x00 "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register"
hexmask.long 0x00 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP"
group.long 0x380070++0x03
line.long 0x00 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1"
newline
hexmask.long.word 0x00 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0"
group.long 0x380074++0x03
line.long 0x00 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3"
newline
hexmask.long.word 0x00 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2"
group.long 0x380078++0x03
line.long 0x00 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5"
newline
hexmask.long.word 0x00 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4"
group.long 0x38007C++0x03
line.long 0x00 "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7"
newline
hexmask.long.word 0x00 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6"
group.long 0x380090++0x03
line.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
bitfld.long 0x00 16. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE)" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
bitfld.long 0x00 0. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE)" "0,1"
group.long 0x3800A0++0x03
line.long 0x00 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
hexmask.long.byte 0x00 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status"
group.long 0x3800A8++0x03
line.long 0x00 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
bitfld.long 0x00 16. "RD_ABORT_INT_MASK,Abort Interrupt Mask" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
bitfld.long 0x00 0. "RD_DONE_INT_MASK,Done Interrupt Mask" "0,1"
group.long 0x3800AC++0x03
line.long 0x00 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
hexmask.long.byte 0x00 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear"
rgroup.long 0x3800B4++0x03
line.long 0x00 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
hexmask.long.byte 0x00 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
hexmask.long.byte 0x00 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected"
rgroup.long 0x3800B8++0x03
line.long 0x00 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register"
hexmask.long.byte 0x00 24.--31. 1. "DATA_POISIONING,Data Poisoning"
newline
hexmask.long.byte 0x00 16.--23. 1. "CPL_TIMEOUT,Completion Time Out"
newline
hexmask.long.byte 0x00 8.--15. 1. "CPL_ABORT,Completer Abort"
newline
hexmask.long.byte 0x00 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request"
group.long 0x3800C4++0x03
line.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register"
hexmask.long.byte 0x00 24.--31. 1. "RSVDP_24,Reserved for future use"
newline
bitfld.long 0x00 16. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE)" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVDP_8,Reserved for future use"
newline
bitfld.long 0x00 0. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE)" "0,1"
group.long 0x3800CC++0x03
line.long 0x00 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register"
hexmask.long 0x00 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP"
group.long 0x3800D0++0x03
line.long 0x00 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register"
hexmask.long 0x00 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP"
group.long 0x3800D4++0x03
line.long 0x00 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register"
hexmask.long 0x00 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP"
group.long 0x3800D8++0x03
line.long 0x00 "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register"
hexmask.long 0x00 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP"
group.long 0x3800DC++0x03
line.long 0x00 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1"
newline
hexmask.long.word 0x00 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0"
group.long 0x3800E0++0x03
line.long 0x00 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3"
newline
hexmask.long.word 0x00 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2"
group.long 0x3800E4++0x03
line.long 0x00 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5"
newline
hexmask.long.word 0x00 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4"
group.long 0x3800E8++0x03
line.long 0x00 "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register"
hexmask.long.word 0x00 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7"
newline
hexmask.long.word 0x00 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6"
group.long 0x380200++0x03
line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register"
bitfld.long 0x00 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs" "0,1,2,3"
newline
bitfld.long 0x00 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 26. "DMA_RESERVED5,Reserved" "0,1"
newline
bitfld.long 0x00 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs" "0,1"
newline
bitfld.long 0x00 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC)" "0,1"
newline
bitfld.long 0x00 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST)" "0,1"
newline
bitfld.long 0x00 17.--22. "DMA_RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--16. "DMA_FUNC_NUM,Function Number (FN)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--11. "DMA_RESERVED1,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 9. "LLE,Linked List Enable (LLE)" "0: Disable linked list operation,1: Enable linked list operation"
newline
bitfld.long 0x00 8. "CCS,Consumer Cycle State (CCS)" "0,1"
newline
bitfld.long 0x00 7. "DMA_RESERVED0,Reserved" "0,1"
newline
rbitfld.long 0x00 5.--6. "CS,Channel Status (CS)" "0: Reserved,1: Running,2: Halted,3: Stopped"
newline
bitfld.long 0x00 4. "RIE,Remote Interrupt Enable (RIE)" "0,1"
newline
bitfld.long 0x00 3. "LIE,Local Interrupt Enable (LIE)" "0,1"
newline
bitfld.long 0x00 2. "LLP,Load Link Pointer (LLP)" "0,1"
newline
bitfld.long 0x00 1. "TCB,Toggle Cycle Bit (TCB)" "0,1"
newline
bitfld.long 0x00 0. "CB,Cycle Bit (CB)" "0,1"
group.long 0x380208++0x03
line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register"
hexmask.long 0x00 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size"
group.long 0x38020C++0x03
line.long 0x00 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register"
hexmask.long 0x00 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits)"
group.long 0x380210++0x03
line.long 0x00 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register"
hexmask.long 0x00 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits)"
group.long 0x380214++0x03
line.long 0x00 "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register"
hexmask.long 0x00 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits)"
group.long 0x380218++0x03
line.long 0x00 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register"
hexmask.long 0x00 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits)"
group.long 0x38021C++0x03
line.long 0x00 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register"
hexmask.long 0x00 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory"
group.long 0x380220++0x03
line.long 0x00 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register"
hexmask.long 0x00 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory"
group.long 0x380300++0x03
line.long 0x00 "DMA_CH_CONTROL1_OFF_RDCH_0,DMA Read Channel Control 1 Register"
bitfld.long 0x00 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs" "0,1,2,3"
newline
bitfld.long 0x00 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 26. "DMA_RESERVED5,Reserved" "0,1"
newline
bitfld.long 0x00 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs" "0,1"
newline
bitfld.long 0x00 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC)" "0,1"
newline
bitfld.long 0x00 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST)" "0,1"
newline
bitfld.long 0x00 17.--22. "DMA_RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--16. "DMA_FUNC_NUM,Function Number (FN)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--11. "DMA_RESERVED1,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 9. "LLE,Linked List Enable (LLE)" "0: Disable linked list operation,1: Enable linked list operation"
newline
bitfld.long 0x00 8. "CCS,Consumer Cycle State (CCS)" "0,1"
newline
bitfld.long 0x00 7. "DMA_RESERVED0,Reserved" "0,1"
newline
rbitfld.long 0x00 5.--6. "CS,Channel Status (CS)" "0: Reserved,1: Running,2: Halted,3: Stopped"
newline
bitfld.long 0x00 4. "RIE,Remote Interrupt Enable (RIE)" "0,1"
newline
bitfld.long 0x00 3. "LIE,Local Interrupt Enable (LIE)" "0,1"
newline
bitfld.long 0x00 2. "LLP,Load Link Pointer (LLP)" "0,1"
newline
bitfld.long 0x00 1. "TCB,Toggle Cycle Bit (TCB)" "0,1"
newline
bitfld.long 0x00 0. "CB,Cycle Bit (CB)" "0,1"
group.long 0x380308++0x03
line.long 0x00 "DMA_TRANSFER_SIZE_OFF_RDCH_0,DMA Read Transfer Size Register"
hexmask.long 0x00 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size"
group.long 0x38030C++0x03
line.long 0x00 "DMA_SAR_LOW_OFF_RDCH_0,DMA Read SAR Low Register"
hexmask.long 0x00 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits)"
group.long 0x380310++0x03
line.long 0x00 "DMA_SAR_HIGH_OFF_RDCH_0,DMA Read SAR High Register"
hexmask.long 0x00 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits)"
group.long 0x380314++0x03
line.long 0x00 "DMA_DAR_LOW_OFF_RDCH_0,DMA Read DAR Low Register"
hexmask.long 0x00 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits)"
group.long 0x380318++0x03
line.long 0x00 "DMA_DAR_HIGH_OFF_RDCH_0,DMA Read DAR High Register"
hexmask.long 0x00 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits)"
group.long 0x38031C++0x03
line.long 0x00 "DMA_LLP_LOW_OFF_RDCH_0,DMA Read Linked List Pointer Low Register"
hexmask.long 0x00 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory"
group.long 0x380320++0x03
line.long 0x00 "DMA_LLP_HIGH_OFF_RDCH_0,DMA Read Linked List Pointer High Register"
hexmask.long 0x00 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory"
tree.end
tree "PCIE_PHY (PCIe PHY)"
base ad:0x32F00000
group.byte 0x00++0x00
line.byte 0x00 "CMN_REG000,no description available"
bitfld.byte 0x00 3. "OVRD_BGR_EN,Override enable for bgr_en" "0,1"
bitfld.byte 0x00 2. "BGR_EN,BGR enable" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_BGR_LPF_BYPASS,Override enable for bgr_lpf_bypass" "0,1"
bitfld.byte 0x00 0. "BGR_LPF_BYPASS,BGR LPF bypass to reduce BGR settle time" "0,1"
group.byte 0x04++0x00
line.byte 0x00 "CMN_REG001,no description available"
bitfld.byte 0x00 2.--6. "ANA_BGR_820M_SEL,BGR 820mV selection ( for current bias )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 1. "ANA_BGR_CLK_EN,BGR chopper clock enable" "0,1"
newline
bitfld.byte 0x00 0. "ANA_BGR_LADDER_EN,BGR output voltage selection" "0,1"
group.byte 0x08++0x00
line.byte 0x00 "CMN_REG002,no description available"
bitfld.byte 0x00 5.--7. "ANA_BGR_LADDER_SEL,Resistor ladder voltage selection" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 4. "ANA_BGR_ATB_SEL,BGR ATB select" "0,1"
newline
bitfld.byte 0x00 3. "OVRD_BIAS_EN,Override enable for bias_en" "0,1"
bitfld.byte 0x00 2. "BIAS_EN,Bias current enable" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_BIAS_RCAL_EN,Override enable for bias_rcal_en" "0,1"
bitfld.byte 0x00 0. "BIAS_RCAL_EN,RX RCAL bias current enable" "0,1"
group.byte 0x0C++0x00
line.byte 0x00 "CMN_REG003,no description available"
bitfld.byte 0x00 4.--5. "ANA_BIAS_IREXT_CTRL,REXT-refered bias current controlI for overall IP" "0,1,2,3"
bitfld.byte 0x00 2.--3. "ANA_BIAS_RX_RCAL_IREXT_CTRL,REXT-refered bias current controlI for RX RCAL" "0,1,2,3"
newline
bitfld.byte 0x00 0.--1. "ANA_BIAS_TX_RCAL_IREXT_CTRL,REXT-refered bias current control MSB for TX RCAL" "0,1,2,3"
group.byte 0x10++0x00
line.byte 0x00 "CMN_REG004,no description available"
bitfld.byte 0x00 1. "OVRD_PLL_EN,Override enable for pll_en" "0,1"
bitfld.byte 0x00 0. "PLL_EN,PLL enable" "0,1"
group.byte 0x14++0x00
line.byte 0x00 "CMN_REG005,no description available"
bitfld.byte 0x00 7. "PLL_VCO_MODE_G1,[GEN1] PLL VCO selection" "0,1"
bitfld.byte 0x00 6. "PLL_VCO_MODE_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 5. "PLL_VCO_MODE_G3,[GEN3]" "0,1"
bitfld.byte 0x00 4. "PLL_VCO_MODE_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 3. "OVRD_PLL_AFC_INIT_RSTN,Override enable for pll_afc_init_rstn" "0,1"
bitfld.byte 0x00 2. "PLL_AFC_INIT_RSTN,PLL AFC initial reset" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_PLL_AFC_RSTN,Override enable for pll_afc_rstn" "0,1"
bitfld.byte 0x00 0. "PLL_AFC_RSTN,PLL AFC reset" "0,1"
group.byte 0x18++0x00
line.byte 0x00 "CMN_REG006,no description available"
bitfld.byte 0x00 5. "ANA_PLL_AFC_CLK_DIV2_EN,PLL AFC clock frequency selection" "0,1"
bitfld.byte 0x00 4. "ANA_PLL_AFC_CODE_FORCE,PLL AFC code manual selection enable" "0,1"
newline
bitfld.byte 0x00 3. "ANA_PLL_AFC_EN,PLL AFC enable if enabled VCO frequency is automatically calibrated" "0,1"
bitfld.byte 0x00 2. "ANA_PLL_AFC_FROM_PRE_CODE,PLL AFC option in restart case" "0,1"
newline
bitfld.byte 0x00 0.--1. "ANA_PLL_AFC_MAN_LC_CODE_SEL,Manual PLL AFC code selection (MSB)" "0,1,2,3"
group.byte 0x1C++0x00
line.byte 0x00 "CMN_REG007,no description available"
bitfld.byte 0x00 4.--7. "ANA_PLL_AFC_MAN_RING_CODE_SEL,Manual PLL AFC code selection (LSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "ANA_PLL_AFC_STB_NUM,Number of reference clock cycle to check VCO stabilization during PLL AFC start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x20++0x00
line.byte 0x00 "CMN_REG008,no description available"
bitfld.byte 0x00 1.--4. "ANA_PLL_AFC_TOL_NUM,PLL VCO stabilization tolerance VCO is considered as settled-down if |counter difference|&lt i_pll_afc_tol during i_pll_afc_stb_num" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "ANA_PLL_AFC_VCI_FORCE,PLL control voltage force for open-loop test purpose" "0,1"
group.byte 0x24++0x00
line.byte 0x00 "CMN_REG009,no description available"
bitfld.byte 0x00 3.--7. "ANA_PLL_AFC_VCO_CNT_RUN_NUM,Number of reference clock cycle to wait VCO clock during AFC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 0.--2. "ANA_PLL_AFC_VCO_CNT_WAIT_NUM,Number of reference clock cycle to count VCO clock during AFC" "0,1,2,3,4,5,6,7"
group.byte 0x28++0x00
line.byte 0x00 "CMN_REG00A,no description available"
bitfld.byte 0x00 5.--7. "ANA_PLL_AFC_VCO_START_CRITERION,Minimum PLL VCO counter value to start AFC (Criterion to suppose PLL VCO successfully start to oscillate)" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 4. "ANA_PLL_AGMC_COMP_EN,Comparator enable for PLL LC VCO automatic gm search" "0,1"
newline
bitfld.byte 0x00 3. "ANA_PLL_AGMC_FROM_MAX_GM,PLL LC VCO automatic gm search initial condition" "0,1"
bitfld.byte 0x00 1.--2. "ANA_PLL_AGMC_GM_ADD,Offset code to be added to final gm code" "0,1,2,3"
newline
bitfld.byte 0x00 0. "ANA_PLL_AGMC_MAN_GM_SEL_EN,PLL LC VCO GM code selection" "0,1"
group.byte 0x2C++0x00
line.byte 0x00 "CMN_REG00B,no description available"
bitfld.byte 0x00 0.--3. "ANA_PLL_AGMC_MAN_GM_SEL,Manual GM code selection for LC VCO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x30++0x00
line.byte 0x00 "CMN_REG00C,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_AGMC_TG_CODE_G1,[GEN1] Target counter value for automatic GM search of LC VCO"
group.byte 0x34++0x00
line.byte 0x00 "CMN_REG00D,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_AGMC_TG_CODE_G2,[GEN2]"
group.byte 0x38++0x00
line.byte 0x00 "CMN_REG00E,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_AGMC_TG_CODE_G3,[GEN3]"
group.byte 0x3C++0x00
line.byte 0x00 "CMN_REG00F,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_AGMC_TG_CODE_G4,[GEN4]"
group.byte 0x40++0x00
line.byte 0x00 "CMN_REG010,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_CPI_CTRL_COARSE_G1,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_CPI_CTRL_COARSE_G2,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
group.byte 0x44++0x00
line.byte 0x00 "CMN_REG011,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_CPI_CTRL_COARSE_G3,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_CPI_CTRL_COARSE_G4,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
group.byte 0x48++0x00
line.byte 0x00 "CMN_REG012,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_CPI_CTRL_FINE_G1,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_CPI_CTRL_FINE_G2,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
group.byte 0x4C++0x00
line.byte 0x00 "CMN_REG013,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_CPI_CTRL_FINE_G3,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_CPI_CTRL_FINE_G4,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7"
group.byte 0x50++0x00
line.byte 0x00 "CMN_REG014,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_CPP_CTRL_COARSE_G1,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_CPP_CTRL_COARSE_G2,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x54++0x00
line.byte 0x00 "CMN_REG015,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_CPP_CTRL_COARSE_G3,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_CPP_CTRL_COARSE_G4,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x58++0x00
line.byte 0x00 "CMN_REG016,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_CPP_CTRL_FINE_G1,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_CPP_CTRL_FINE_G2,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x5C++0x00
line.byte 0x00 "CMN_REG017,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_CPP_CTRL_FINE_G3,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_CPP_CTRL_FINE_G4,[GEN1] PLL integral path charge-pump current contorl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x60++0x00
line.byte 0x00 "CMN_REG018,no description available"
bitfld.byte 0x00 4.--6. "ANA_PLL_ANA_LC_CAP_OFFSET_SEL,LC VCO varactor bias voltage selection" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 3. "ANA_PLL_ANA_LC_GM_COMP_CTRL,no description available" "0,1"
newline
bitfld.byte 0x00 0.--2. "ANA_PLL_ANA_LC_GM_COMP_VREF_SEL,PLL GM comparator reference voltage selection" "0,1,2,3,4,5,6,7"
group.byte 0x64++0x00
line.byte 0x00 "CMN_REG019,no description available"
bitfld.byte 0x00 4.--5. "ANA_PLL_ANA_LC_VREG_I_CTRL,LC VCO Vreg current branch enable (1+1/20 or 1+ 1/33)" "0,1,2,3"
bitfld.byte 0x00 3. "ANA_PLL_ANA_LC_VREF_BYPASS,LPF on reference voltage for PLL LC VCO bypass" "0,1"
newline
bitfld.byte 0x00 0.--2. "ANA_PLL_ANA_LC_VREG_R_SEL,LC VCO voltage regulator output control" "0,1,2,3,4,5,6,7"
group.byte 0x68++0x00
line.byte 0x00 "CMN_REG01A,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_LPF_C_SEL_COARSE_G1,[GEN1] [Coarse Mode] PLL loop filter capacitor control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_LPF_C_SEL_COARSE_G2,[GEN2] [Coarse Mode]" "0,1,2,3,4,5,6,7"
group.byte 0x6C++0x00
line.byte 0x00 "CMN_REG01B,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_LPF_C_SEL_COARSE_G3,[GEN3] [Coarse Mode]" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_LPF_C_SEL_COARSE_G4,[GEN4] [Coarse Mode]" "0,1,2,3,4,5,6,7"
group.byte 0x70++0x00
line.byte 0x00 "CMN_REG01C,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_LPF_C_SEL_FINE_G1,[GEN1] [Fine Mode] PLL loop filter capacitor control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_LPF_C_SEL_FINE_G2,[GEN2] [Fine Mode]" "0,1,2,3,4,5,6,7"
group.byte 0x74++0x00
line.byte 0x00 "CMN_REG01D,no description available"
bitfld.byte 0x00 3.--5. "PLL_ANA_LPF_C_SEL_FINE_G3,[GEN3] [Fine Mode]" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_ANA_LPF_C_SEL_FINE_G4,[GEN4] [Fine Mode]" "0,1,2,3,4,5,6,7"
group.byte 0x78++0x00
line.byte 0x00 "CMN_REG01E,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_LPF_R_SEL_COARSE_G1,[GEN1] [Coarse Mode] PLL loop filter resistor control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_LPF_R_SEL_COARSE_G2,[GEN2] [Coarse Mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x7C++0x00
line.byte 0x00 "CMN_REG01F,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_LPF_R_SEL_COARSE_G3,[GEN3] [Coarse Mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_LPF_R_SEL_COARSE_G4,[GEN4] [Coarse Mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x80++0x00
line.byte 0x00 "CMN_REG020,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_LPF_R_SEL_FINE_G1,[GEN1] [Fine Mode] PLL loop filter resistor control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_LPF_R_SEL_FINE_G2,[GEN2] [Fine Mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x84++0x00
line.byte 0x00 "CMN_REG021,no description available"
bitfld.byte 0x00 4.--7. "PLL_ANA_LPF_R_SEL_FINE_G3,[GEN3] [Fine Mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_ANA_LPF_R_SEL_FINE_G4,[GEN4] [Fine Mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x88++0x00
line.byte 0x00 "CMN_REG022,no description available"
bitfld.byte 0x00 1.--4. "ANA_PLL_ANA_RING_DCC_EN,PLL ring VCO DCC enable for each phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "ANA_PLL_ANA_RING_IQ_DIV_EN,I/Q divider enable for PLL ring VCO clock" "0,1"
group.byte 0x8C++0x00
line.byte 0x00 "CMN_REG023,no description available"
bitfld.byte 0x00 6.--7. "PLL_ANA_RING_PI_RATIO_CTRL_COARSE,Ratio between proportional and integral path gain" "0,1,2,3"
bitfld.byte 0x00 4.--5. "PLL_ANA_RING_PI_RATIO_CTRL_FINE,Ratio between proportional and integral path gain" "0,1,2,3"
newline
bitfld.byte 0x00 1.--3. "ANA_PLL_ANA_VCI_SEL,PLL control voltage selection in AFC or open-loop test" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0. "ANA_PLL_ANA_VCI_TEST_EN,PLL VCO test mode enable" "0,1"
group.byte 0x90++0x00
line.byte 0x00 "CMN_REG024,no description available"
hexmask.byte 0x00 1.--7. 1. "ANA_PLL_ATB_SEL,Select PLL ATB"
bitfld.byte 0x00 0. "ANA_PLL_EOM_PH_FINE_STEP,EOM phase resolution enhancement" "0,1"
group.byte 0x94++0x00
line.byte 0x00 "CMN_REG025,no description available"
bitfld.byte 0x00 5. "ANA_PLL_EOM_PH_FIX,Phase shift enable for EOM" "0,1"
bitfld.byte 0x00 1.--4. "ANA_PLL_EOM_PH_SEL,EOM phase selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "ANA_PLL_FLD_FAST_BYPASS,PLL fast frequency lock detection bypass" "0,1"
group.byte 0x98++0x00
line.byte 0x00 "CMN_REG026,no description available"
bitfld.byte 0x00 5.--7. "ANA_PLL_FLD_FAST_SETTLE_NUM,Number of reference clock cycle to check VCO stabilization in fast FLD" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--4. "ANA_PLL_FLD_LOCK_TOL_NUM,FLD lock tolerance setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x9C++0x00
line.byte 0x00 "CMN_REG027,no description available"
bitfld.byte 0x00 1. "ANA_PLL_FLD_NON_CONTINUOUS_MODE,Check frequency lock detection of PLL" "0,1"
bitfld.byte 0x00 0. "ANA_PLL_FLD_SLOW_BYPASS,PLL slow frequency lock detection bypass" "0,1"
group.byte 0xA0++0x00
line.byte 0x00 "CMN_REG028,no description available"
bitfld.byte 0x00 3. "PLL_PI_EN_G1,[GEN1] PLL phase interpolator enable" "0,1"
bitfld.byte 0x00 2. "PLL_PI_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "PLL_PI_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "PLL_PI_EN_G4,[GEN4]" "0,1"
group.byte 0xA4++0x00
line.byte 0x00 "CMN_REG029,no description available"
bitfld.byte 0x00 4.--7. "PLL_PI_STR_G1,[GEN1] PLL phase interpolator input buffer strength control for Gen3 and Gen4 ( for 8GHz VCO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_PI_STR_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xA8++0x00
line.byte 0x00 "CMN_REG02A,no description available"
bitfld.byte 0x00 4.--7. "PLL_PI_STR_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_PI_STR_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xAC++0x00
line.byte 0x00 "CMN_REG02B,no description available"
bitfld.byte 0x00 3. "OVRD_PLL_PMS_MDIV_RSTN,Override enable for pll_pms_mdiv_rstn" "0,1"
bitfld.byte 0x00 2. "PLL_PMS_MDIV_RSTN,PLL main divider reset" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_PLL_PMS_PDIV_RSTN,Override enable for pll_pms_pdiv_rstn" "0,1"
bitfld.byte 0x00 0. "PLL_PMS_PDIV_RSTN,PLL pre-divider reset" "0,1"
group.byte 0xB0++0x00
line.byte 0x00 "CMN_REG02C,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_AFC_G1,[GEN1] PLL AFC target value (fVCO/fREF) setting"
group.byte 0xB4++0x00
line.byte 0x00 "CMN_REG02D,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_AFC_G2,[GEN2]"
group.byte 0xB8++0x00
line.byte 0x00 "CMN_REG02E,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_AFC_G3,[GEN3]"
group.byte 0xBC++0x00
line.byte 0x00 "CMN_REG02F,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_AFC_G4,[GEN4]"
group.byte 0xC0++0x00
line.byte 0x00 "CMN_REG030,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_G1,[GEN1] PLL main divider setting"
group.byte 0xC4++0x00
line.byte 0x00 "CMN_REG031,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_G2,[GEN2]"
group.byte 0xC8++0x00
line.byte 0x00 "CMN_REG032,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_G3,[GEN3]"
group.byte 0xCC++0x00
line.byte 0x00 "CMN_REG033,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_PMS_MDIV_G4,[GEN4]"
group.byte 0xD0++0x00
line.byte 0x00 "CMN_REG034,no description available"
bitfld.byte 0x00 4. "ANA_PLL_PMS_MDIV_X2_EN,PLL main divider extra X2 enable" "0,1"
bitfld.byte 0x00 0.--3. "ANA_PLL_PMS_PDIV,PLL pre-divider setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD4++0x00
line.byte 0x00 "CMN_REG035,no description available"
bitfld.byte 0x00 0.--3. "ANA_PLL_PMS_REFDIV,PLL reference clock divider setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD8++0x00
line.byte 0x00 "CMN_REG036,no description available"
bitfld.byte 0x00 4.--7. "PLL_PMS_SDIV_G1,[GEN1] PLL post divider setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_PMS_SDIV_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xDC++0x00
line.byte 0x00 "CMN_REG037,no description available"
bitfld.byte 0x00 4.--7. "PLL_PMS_SDIV_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_PMS_SDIV_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xE0++0x00
line.byte 0x00 "CMN_REG038,no description available"
bitfld.byte 0x00 6. "OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN,Override enable for pll_ref_chopper_clk_div_rstn" "0,1"
bitfld.byte 0x00 5. "PLL_REF_CHOPPER_CLK_DIV_RSTN,Chopper clk divider reset" "0,1"
newline
bitfld.byte 0x00 3.--4. "ANA_PLL_REF_BYPASS_CLK_SEL,PLL Bypass clock selection" "0,1,2,3"
bitfld.byte 0x00 1.--2. "ANA_PLL_REF_CHOPPER_CLK_DIV_SEL,Chopper clk divider value" "0,1,2,3"
newline
bitfld.byte 0x00 0. "ANA_PLL_REF_CHOPPER_CLK_EN,Chopper clk enable" "0,1"
group.byte 0xE4++0x00
line.byte 0x00 "CMN_REG039,no description available"
bitfld.byte 0x00 3. "OVRD_PLL_REF_CLK_SEL,Override enable for pll_ref_clk_sel" "0,1"
bitfld.byte 0x00 1.--2. "PLL_REF_CLK_SEL,PLL reference clock selection" "0,1,2,3"
newline
bitfld.byte 0x00 0. "ANA_PLL_REF_DIG_CLK_SEL,no description available" "0,1"
group.byte 0xE8++0x00
line.byte 0x00 "CMN_REG03A,no description available"
bitfld.byte 0x00 5. "PLL_SDM_EN_G1,[GEN1] PLL SDM enable" "0,1"
bitfld.byte 0x00 4. "PLL_SDM_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 3. "PLL_SDM_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 2. "PLL_SDM_EN_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_PLL_SDM_RSTN,Override enable for pll_sdm_rstn" "0,1"
bitfld.byte 0x00 0. "PLL_SDM_RSTN,PLL SDM reset" "0,1"
group.byte 0xEC++0x00
line.byte 0x00 "CMN_REG03B,no description available"
bitfld.byte 0x00 5. "PLL_SDC_FRACTIONAL_EN_G1,[GEN1] Fractional clock divide in SDM clock generation" "0,1"
bitfld.byte 0x00 4. "PLL_SDC_FRACTIONAL_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 3. "PLL_SDC_FRACTIONAL_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 2. "PLL_SDC_FRACTIONAL_EN_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_PLL_SDC_RSTN,Override enable for pll_sdc_rstn" "0,1"
bitfld.byte 0x00 0. "PLL_SDC_RSTN,PLL SDM clock generation (SDC) reset" "0,1"
group.byte 0xF0++0x00
line.byte 0x00 "CMN_REG03C,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_DENOMINATOR_G1,[GEN1] Denominator of SDM (Max. 255)"
group.byte 0xF4++0x00
line.byte 0x00 "CMN_REG03D,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_DENOMINATOR_G2,[GEN2]"
group.byte 0xF8++0x00
line.byte 0x00 "CMN_REG03E,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_DENOMINATOR_G3,[GEN3]"
group.byte 0xFC++0x00
line.byte 0x00 "CMN_REG03F,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_DENOMINATOR_G4,[GEN4]"
group.byte 0x100++0x00
line.byte 0x00 "CMN_REG040,no description available"
bitfld.byte 0x00 3. "PLL_SDM_NUMERATOR_SIGN_G1,[GEN1] Sign of SDM numerator" "0,1"
bitfld.byte 0x00 2. "PLL_SDM_NUMERATOR_SIGN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "PLL_SDM_NUMERATOR_SIGN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "PLL_SDM_NUMERATOR_SIGN_G4,[GEN4]" "0,1"
group.byte 0x104++0x00
line.byte 0x00 "CMN_REG041,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_NUMERATOR_G1,[GEN1] Numerator of SDM with i_pll_sdm_k_sign (-255~255)"
group.byte 0x108++0x00
line.byte 0x00 "CMN_REG042,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_NUMERATOR_G2,[GEN2]"
group.byte 0x10C++0x00
line.byte 0x00 "CMN_REG043,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_NUMERATOR_G3,[GEN3]"
group.byte 0x110++0x00
line.byte 0x00 "CMN_REG044,no description available"
hexmask.byte 0x00 0.--7. 1. "PLL_SDM_NUMERATOR_G4,[GEN4]"
group.byte 0x114++0x00
line.byte 0x00 "CMN_REG045,no description available"
bitfld.byte 0x00 3. "PLL_SDM_PH_NUM_SEL_G1,[GEN1] PLL PI input clock phase number" "0,1"
bitfld.byte 0x00 2. "PLL_SDM_PH_NUM_SEL_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "PLL_SDM_PH_NUM_SEL_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "PLL_SDM_PH_NUM_SEL_G4,[GEN4]" "0,1"
group.byte 0x118++0x00
line.byte 0x00 "CMN_REG046,no description available"
bitfld.byte 0x00 6.--7. "PLL_SDM_PI_STEP_G1,[GEN1] PLL phase interpolstor step" "0,1,2,3"
bitfld.byte 0x00 4.--5. "PLL_SDM_PI_STEP_G2,[GEN2]" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "PLL_SDM_PI_STEP_G3,[GEN3]" "0,1,2,3"
bitfld.byte 0x00 0.--1. "PLL_SDM_PI_STEP_G4,[GEN4]" "0,1,2,3"
group.byte 0x11C++0x00
line.byte 0x00 "CMN_REG047,no description available"
bitfld.byte 0x00 3.--5. "PLL_SDC_N_G1,[GEN1] PLL SDC divide-ratio selection" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_SDC_N_G2,[GEN2]" "0,1,2,3,4,5,6,7"
group.byte 0x120++0x00
line.byte 0x00 "CMN_REG048,no description available"
bitfld.byte 0x00 3.--5. "PLL_SDC_N_G3,[GEN3]" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "PLL_SDC_N_G4,[GEN4]" "0,1,2,3,4,5,6,7"
group.byte 0x124++0x00
line.byte 0x00 "CMN_REG049,no description available"
bitfld.byte 0x00 3. "PLL_SDC_N2_G1,[GEN1] PLL SDC divide-ratio selection" "0,1"
bitfld.byte 0x00 2. "PLL_SDC_N2_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "PLL_SDC_N2_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "PLL_SDC_N2_G4,[GEN4]" "0,1"
group.byte 0x128++0x00
line.byte 0x00 "CMN_REG04A,no description available"
bitfld.byte 0x00 0.--5. "PLL_SDC_NUMERATOR_G1,[GEN1] Numerator of SDC (Max 65)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x12C++0x00
line.byte 0x00 "CMN_REG04B,no description available"
bitfld.byte 0x00 0.--5. "PLL_SDC_NUMERATOR_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x130++0x00
line.byte 0x00 "CMN_REG04C,no description available"
bitfld.byte 0x00 0.--5. "PLL_SDC_NUMERATOR_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x134++0x00
line.byte 0x00 "CMN_REG04D,no description available"
bitfld.byte 0x00 0.--5. "PLL_SDC_NUMERATOR_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x138++0x00
line.byte 0x00 "CMN_REG04E,no description available"
bitfld.byte 0x00 0.--5. "PLL_SDC_DENOMINATOR_G1,[GEN1] Denominator of SDC (Max 65)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x13C++0x00
line.byte 0x00 "CMN_REG04F,no description available"
bitfld.byte 0x00 0.--5. "PLL_SDC_DENOMINATOR_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x140++0x00
line.byte 0x00 "CMN_REG050,no description available"
bitfld.byte 0x00 0.--5. "PLL_SDC_DENOMINATOR_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x144++0x00
line.byte 0x00 "CMN_REG051,no description available"
bitfld.byte 0x00 1.--6. "PLL_SDC_DENOMINATOR_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.byte 0x00 0. "ANA_PLL_SDC_MC_VALUE_SEL,PLL SDC value force" "0,1"
group.byte 0x148++0x00
line.byte 0x00 "CMN_REG052,no description available"
bitfld.byte 0x00 1. "OVRD_PLL_SSC_EN,Override enable for pll_ssc_en" "0,1"
bitfld.byte 0x00 0. "PLL_SSC_EN,PLL SSC enable" "0,1"
group.byte 0x14C++0x00
line.byte 0x00 "CMN_REG053,no description available"
bitfld.byte 0x00 0.--5. "PLL_SSC_FM_DEVIATION_G1,[GEN1] PLL SSC modulation deviation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x150++0x00
line.byte 0x00 "CMN_REG054,no description available"
bitfld.byte 0x00 0.--5. "PLL_SSC_FM_DEVIATION_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x154++0x00
line.byte 0x00 "CMN_REG055,no description available"
bitfld.byte 0x00 0.--5. "PLL_SSC_FM_DEVIATION_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x158++0x00
line.byte 0x00 "CMN_REG056,no description available"
bitfld.byte 0x00 0.--5. "PLL_SSC_FM_DEVIATION_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x15C++0x00
line.byte 0x00 "CMN_REG057,no description available"
bitfld.byte 0x00 0.--4. "PLL_SSC_FM_FREQ_G1,[GEN1] PLL SSC modulation frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x160++0x00
line.byte 0x00 "CMN_REG058,no description available"
bitfld.byte 0x00 0.--4. "PLL_SSC_FM_FREQ_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x164++0x00
line.byte 0x00 "CMN_REG059,no description available"
bitfld.byte 0x00 0.--4. "PLL_SSC_FM_FREQ_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x168++0x00
line.byte 0x00 "CMN_REG05A,no description available"
bitfld.byte 0x00 0.--4. "PLL_SSC_FM_FREQ_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x16C++0x00
line.byte 0x00 "CMN_REG05B,no description available"
bitfld.byte 0x00 6.--7. "PLL_SSC_PROFILE_OPT_G1,[GEN1] PLL SSC modulation profile shape control" "0,1,2,3"
bitfld.byte 0x00 4.--5. "PLL_SSC_PROFILE_OPT_G2,[GEN2]" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "PLL_SSC_PROFILE_OPT_G3,[GEN3]" "0,1,2,3"
bitfld.byte 0x00 0.--1. "PLL_SSC_PROFILE_OPT_G4,[GEN4]" "0,1,2,3"
group.byte 0x170++0x00
line.byte 0x00 "CMN_REG05C,no description available"
bitfld.byte 0x00 4.--7. "ANA_PLL_SSC_CLK_DIV_SEL,PLL SSC clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 3. "OVRD_PLL_CD_CLK_EN,Override enable for pll_cd_clk_en" "0,1"
newline
bitfld.byte 0x00 2. "PLL_CD_CLK_EN,CD enable" "0,1"
bitfld.byte 0x00 1. "OVRD_PLL_CD_TX_SER_RSTN,Override enable for pll_cd_tx_ser_rstn" "0,1"
newline
bitfld.byte 0x00 0. "PLL_CD_TX_SER_RSTN,TX_SER resetn" "0,1"
group.byte 0x174++0x00
line.byte 0x00 "CMN_REG05D,no description available"
bitfld.byte 0x00 6. "PLL_CD_TX_SER_RATE_SEL_G1,[GEN1] TX serializer data rate selection for Gen4 (Need to be controlled with i_tx_en_40bit)" "0,1"
bitfld.byte 0x00 5. "PLL_CD_TX_SER_RATE_SEL_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 4. "PLL_CD_TX_SER_RATE_SEL_G3,[GEN3]" "0,1"
bitfld.byte 0x00 3. "PLL_CD_TX_SER_RATE_SEL_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 2. "ANA_PLL_CD_HSCLK_INV,CD output clock polarity inversion" "0,1"
bitfld.byte 0x00 1. "ANA_PLL_CD_HSCLK_WEST_EN,CD driver nmos strength control" "0,1"
newline
bitfld.byte 0x00 0. "ANA_PLL_CD_HSCLK_EAST_EN,CD driver pmos strength control" "0,1"
group.byte 0x178++0x00
line.byte 0x00 "CMN_REG05E,no description available"
bitfld.byte 0x00 4. "OVRD_PLL_BEACON_LFPS_OUT_EN,Override enable for pll_beacon_lfps_out_en" "0,1"
bitfld.byte 0x00 3. "PLL_BEACON_LFPS_OUT_EN,TX beacon clock enable" "0,1"
newline
bitfld.byte 0x00 2. "ANA_PLL_MISC_CLK_SYNC_EN,PLL miscellaneous clock synchronization enable" "0,1"
bitfld.byte 0x00 0.--1. "ANA_PLL_MISC_CLK_SEL,PLL low-frequency clock output source selection" "0,1,2,3"
group.byte 0x17C++0x00
line.byte 0x00 "CMN_REG05F,no description available"
bitfld.byte 0x00 4.--7. "PLL_MISC_CLK_DIV_G1,[GEN1] PLL miscellaneous clock divider ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_MISC_CLK_DIV_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x180++0x00
line.byte 0x00 "CMN_REG060,no description available"
bitfld.byte 0x00 4.--7. "PLL_MISC_CLK_DIV_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PLL_MISC_CLK_DIV_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x184++0x00
line.byte 0x00 "CMN_REG061,no description available"
bitfld.byte 0x00 7. "OVRD_PLL_MISC_OSC_FREQ_SEL,Override enable for pll_misc_osc_freq_sel" "0,1"
bitfld.byte 0x00 3.--6. "PLL_MISC_OSC_FREQ_SEL,PLL miscellaneous clock frequency selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 2. "OVRD_PLL_MISC_OSC_RSTN,Override enable for pll_misc_osc_rstn" "0,1"
bitfld.byte 0x00 1. "PLL_MISC_OSC_RSTN,PLL miscellaneous clock oscillator reset" "0,1"
newline
bitfld.byte 0x00 0. "ANA_PLL_CLK_OUT_TO_EXT_IO_EN,PLL low-frequency clock output to external I/O enable" "0,1"
group.byte 0x188++0x00
line.byte 0x00 "CMN_REG062,no description available"
bitfld.byte 0x00 3. "ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,PLL low-frequency clock output to external I/O source selection" "0,1"
bitfld.byte 0x00 2. "ANA_PLL_REF_CLK_MON_EN,PLL reference clock monitor enable" "0,1"
newline
bitfld.byte 0x00 0.--1. "ANA_PLL_REF_CLK_MON_SEL,PLL reference clock selection for monitor" "0,1,2,3"
group.byte 0x18C++0x00
line.byte 0x00 "CMN_REG063,no description available"
bitfld.byte 0x00 6.--7. "AUX_PLL_REFCLK_SEL,0X: AUX_IN (PLL clock)" "0,1,2,3"
bitfld.byte 0x00 0.--5. "ANA_PLL_RESERVED,PLL Reserved pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x190++0x00
line.byte 0x00 "CMN_REG064,no description available"
bitfld.byte 0x00 7. "ANA_AUX_RX_TX_SEL,Select mode (TX or RX)" "0,1"
bitfld.byte 0x00 6. "OVRD_AUX_EN,Override enable for aux_en" "0,1"
newline
bitfld.byte 0x00 5. "AUX_EN,AUX Enable" "0,1"
bitfld.byte 0x00 4. "ANA_AUX_RX_CAP_BYPASS,External reference clock I/O AC-coupling capacitor bypass enable" "0,1"
newline
bitfld.byte 0x00 3. "ANA_AUX_RX_TERM_GND_EN,External reference clock I/O termination to ground" "0,1"
bitfld.byte 0x00 0.--2. "ANA_AUX_TX_TERM,TX termination resistor control" "0,1,2,3,4,5,6,7"
group.byte 0x194++0x00
line.byte 0x00 "CMN_REG065,no description available"
bitfld.byte 0x00 4.--7. "ANA_AUX_RX_TERM,RX termination resistor control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "ANA_AUX_TX_LVL_CTRL,TX Amplitude resistor control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x198++0x00
line.byte 0x00 "CMN_REG066,no description available"
bitfld.byte 0x00 7. "ANA_AUX_RX_VCM_SEL,Input common mode voltage control" "0,1"
bitfld.byte 0x00 5.--6. "ANA_AUX_RX_VCM_COARSE_CTRL,VCM of RX control" "0,1,2,3"
newline
bitfld.byte 0x00 3.--4. "ANA_AUX_RX_VCM_FINE_CTRL,VCM of RX control" "0,1,2,3"
bitfld.byte 0x00 0.--2. "ANA_AUX_RX_HYS_CTRL,Hysteresis for RX noise blocking control" "0,1,2,3,4,5,6,7"
group.byte 0x19C++0x00
line.byte 0x00 "CMN_REG067,no description available"
hexmask.byte 0x00 0.--7. 1. "ANA_AUX_RESERVED,Reserved port"
group.byte 0x1A0++0x00
line.byte 0x00 "CMN_REG068,no description available"
bitfld.byte 0x00 5. "OVRD_BGR_SET_DONE,Override enable for bgr_set_done" "0,1"
bitfld.byte 0x00 4. "BGR_SET_DONE,BGR set done" "0,1"
newline
bitfld.byte 0x00 3. "OVRD_PLL_AFC_DONE,Override enable for pll_afc_done" "0,1"
bitfld.byte 0x00 2. "PLL_AFC_DONE,PLL AFC done overide value" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_PLL_LOCK_DONE,Override enable for pll_lock_done" "0,1"
bitfld.byte 0x00 0. "PLL_LOCK_DONE,PLL lock done overide value" "0,1"
group.byte 0x1A4++0x00
line.byte 0x00 "CMN_REG069,no description available"
bitfld.byte 0x00 6. "OVRD_PHY_MODE,Override enable for phy_mode" "0,1"
bitfld.byte 0x00 4.--5. "PHY_MODE,no description available" "0,1,2,3"
newline
bitfld.byte 0x00 3. "OVRD_HIGH_SPEED,Override enable for high_speed" "0,1"
bitfld.byte 0x00 2. "HIGH_SPEED,HIGH SPEED indicator by operating LC VCO" "0,1"
newline
bitfld.byte 0x00 1. "OVRD_PLL_FINE_TUNE_START,Override enable for pll_fine_tune_start" "0,1"
bitfld.byte 0x00 0. "PLL_FINE_TUNE_START,no description available" "0,1"
group.byte 0x1A8++0x00
line.byte 0x00 "CMN_REG06A,no description available"
bitfld.byte 0x00 7. "OVRD_CMN_RATE,Override enable for cmn_rate" "0,1"
bitfld.byte 0x00 5.--6. "CMN_RATE,TX Data Rate manual setting" "0,1,2,3"
newline
bitfld.byte 0x00 4. "CMN_TIMER_SEL,no description available" "0,1"
bitfld.byte 0x00 0.--3. "TG_BGR_FAST_PULSE_TIME,BGR LPF bypass duration after BGR_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1AC++0x00
line.byte 0x00 "CMN_REG06B,no description available"
bitfld.byte 0x00 3.--5. "TG_BGR_SET_DELAY_TIME,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "TG_PLL_SDM_RSTN_DELAY_TIME,PLL SDM start delay after PLL integer-mode lock(PLL lock)" "0,1,2,3,4,5,6,7"
group.byte 0x1B0++0x00
line.byte 0x00 "CMN_REG06C,no description available"
bitfld.byte 0x00 3.--5. "TG_PLL_AFC_RSTN_DELAY_TIME,PLL AFC reset delay time after bypassing BGR LPF" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "TG_PLL_FINE_LOCK_DELAY_TIME,PLL Fine LOCK DLY CODE" "0,1,2,3,4,5,6,7"
group.byte 0x1B4++0x00
line.byte 0x00 "CMN_REG06D,no description available"
bitfld.byte 0x00 3.--5. "TG_PLL_SSC_EN_DELAY_TIME,PLL SSC start delay time after" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "TG_PLL_SDC_RSTN_DELAY_TIME,PLL SDM RESET STABLE DLY CODE" "0,1,2,3,4,5,6,7"
group.byte 0x1B8++0x00
line.byte 0x00 "CMN_REG06E,no description available"
bitfld.byte 0x00 0.--2. "TG_PLL_CD_TX_SER_RSTN_DELAY_TIME,no description available" "0,1,2,3,4,5,6,7"
group.byte 0x1BC++0x00
line.byte 0x00 "CMN_REG06F,no description available"
hexmask.byte 0x00 0.--7. 1. "DTB_SEL,Digital Test Bus (DTB) selection"
group.byte 0x1C0++0x00
line.byte 0x00 "CMN_REG070,no description available"
bitfld.byte 0x00 4.--5. "ANA_PLL_AFC_LC_CODE_MON,LC AFC code MSB monitor" "0,1,2,3"
bitfld.byte 0x00 0.--3. "ANA_PLL_AFC_RING_CODE_MON,LC AFC code MSB monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1C4++0x00
line.byte 0x00 "CMN_REG071,no description available"
bitfld.byte 0x00 0.--3. "ANA_PLL_AGMC_CODE_MON,LC VCO GM code monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1C8++0x00
line.byte 0x00 "CMN_REG072,no description available"
bitfld.byte 0x00 0.--4. "MON_CMN_STATE,CMN state monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x1CC++0x00
line.byte 0x00 "CMN_REG073,no description available"
hexmask.byte 0x00 0.--6. 1. "MON_CMN_TIME__14_8,CMN timer monitor"
group.byte 0x1D0++0x00
line.byte 0x00 "CMN_REG074,no description available"
hexmask.byte 0x00 0.--7. 1. "MON_CMN_TIME__7_0,CMN timer monitor"
group.byte 0x1D4++0x00
line.byte 0x00 "CMN_REG075,no description available"
bitfld.byte 0x00 1. "ANA_PLL_LOCK_DONE,PLL Lock Done" "0,1"
bitfld.byte 0x00 0. "ANA_PLL_AFC_DONE,PLL AFC Done" "0,1"
group.byte 0x200++0x00
line.byte 0x00 "CMN_REG076,no description available"
bitfld.byte 0x00 6.--7. "LANE3_RESET_MUX_SEL," "0,1,2,3"
bitfld.byte 0x00 4.--5. "LANE2_RESET_MUX_SEL," "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LANE1_RESET_MUX_SEL," "0,1,2,3"
bitfld.byte 0x00 0.--1. "LANE0_RESET_MUX_SEL," "0,1,2,3"
group.byte 0x204++0x00
line.byte 0x00 "CMN_REG077,no description available"
bitfld.byte 0x00 4. "CMN_SW_RESET," "0,1"
bitfld.byte 0x00 3. "LANE3_SW_RESET," "0,1"
newline
bitfld.byte 0x00 2. "LANE2_SW_RESET," "0,1"
bitfld.byte 0x00 1. "LANE1_SW_RESET," "0,1"
newline
bitfld.byte 0x00 0. "LANE0_SW_RESET," "0,1"
group.byte 0x208++0x00
line.byte 0x00 "CMN_REG078,no description available"
bitfld.byte 0x00 6.--7. "LANE3_TX_DATA_CLK_MUX_SEL," "0,1,2,3"
bitfld.byte 0x00 4.--5. "LANE2_TX_DATA_CLK_MUX_SEL,no description available" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LANE1_TX_DATA_CLK_MUX_SEL,no description available" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LANE0_TX_DATA_CLK_MUX_SEL,no description available" "0,1,2,3"
group.byte 0x20C++0x00
line.byte 0x00 "CMN_REG079,no description available"
bitfld.byte 0x00 0. "CMN_RESET_CONTROL,no description available" "0,1"
group.byte 0x210++0x00
line.byte 0x00 "CMN_REG080,no description available"
hexmask.byte 0x00 0.--7. 1. "RATE_CHANGE_DELAY,no description available"
group.byte 0x214++0x00
line.byte 0x00 "CMN_REG081,no description available"
hexmask.byte 0x00 0.--7. 1. "RX_EFOM_ERROR_TH_7_0,no description available"
group.byte 0x218++0x00
line.byte 0x00 "CMN_REG082,no description available"
bitfld.byte 0x00 0.--1. "RX_EFOM_ERROR_TH_9_8,no description available" "0,1,2,3"
group.byte 0x400++0x00
line.byte 0x00 "TRSV_REG000,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_TX_DRV_EN,Override enable for tx_drv_en" "0,1"
bitfld.byte 0x00 6. "LN0_TX_DRV_EN,TX driver enable" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN,Override enable for tx_drv_beacon_lfps_out_en" "0,1"
bitfld.byte 0x00 4. "LN0_TX_DRV_BEACON_LFPS_OUT_EN,TX beacon or LFPS enable" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_TX_DRV_CM_KEEPER_EN,Override enable for tx_drv_cm_keeper_en" "0,1"
bitfld.byte 0x00 2. "LN0_TX_DRV_CM_KEEPER_EN,TX driver common-mode keep enable" "0,1"
newline
bitfld.byte 0x00 1. "LN0_OVRD_TX_DRV_EI_EN,Override enable for tx_drv_ei_en" "0,1"
bitfld.byte 0x00 0. "LN0_TX_DRV_EI_EN,TX driver electrical-idle state enable" "0,1"
group.byte 0x404++0x00
line.byte 0x00 "TRSV_REG001,no description available"
bitfld.byte 0x00 5. "LN0_OVRD_TX_DRV_LVL_CTRL,Override enable for tx_drv_lvl_ctrl_g1" "0,1"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_LVL_CTRL_G1,[GEN1] TX driver main-tap level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x408++0x00
line.byte 0x00 "TRSV_REG002,no description available"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_LVL_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x40C++0x00
line.byte 0x00 "TRSV_REG003,no description available"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_LVL_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x410++0x00
line.byte 0x00 "TRSV_REG004,no description available"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_LVL_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x414++0x00
line.byte 0x00 "TRSV_REG005,no description available"
bitfld.byte 0x00 5. "LN0_OVRD_TX_DRV_POST_LVL_CTRL,Override enable for tx_drv_post_lvl_ctrl_g1" "0,1"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_POST_LVL_CTRL_G1,[GEN1] TX driver de-emphasis level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x418++0x00
line.byte 0x00 "TRSV_REG006,no description available"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_POST_LVL_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x41C++0x00
line.byte 0x00 "TRSV_REG007,no description available"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_POST_LVL_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x420++0x00
line.byte 0x00 "TRSV_REG008,no description available"
bitfld.byte 0x00 0.--4. "LN0_TX_DRV_POST_LVL_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x424++0x00
line.byte 0x00 "TRSV_REG009,no description available"
bitfld.byte 0x00 4. "LN0_OVRD_TX_DRV_PRE_LVL_CTRL,Override enable for tx_drv_pre_lvl_ctrl_g1" "0,1"
bitfld.byte 0x00 0.--3. "LN0_TX_DRV_PRE_LVL_CTRL_G1,[GEN1] TX driver pre-shoot level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x428++0x00
line.byte 0x00 "TRSV_REG00A,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_DRV_PRE_LVL_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_DRV_PRE_LVL_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x42C++0x00
line.byte 0x00 "TRSV_REG00B,no description available"
bitfld.byte 0x00 3.--6. "LN0_TX_DRV_PRE_LVL_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 2. "LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN,TX LFPS/BEACON synchronization enable" "0,1"
newline
bitfld.byte 0x00 1. "LN0_OVRD_TX_DRV_IDRV_EN,Override enable for tx_drv_idrv_en" "0,1"
bitfld.byte 0x00 0. "LN0_TX_DRV_IDRV_EN,TX current-driver enable" "0,1"
group.byte 0x430++0x00
line.byte 0x00 "TRSV_REG00C,no description available"
bitfld.byte 0x00 5.--7. "LN0_ANA_TX_DRV_IDRV_IDN_CTRL,TX current driver pmos current control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 2.--4. "LN0_ANA_TX_DRV_IDRV_IUP_CTRL,TX current driver pmos current control" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 1. "LN0_ANA_TX_DRV_IDRV_VREF_SEL,TX current driver reference selection" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_TX_DRV_ACCDRV_EN,Enable of Cap" "0,1"
group.byte 0x434++0x00
line.byte 0x00 "TRSV_REG00D,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_VALID_RSTN_DELAY,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x438++0x00
line.byte 0x00 "TRSV_REG00E,no description available"
bitfld.byte 0x00 6.--7. "LN0_TX_DRV_EI_EN_DELAY_SEL_G1,[GEN1] TX EI enable latency control" "0,1,2,3"
bitfld.byte 0x00 4.--5. "LN0_TX_DRV_EI_EN_DELAY_SEL_G2,[GEN2]" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LN0_TX_DRV_EI_EN_DELAY_SEL_G3,[GEN3]" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_TX_DRV_EI_EN_DELAY_SEL_G4,[GEN4]" "0,1,2,3"
group.byte 0x43C++0x00
line.byte 0x00 "TRSV_REG00F,no description available"
bitfld.byte 0x00 1. "LN0_ANA_TX_DRV_HSCLK_MON_EN,Enable of high-speed clock monitor through Tx driver" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_TX_DRV_PLL_REF_MON_EN,Enable of PLL reference clock monitor through Tx driver" "0,1"
group.byte 0x440++0x00
line.byte 0x00 "TRSV_REG010,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_JEQ_CAP_CTRL_G1,[GEN1] TX jitter EQ loding capacitance control in thermomether" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_JEQ_CAP_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x444++0x00
line.byte 0x00 "TRSV_REG011,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_JEQ_CAP_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_JEQ_CAP_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x448++0x00
line.byte 0x00 "TRSV_REG012,no description available"
bitfld.byte 0x00 0. "LN0_ANA_TX_JEQ_EN,TX jitter EQ enable" "0,1"
group.byte 0x44C++0x00
line.byte 0x00 "TRSV_REG013,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_JEQ_EVEN_CTRL_G1,[GEN1] TX jitter EQ driver (even) strength control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_JEQ_EVEN_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x450++0x00
line.byte 0x00 "TRSV_REG014,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_JEQ_EVEN_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_JEQ_EVEN_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x454++0x00
line.byte 0x00 "TRSV_REG015,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_JEQ_ODD_CTRL_G1,[GEN1] TX jitter EQ driver (odd) strength control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_JEQ_ODD_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x458++0x00
line.byte 0x00 "TRSV_REG016,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_JEQ_ODD_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_JEQ_ODD_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x45C++0x00
line.byte 0x00 "TRSV_REG017,no description available"
bitfld.byte 0x00 3. "LN0_OVRD_TX_RCAL_EN,Override enable for tx_rcal_en" "0,1"
bitfld.byte 0x00 2. "LN0_TX_RCAL_EN,TX RCAL enable" "0,1"
newline
bitfld.byte 0x00 0.--1. "LN0_ANA_TX_RCAL_IRMRES_CTRL,TX RCAL rmres bias current control" "0,1,2,3"
group.byte 0x460++0x00
line.byte 0x00 "TRSV_REG018,no description available"
bitfld.byte 0x00 7. "LN0_TX_RTERM_42P5_EN_G1,[GEN1]" "0,1"
bitfld.byte 0x00 6. "LN0_TX_RTERM_42P5_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 5. "LN0_TX_RTERM_42P5_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 4. "LN0_TX_RTERM_42P5_EN_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_TX_RXD_COMP_EN,Override enable for tx_rxd_comp_en" "0,1"
bitfld.byte 0x00 2. "LN0_TX_RXD_COMP_EN,TX receiver detector comparator enable" "0,1"
newline
bitfld.byte 0x00 1. "LN0_OVRD_TX_RXD_EN,Override enable for tx_rxd_en" "0,1"
bitfld.byte 0x00 0. "LN0_TX_RXD_EN,TX receiver detector enable" "0,1"
group.byte 0x464++0x00
line.byte 0x00 "TRSV_REG019,no description available"
bitfld.byte 0x00 0. "LN0_ANA_TX_RXD_COMP_I_CTRL,TX receiver detector comparator bias control" "0,1"
group.byte 0x468++0x00
line.byte 0x00 "TRSV_REG01A,no description available"
bitfld.byte 0x00 5. "LN0_TX_SER_40BIT_EN_G1,[GEN1] TX serializer data width selection" "0,1"
bitfld.byte 0x00 4. "LN0_TX_SER_40BIT_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 3. "LN0_TX_SER_40BIT_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 2. "LN0_TX_SER_40BIT_EN_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 1. "LN0_OVRD_TX_SER_DATA_RSTN,Override enable for tx_ser_data_rstn" "0,1"
bitfld.byte 0x00 0. "LN0_TX_SER_DATA_RSTN,TX serializer data-path resetn" "0,1"
group.byte 0x46C++0x00
line.byte 0x00 "TRSV_REG01B,no description available"
bitfld.byte 0x00 7. "LN0_TX_SER_RATE_SEL_G1,[GEN1] TX serializer data rate selection for Gen4 (Need to be controlled with i_tx_en_40bit)" "0,1"
bitfld.byte 0x00 6. "LN0_TX_SER_RATE_SEL_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 5. "LN0_TX_SER_RATE_SEL_G3,[GEN3]" "0,1"
bitfld.byte 0x00 4. "LN0_TX_SER_RATE_SEL_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_TX_SER_CLK_RSTN,Override enable for tx_ser_clk_rstn" "0,1"
bitfld.byte 0x00 2. "LN0_TX_SER_CLK_RSTN,TX serializer clock-path resetn" "0,1"
newline
bitfld.byte 0x00 1. "LN0_ANA_TX_CDR_CLK_MON_EN,TX serializer clock selection" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_TX_SER_TXCLK_INV,TX byte clock polarity inversion" "0,1"
group.byte 0x470++0x00
line.byte 0x00 "TRSV_REG01C,no description available"
bitfld.byte 0x00 1.--5. "LN0_ANA_TX_ATB_SEL," "?,1: Pre Driver VDD,?,?,?,?,?,?,?,?,10: Driver VDD,11: Driver VDDH,?..."
bitfld.byte 0x00 0. "LN0_ANA_TX_ATB_EN,TX ATB enable" "0,1"
group.byte 0x474++0x00
line.byte 0x00 "TRSV_REG01D,no description available"
bitfld.byte 0x00 3.--5. "LN0_ANA_TX_BIAS_RMRES_CTRL,RX RMRES bias current control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 2. "LN0_ANA_TX_SLB_EN,Serial loopback enable" "0,1"
newline
bitfld.byte 0x00 1. "LN0_ANA_TX_LLB_EN,Line loopback enalble" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_TX_SRLB_EN,Serial retimed loopback enable" "0,1"
group.byte 0x478++0x00
line.byte 0x00 "TRSV_REG01E,no description available"
bitfld.byte 0x00 7. "LN0_TX_EQ_2UI_DELAY_EN_G1,[GEN1] TX FIR filter delay control when bit-duplication" "0,1"
bitfld.byte 0x00 6. "LN0_TX_EQ_2UI_DELAY_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 5. "LN0_TX_EQ_2UI_DELAY_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 4. "LN0_TX_EQ_2UI_DELAY_EN_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 0.--3. "LN0_ANA_TX_RESERVED,Reserved port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x47C++0x00
line.byte 0x00 "TRSV_REG01F,no description available"
bitfld.byte 0x00 4. "LN0_OVRD_RX_CDR_EN,Override enable for rx_cdr_en" "0,1"
bitfld.byte 0x00 3. "LN0_RX_CDR_EN,RX CDR enable" "0,1"
newline
bitfld.byte 0x00 2. "LN0_OVRD_RX_CDR_MODE_CTRL,Override enable for rx_cdr_mode_ctrl" "0,1"
bitfld.byte 0x00 0.--1. "LN0_RX_CDR_MODE_CTRL,RX CDR mode select" "0,1,2,3"
group.byte 0x480++0x00
line.byte 0x00 "TRSV_REG020,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_REFDIV_SEL_PLL_G1,[GEN1] [PLL mode] Decision of CDR ref" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_REFDIV_SEL_PLL_G2,[GEN2] [PLL mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x484++0x00
line.byte 0x00 "TRSV_REG021,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_REFDIV_SEL_PLL_G3,[GEN3] [PLL mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_REFDIV_SEL_PLL_G4,[GEN4] [PLL mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x488++0x00
line.byte 0x00 "TRSV_REG022,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_REFDIV_SEL_DATA_G1,[GEN1] [Data mode] Decision of CDR ref" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_REFDIV_SEL_DATA_G2,[GEN2] [Data mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x48C++0x00
line.byte 0x00 "TRSV_REG023,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_REFDIV_SEL_DATA_G3,[GEN3] [Data mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_REFDIV_SEL_DATA_G4,[GEN4] [Data mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x490++0x00
line.byte 0x00 "TRSV_REG024,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_MDIV_SEL_PLL_G1,[GEN1] [PLL mode] Decision of CDR main-divider ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_MDIV_SEL_PLL_G2,[GEN2] [PLL mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x494++0x00
line.byte 0x00 "TRSV_REG025,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_MDIV_SEL_PLL_G3,[GEN3] [PLL mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_MDIV_SEL_PLL_G4,[GEN4] [PLL mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x498++0x00
line.byte 0x00 "TRSV_REG026,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_MDIV_SEL_DATA_G1,[GEN1] [Data mode] Decision of CDR main-divider ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_MDIV_SEL_DATA_G2,[GEN2] [Data mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x49C++0x00
line.byte 0x00 "TRSV_REG027,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_MDIV_SEL_DATA_G3,[GEN3] [Data mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_MDIV_SEL_DATA_G4,[GEN4] [Data mode]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x4A0++0x00
line.byte 0x00 "TRSV_REG028,no description available"
bitfld.byte 0x00 5. "LN0_OVRD_RX_CDR_BW_CTRL,Override enable for rx_cdr_bw_ctrl" "0,1"
bitfld.byte 0x00 4. "LN0_RX_CDR_BW_CTRL,RX CDR bandwidth control" "0,1"
newline
bitfld.byte 0x00 3. "LN0_ANA_RX_CDR_DES_RXCLK_INV,RX byte clock polarity inversion" "0,1"
bitfld.byte 0x00 2. "LN0_ANA_RX_CDR_AFC_EN,RX CDR AFC enable" "0,1"
newline
bitfld.byte 0x00 1. "LN0_ANA_RX_CDR_AFC_TEST_EN,RX CDR test mode enable" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_RX_CDR_AFC_VCI_FORCE,RX CDR control voltage force" "0,1"
group.byte 0x4A4++0x00
line.byte 0x00 "TRSV_REG029,no description available"
bitfld.byte 0x00 4. "LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL,RX CDR VCI reference voltage selection" "0,1"
bitfld.byte 0x00 1.--3. "LN0_ANA_RX_CDR_CP_CTRL,RX CDR charge pump current control (Ieven + Iodd)" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0. "LN0_ANA_RX_CDR_CP_E_EN,RX CDR even charge-pump enable" "0,1"
group.byte 0x4A8++0x00
line.byte 0x00 "TRSV_REG02A,no description available"
bitfld.byte 0x00 6. "LN0_ANA_RX_CDR_CP_O_EN,RX CDR odd charge-pump enable" "0,1"
bitfld.byte 0x00 5. "LN0_ANA_RX_CDR_CP_VREG_IN_SEL,RX CDR charge pump regulator reference voltage selection" "0,1"
newline
bitfld.byte 0x00 4. "LN0_ANA_RX_CDR_CP_VREG_LPF_EN,LPF enable for RX CDR charge pump regualtor" "0,1"
bitfld.byte 0x00 3. "LN0_OVRD_RX_CDR_FBB_CAL_EN,Override enable for rx_cdr_fbb_cal_en" "0,1"
newline
bitfld.byte 0x00 2. "LN0_RX_CDR_FBB_CAL_EN,RX CDR FBB calibration enable" "0,1"
bitfld.byte 0x00 1. "LN0_OVRD_RX_CDR_VCO_STARTUP,Override enable for rx_cdr_vco_startup" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_CDR_VCO_STARTUP,RX CDR VCO startup signal low to high transition" "0,1"
group.byte 0x4AC++0x00
line.byte 0x00 "TRSV_REG02B,no description available"
bitfld.byte 0x00 0.--3. "LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL,RX CDR BBVCO dummy cap control to decrease frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x4B0++0x00
line.byte 0x00 "TRSV_REG02C,no description available"
bitfld.byte 0x00 3. "LN0_RX_CDR_VCO_FREQ_BOOST_G1,[GEN1] RX CDR VCO frequency boost enable" "0,1"
bitfld.byte 0x00 2. "LN0_RX_CDR_VCO_FREQ_BOOST_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "LN0_RX_CDR_VCO_FREQ_BOOST_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "LN0_RX_CDR_VCO_FREQ_BOOST_G4,[GEN4]" "0,1"
group.byte 0x4B4++0x00
line.byte 0x00 "TRSV_REG02D,no description available"
bitfld.byte 0x00 3.--5. "LN0_RX_CDR_VCO_VREG_SEL_G1,[GEN1] RX CDR voltage regualtor selection" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_RX_CDR_VCO_VREG_SEL_G2,[GEN2]" "0,1,2,3,4,5,6,7"
group.byte 0x4B8++0x00
line.byte 0x00 "TRSV_REG02E,no description available"
bitfld.byte 0x00 5.--7. "LN0_RX_CDR_VCO_VREG_SEL_G3,[GEN3]" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 2.--4. "LN0_RX_CDR_VCO_VREG_SEL_G4,[GEN4]" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 1. "LN0_OVRD_RX_CTLE_EN,Override enable for rx_ctle_en" "0,1"
bitfld.byte 0x00 0. "LN0_RX_CTLE_EN,RX CTLE enable" "0,1"
group.byte 0x4BC++0x00
line.byte 0x00 "TRSV_REG02F,no description available"
bitfld.byte 0x00 3. "LN0_RX_CTLE_HIGH_BW_EN_G1,[GEN1] RX CTLE bandwidth enhancement by boosting up current" "0,1"
bitfld.byte 0x00 2. "LN0_RX_CTLE_HIGH_BW_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "LN0_RX_CTLE_HIGH_BW_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "LN0_RX_CTLE_HIGH_BW_EN_G4,[GEN4]" "0,1"
group.byte 0x4C0++0x00
line.byte 0x00 "TRSV_REG030,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_CTLE_ITAIL_CTRL_G1,[GEN1] RX CTLE main tail current"
group.byte 0x4C4++0x00
line.byte 0x00 "TRSV_REG031,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_CTLE_ITAIL_CTRL_G2,[GEN2]"
group.byte 0x4C8++0x00
line.byte 0x00 "TRSV_REG032,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_CTLE_ITAIL_CTRL_G3,[GEN3]"
group.byte 0x4CC++0x00
line.byte 0x00 "TRSV_REG033,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_CTLE_ITAIL_CTRL_G4,[GEN4]"
group.byte 0x4D0++0x00
line.byte 0x00 "TRSV_REG034,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_CTLE_OC_CODE,Override enable for rx_ctle_oc_code" "0,1"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_CTLE_OC_CODE,RX CTLE manual offset code"
group.byte 0x4D4++0x00
line.byte 0x00 "TRSV_REG035,no description available"
bitfld.byte 0x00 1. "LN0_OVRD_RX_CTLE_OC_EN,Override enable for rx_ctle_oc_en" "0,1"
bitfld.byte 0x00 0. "LN0_RX_CTLE_OC_EN,RX CTLE offset calibration enable" "0,1"
group.byte 0x4D8++0x00
line.byte 0x00 "TRSV_REG036,no description available"
bitfld.byte 0x00 3. "LN0_RX_CTLE_OC_VCM_SEL_G1,[GEN1] RX CTLE input common-mode selection in offset calibration" "0,1"
bitfld.byte 0x00 2. "LN0_RX_CTLE_OC_VCM_SEL_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "LN0_RX_CTLE_OC_VCM_SEL_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "LN0_RX_CTLE_OC_VCM_SEL_G4,[GEN4]" "0,1"
group.byte 0x4DC++0x00
line.byte 0x00 "TRSV_REG037,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_CTLE_RL_CTRL_G1,[GEN1] RX CTLE load resistance control for Gen1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x4E0++0x00
line.byte 0x00 "TRSV_REG038,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_CTLE_RL_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x4E4++0x00
line.byte 0x00 "TRSV_REG039,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_CTLE_RL_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x4E8++0x00
line.byte 0x00 "TRSV_REG03A,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_CTLE_RL_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x4EC++0x00
line.byte 0x00 "TRSV_REG03B,no description available"
bitfld.byte 0x00 4. "LN0_OVRD_RX_CTLE_RS1_CTRL,Override enable for rx_ctle_rs1_ctrl_g1" "0,1"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_RS1_CTRL_G1,[GEN1] RX CTLE 1st stage source series resistance control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x4F0++0x00
line.byte 0x00 "TRSV_REG03C,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_RS1_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_RS1_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x4F4++0x00
line.byte 0x00 "TRSV_REG03D,no description available"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_RS1_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x4F8++0x00
line.byte 0x00 "TRSV_REG03E,no description available"
bitfld.byte 0x00 4. "LN0_OVRD_RX_CTLE_RS2_CTRL,Override enable for rx_ctle_rs2_ctrl_g1" "0,1"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_RS2_CTRL_G1,[GEN1] RX CTLE 2nd stage source series resistance control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x4FC++0x00
line.byte 0x00 "TRSV_REG03F,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_RS2_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_RS2_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x500++0x00
line.byte 0x00 "TRSV_REG040,no description available"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_RS2_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x504++0x00
line.byte 0x00 "TRSV_REG041,no description available"
bitfld.byte 0x00 3. "LN0_RX_CTLE_CHFB_EN_G1,[GEN1] RX CTLE Cherry-Hooper feedback amplifier enable" "0,1"
bitfld.byte 0x00 2. "LN0_RX_CTLE_CHFB_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 1. "LN0_RX_CTLE_CHFB_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 0. "LN0_RX_CTLE_CHFB_EN_G4,[GEN4]" "0,1"
group.byte 0x508++0x00
line.byte 0x00 "TRSV_REG042,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_CS_CTRL_G1,[GEN1] CTLE capacitance control" "0: Gen4 3,?,?,3: Gen2,?,?,?,7: Gen1,?..."
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_CS_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x50C++0x00
line.byte 0x00 "TRSV_REG043,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_CS_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_CS_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x510++0x00
line.byte 0x00 "TRSV_REG044,no description available"
bitfld.byte 0x00 6.--7. "LN0_RX_CTLE_PEAKING_EN_G1,[GEN1] RX CTLE stage enable for Gen1" "0,1,2,3"
bitfld.byte 0x00 4.--5. "LN0_RX_CTLE_PEAKING_EN_G2,[GEN2]" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LN0_RX_CTLE_PEAKING_EN_G3,[GEN3]" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_RX_CTLE_PEAKING_EN_G4,[GEN4]" "0,1,2,3"
group.byte 0x514++0x00
line.byte 0x00 "TRSV_REG045,no description available"
bitfld.byte 0x00 0.--2. "LN0_ANA_RX_CTLE_IBLEED_CTRL,RX CTLE bleeder current control" "0,1,2,3,4,5,6,7"
group.byte 0x518++0x00
line.byte 0x00 "TRSV_REG046,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_NEGC_EN_G1,[GEN1] RX CTLE negative-C enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_NEGC_EN_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x51C++0x00
line.byte 0x00 "TRSV_REG047,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_NEGC_EN_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_NEGC_EN_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x520++0x00
line.byte 0x00 "TRSV_REG048,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1,[GEN1] RX CTLE negative-C tail current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x524++0x00
line.byte 0x00 "TRSV_REG049,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x528++0x00
line.byte 0x00 "TRSV_REG04A,no description available"
bitfld.byte 0x00 0.--1. "LN0_ANA_RX_CTLE_VCM_SEL,RX AFE (CTLE output) common-mode voltage selection" "0,1,2,3"
group.byte 0x52C++0x00
line.byte 0x00 "TRSV_REG04B,no description available"
bitfld.byte 0x00 6.--7. "LN0_RX_CTLE_CHFB_BW_CTRL_G1,[GEN1] RX CTLE Cherry-Hooper feedback amplifier bandwidth control" "0,1,2,3"
bitfld.byte 0x00 4.--5. "LN0_RX_CTLE_CHFB_BW_CTRL_G2,[GEN2]" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LN0_RX_CTLE_CHFB_BW_CTRL_G3,[GEN3]" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_RX_CTLE_CHFB_BW_CTRL_G4,[GEN4]" "0,1,2,3"
group.byte 0x530++0x00
line.byte 0x00 "TRSV_REG04C,no description available"
bitfld.byte 0x00 3.--5. "LN0_RX_CTLE_CHFB_GAIN_CTRL_G1,[GEN1] RX CTLE Cherry-Hooper feedback amplifier gain control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_RX_CTLE_CHFB_GAIN_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7"
group.byte 0x534++0x00
line.byte 0x00 "TRSV_REG04D,no description available"
bitfld.byte 0x00 3.--5. "LN0_RX_CTLE_CHFB_GAIN_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_RX_CTLE_CHFB_GAIN_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7"
group.byte 0x538++0x00
line.byte 0x00 "TRSV_REG04E,no description available"
bitfld.byte 0x00 6.--7. "LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1,[GEN1] RX CTLE active load control" "0,1,2,3"
bitfld.byte 0x00 4.--5. "LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2,[GEN2]" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3,[GEN3]" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4,[GEN4]" "0,1,2,3"
group.byte 0x53C++0x00
line.byte 0x00 "TRSV_REG04F,no description available"
bitfld.byte 0x00 5.--7. "LN0_ANA_RX_CTLE_VGA_CTRL,RX CTLE stage3 gain control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 1.--4. "LN0_ANA_RX_CTLE_VREG_SEL,RX CTLE voltage regulator output voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "LN0_ANA_RX_CTLE_PTAT_EN,RX CTLE PTAT current enable" "0,1"
group.byte 0x540++0x00
line.byte 0x00 "TRSV_REG050,no description available"
bitfld.byte 0x00 2.--4. "LN0_ANA_RX_CTLE_RESERVED,Reserved port" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 1. "LN0_OVRD_RX_DES_DATA_CLEAR,Override enable for rx_des_data_clear" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_DES_DATA_CLEAR,RX deserializer data clear to prevent garbage data" "0,1"
group.byte 0x544++0x00
line.byte 0x00 "TRSV_REG051,no description available"
bitfld.byte 0x00 6.--7. "LN0_RX_DES_DATA_WIDTH_SEL_G1,[GEN1] RX deserializer data width selection" "0,1,2,3"
bitfld.byte 0x00 4.--5. "LN0_RX_DES_DATA_WIDTH_SEL_G2,[GEN2]" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LN0_RX_DES_DATA_WIDTH_SEL_G3,[GEN3]" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_RX_DES_DATA_WIDTH_SEL_G4,[GEN4]" "0,1,2,3"
group.byte 0x548++0x00
line.byte 0x00 "TRSV_REG052,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_DES_EN,Override enable for rx_des_en" "0,1"
bitfld.byte 0x00 6. "LN0_RX_DES_EN,RX deserializer enable" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_RX_DES_NON_DATA_SEL,Override enable for rx_des_non_data_sel" "0,1"
bitfld.byte 0x00 4. "LN0_RX_DES_NON_DATA_SEL,RX deserializer non-data selection for edge/error sampler calibration" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_RX_DES_RSTN,Override enable for rx_des_rstn" "0,1"
bitfld.byte 0x00 2. "LN0_RX_DES_RSTN,RX deserializer reset" "0,1"
newline
bitfld.byte 0x00 0.--1. "LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL,no description available" "0,1,2,3"
group.byte 0x54C++0x00
line.byte 0x00 "TRSV_REG053,no description available"
bitfld.byte 0x00 6. "LN0_OVRD_RX_DFE_ADAP_EN,Override enable for rx_dfe_adap_en" "0,1"
bitfld.byte 0x00 5. "LN0_RX_DFE_ADAP_EN,RX DFE adaptation path enable" "0,1"
newline
bitfld.byte 0x00 4. "LN0_OVRD_RX_DFE_EOM_EN,Override enable for rx_dfe_eom_en" "0,1"
bitfld.byte 0x00 3. "LN0_RX_DFE_EOM_EN,RX EOM enable" "0,1"
newline
bitfld.byte 0x00 0.--2. "LN0_ANA_RX_DFE_EOM_PI_DIV_SEL,Clock divider control before RX EOM phase interpolator" "0,1,2,3,4,5,6,7"
group.byte 0x550++0x00
line.byte 0x00 "TRSV_REG054,no description available"
bitfld.byte 0x00 0.--3. "LN0_ANA_RX_DFE_EOM_PI_STR_CTRL,RX EOM PI drive strengh in pre-buffer stage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x554++0x00
line.byte 0x00 "TRSV_REG055,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE,Override enable for rx_dfe_oc_adder_even_code" "0,1"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_DFE_OC_ADDER_EVEN_CODE,RX DFE even data path offset calibration code"
group.byte 0x558++0x00
line.byte 0x00 "TRSV_REG056,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE,Override enable for rx_dfe_oc_adder_odd_code" "0,1"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_DFE_OC_ADDER_ODD_CODE,RX DFE odd data path offset calibration code"
group.byte 0x55C++0x00
line.byte 0x00 "TRSV_REG057,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE,Override enable for rx_dfe_oc_dac_adder_even_code" "0,1"
bitfld.byte 0x00 6. "LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE,Fine control of zero-crossing in RX DFE DAC for even adder offset calibration" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE,Override enable for rx_dfe_oc_dac_adder_odd_code" "0,1"
bitfld.byte 0x00 4. "LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE,Fine control of zero-crossing in RX DFE DAC for odd adder offset calibration" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE,Override enable for rx_dfe_oc_dac_edge_even_code" "0,1"
bitfld.byte 0x00 0.--2. "LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE,Fine control of zero-crossing in RX DFE DAC for even edge path offset calibration" "0,1,2,3,4,5,6,7"
group.byte 0x560++0x00
line.byte 0x00 "TRSV_REG058,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE,Override enable for rx_dfe_oc_dac_edge_odd_code" "0,1"
bitfld.byte 0x00 4.--6. "LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE,Fine control of zero-crossing in RX DFE DAC for odd edge path offset calibration" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 3. "LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE,Override enable for rx_dfe_oc_dac_err_even_code" "0,1"
bitfld.byte 0x00 0.--2. "LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE,Fine control of zero-crossing in RX DFE DAC for even error path offset calibration" "0,1,2,3,4,5,6,7"
group.byte 0x564++0x00
line.byte 0x00 "TRSV_REG059,no description available"
bitfld.byte 0x00 5. "LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE,Override enable for rx_dfe_oc_dac_err_odd_code" "0,1"
bitfld.byte 0x00 2.--4. "LN0_RX_DFE_OC_DAC_ERR_ODD_CODE,Fine control of zero-crossing in RX DFE DAC for odd error path offset calibration" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 1. "LN0_OVRD_RX_DFE_OC_EN,Override enable for rx_dfe_oc_en" "0,1"
bitfld.byte 0x00 0. "LN0_RX_DFE_OC_EN,RX DFE offset calibration progress enable" "0,1"
group.byte 0x568++0x00
line.byte 0x00 "TRSV_REG05A,no description available"
bitfld.byte 0x00 1. "LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE,Override enable for rx_dfe_oc_sa_edge_even_code" "0,1"
bitfld.byte 0x00 0. "LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8,RX DFE even edge path offset calibration code" "0,1"
group.byte 0x56C++0x00
line.byte 0x00 "TRSV_REG05B,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0,RX DFE even edge path offset calibration code"
group.byte 0x570++0x00
line.byte 0x00 "TRSV_REG05C,no description available"
bitfld.byte 0x00 1. "LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE,Override enable for rx_dfe_oc_sa_edge_odd_code" "0,1"
bitfld.byte 0x00 0. "LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8,RX DFE odd edge path offset calibration code" "0,1"
group.byte 0x574++0x00
line.byte 0x00 "TRSV_REG05D,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0,RX DFE odd edge path offset calibration code"
group.byte 0x578++0x00
line.byte 0x00 "TRSV_REG05E,no description available"
bitfld.byte 0x00 1. "LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE,Override enable for rx_dfe_oc_sa_err_even_code" "0,1"
bitfld.byte 0x00 0. "LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8,RX DFE even error path offset calibration code" "0,1"
group.byte 0x57C++0x00
line.byte 0x00 "TRSV_REG05F,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0,RX DFE even error path offset calibration code"
group.byte 0x580++0x00
line.byte 0x00 "TRSV_REG060,no description available"
bitfld.byte 0x00 1. "LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE,Override enable for rx_dfe_oc_sa_err_odd_code" "0,1"
bitfld.byte 0x00 0. "LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8,RX DFE odd error path offset calibration code" "0,1"
group.byte 0x584++0x00
line.byte 0x00 "TRSV_REG061,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0,RX DFE odd error path offset calibration code"
group.byte 0x588++0x00
line.byte 0x00 "TRSV_REG062,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN,Override enable for rx_dfe_sa_data_even_oc_en" "0,1"
bitfld.byte 0x00 6. "LN0_RX_DFE_SA_DATA_EVEN_OC_EN,RX DFE data odd path enable in offset calibration (If all of rx_dfe_sa_*_oc_en are 0 all path are autimatically activated as normal mode)" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN,Override enable for rx_dfe_sa_data_odd_oc_en" "0,1"
bitfld.byte 0x00 4. "LN0_RX_DFE_SA_DATA_ODD_OC_EN,RX DFE data even path enable in offset calibration (If all of rx_dfe_sa_*_oc_en are 0 all path are autimatically activated as normal mode)" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_RX_DFE_SA_EDGE_OC_EN,Override enable for rx_dfe_sa_edge_oc_en" "0,1"
bitfld.byte 0x00 2. "LN0_RX_DFE_SA_EDGE_OC_EN,RX DFE edge path enable in offset calibration (If all of rx_dfe_sa_*_oc_en are 0 all path are autimatically activated as normal mode)" "0,1"
newline
bitfld.byte 0x00 1. "LN0_OVRD_RX_DFE_SA_ERR_OC_EN,Override enable for rx_dfe_sa_err_oc_en" "0,1"
bitfld.byte 0x00 0. "LN0_RX_DFE_SA_ERR_OC_EN,RX DFE error path enable in offset calibration (If all of rx_dfe_sa_*_oc_en are 0 all path are autimatically activated as normal mode)" "0,1"
group.byte 0x58C++0x00
line.byte 0x00 "TRSV_REG063,no description available"
bitfld.byte 0x00 1. "LN0_OVRD_RX_DFE_VREF_CTRL,Override enable for rx_dfe_vref_ctrl" "0,1"
bitfld.byte 0x00 0. "LN0_RX_DFE_VREF_CTRL__8,RX DFE Vref control" "0,1"
group.byte 0x590++0x00
line.byte 0x00 "TRSV_REG064,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_DFE_VREF_CTRL__7_0,RX DFE Vref control"
group.byte 0x594++0x00
line.byte 0x00 "TRSV_REG065,no description available"
bitfld.byte 0x00 4.--7. "LN0_ANA_RX_DFE_ADDER_BLEED_CTRL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_ANA_RX_DFE_VREG_SEL,N/A DFE bias current control [3:2]: DFE adder bias current [1:0]: OC DAC bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x598++0x00
line.byte 0x00 "TRSV_REG066,no description available"
bitfld.byte 0x00 6. "LN0_ANA_RX_DFE_DAC_OUT_PULLUP,Pull-up all DAC output in RX DFE to disable all offset code effect" "0,1"
bitfld.byte 0x00 3.--5. "LN0_ANA_RX_DFE_DAC_VCM_CTRL,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 2. "LN0_ANA_RX_DFE_EOM_CLK_SEL,RX EOM clock selection" "0,1"
bitfld.byte 0x00 1. "LN0_OVRD_RX_RCAL_EN,Override enable for rx_rcal_en" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_RCAL_EN,RX RCAL enable" "0,1"
group.byte 0x59C++0x00
line.byte 0x00 "TRSV_REG067,no description available"
bitfld.byte 0x00 5. "LN0_OVRD_RX_RCAL_BIAS_EN,Override enable for rx_rcal_bias_en" "0,1"
bitfld.byte 0x00 4. "LN0_RX_RCAL_BIAS_EN,RX RCAL bias current enable" "0,1"
newline
bitfld.byte 0x00 2.--3. "LN0_ANA_RX_RCAL_IRMRES_CTRL,no description available" "0,1,2,3"
bitfld.byte 0x00 1. "LN0_OVRD_RX_RTERM_EN,Override enable for rx_rterm_en" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_RTERM_EN,RX RTERM enable" "0,1"
group.byte 0x5A0++0x00
line.byte 0x00 "TRSV_REG068,no description available"
bitfld.byte 0x00 7. "LN0_RX_RTERM_42P5_EN_G1,[GEN1] RX RTERM resistance shift" "0,1"
bitfld.byte 0x00 6. "LN0_RX_RTERM_42P5_EN_G2,[GEN2]" "0,1"
newline
bitfld.byte 0x00 5. "LN0_RX_RTERM_42P5_EN_G3,[GEN3]" "0,1"
bitfld.byte 0x00 4. "LN0_RX_RTERM_42P5_EN_G4,[GEN4]" "0,1"
newline
bitfld.byte 0x00 2.--3. "LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL,RX RTERM single-ended impedance control by current control" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_ANA_RX_RTERM_INCM_SW_CTRL,RX RTERM single-ended impedance control by switch control" "0,1,2,3"
group.byte 0x5A4++0x00
line.byte 0x00 "TRSV_REG069,no description available"
bitfld.byte 0x00 2.--3. "LN0_ANA_RX_RTERM_INCM_VCM_CTRL,RX RTERM output common-mode voltage control" "0,1,2,3"
bitfld.byte 0x00 1. "LN0_ANA_RX_RTERM_OFSN_CTRL,Offset code for RX RTERM N node" "0,1"
newline
bitfld.byte 0x00 0. "LN0_ANA_RX_RTERM_OFSP_CTRL,Offset code for RX RTERM P node" "0,1"
group.byte 0x5A8++0x00
line.byte 0x00 "TRSV_REG06A,no description available"
bitfld.byte 0x00 4. "LN0_OVRD_RX_RTERM_CM_PULLDN,Override enable for rx_rterm_cm_pulldn_g1" "0,1"
bitfld.byte 0x00 3. "LN0_RX_RTERM_CM_PULLDN_G1,[GEN1] RX RTERM termination voltage pull-down" "0,1"
newline
bitfld.byte 0x00 2. "LN0_RX_RTERM_CM_PULLDN_G2,[GEN2]" "0,1"
bitfld.byte 0x00 1. "LN0_RX_RTERM_CM_PULLDN_G3,[GEN3]" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_RTERM_CM_PULLDN_G4,[GEN4]" "0,1"
group.byte 0x5AC++0x00
line.byte 0x00 "TRSV_REG06B,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_RTERM_VCM_EN,Override enable for rx_rterm_vcm_en_g1" "0,1"
bitfld.byte 0x00 6. "LN0_RX_RTERM_VCM_EN_G1,[GEN1]" "0,1"
newline
bitfld.byte 0x00 5. "LN0_RX_RTERM_VCM_EN_G2,[GEN2]" "0,1"
bitfld.byte 0x00 4. "LN0_RX_RTERM_VCM_EN_G3,[GEN3]" "0,1"
newline
bitfld.byte 0x00 3. "LN0_RX_RTERM_VCM_EN_G4,[GEN4]" "0,1"
bitfld.byte 0x00 2. "LN0_OVRD_RX_SQ_BMR_EN,Override enable for rx_sq_bmr_en" "0,1"
newline
bitfld.byte 0x00 1. "LN0_RX_SQ_BMR_EN,no description available" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS,no description available" "0,1"
group.byte 0x5B0++0x00
line.byte 0x00 "TRSV_REG06C,no description available"
bitfld.byte 0x00 5.--6. "LN0_ANA_RX_SQ_VREF_820M_SEL,no description available" "0,1,2,3"
bitfld.byte 0x00 4. "LN0_OVRD_RX_SQHS_EN,Override enable for rx_sqhs_en" "0,1"
newline
bitfld.byte 0x00 3. "LN0_RX_SQHS_EN,RX high-speed squelch enable" "0,1"
bitfld.byte 0x00 2. "LN0_OVRD_RX_SQHS_DIFN_OC_EN,Override enable for rx_sqhs_difn_oc_en" "0,1"
newline
bitfld.byte 0x00 1. "LN0_RX_SQHS_DIFN_OC_EN,RX high-squelch diff-N offset calibration enable" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN,RX high-squelch diff-N offset sign" "0,1"
group.byte 0x5B4++0x00
line.byte 0x00 "TRSV_REG06D,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_SQHS_DIFN_OC_CODE,Override enable for rx_sqhs_difn_oc_code" "0,1"
bitfld.byte 0x00 3.--6. "LN0_RX_SQHS_DIFN_OC_CODE,RX high-squelch diff-N manual offset code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 2. "LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_OVRD_RX_SQHS_DIFP_OC_EN,Override enable for rx_sqhs_difp_oc_en" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_SQHS_DIFP_OC_EN,RX high-squelch diff-P offset calibration enable" "0,1"
group.byte 0x5B8++0x00
line.byte 0x00 "TRSV_REG06E,no description available"
bitfld.byte 0x00 7. "LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN,RX high-squelch diff-P offset sign" "0,1"
bitfld.byte 0x00 6. "LN0_OVRD_RX_SQHS_DIFP_OC_CODE,Override enable for rx_sqhs_difp_oc_code" "0,1"
newline
bitfld.byte 0x00 2.--5. "LN0_RX_SQHS_DIFP_OC_CODE,RX squelch diff-P manual offset code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 1. "LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN,Enable the high speed Squelch DIFP SKEW BUFFER" "0,1"
newline
bitfld.byte 0x00 0. "LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN,Fixed skew for PCIe/SATA Squelch" "0,1"
group.byte 0x5BC++0x00
line.byte 0x00 "TRSV_REG06F,no description available"
bitfld.byte 0x00 4.--7. "LN0_ANA_RX_SQHS_TH_CTRL,RX squelch threshold voltage selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 3. "LN0_ANA_RX_SQHS_FILTER_EN,SQHS loss detector enable" "0,1"
newline
bitfld.byte 0x00 1.--2. "LN0_ANA_RX_SQHS_BW_CTRL,no description available" "0,1,2,3"
bitfld.byte 0x00 0. "LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL,Selection of supply voltage of reference voltage for threshold calibration of HS SQ" "0,1"
group.byte 0x5C0++0x00
line.byte 0x00 "TRSV_REG070,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_SQLS_DIFN_DET_EN,Override enable for rx_sqls_difn_det_en" "0,1"
bitfld.byte 0x00 6. "LN0_RX_SQLS_DIFN_DET_EN,RX low-speed DIFN squelch enable" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_RX_SQLS_DIFP_DET_EN,Override enable for rx_sqls_difp_det_en" "0,1"
bitfld.byte 0x00 4. "LN0_RX_SQLS_DIFP_DET_EN,RX low-speed DIFP squelch enable" "0,1"
newline
bitfld.byte 0x00 3. "LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL,RX DIFP detect signal selection for PRE_DATA_VALID and DATA_VALID signal" "0,1"
bitfld.byte 0x00 0.--2. "LN0_ANA_RX_SQLS_DIFN_TH_CTRL,DIFN in MPHY LFPS in USB" "0,1,2,3,4,5,6,7"
group.byte 0x5C4++0x00
line.byte 0x00 "TRSV_REG071,no description available"
bitfld.byte 0x00 5.--7. "LN0_ANA_RX_SQLS_DIFP_TH_CTRL,DIFP in MPHY" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 2.--4. "LN0_ANA_RX_SQLS_IN_LPF_CTRL,Low pass filter resistor control for Squelch input : 00:30MHz 01:60MHz 10:100MHz" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0.--1. "LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL,Current controls for low-speed Squelch comparator current source" "0,1,2,3"
group.byte 0x5C8++0x00
line.byte 0x00 "TRSV_REG072,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_PWM_OSC_EN,Override enable for rx_pwm_osc_en" "0,1"
bitfld.byte 0x00 6. "LN0_RX_PWM_OSC_EN,RX MPHY PWM oscillator enable which is used in analog RX block in order to oversample" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_RX_PWM_CNT_EN,Override enable for rx_pwm_cnt_en" "0,1"
bitfld.byte 0x00 4. "LN0_RX_PWM_CNT_EN,Enalbe counter clock for PWM over sampling" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_RX_PWM_RSTN,Override enable for rx_pwm_rstn" "0,1"
bitfld.byte 0x00 2. "LN0_RX_PWM_RSTN,RX MPHY PWM reset" "0,1"
newline
bitfld.byte 0x00 1. "LN0_OVRD_RX_PWM_AFC_RSTN,Override enable for rx_pwm_afc_rstn" "0,1"
bitfld.byte 0x00 0. "LN0_RX_PWM_AFC_RSTN,RX MPHY PWM AFC reset" "0,1"
group.byte 0x5CC++0x00
line.byte 0x00 "TRSV_REG073,no description available"
bitfld.byte 0x00 4. "LN0_OVRD_RX_PWM_AFC_DONE,Override enable for rx_pwm_afc_done" "0,1"
bitfld.byte 0x00 3. "LN0_RX_PWM_AFC_DONE,RX MPHY PWM AFC done signal" "0,1"
newline
bitfld.byte 0x00 0.--2. "LN0_ANA_RX_PWM_DIV_RATIO,RX MPHY PWM oversampling clock divide ratio from PWM oscillator" "0,1,2,3,4,5,6,7"
group.byte 0x5D0++0x00
line.byte 0x00 "TRSV_REG074,no description available"
bitfld.byte 0x00 5. "LN0_OVRD_RX_PWM_OSC_CODE,Override enable for rx_pwm_osc_code" "0,1"
bitfld.byte 0x00 1.--4. "LN0_RX_PWM_OSC_CODE,RX MPHY PWM AFC code for oscillator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "LN0_ANA_RX_PWM_OC_EN,no description available" "0,1"
group.byte 0x5D4++0x00
line.byte 0x00 "TRSV_REG075,no description available"
bitfld.byte 0x00 3.--6. "LN0_ANA_RX_PWM_OC_CODE,min(-7 or 0_111){maximum negative offset} - max(+7 or 1_111) {maximum positive offset}" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 2. "LN0_OVRD_RX_LFPS_DET_EN,Override enable for rx_lfps_det_en" "0,1"
newline
bitfld.byte 0x00 1. "LN0_RX_LFPS_DET_EN,LFPS detector enable" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_RX_LFPS_LOSS_DET_EN,LFPS loss detector enable" "0,1"
group.byte 0x5D8++0x00
line.byte 0x00 "TRSV_REG076,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_BIAS_EN,Override enable for rx_bias_en" "0,1"
bitfld.byte 0x00 6. "LN0_RX_BIAS_EN,RX bias current enable" "0,1"
newline
bitfld.byte 0x00 3.--5. "LN0_ANA_RX_BIAS_RMRES_CTRL,RX RMRES bias current control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 2. "LN0_ANA_RX_SLB_EN,Serial loopback enable" "0,1"
newline
bitfld.byte 0x00 1. "LN0_ANA_RX_LLB_EN,Line loopback enalble" "0,1"
bitfld.byte 0x00 0. "LN0_ANA_RX_SRLB_EN,Serial retimed loopback enable" "0,1"
group.byte 0x5DC++0x00
line.byte 0x00 "TRSV_REG077,no description available"
bitfld.byte 0x00 7. "LN0_ANA_RX_SRLB_EVEN_ODD_SEL,Serial retimed loopback path selection" "0,1"
bitfld.byte 0x00 6. "LN0_ANA_RX_SRLB_DATA_EDGE_SEL,Serial retimed loopback path selection" "0,1"
newline
bitfld.byte 0x00 5. "LN0_ANA_RX_LLB_ACCAP_EN,Line loopback path selection" "0,1"
bitfld.byte 0x00 2.--4. "LN0_ANA_RX_LLB_DUTY_CTRL,Line loopback duty-ratio control" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0.--1. "LN0_ANA_RX_LLB_ITAIL_CTRL,Line loopback tail-current control" "0,1,2,3"
group.byte 0x5E0++0x00
line.byte 0x00 "TRSV_REG078,no description available"
bitfld.byte 0x00 2. "LN0_ANA_RX_LLB_RLOAD_CTRL,Line loopback load resistance control" "0,1"
bitfld.byte 0x00 1. "LN0_ANA_RX_CDR_CLK_MON_EN,no description available" "0,1"
newline
bitfld.byte 0x00 0. "LN0_ANA_RX_ATB_EN,RX ATB enable" "0,1"
group.byte 0x5E4++0x00
line.byte 0x00 "TRSV_REG079,no description available"
bitfld.byte 0x00 0.--5. "LN0_ANA_RX_ATB_SEL,When i_sfr_rx_atb_en=1 and i_sfr_rx_atb_sel&lt 5&gt =0 RX AFE nodes are under monitoring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x5E8++0x00
line.byte 0x00 "TRSV_REG07A,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_ANA_RX_RESERVED,Reserved port"
group.byte 0x5EC++0x00
line.byte 0x00 "TRSV_REG07B,no description available"
bitfld.byte 0x00 5.--7. "LN0_RX_OC_TRIAL_CNT,RX offset calibration trial number selection" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 3.--4. "LN0_RX_OC_CNT_SEL,RX SQ offset calibraiton counter selection for waiting time" "0,1,2,3"
newline
bitfld.byte 0x00 1.--2. "LN0_RX_OC_TOL,RX offset calibration enable" "0,1,2,3"
bitfld.byte 0x00 0. "LN0_RX_OC_EN,RX offset calibration tolerance for average value" "0,1"
group.byte 0x5F0++0x00
line.byte 0x00 "TRSV_REG07C,no description available"
bitfld.byte 0x00 6.--7. "LN0_RX_OC_UPD_CNT_SEL,RX offset calibration code wating time selection for SA & CTLE only" "0,1,2,3"
bitfld.byte 0x00 5. "LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD,Bypass" "0,1"
newline
bitfld.byte 0x00 4. "LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN,no description available" "0,1"
bitfld.byte 0x00 3. "LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD,no description available" "0,1"
newline
bitfld.byte 0x00 2. "LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL,no description available" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL,no description available" "0,1"
group.byte 0x5F4++0x00
line.byte 0x00 "TRSV_REG07D,no description available"
bitfld.byte 0x00 6. "LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT,no description available" "0,1"
bitfld.byte 0x00 5. "LN0_RX_OC_BYPASS_RX_SQ_DIFN,no description available" "0,1"
newline
bitfld.byte 0x00 4. "LN0_RX_OC_BYPASS_RX_SQ_DIFP,no description available" "0,1"
bitfld.byte 0x00 3. "LN0_RX_OC_BYPASS_CTLE,Bypass offset calibration for CTLE" "0,1"
newline
bitfld.byte 0x00 2. "LN0_RX_OC_ALL_RATE_MODE,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_OVRD_RX_OC_DONE,Override enable for rx_oc_done" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_OC_DONE,RX offset calibration overide value" "0,1"
group.byte 0x5F8++0x00
line.byte 0x00 "TRSV_REG07E,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_SSLMS_C0_INIT,no description available"
group.byte 0x5FC++0x00
line.byte 0x00 "TRSV_REG07F,no description available"
bitfld.byte 0x00 1.--6. "LN0_RX_SSLMS_C1_INIT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.byte 0x00 0. "LN0_RX_SSLMS_C2_SGN_INIT,no description available" "0,1"
group.byte 0x600++0x00
line.byte 0x00 "TRSV_REG080,no description available"
bitfld.byte 0x00 1.--5. "LN0_RX_SSLMS_C2_INIT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 0. "LN0_RX_SSLMS_C3_SGN_INIT,no description available" "0,1"
group.byte 0x604++0x00
line.byte 0x00 "TRSV_REG081,no description available"
bitfld.byte 0x00 1.--5. "LN0_RX_SSLMS_C3_INIT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 0. "LN0_RX_SSLMS_C4_SGN_INIT,no description available" "0,1"
group.byte 0x608++0x00
line.byte 0x00 "TRSV_REG082,no description available"
bitfld.byte 0x00 1.--4. "LN0_RX_SSLMS_C4_INIT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "LN0_RX_SSLMS_C5_SGN_INIT,no description available" "0,1"
group.byte 0x60C++0x00
line.byte 0x00 "TRSV_REG083,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_SSLMS_C5_INIT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 2.--3. "LN0_RX_SSLMS_C0_ADAP_SPEED,RX DFE SSLMS c0 adaptation speed selection" "0,1,2,3"
newline
bitfld.byte 0x00 0.--1. "LN0_RX_SSLMS_C1_ADAP_SPEED,RX DFE SSLMS c1 adaptation speed selection" "0,1,2,3"
group.byte 0x610++0x00
line.byte 0x00 "TRSV_REG084,no description available"
bitfld.byte 0x00 6.--7. "LN0_RX_SSLMS_C2_ADAP_SPEED,RX DFE SSLMS c2 adaptation speed selection" "0,1,2,3"
bitfld.byte 0x00 4.--5. "LN0_RX_SSLMS_C0_ADAP_GAIN,no description available" "0,1,2,3"
newline
bitfld.byte 0x00 2.--3. "LN0_RX_SSLMS_C1_ADAP_GAIN,no description available" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_RX_SSLMS_C2_ADAP_GAIN,no description available" "0,1,2,3"
group.byte 0x614++0x00
line.byte 0x00 "TRSV_REG085,no description available"
bitfld.byte 0x00 4. "LN0_RX_SSLMS_STAB_CONT,no description available" "0,1"
bitfld.byte 0x00 2.--3. "LN0_RX_SSLMS_ADAP_STAB,no description available" "0,1,2,3"
newline
bitfld.byte 0x00 0.--1. "LN0_RX_SSLMS_ADAP_TOL,no description available" "0,1,2,3"
group.byte 0x618++0x00
line.byte 0x00 "TRSV_REG086,no description available"
bitfld.byte 0x00 2.--7. "LN0_RX_SSLMS_ADAP_COEF_SEL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.byte 0x00 1. "LN0_RX_SSLMS_ADAP_COEF_CHK,no description available" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_SSLMS_ADAP_CONT,no description available" "0,1"
group.byte 0x61C++0x00
line.byte 0x00 "TRSV_REG087,no description available"
bitfld.byte 0x00 6.--7. "LN0_RX_SSLMS_ADAP_TIMEOUT_SEL,no description available" "0,1,2,3"
bitfld.byte 0x00 5. "LN0_RX_SSLMS_ADAP_TIMEOUT_EN,no description available" "0,1"
newline
bitfld.byte 0x00 4. "LN0_RX_SSLMS_RSTN,no description available" "0,1"
bitfld.byte 0x00 3. "LN0_OVRD_RX_SSLMS_ADAP_EN,Override enable for rx_sslms_adap_en" "0,1"
newline
bitfld.byte 0x00 2. "LN0_RX_SSLMS_ADAP_EN,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_OVRD_RX_SSLMS_ADAP_HOLD,Override enable for rx_sslms_adap_hold" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_SSLMS_ADAP_HOLD,no description available" "0,1"
group.byte 0x620++0x00
line.byte 0x00 "TRSV_REG088,no description available"
bitfld.byte 0x00 0. "LN0_RX_CDR_PMS_M_G1__8,no description available" "0,1"
group.byte 0x624++0x00
line.byte 0x00 "TRSV_REG089,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_CDR_PMS_M_G1__7_0,no description available"
group.byte 0x628++0x00
line.byte 0x00 "TRSV_REG08A,no description available"
bitfld.byte 0x00 0. "LN0_RX_CDR_PMS_M_G2__8,no description available" "0,1"
group.byte 0x62C++0x00
line.byte 0x00 "TRSV_REG08B,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_CDR_PMS_M_G2__7_0,no description available"
group.byte 0x630++0x00
line.byte 0x00 "TRSV_REG08C,no description available"
bitfld.byte 0x00 0. "LN0_RX_CDR_PMS_M_G3__8,no description available" "0,1"
group.byte 0x634++0x00
line.byte 0x00 "TRSV_REG08D,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_CDR_PMS_M_G3__7_0,no description available"
group.byte 0x638++0x00
line.byte 0x00 "TRSV_REG08E,no description available"
bitfld.byte 0x00 0. "LN0_RX_CDR_PMS_M_G4__8,no description available" "0,1"
group.byte 0x63C++0x00
line.byte 0x00 "TRSV_REG08F,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_CDR_PMS_M_G4__7_0,no description available"
group.byte 0x640++0x00
line.byte 0x00 "TRSV_REG090,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_RX_CDR_AFC_RSTN,Override enable for rx_cdr_afc_rstn" "0,1"
bitfld.byte 0x00 6. "LN0_RX_CDR_AFC_RSTN,no description available" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_RX_CDR_AFC_INIT_RSTN,Override enable for rx_cdr_afc_init_rstn" "0,1"
bitfld.byte 0x00 4. "LN0_RX_CDR_AFC_INIT_RSTN,no description available" "0,1"
newline
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_AFC_STB_NUM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x644++0x00
line.byte 0x00 "TRSV_REG091,no description available"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_AFC_TOL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x648++0x00
line.byte 0x00 "TRSV_REG092,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_CDR_AFC_VCO_CNT_RUN_NO,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x64C++0x00
line.byte 0x00 "TRSV_REG093,no description available"
bitfld.byte 0x00 1.--4. "LN0_RX_CDR_AFC_VCO_CNT_WAIT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "LN0_RX_CDR_AFC_FIX_CODE,no description available" "0,1"
group.byte 0x650++0x00
line.byte 0x00 "TRSV_REG094,no description available"
bitfld.byte 0x00 1.--4. "LN0_RX_CDR_AFC_PRESET_VCO_CNT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "LN0_RX_CDR_AFC_MAN_BSEL_TIME,no description available" "0,1"
group.byte 0x654++0x00
line.byte 0x00 "TRSV_REG095,no description available"
bitfld.byte 0x00 1.--4. "LN0_RX_CDR_AFC_MAN_BSEL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "LN0_RX_CDR_AFC_BSEL,no description available" "0,1"
group.byte 0x658++0x00
line.byte 0x00 "TRSV_REG096,no description available"
bitfld.byte 0x00 0.--5. "LN0_RX_CDR_FBB_VCO_CNT_RUN_NO,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x65C++0x00
line.byte 0x00 "TRSV_REG097,no description available"
bitfld.byte 0x00 1.--4. "LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "LN0_RX_CDR_FBB_MAN_SEL,no description available" "0,1"
group.byte 0x660++0x00
line.byte 0x00 "TRSV_REG098,no description available"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_MAN_CODE_UPDC,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x664++0x00
line.byte 0x00 "TRSV_REG099,no description available"
bitfld.byte 0x00 0.--5. "LN0_RX_CDR_FBB_DELTA_CNT,Target delta number in VCO counter in CDR FBB cal mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x668++0x00
line.byte 0x00 "TRSV_REG09A,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1,[GEN1] RX CDR BBVCO FBB gain control in PLL mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x66C++0x00
line.byte 0x00 "TRSV_REG09B,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x670++0x00
line.byte 0x00 "TRSV_REG09C,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_COARSE_CTRL_G1,[GEN1] RX CDR BBVCO FBB gain control in coarse mode (high bandwidth)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_COARSE_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x674++0x00
line.byte 0x00 "TRSV_REG09D,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_COARSE_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_COARSE_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x678++0x00
line.byte 0x00 "TRSV_REG09E,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_FINE_CTRL_G1,[GEN1] RX CDR BBVCO FBB gain control in fine mode (low bandwidth)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_FINE_CTRL_G2,[GEN2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x67C++0x00
line.byte 0x00 "TRSV_REG09F,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_FINE_CTRL_G3,[GEN3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_FINE_CTRL_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x680++0x00
line.byte 0x00 "TRSV_REG0A0,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_PLL_BW_DIFF_G1,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_PLL_BW_DIFF_G2,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x684++0x00
line.byte 0x00 "TRSV_REG0A1,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_PLL_BW_DIFF_G3,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_PLL_BW_DIFF_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x688++0x00
line.byte 0x00 "TRSV_REG0A2,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_HI_BW_DIFF_G1,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_HI_BW_DIFF_G2,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x68C++0x00
line.byte 0x00 "TRSV_REG0A3,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_HI_BW_DIFF_G3,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_HI_BW_DIFF_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x690++0x00
line.byte 0x00 "TRSV_REG0A4,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_LO_BW_DIFF_G1,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_LO_BW_DIFF_G2,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x694++0x00
line.byte 0x00 "TRSV_REG0A5,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_CDR_FBB_LO_BW_DIFF_G3,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_FBB_LO_BW_DIFF_G4,[GEN4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x698++0x00
line.byte 0x00 "TRSV_REG0A6,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_CDR_PLL_VCO_CNT_RUN_NO,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x69C++0x00
line.byte 0x00 "TRSV_REG0A7,no description available"
bitfld.byte 0x00 0.--3. "LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6A0++0x00
line.byte 0x00 "TRSV_REG0A8,no description available"
bitfld.byte 0x00 2.--6. "LN0_RX_CDR_PLL_LOCK_PPM_SET,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 1. "LN0_RX_CDR_PLL_MODE_ENTRY_SRC,no description available" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_CDR_PLL_MODE_RESTART,no description available" "0,1"
group.byte 0x6A4++0x00
line.byte 0x00 "TRSV_REG0A9,no description available"
bitfld.byte 0x00 0.--4. "LN0_RX_CDR_CK_VCO_CNT_RUN_NO,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x6A8++0x00
line.byte 0x00 "TRSV_REG0AA,no description available"
bitfld.byte 0x00 3.--6. "LN0_RX_CDR_CK_VCO_CNT_WAIT_NO,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--2. "LN0_RX_CDR_LOCK_SETTLE_NO,no description available" "0,1,2,3,4,5,6,7"
group.byte 0x6AC++0x00
line.byte 0x00 "TRSV_REG0AB,no description available"
bitfld.byte 0x00 2.--6. "LN0_RX_CDR_CK_LOCK_PPM_SET,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 1. "LN0_OVRD_RX_CDR_CAL_DONE,Override enable for rx_cdr_cal_done" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_CDR_CAL_DONE,no description available" "0,1"
group.byte 0x6B0++0x00
line.byte 0x00 "TRSV_REG0AC,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_PWM_TG_OSC_CNT_MIN,no description available"
group.byte 0x6B4++0x00
line.byte 0x00 "TRSV_REG0AD,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_PWM_TG_OSC_CNT_MAX,no description available"
group.byte 0x6B8++0x00
line.byte 0x00 "TRSV_REG0AE,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_PWM_AFC_TOL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_RX_PWM_AFC_STB_NUM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6BC++0x00
line.byte 0x00 "TRSV_REG0AF,no description available"
bitfld.byte 0x00 0. "LN0_RX_PWM_AFC_EN,no description available" "0,1"
group.byte 0x6C0++0x00
line.byte 0x00 "TRSV_REG0B0,no description available"
bitfld.byte 0x00 0. "LN0_OVRD_RX_EFOM_FEEDBACK,Override enable for" "0,1"
group.byte 0x6C4++0x00
line.byte 0x00 "TRSV_REG0B1,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_EFOM_FEEDBACK__15_8,no description available"
group.byte 0x6C8++0x00
line.byte 0x00 "TRSV_REG0B2,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_EFOM_FEEDBACK__7_0,no description available"
group.byte 0x6CC++0x00
line.byte 0x00 "TRSV_REG0B3,no description available"
bitfld.byte 0x00 6. "LN0_OVRD_RX_EFOM_DONE,Override enable for rx_efom_done" "0,1"
bitfld.byte 0x00 5. "LN0_RX_EFOM_DONE,no description available" "0,1"
newline
bitfld.byte 0x00 2.--4. "LN0_RX_EFOM_MODE,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 1. "LN0_OVRD_RX_EFOM_START,Override enable for rx_efom_start" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_EFOM_START,no description available" "0,1"
group.byte 0x6D0++0x00
line.byte 0x00 "TRSV_REG0B4,no description available"
bitfld.byte 0x00 5.--7. "LN0_RX_EFOM_VREF_RESOL,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 4. "LN0_RX_EFOM_START_SSM_DISABLE,no description available" "0,1"
newline
bitfld.byte 0x00 2.--3. "LN0_RX_EFOM_H_WEIGHT,no description available" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_RX_EFOM_V_WEIGHT,no description available" "0,1,2,3"
group.byte 0x6D4++0x00
line.byte 0x00 "TRSV_REG0B5,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_EFOM_SETTLE_TIME,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 2.--3. "LN0_RX_EFOM_BIT_WIDTH_SEL,no description available" "0,1,2,3"
newline
bitfld.byte 0x00 1. "LN0_RX_EFOM_RSTN,no description available" "0,1"
bitfld.byte 0x00 0. "LN0_RX_EFOM_EN,no description available" "0,1"
group.byte 0x6D8++0x00
line.byte 0x00 "TRSV_REG0B6,no description available"
bitfld.byte 0x00 0.--5. "LN0_RX_EFOM_NUM_OF_SAMPLE__13_8,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x6DC++0x00
line.byte 0x00 "TRSV_REG0B7,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_EFOM_NUM_OF_SAMPLE__7_0,no description available"
group.byte 0x6E0++0x00
line.byte 0x00 "TRSV_REG0B8,no description available"
bitfld.byte 0x00 1.--3. "LN0_RX_EFOM_TRIAL_NUM,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0. "LN0_RX_EFOM_OUT_WIDTH_SEL,no description available" "0,1"
group.byte 0x6E4++0x00
line.byte 0x00 "TRSV_REG0B9,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_RX_EFOM_DFE_VREF_CTRL,no description available"
group.byte 0x6E8++0x00
line.byte 0x00 "TRSV_REG0BA,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_RX_EFOM_EOM_PH_SEL,no description available"
group.byte 0x6EC++0x00
line.byte 0x00 "TRSV_REG0BB,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_TXD_DESKEW_RSTN,Override enable for txd_deskew_rstn" "0,1"
bitfld.byte 0x00 6. "LN0_TXD_DESKEW_RSTN,no description available" "0,1"
newline
bitfld.byte 0x00 5. "LN0_TXD_DESKEW_BYPASS_ERR_CHK,no description available" "0,1"
bitfld.byte 0x00 4. "LN0_TXD_DESKEW_FIX_DA,no description available" "0,1"
newline
bitfld.byte 0x00 3. "LN0_TXD_DESKEW_FIX_DB,no description available" "0,1"
bitfld.byte 0x00 2. "LN0_TXD_DESKEW_BYPASS,no description available" "0,1"
newline
bitfld.byte 0x00 1. "LN0_NEARLB_EN,no description available" "0,1"
bitfld.byte 0x00 0. "LN0_RETIMEDLB_EN,no description available" "0,1"
group.byte 0x6F0++0x00
line.byte 0x00 "TRSV_REG0BC,no description available"
bitfld.byte 0x00 7. "LN0_RXD_ALIGN_EN,no description available" "0,1"
bitfld.byte 0x00 6. "LN0_RXD_ALIGN_HOLD,no description available" "0,1"
newline
bitfld.byte 0x00 5. "LN0_RXD_ALIGN_WORD,no description available" "0,1"
bitfld.byte 0x00 1.--4. "LN0_RXD_LOCK_NUM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "LN0_RXD_FLIP_BYTE,no description available" "0,1"
group.byte 0x6F4++0x00
line.byte 0x00 "TRSV_REG0BD,no description available"
bitfld.byte 0x00 7. "LN0_RXD_FLIP_BIT,no description available" "0,1"
bitfld.byte 0x00 6. "LN0_RXD_POLARITY,no description available" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_TX_RCAL_RSTN,Override enable for tx_rcal_rstn" "0,1"
bitfld.byte 0x00 4. "LN0_TX_RCAL_RSTN,no description available" "0,1"
newline
bitfld.byte 0x00 2.--3. "LN0_TX_RCAL_UP_OPT_CODE,no description available" "0,1,2,3"
bitfld.byte 0x00 0.--1. "LN0_TX_RCAL_DN_OPT_CODE,no description available" "0,1,2,3"
group.byte 0x6F8++0x00
line.byte 0x00 "TRSV_REG0BE,no description available"
bitfld.byte 0x00 4.--7. "LN0_TX_RCAL_UP_CODE,Termination up control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_TX_RCAL_DN_CODE,Termination down control bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6FC++0x00
line.byte 0x00 "TRSV_REG0BF,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_TX_RCAL_COMP_OUT,Override enable for tx_rcal_comp_out" "0,1"
bitfld.byte 0x00 6. "LN0_TX_RCAL_COMP_OUT,no description available" "0,1"
newline
bitfld.byte 0x00 5. "LN0_OVRD_TX_RCAL_DONE,Override enable for tx_rcal_done" "0,1"
bitfld.byte 0x00 4. "LN0_TX_RCAL_DONE,Monitoring for TX RCAL done" "0,1"
newline
bitfld.byte 0x00 3. "LN0_OVRD_RX_RCAL_RSTN,Override enable for rx_rcal_rstn" "0,1"
bitfld.byte 0x00 2. "LN0_RX_RCAL_RSTN,no description available" "0,1"
newline
bitfld.byte 0x00 0.--1. "LN0_RX_RCAL_OPT_CODE,no description available" "0,1,2,3"
group.byte 0x700++0x00
line.byte 0x00 "TRSV_REG0C0,no description available"
bitfld.byte 0x00 4.--7. "LN0_RX_RTERM_CTRL,Termination Calibration will send control signals to make 42.5 ohms" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 3. "LN0_OVRD_RX_RCAL_COMP_OUT,Override enable for rx_rcal_comp_out" "0,1"
newline
bitfld.byte 0x00 2. "LN0_RX_RCAL_COMP_OUT,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_OVRD_RX_RCAL_DONE,Override enable for rx_rcal_done" "0,1"
newline
bitfld.byte 0x00 0. "LN0_RX_RCAL_DONE,RX RCAL done" "0,1"
group.byte 0x704++0x00
line.byte 0x00 "TRSV_REG0C1,no description available"
bitfld.byte 0x00 7. "LN0_BIST_AUTO_RUN,no description available" "0,1"
bitfld.byte 0x00 5.--6. "LN0_BIST_COMDET_NUM,no description available" "0,1,2,3"
newline
bitfld.byte 0x00 2.--4. "LN0_BIST_SEED_SEL,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--1. "LN0_BIST_PRBS_MODE,no description available" "0,1,2,3"
group.byte 0x708++0x00
line.byte 0x00 "TRSV_REG0C2,no description available"
bitfld.byte 0x00 7. "LN0_BIST_EN,no description available" "0,1"
bitfld.byte 0x00 6. "LN0_BIST_DATA_EN,no description available" "0,1"
newline
bitfld.byte 0x00 5. "LN0_BIST_RX_EN,no description available" "0,1"
bitfld.byte 0x00 4. "LN0_BIST_RX_HOLD,no description available" "0,1"
newline
bitfld.byte 0x00 3. "LN0_BIST_RX_START,no description available" "0,1"
bitfld.byte 0x00 2. "LN0_BIST_TX_EN,no description available" "0,1"
newline
bitfld.byte 0x00 1. "LN0_BIST_TX_ERRINJ,no description available" "0,1"
bitfld.byte 0x00 0. "LN0_BIST_TX_START,no description available" "0,1"
group.byte 0x70C++0x00
line.byte 0x00 "TRSV_REG0C3,no description available"
bitfld.byte 0x00 0. "LN0_BIST_USER_PAT_EN,no description available" "0,1"
group.byte 0x710++0x00
line.byte 0x00 "TRSV_REG0C4,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__79_72,no description available"
group.byte 0x714++0x00
line.byte 0x00 "TRSV_REG0C5,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__71_64,no description available"
group.byte 0x718++0x00
line.byte 0x00 "TRSV_REG0C6,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__63_56,no description available"
group.byte 0x71C++0x00
line.byte 0x00 "TRSV_REG0C7,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__55_48,no description available"
group.byte 0x720++0x00
line.byte 0x00 "TRSV_REG0C8,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__47_40,no description available"
group.byte 0x724++0x00
line.byte 0x00 "TRSV_REG0C9,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__39_32,no description available"
group.byte 0x728++0x00
line.byte 0x00 "TRSV_REG0CA,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__31_24,no description available"
group.byte 0x72C++0x00
line.byte 0x00 "TRSV_REG0CB,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__23_16,no description available"
group.byte 0x730++0x00
line.byte 0x00 "TRSV_REG0CC,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__15_8,no description available"
group.byte 0x734++0x00
line.byte 0x00 "TRSV_REG0CD,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_BIST_USER_PAT__7_0,no description available"
group.byte 0x738++0x00
line.byte 0x00 "TRSV_REG0CE,no description available"
bitfld.byte 0x00 4.--5. "LN0_RX_SIGVAL_LPF_BYPASS,no description available" "0,1,2,3"
bitfld.byte 0x00 1.--3. "LN0_TG_RX_SIGVAL_LPF_DELAY_TIME,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0. "LN0_LANE_MODE,Lane operation mode" "0,1"
group.byte 0x73C++0x00
line.byte 0x00 "TRSV_REG0CF,no description available"
bitfld.byte 0x00 6. "LN0_OVRD_LANE_RATE,Override enable for lane_rate" "0,1"
bitfld.byte 0x00 4.--5. "LN0_LANE_RATE,no description available" "0,1,2,3"
newline
bitfld.byte 0x00 3. "LN0_LANE_TIMER_SEL,no description available" "0,1"
bitfld.byte 0x00 2. "LN0_MISC_TX_CLK_SRC,no description available" "0,1"
newline
bitfld.byte 0x00 1. "LN0_MISC_RX_CLK_SRC,no description available" "0,1"
bitfld.byte 0x00 0. "LN0_MISC_RX_CLK_INV,no description available" "0,1"
group.byte 0x740++0x00
line.byte 0x00 "TRSV_REG0D0,no description available"
bitfld.byte 0x00 6. "LN0_OVRD_MISC_RX_SQHS_SIGVAL,Override enable for misc_rx_sqhs_sigval" "0,1"
bitfld.byte 0x00 5. "LN0_MISC_RX_SQHS_SIGVAL,no description available" "0,1"
newline
bitfld.byte 0x00 4. "LN0_MISC_RX_DATA_CLEAR_SRC,no description available" "0,1"
bitfld.byte 0x00 3. "LN0_OVRD_MISC_RX_LFPS_DET,Override enable for misc_rx_lfps_det" "0,1"
newline
bitfld.byte 0x00 2. "LN0_MISC_RX_LFPS_DET,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_OVRD_MISC_TX_RXD_DETECTED,Override enable for misc_tx_rxd_detected" "0,1"
newline
bitfld.byte 0x00 0. "LN0_MISC_TX_RXD_DETECTED,no description available" "0,1"
group.byte 0x744++0x00
line.byte 0x00 "TRSV_REG0D1,no description available"
bitfld.byte 0x00 7. "LN0_OVRD_MISC_RX_VALID_RSTN,Override enable for misc_rx_valid_rstn" "0,1"
bitfld.byte 0x00 6. "LN0_MISC_RX_VALID_RSTN,no description available" "0,1"
newline
bitfld.byte 0x00 3.--5. "LN0_TG_CDR_BW_CTRL_DELAY_TIME,RX CDR bandwidth change time control" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_TG_RCAL_RSTN_DELAY_TIME,Rx Rcal reset delay time after PLL AFC done" "0,1,2,3,4,5,6,7"
group.byte 0x748++0x00
line.byte 0x00 "TRSV_REG0D2,no description available"
bitfld.byte 0x00 0.--1. "LN0_TG_RXD_COMP_DELAY_TIME,no description available" "0,1,2,3"
group.byte 0x74C++0x00
line.byte 0x00 "TRSV_REG0D3,no description available"
bitfld.byte 0x00 5. "LN0_ANA_RX_SQLS_DIFN_DET,DIFN Detection signal" "0,1"
bitfld.byte 0x00 4. "LN0_ANA_RX_SQLS_DIFP_DET,DIFP Detection signal" "0,1"
newline
bitfld.byte 0x00 0.--3. "LN0_MON_LANE_STATE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x750++0x00
line.byte 0x00 "TRSV_REG0D4,no description available"
bitfld.byte 0x00 0.--3. "LN0_MON_CDR_STATE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x754++0x00
line.byte 0x00 "TRSV_REG0D5,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_MON_LANE_TIME__14_8,no description available"
group.byte 0x758++0x00
line.byte 0x00 "TRSV_REG0D6,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_LANE_TIME__7_0,no description available"
group.byte 0x75C++0x00
line.byte 0x00 "TRSV_REG0D7,no description available"
bitfld.byte 0x00 4.--7. "LN0_MON_RX_CDR_AFC_SEL_LOGIC,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_MON_RX_CDR_FBB_FINE_CTRL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x760++0x00
line.byte 0x00 "TRSV_REG0D8,no description available"
bitfld.byte 0x00 4.--7. "LN0_MON_RX_CDR_FBB_COARSE_CTRL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x764++0x00
line.byte 0x00 "TRSV_REG0D9,no description available"
bitfld.byte 0x00 0.--1. "LN0_MON_RX_CDR_MODE_CTRL,no description available" "0,1,2,3"
group.byte 0x768++0x00
line.byte 0x00 "TRSV_REG0DA,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_MON_RX_OC_DFE_ADDER_EVEN,no description available"
group.byte 0x76C++0x00
line.byte 0x00 "TRSV_REG0DB,no description available"
hexmask.byte 0x00 1.--7. 1. "LN0_MON_RX_OC_DFE_ADDER_ODD,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN,no description available" "0,1"
group.byte 0x770++0x00
line.byte 0x00 "TRSV_REG0DC,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_OC_DFE_DAC_ADDER_ODD,no description available" "0,1"
group.byte 0x774++0x00
line.byte 0x00 "TRSV_REG0DD,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8,no description available" "0,1"
group.byte 0x778++0x00
line.byte 0x00 "TRSV_REG0DE,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0,no description available"
group.byte 0x77C++0x00
line.byte 0x00 "TRSV_REG0DF,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8,no description available" "0,1"
group.byte 0x780++0x00
line.byte 0x00 "TRSV_REG0E0,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0,no description available"
group.byte 0x784++0x00
line.byte 0x00 "TRSV_REG0E1,no description available"
bitfld.byte 0x00 3.--5. "LN0_MON_RX_OC_DFE_DAC_EDGE_ODD,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN,no description available" "0,1,2,3,4,5,6,7"
group.byte 0x788++0x00
line.byte 0x00 "TRSV_REG0E2,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8,no description available" "0,1"
group.byte 0x78C++0x00
line.byte 0x00 "TRSV_REG0E3,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0,no description available"
group.byte 0x790++0x00
line.byte 0x00 "TRSV_REG0E4,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_OC_DFE_SA_ERR_ODD__8,no description available" "0,1"
group.byte 0x794++0x00
line.byte 0x00 "TRSV_REG0E5,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0,no description available"
group.byte 0x798++0x00
line.byte 0x00 "TRSV_REG0E6,no description available"
bitfld.byte 0x00 3.--5. "LN0_MON_RX_OC_DFE_DAC_ERR_EVEN,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_MON_RX_OC_DFE_DAC_ERR_ODD,no description available" "0,1,2,3,4,5,6,7"
group.byte 0x79C++0x00
line.byte 0x00 "TRSV_REG0E7,no description available"
hexmask.byte 0x00 0.--6. 1. "LN0_MON_RX_OC_CTLE,no description available"
group.byte 0x7A0++0x00
line.byte 0x00 "TRSV_REG0E8,no description available"
bitfld.byte 0x00 4.--7. "LN0_MON_RX_OC_SQ_DIFN,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "LN0_MON_RX_OC_SQ_DIFP,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x7A4++0x00
line.byte 0x00 "TRSV_REG0E9,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_OC_CAL_DONE,no description available" "0,1"
group.byte 0x7A8++0x00
line.byte 0x00 "TRSV_REG0EA,no description available"
bitfld.byte 0x00 0.--1. "LN0_MON_RX_OC_FAIL__9_8,no description available" "0,1,2,3"
group.byte 0x7AC++0x00
line.byte 0x00 "TRSV_REG0EB,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_OC_FAIL__7_0,no description available"
group.byte 0x7B0++0x00
line.byte 0x00 "TRSV_REG0EC,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_SSLMS_C0__8,no description available" "0,1"
group.byte 0x7B4++0x00
line.byte 0x00 "TRSV_REG0ED,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_SSLMS_C0__7_0,no description available"
group.byte 0x7B8++0x00
line.byte 0x00 "TRSV_REG0EE,no description available"
hexmask.byte 0x00 1.--7. 1. "LN0_MON_RX_SSLMS_C1,no description available"
bitfld.byte 0x00 0. "LN0_MON_RX_SSLMS_C2_SGN,no description available" "0,1"
group.byte 0x7BC++0x00
line.byte 0x00 "TRSV_REG0EF,no description available"
bitfld.byte 0x00 1.--5. "LN0_MON_RX_SSLMS_C2,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 0. "LN0_MON_RX_SSLMS_C3_SGN,no description available" "0,1"
group.byte 0x7C0++0x00
line.byte 0x00 "TRSV_REG0F0,no description available"
bitfld.byte 0x00 1.--5. "LN0_MON_RX_SSLMS_C3,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 0. "LN0_MON_RX_SSLMS_C4_SGN,no description available" "0,1"
group.byte 0x7C4++0x00
line.byte 0x00 "TRSV_REG0F1,no description available"
bitfld.byte 0x00 1.--4. "LN0_MON_RX_SSLMS_C4,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "LN0_MON_RX_SSLMS_C5_SGN,no description available" "0,1"
group.byte 0x7C8++0x00
line.byte 0x00 "TRSV_REG0F2,no description available"
bitfld.byte 0x00 2.--5. "LN0_MON_RX_SSLMS_C5,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 1. "LN0_MON_RX_SSLMS_ADAP_DONE,no description available" "0,1"
newline
bitfld.byte 0x00 0. "LN0_MON_RX_EFOM_DONE,no description available" "0,1"
group.byte 0x7CC++0x00
line.byte 0x00 "TRSV_REG0F3,no description available"
bitfld.byte 0x00 0.--5. "LN0_MON_RX_EFOM_ERR_CNT__13_8,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x7D0++0x00
line.byte 0x00 "TRSV_REG0F4,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_EFOM_ERR_CNT__7_0,no description available"
group.byte 0x7D4++0x00
line.byte 0x00 "TRSV_REG0F5,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_EFOM_FEEDBACK__15_8,no description available"
group.byte 0x7D8++0x00
line.byte 0x00 "TRSV_REG0F6,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_RX_EFOM_FEEDBACK__7_0,no description available"
group.byte 0x7DC++0x00
line.byte 0x00 "TRSV_REG0F7,no description available"
bitfld.byte 0x00 1.--4. "LN0_MON_TX_RCAL_TUNE_CODE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0. "LN0_MON_TX_RCAL_DONE,no description available" "0,1"
group.byte 0x7E0++0x00
line.byte 0x00 "TRSV_REG0F8,no description available"
bitfld.byte 0x00 4.--7. "LN0_MON_RX_RCAL_TUNE_CODE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 3. "LN0_MON_RX_RCAL_DONE,no description available" "0,1"
newline
bitfld.byte 0x00 2. "LN0_MON_RX_PWM_AFC_DONE,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_MON_RX_PWM_AFC_FAIL,no description available" "0,1"
newline
bitfld.byte 0x00 0. "LN0_MON_RX_PWM_AFC_REPEAT,no description available" "0,1"
group.byte 0x7E4++0x00
line.byte 0x00 "TRSV_REG0F9,no description available"
bitfld.byte 0x00 0.--3. "LN0_MON_RX_PWM_AFC_CODE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x7E8++0x00
line.byte 0x00 "TRSV_REG0FA,no description available"
bitfld.byte 0x00 6. "LN0_MON_RX_CDR_AFC_DONE,no description available" "0,1"
bitfld.byte 0x00 5. "LN0_MON_RX_CDR_CAL_DONE,no description available" "0,1"
newline
bitfld.byte 0x00 4. "LN0_MON_RX_CDR_FLD_PLL_MODE_DONE,no description available" "0,1"
bitfld.byte 0x00 3. "LN0_MON_RX_CDR_LOCK_DONE,no description available" "0,1"
newline
bitfld.byte 0x00 2. "LN0_MON_BIST_COMP_TEST,no description available" "0,1"
bitfld.byte 0x00 1. "LN0_MON_BIST_ERRINJ_TEST,no description available" "0,1"
newline
bitfld.byte 0x00 0. "LN0_MON_BIST_COMP_START,no description available" "0,1"
group.byte 0x7EC++0x00
line.byte 0x00 "TRSV_REG0FB,no description available"
hexmask.byte 0x00 0.--7. 1. "LN0_MON_BIST_EOUT,no description available"
group.byte 0x7F0++0x00
line.byte 0x00 "TRSV_REG0FC,no description available"
bitfld.byte 0x00 7. "LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1,no description available" "0,1"
bitfld.byte 0x00 4.--6. "LN0_ANA_TX_DRV_ACCDRV_CTRL_G1,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 3. "LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2,no description available" "0,1"
bitfld.byte 0x00 0.--2. "LN0_ANA_TX_DRV_ACCDRV_CTRL_G2,no description available" "0,1,2,3,4,5,6,7"
group.byte 0x7F4++0x00
line.byte 0x00 "TRSV_REG0FD,no description available"
bitfld.byte 0x00 7. "LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3,no description available" "0,1"
bitfld.byte 0x00 4.--6. "LN0_ANA_TX_DRV_ACCDRV_CTRL_G3,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 3. "LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4,no description available" "0,1"
bitfld.byte 0x00 0.--2. "LN0_ANA_TX_DRV_ACCDRV_CTRL_G4,no description available" "0,1,2,3,4,5,6,7"
group.byte 0x7F8++0x00
line.byte 0x00 "TRSV_REG0FE,no description available"
bitfld.byte 0x00 4.--6. "LN0_ANA_RX_CDR_AFC_VCI_SEL_G1,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_ANA_RX_CDR_AFC_VCI_SEL_G2,no description available" "0,1,2,3,4,5,6,7"
group.byte 0x7FC++0x00
line.byte 0x00 "TRSV_REG0FF,no description available"
bitfld.byte 0x00 4.--6. "LN0_ANA_RX_CDR_AFC_VCI_SEL_G3,no description available" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0.--2. "LN0_ANA_RX_CDR_AFC_VCI_SEL_G4,no description available" "0,1,2,3,4,5,6,7"
tree.end
tree "PDM (Pulse Density Modulation (Digital Microphone) Interface)"
base ad:0x30CA0000
group.long 0x00++0x03
line.long 0x00 "CTRL_1,MICFIL Control register 1"
bitfld.long 0x00 31. "MDIS,Module Disable" "0: NORMAL_MODE,1: DISABLE_LOW_LEAKAGE_MODE"
bitfld.long 0x00 30. "DOZEN,DOZE enable" "0: DOZE enable bit is not asserted,1: DOZE enable bit is asserted"
newline
bitfld.long 0x00 29. "PDMIEN,PDM Inteface Enable" "0: PDM Interface disabled,1: PDM Interface enabled"
bitfld.long 0x00 28. "DBG,Debug Mode" "0: PDM Interface is in Normal Mode,1: PDM Interface is in Debug Mode"
newline
bitfld.long 0x00 27. "SRES,Software-reset bit" "0: NO_ACTION,1: Software reset"
bitfld.long 0x00 26. "DBGE,Module Enable in Debug" "0: PDM Interface is disabled in debug mode after..,1: PDM Interface is enabled in debug mode"
newline
bitfld.long 0x00 24.--25. "DISEL,DMA Interrupt Selection" "0: DMA and interrupt requests disabled,1: DMA_INTERRUPT_ENABLE,2: Interrupt requests enabled,?..."
bitfld.long 0x00 23. "ERREN,Error Interruption Enable" "0: Error Interrupts disabled,1: Error Interrupts enabled"
newline
bitfld.long 0x00 7. "CH7EN,Channel 7 Enable" "0,1"
bitfld.long 0x00 6. "CH6EN,Channel 6 Enable" "0,1"
newline
bitfld.long 0x00 5. "CH5EN,Channel 5 Enable" "0,1"
bitfld.long 0x00 4. "CH4EN,Channel 4 Enable" "0,1"
newline
bitfld.long 0x00 3. "CH3EN,Channel 3 Enable" "0,1"
bitfld.long 0x00 2. "CH2EN,Channel 2 Enable" "0,1"
newline
bitfld.long 0x00 1. "CH1EN,Channel 1 Enable" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 Enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTRL_2,MICFIL Control register 2"
bitfld.long 0x00 25.--27. "QSEL,Quality Select" "0: Medium quality mode,1: High quality mode,?,?,4: Very low quality 2 mode,5: Very low quality 1 mode,6: Very low quality 0 mode,7: Low quality mode"
bitfld.long 0x00 16.--19. "CICOSR,CIC Oversampling Rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 0.--7. 1. "CLKDIV,Clock Divider"
group.long 0x08++0x03
line.long 0x00 "STAT,MICFIL Status register"
rbitfld.long 0x00 31. "BSY_FIL,Decimation Filter Busy Flag" "0: All Decimation Filters are stopped,1: At least one Decimation Filter channel is.."
rbitfld.long 0x00 30. "FIR_RDY,FIR Filter Data Ready" "0: FIR Filter data not reliable,1: FIR Filter data reliable"
newline
eventfld.long 0x00 29. "LOWFREQF,Low Frequency Flag" "0: CLKDIV value is OK,1: CLKDIV value is too low"
eventfld.long 0x00 7. "CH7F,Channel 7 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
newline
eventfld.long 0x00 6. "CH6F,Channel 6 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
eventfld.long 0x00 5. "CH5F,Channel 5 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
newline
eventfld.long 0x00 4. "CH4F,Channel 4 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
eventfld.long 0x00 3. "CH3F,Channel 3 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
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eventfld.long 0x00 2. "CH2F,Channel 2 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
eventfld.long 0x00 1. "CH1F,Channel 1 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
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eventfld.long 0x00 0. "CH0F,Channel 0 Output Data Flag" "0: Channel's FIFO did not reach the number of..,1: Channel's FIFO reached the number of elements.."
group.long 0x10++0x03
line.long 0x00 "FIFO_CTRL,MICFIL FIFO Control register"
bitfld.long 0x00 0.--4. "FIFOWMK,FIFO Watermark Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "FIFO_STAT,MICFIL FIFO Status register"
eventfld.long 0x00 15. "FIFOUND7,FIFO Underflow Exception flag for Channel 7" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
eventfld.long 0x00 14. "FIFOUND6,FIFO Underflow Exception flag for Channel 6" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
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eventfld.long 0x00 13. "FIFOUND5,FIFO Underflow Exception flag for Channel 5" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
eventfld.long 0x00 12. "FIFOUND4,FIFO Underflow Exception flag for Channel 4" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
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eventfld.long 0x00 11. "FIFOUND3,FIFO Underflow Exception flag for Channel 3" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
eventfld.long 0x00 10. "FIFOUND2,FIFO Underflow Exception flag for Channel 2" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
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eventfld.long 0x00 9. "FIFOUND1,FIFO Underflow Exception flag for Channel 1" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
eventfld.long 0x00 8. "FIFOUND0,FIFO Underflow Exception flag for Channel 0" "0: No exception by FIFO Underflow,1: Exception by FIFO underflow"
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eventfld.long 0x00 7. "FIFOOVF7,FIFO Overflow Exception flag for Channel 7" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
eventfld.long 0x00 6. "FIFOOVF6,FIFO Overflow Exception flag for Channel 6" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
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eventfld.long 0x00 5. "FIFOOVF5,FIFO Overflow Exception flag for Channel 5" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
eventfld.long 0x00 4. "FIFOOVF4,FIFO Overflow Exception flag for Channel 4" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
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eventfld.long 0x00 3. "FIFOOVF3,FIFO Overflow Exception flag for Channel 3" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
eventfld.long 0x00 2. "FIFOOVF2,FIFO Overflow Exception flag for Channel 2" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
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eventfld.long 0x00 1. "FIFOOVF1,FIFO Overflow Exception flag for Channel 1" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
eventfld.long 0x00 0. "FIFOOVF0,FIFO Overflow Exception flag for Channel 0" "0: No exception by FIFO overflow,1: Exception by FIFO overflow"
repeat 8. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x24)++0x03
line.long 0x00 "DATACH[$1],MICFIL Output Result Register $1"
hexmask.long 0x00 0.--31. 1. "DATA,Channel n Data"
repeat.end
group.long 0x64++0x03
line.long 0x00 "DC_CTRL,MICFIL DC Remover Control register"
bitfld.long 0x00 14.--15. "DCCONFIG7,Channel 7 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
bitfld.long 0x00 12.--13. "DCCONFIG6,Channel 6 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
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bitfld.long 0x00 10.--11. "DCCONFIG5,Channel 5 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
bitfld.long 0x00 8.--9. "DCCONFIG4,Channel 4 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
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bitfld.long 0x00 6.--7. "DCCONFIG3,Channel 3 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
bitfld.long 0x00 4.--5. "DCCONFIG2,Channel 2 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
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bitfld.long 0x00 2.--3. "DCCONFIG1,Channel 1 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
bitfld.long 0x00 0.--1. "DCCONFIG0,Channel 0 DC Remover Configuration" "0: DC Remover cut-off at 21Hz,1: DC Remover cut-off at 83Hz,2: DC Remover cut-off at 152Hz,3: DC Remover is bypassed"
group.long 0x74++0x03
line.long 0x00 "RANGE_CTRL,MICFIL Range Control register"
bitfld.long 0x00 28.--31. "RANGEADJ7,Channel 7 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "RANGEADJ6,Channel 6 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "RANGEADJ5,Channel 5 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "RANGEADJ4,Channel 4 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "RANGEADJ3,Channel 3 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "RANGEADJ2,Channel 2 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "RANGEADJ1,Channel 1 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "RANGEADJ0,Channel 0 Range Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7C++0x03
line.long 0x00 "RANGE_STAT,MICFIL Range Status register"
eventfld.long 0x00 23. "RANGEUNF7,Channel 7 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
eventfld.long 0x00 22. "RANGEUNF6,Channel 6 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
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eventfld.long 0x00 21. "RANGEUNF5,Channel 5 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
eventfld.long 0x00 20. "RANGEUNF4,Channel 4 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
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eventfld.long 0x00 19. "RANGEUNF3,Channel 3 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
eventfld.long 0x00 18. "RANGEUNF2,Channel 2 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
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eventfld.long 0x00 17. "RANGEUNF1,Channel 1 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
eventfld.long 0x00 16. "RANGEUNF0,Channel 0 Range Underflow Error Flag" "0: No exception by range underflow,1: Exception by range underflow"
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eventfld.long 0x00 7. "RANGEOVF7,Channel 7 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
eventfld.long 0x00 6. "RANGEOVF6,Channel 6 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
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eventfld.long 0x00 5. "RANGEOVF5,Channel 5 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
eventfld.long 0x00 4. "RANGEOVF4,Channel 4 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
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eventfld.long 0x00 3. "RANGEOVF3,Channel 3 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
eventfld.long 0x00 2. "RANGEOVF2,Channel 2 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
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eventfld.long 0x00 1. "RANGEOVF1,Channel 1 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
eventfld.long 0x00 0. "RANGEOVF0,Channel 0 Range Overflow Error Flag" "0: No exception by range overflow,1: Exception by range overflow"
group.long 0x90++0x03
line.long 0x00 "VAD0_CTRL_1,Voice Activity Detector Control register"
bitfld.long 0x00 24.--26. "VADCHSEL,Voice Activity Detector Channel Selector" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "VADCICOSR,Voice Activity Detector CIC Oversampling Rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--12. "VADINITT,Voice Activity Detector Initialization Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. "VADST10,Voice Activity Detector Internal Filters Initialization" "0: Normal operation,1: Filters are initialized"
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bitfld.long 0x00 3. "VADERIE,Voice Activity Detector Error Interruption Enable" "0: HWVAD Error Interrupts disabled,1: HWVAD Error Interrupts enabled"
bitfld.long 0x00 2. "VADIE,Voice Activity Detector Interruption Enable" "0: HWVAD Interrupts disabled,1: HWVAD Interrupts enabled"
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bitfld.long 0x00 1. "VADRST,Voice Activity Detector Reset" "0,1"
bitfld.long 0x00 0. "VADEN,Voice Activity Detector Enable" "0: The HWVAD is disabled,1: The HWVAD is enabled"
group.long 0x94++0x03
line.long 0x00 "VAD0_CTRL_2,Voice Activity Detector Control register"
bitfld.long 0x00 31. "VADFRENDIS,Voice Activity Detector Frame Energy Disable" "0: Frame energy calculus enabled,1: Frame energy calculus disabled"
bitfld.long 0x00 30. "VADPREFEN,Voice Activity Detector Pre Filter Enable" "0: Pre-filter is bypassed,1: Pre-filter is enabled"
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bitfld.long 0x00 28. "VADFOUTDIS,Voice Activity Detector Force Output Disable" "0: Output is enabled,1: Output is disabled"
bitfld.long 0x00 16.--21. "VADFRAMET,Voice Activity Detector Frame Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "VADINPGAIN,Voice Activity Detector Input Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "VADHPF,Voice Activity Detector High-Pass Filter" "0: Filter bypassed,1: Cut-off frequency at 1750Hz,2: Cut-off frequency at 215Hz,3: Cut-off frequency at 102Hz"
group.long 0x98++0x03
line.long 0x00 "VAD0_STAT,Voice Activity Detector Status register"
rbitfld.long 0x00 31. "VADINITF,Voice Activity Detector Initialization Flag" "0: HWVAD is not being initialized,1: HWVAD is being initialized"
eventfld.long 0x00 16. "VADINSATF,Voice Activity Detector Input Saturation Flag" "0: No exception by HWVAD input saturation,1: Exception by HWVAD input saturation"
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rbitfld.long 0x00 15. "VADEF,Voice Activity Detector Event Flag" "0: Voice activity has not been detected by the..,1: Voice activity has been detected by the HWVAD"
eventfld.long 0x00 0. "VADIF,Voice Activity Detector Interrupt Flag" "0: Voice activity has not been detected by the..,1: Voice activity has been detected by the HWVAD"
group.long 0x9C++0x03
line.long 0x00 "VAD0_SCONFIG,Voice Activity Detector Signal Configuration"
bitfld.long 0x00 31. "VADSFILEN,Voice Activity Detector Signal Filter Enable" "0: Signal filter is disabled,1: Signal filter is enabled"
bitfld.long 0x00 30. "VADSMAXEN,Voice Activity Detector Signal Maximum Enable" "0: Maximum block is bypassed,1: Maximum block is enabled"
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bitfld.long 0x00 0.--3. "VADSGAIN,Voice Activity Detector Signal Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x03
line.long 0x00 "VAD0_NCONFIG,Voice Activity Detector Noise Configuration"
bitfld.long 0x00 31. "VADNFILAUTO,Voice Activity Detector Noise Filter Auto" "0: Noise filter is always enabled,1: Noise filter is enabled/disabled based on.."
bitfld.long 0x00 30. "VADNMINEN,Voice Activity Detector Noise Minimum Enable" "0: Minimum block is bypassed,1: Minimum block is enabled"
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bitfld.long 0x00 29. "VADNDECEN,Voice Activity Detector Noise Decimation Enable" "0: Noise input is not decimated,1: Noise input is decimated"
bitfld.long 0x00 28. "VADNOREN,Voice Activity Detector Noise OR Enable" "0: Noise input is not decimated,1: Noise input is decimated"
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bitfld.long 0x00 8.--12. "VADNFILADJ,Voice Activity Detector Noise Filter Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "VADNGAIN,Voice Activity Detector Noise Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xA4++0x03
line.long 0x00 "VAD0_NDATA,Voice Activity Detector Noise Data"
hexmask.long.word 0x00 0.--15. 1. "VADNDATA,Voice Activity Detector Noise Data"
group.long 0xA8++0x03
line.long 0x00 "VAD0_ZCD,Voice Activity Detector Zero-Crossing Detector"
hexmask.long.word 0x00 16.--25. 1. "VADZCDTH,Zero-Crossing Detector Threshold"
bitfld.long 0x00 8.--11. "VADZCDADJ,Zero-Crossing Detector Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4. "VADZCDAND,Zero-Crossing Detector AND Behavior" "0: The ZCD result is OR'ed with the energy-based..,1: The ZCD result is AND'ed with the.."
bitfld.long 0x00 2. "VADZCDAUTO,Zero-Crossing Detector Automatic Threshold" "0: The ZCD threshold is not estimated..,1: The ZCD threshold is estimated automatically"
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bitfld.long 0x00 0. "VADZCDEN,Zero-Crossing Detector Enable" "0: The ZCD is disabled,1: The ZCD is enabled"
tree.end
tree "PHYCONFIGURATION (PHYConfiguration)"
base ad:0x32FDB000
group.byte 0x00++0x00
line.byte 0x00 "phy_conf0,PHY Configuration Register This register holds the power down data enable polarity and interface control of the HDMI Source PHY control"
bitfld.byte 0x00 7. "spares_2,Reserved as spare register with no associated functionality" "0,1"
bitfld.byte 0x00 6. "spares_1,Reserved as spare register with no associated functionality" "0,1"
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bitfld.byte 0x00 5. "sparectrl,Reserved as spare register with no associated functionality" "0,1"
bitfld.byte 0x00 4. "pddq,PHY PDDQ signal" "0,1"
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bitfld.byte 0x00 3. "txpwron,PHY TXPWRON signal" "0,1"
bitfld.byte 0x00 2. "enhpdrxsense,PHY ENHPDRXSENSE signal" "0,1"
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bitfld.byte 0x00 1. "seldataenpol,Select data enable polarity" "0,1"
bitfld.byte 0x00 0. "seldipif,Select interface control" "0,1"
group.byte 0x01++0x00
line.byte 0x00 "phy_tst0,PHY Test Interface Register 0 PHY TX mapped test interface (control)"
bitfld.byte 0x00 6.--7. "spare_2,Reserved as spare bit with no associated functionality" "0,1,2,3"
bitfld.byte 0x00 5. "spare_4,Reserved as spare register with no associated functionality" "0,1"
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bitfld.byte 0x00 4. "spare_3,Reserved as spare register with no associated functionality" "0,1"
bitfld.byte 0x00 1.--3. "spare_1,Reserved as spare bit with no associated functionality" "0,1,2,3,4,5,6,7"
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bitfld.byte 0x00 0. "spare_0,Reserved as spare register with no associated functionality" "0,1"
group.byte 0x02++0x00
line.byte 0x00 "phy_tst1,PHY Test Interface Register 1 PHY TX mapped text interface (data in)"
hexmask.byte 0x00 0.--7. 1. "spare,Reserved as spare register with no associated functionality"
rgroup.byte 0x03++0x00
line.byte 0x00 "phy_tst2,PHY Test Interface Register 2 PHY TX mapped text interface (data out)"
hexmask.byte 0x00 0.--7. 1. "spare,Reserved as spare register with no associated functionality"
rgroup.byte 0x04++0x00
line.byte 0x00 "phy_stat0,PHY RXSENSE PLL Lock and HPD Status Register This register contains the following active high packet sent status indications"
bitfld.byte 0x00 7. "RX_SENSE_3,Status bit" "0,1"
bitfld.byte 0x00 6. "RX_SENSE_2,Status bit" "0,1"
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bitfld.byte 0x00 5. "RX_SENSE_1,Status bit" "0,1"
bitfld.byte 0x00 4. "RX_SENSE_0,Status bit" "0,1"
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bitfld.byte 0x00 1. "HPD,Status bit" "0,1"
bitfld.byte 0x00 0. "TX_PHY_LOCK,Status bit" "0,1"
rgroup.byte 0x05++0x00
line.byte 0x00 "phy_int0,PHY RXSENSE PLL Lock and HPD Interrupt Register This register contains the interrupt indication of the PHY_STAT0 status interrupts"
bitfld.byte 0x00 7. "RX_SENSE_3,Interrupt indication bit" "0,1"
bitfld.byte 0x00 6. "RX_SENSE_2,Interrupt indication bit" "0,1"
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bitfld.byte 0x00 5. "RX_SENSE_1,Interrupt indication bit" "0,1"
bitfld.byte 0x00 4. "RX_SENSE_0,Interrupt indication bit" "0,1"
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bitfld.byte 0x00 1. "HPD,Interrupt indication bit" "0,1"
bitfld.byte 0x00 0. "TX_PHY_LOCK,Interrupt indication bit" "0,1"
group.byte 0x06++0x00
line.byte 0x00 "phy_mask0,PHY RXSENSE PLL Lock and HPD Mask Register Mask register for generation of PHY_INT0 interrupts"
bitfld.byte 0x00 7. "RX_SENSE_3,Mask bit for PHY_INT0" "0,1"
bitfld.byte 0x00 6. "RX_SENSE_2,Mask bit for PHY_INT0" "0,1"
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bitfld.byte 0x00 5. "RX_SENSE_1,Mask bit for PHY_INT0" "0,1"
bitfld.byte 0x00 4. "RX_SENSE_0,Mask bit for PHY_INT0" "0,1"
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bitfld.byte 0x00 1. "HPD,Mask bit for PHY_INT0" "0,1"
bitfld.byte 0x00 0. "TX_PHY_LOCK,Mask bit for PHY_INT0" "0,1"
group.byte 0x07++0x00
line.byte 0x00 "phy_pol0,PHY RXSENSE PLL Lock and HPD Polarity Register Polarity register for generation of PHY_INT0 interrupts"
bitfld.byte 0x00 7. "RX_SENSE_3,Polarity bit for PHY_INT0" "0,1"
bitfld.byte 0x00 6. "RX_SENSE_2,Polarity bit for PHY_INT0" "0,1"
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bitfld.byte 0x00 5. "RX_SENSE_1,Polarity bit for PHY_INT0" "0,1"
bitfld.byte 0x00 4. "RX_SENSE_0,Polarity bit for PHY_INT0" "0,1"
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bitfld.byte 0x00 1. "HPD,Polarity bit for PHY_INT0" "0,1"
bitfld.byte 0x00 0. "TX_PHY_LOCK,Polarity bit for PHY_INT0" "0,1"
group.byte 0x20++0x00
line.byte 0x00 "phy_i2cm_slave,PHY I2C Slave Address Configuration Register"
hexmask.byte 0x00 0.--6. 1. "slaveaddr,Slave address to be sent during read and write operations"
group.byte 0x21++0x00
line.byte 0x00 "phy_i2cm_address,PHY I2C Address Configuration Register This register writes the address for read and write operations"
hexmask.byte 0x00 0.--7. 1. "address,Register address for read and write operations"
group.byte 0x22++0x00
line.byte 0x00 "phy_i2cm_datao_1,PHY I2C Data Write Register 1"
hexmask.byte 0x00 0.--7. 1. "datao,Data MSB (datao[15:8]) to be written on register pointed by phy_i2cm_address [7:0]"
group.byte 0x23++0x00
line.byte 0x00 "phy_i2cm_datao_0,PHY I2C Data Write Register 0"
hexmask.byte 0x00 0.--7. 1. "datao,Data LSB (datao[7:0]) to be written on register pointed by phy_i2cm_address [7:0]"
rgroup.byte 0x24++0x00
line.byte 0x00 "phy_i2cm_datai_1,PHY I2C Data Read Register 1"
hexmask.byte 0x00 0.--7. 1. "datai,Data MSB (datai[15:8]) read from register pointed by phy_i2cm_address[7:0]"
rgroup.byte 0x25++0x00
line.byte 0x00 "phy_i2cm_datai_0,PHY I2C Data Read Register 0"
hexmask.byte 0x00 0.--7. 1. "datai,Data LSB (datai[7:0]) read from register pointed by phy_i2cm_address[7:0]"
wgroup.byte 0x26++0x00
line.byte 0x00 "phy_i2cm_operation,PHY I2C RD/RD_EXT/WR Operation Register This register requests read and write operations from the I2C Master PHY"
bitfld.byte 0x00 4. "wr,Write operation request" "0,1"
bitfld.byte 0x00 0. "rd,Read operation request" "0,1"
group.byte 0x27++0x00
line.byte 0x00 "phy_i2cm_int,PHY I2C Done Interrupt Register This register contains and configures I2C master PHY done interrupt"
bitfld.byte 0x00 3. "done_pol,Done interrupt polarity configuration" "0,1"
bitfld.byte 0x00 2. "done_mask,Done interrupt mask signal" "0,1"
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rbitfld.byte 0x00 1. "done_interrupt,Operation done interrupt bit" "0,1"
rbitfld.byte 0x00 0. "done_status,Operation done status bit" "0,1"
group.byte 0x28++0x00
line.byte 0x00 "phy_i2cm_ctlint,PHY I2C error Interrupt Register This register contains and configures the I2C master PHY error interrupts"
bitfld.byte 0x00 7. "nack_pol,Not acknowledge error interrupt polarity configuration" "0,1"
bitfld.byte 0x00 6. "nack_mask,Not acknowledge error interrupt mask signal" "0,1"
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rbitfld.byte 0x00 5. "nack_interrupt,Not acknowledge error interrupt bit" "0,1"
rbitfld.byte 0x00 4. "nack_status,Not acknowledge error status bit" "0,1"
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bitfld.byte 0x00 3. "arbitration_pol,Arbitration error interrupt polarity configuration" "0,1"
bitfld.byte 0x00 2. "arbitration_mask,Arbitration error interrupt mask signal" "0,1"
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rbitfld.byte 0x00 1. "arbitration_interrupt,Arbitration error interrupt bit {arbitration_interrupt = (arbitration_mask==0b) && (arbitration_status==arbitration_pol)} Note: This bit field is read by the sticky bits present on the ih_i2cmphy_stat0 register" "0,1"
rbitfld.byte 0x00 0. "arbitration_status,Arbitration error status bit" "0,1"
group.byte 0x29++0x00
line.byte 0x00 "phy_i2cm_div,PHY I2C Speed control Register This register wets the I2C Master PHY to work in either Fast or Standard mode"
bitfld.byte 0x00 3. "fast_std_mode,Sets the I2C Master to work in Fast Mode or Standard Mode" "0: Standard Mode,1: Fast Mode"
bitfld.byte 0x00 0.--2. "spare,Reserved as spare register with no associated functionality" "0,1,2,3,4,5,6,7"
group.byte 0x2A++0x00
line.byte 0x00 "phy_i2cm_softrstz,PHY I2C SW reset control register This register sets the I2C Master PHY software reset"
bitfld.byte 0x00 0. "i2c_softrstz,I2C Master Software Reset" "0,1"
group.byte 0x2B++0x00
line.byte 0x00 "phy_i2cm_ss_scl_hcnt_1_addr,PHY I2C Slow Speed SCL High Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_hcnt1,PHY I2C Slow Speed SCL High Level Control Register 1"
group.byte 0x2C++0x00
line.byte 0x00 "phy_i2cm_ss_scl_hcnt_0_addr,PHY I2C Slow Speed SCL High Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_hcnt0,PHY I2C Slow Speed SCL High Level Control Register 0"
group.byte 0x2D++0x00
line.byte 0x00 "phy_i2cm_ss_scl_lcnt_1_addr,PHY I2C Slow Speed SCL Low Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_lcnt1,PHY I2C Slow Speed SCL Low Level Control Register 1"
group.byte 0x2E++0x00
line.byte 0x00 "phy_i2cm_ss_scl_lcnt_0_addr,PHY I2C Slow Speed SCL Low Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_ss_scl_lcnt0,PHY I2C Slow Speed SCL Low Level Control Register 0"
group.byte 0x2F++0x00
line.byte 0x00 "phy_i2cm_fs_scl_hcnt_1_addr,PHY I2C Fast Speed SCL High Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_hcnt1,PHY I2C Fast Speed SCL High Level Control Register 1"
group.byte 0x30++0x00
line.byte 0x00 "phy_i2cm_fs_scl_hcnt_0_addr,PHY I2C Fast Speed SCL High Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_hcnt0,PHY I2C Fast Speed SCL High Level Control Register 0"
group.byte 0x31++0x00
line.byte 0x00 "phy_i2cm_fs_scl_lcnt_1_addr,PHY I2C Fast Speed SCL Low Level Control Register 1"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_lcnt1,PHY I2C Fast Speed SCL Low Level Control Register 1"
group.byte 0x32++0x00
line.byte 0x00 "phy_i2cm_fs_scl_lcnt_0_addr,PHY I2C Fast Speed SCL Low Level Control Register 0"
hexmask.byte 0x00 0.--7. 1. "i2cmp_fs_scl_lcnt0,PHY I2C Fast Speed SCL Low Level Control Register 0"
group.byte 0x33++0x00
line.byte 0x00 "phy_i2cm_sda_hold,PHY I2C SDA HOLD Control Register"
hexmask.byte 0x00 0.--7. 1. "osda_hold,Defines the number of SFR clock cycles to meet tHD:DAT (300 ns) osda_hold = round_to_high_integer (300 ns / (1/isfrclk_frequency))"
group.byte 0x34++0x00
line.byte 0x00 "jtag_phy_config,PHY I2C/JTAG I/O Configuration Control Register"
bitfld.byte 0x00 4. "i2c_jtagz,Configures the JTAG PHY interface output pin I2C_JTAGZ to select the PHY configuration interface when in internal control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_i2c_jtagz when PHY_EXTERNAL=1" "0,1"
bitfld.byte 0x00 0. "jtag_trst_n,Configures the JTAG PHY interface output pin JTAG_TRST_N when in internal control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_trst_n when PHY_EXTERNAL=1" "0,1"
group.byte 0x35++0x00
line.byte 0x00 "jtag_phy_tap_tck,PHY JTAG Clock Control Register"
bitfld.byte 0x00 0. "jtag_tck,Configures the JTAG PHY interface pin JTAG_TCK when in internal control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_tck when PHY_EXTERNAL=1" "0,1"
group.byte 0x36++0x00
line.byte 0x00 "jtag_phy_tap_in,PHY JTAG TAP In Control Register"
bitfld.byte 0x00 4. "jtag_tms,Configures the JTAG PHY interface pin JTAG_TMS when in internal control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_tms when PHY_EXTERNAL=1" "0,1"
bitfld.byte 0x00 0. "jtag_tdi,Configures the JTAG PHY interface pin JTAG_TDI when in internal control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_tdi when PHY_EXTERNAL=1" "0,1"
rgroup.byte 0x37++0x00
line.byte 0x00 "jtag_phy_tap_out,PHY JTAG TAP Out Control Register"
bitfld.byte 0x00 4. "jtag_tdo_en,Read JTAG PHY interface input pin JTAG_TDO_EN when in internal control mode (iphy_ext_ctrl=1'b0) or iphyext_jtag_tdo_en when PHY_EXTERNAL=1" "0,1"
bitfld.byte 0x00 0. "jtag_tdo,Read JTAG PHY interface input pin JTAG_TDO when in internal control mode (iphy_ext_ctrl=1'b0) or iphyext_jtag_tdo when PHY_EXTERNAL=1" "0,1"
group.byte 0x38++0x00
line.byte 0x00 "jtag_phy_addr,PHY JTAG Address Control Register"
hexmask.byte 0x00 0.--7. 1. "jtag_addr,Configures the JTAG PHY interface pin JTAG_ADDR[7:0] when in internal control mode (iphy_ext_ctrl=1'b0) or iphyext_jtag_addr[7:0] when PHY_EXTERNAL=1"
tree.end
tree "PWM (Pulse-Width Modulator)"
repeat 4. (list 1. 2. 3. 4.) (list ad:0x30660000 ad:0x30670000 ad:0x30680000 ad:0x30690000)
tree "PWM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "PWMCR,PWM Control Register"
bitfld.long 0x00 26.--27. "FWM,FIFO Water Mark" "0: FIFO empty flag is set when there are more..,1: FIFO empty flag is set when there are more..,2: FIFO empty flag is set when there are more..,3: FIFO empty flag is set when there are more.."
bitfld.long 0x00 25. "STOPEN,Stop Mode Enable" "0: Inactive in stop mode,1: Active in stop mode"
newline
bitfld.long 0x00 24. "DOZEN,Doze Mode Enable" "0: Inactive in doze mode,1: Active in doze mode"
bitfld.long 0x00 23. "WAITEN,Wait Mode Enable" "0: Inactive in wait mode,1: Active in wait mode"
newline
bitfld.long 0x00 22. "DBGEN,Debug Mode Enable" "0: Inactive in debug mode,1: Active in debug mode"
bitfld.long 0x00 21. "BCTR,Byte Data Swap Control" "0: byte ordering remains the same,1: byte ordering is reversed"
newline
bitfld.long 0x00 20. "HCTR,Half-word Data Swap Control" "0: Half word swapping does not take place,1: Half words from write data bus are swapped"
bitfld.long 0x00 18.--19. "POUTC,PWM Output Configuration" "0: Output pin is set at rollover and cleared at..,1: Output pin is cleared at rollover and set at..,2: PWM output is disconnected,3: PWM output is disconnected"
newline
bitfld.long 0x00 16.--17. "CLKSRC,Select Clock Source" "0: Clock is off,1: CLKSRC_1,2: ipg_clk_highfreq,3: ipg_clk_32k"
hexmask.long.word 0x00 4.--15. 1. "PRESCALER,Counter Clock Prescaler Value"
newline
bitfld.long 0x00 3. "SWR,Software Reset" "0: PWM is out of reset,1: PWM is undergoing reset"
bitfld.long 0x00 1.--2. "REPEAT,Sample Repeat" "0: Use each sample once,1: Use each sample twice,2: Use each sample four times,3: Use each sample eight times"
newline
bitfld.long 0x00 0. "EN,PWM Enable" "0: PWM disabled,1: PWM enabled"
group.long 0x04++0x03
line.long 0x00 "PWMSR,PWM Status Register"
eventfld.long 0x00 6. "FWE,FIFO Write Error Status" "0: FIFO write error not occurred,1: FIFO write error occurred"
eventfld.long 0x00 5. "CMP,Compare Status" "0: Compare event not occurred,1: Compare event occurred"
newline
eventfld.long 0x00 4. "ROV,Roll-over Status" "0: Roll-over event not occurred,1: Roll-over event occurred"
eventfld.long 0x00 3. "FE,FIFO Empty Status Bit" "0: Data level is above water mark,1: When the data level falls below the mark set.."
newline
rbitfld.long 0x00 0.--2. "FIFOAV,FIFO Available" "0: No data available,1: 1 word of data in FIFO,2: 2 words of data in FIFO,3: 3 words of data in FIFO,4: 4 words of data in FIFO,5: FIFOAV_5,6: FIFOAV_6,7: FIFOAV_7"
group.long 0x08++0x03
line.long 0x00 "PWMIR,PWM Interrupt Register"
bitfld.long 0x00 2. "CIE,Compare Interrupt Enable" "0: Compare Interrupt not enabled,1: Compare Interrupt enabled"
bitfld.long 0x00 1. "RIE,Roll-over Interrupt Enable" "0: Roll-over interrupt not enabled,1: Roll-over Interrupt enabled"
newline
bitfld.long 0x00 0. "FIE,FIFO Empty Interrupt Enable" "0: FIFO Empty interrupt disabled,1: FIFO Empty interrupt enabled"
group.long 0x0C++0x03
line.long 0x00 "PWMSAR,PWM Sample Register"
hexmask.long.word 0x00 0.--15. 1. "SAMPLE,Sample Value"
group.long 0x10++0x03
line.long 0x00 "PWMPR,PWM Period Register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period Value"
rgroup.long 0x14++0x03
line.long 0x00 "PWMCNR,PWM Counter Register"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
tree.end
repeat.end
tree.end
tree "RDC"
base ad:0x303D0000
rgroup.long 0x00++0x03
line.long 0x00 "VIR,Version Information"
hexmask.long.byte 0x00 20.--27. 1. "NRGN,Number of Memory Regions"
hexmask.long.byte 0x00 12.--19. 1. "NPER,Number of Peripherals"
newline
hexmask.long.byte 0x00 4.--11. 1. "NMSTR,Number of Masters"
bitfld.long 0x00 0.--3. "NDID,Number of Domains" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "STAT,Status"
bitfld.long 0x00 8. "PDS,Power Domain Status" "0: Power Down Domain is OFF,1: Power Down Domain is ON"
bitfld.long 0x00 0.--3. "DID,Domain ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x03
line.long 0x00 "INTCTRL,Interrupt and Control"
bitfld.long 0x00 0. "RCI_EN,Restoration Complete Interrupt" "0: Interrupt Disabled,1: Interrupt Enabled"
group.long 0x2C++0x03
line.long 0x00 "INTSTAT,Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Status" "0: No Interrupt Pending,1: Interrupt Pending"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "MDA$1,Master Domain Assignment"
bitfld.long 0x00 31. "LCK,Assignment Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 0.--1. "DID,Domain ID" "0: Master assigned to Processing Domain 0,1: Master assigned to Processing Domain 1,2: Master assigned to Processing Domain 2,3: Master assigned to Processing Domain 3"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "MDA$1,Master Domain Assignment"
bitfld.long 0x00 31. "LCK,Assignment Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 0.--1. "DID,Domain ID" "0: Master assigned to Processing Domain 0,1: Master assigned to Processing Domain 1,2: Master assigned to Processing Domain 2,3: Master assigned to Processing Domain 3"
repeat.end
repeat 8. (strings "32" "33" "34" "35" "36" "37" "38" "39" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x280)++0x03
line.long 0x00 "MDA$1,Master Domain Assignment"
bitfld.long 0x00 31. "LCK,Assignment Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 0.--1. "DID,Domain ID" "0: Master assigned to Processing Domain 0,1: Master assigned to Processing Domain 1,2: Master assigned to Processing Domain 2,3: Master assigned to Processing Domain 3"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "PDAP$1,Peripheral Domain Access Permissions"
bitfld.long 0x00 31. "LCK,Peripheral Permissions Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 30. "SREQ,Semaphore Required" "0: Semaphores have no effect,1: Semaphores are enforced"
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 6. "D3W,Domain 3 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 4. "D2W,Domain 2 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 2. "D1W,Domain 1 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 0. "D0W,Domain 0 Write Access" "0: No Write Access,1: Write Access Allowed"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x440)++0x03
line.long 0x00 "PDAP$1,Peripheral Domain Access Permissions"
bitfld.long 0x00 31. "LCK,Peripheral Permissions Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 30. "SREQ,Semaphore Required" "0: Semaphores have no effect,1: Semaphores are enforced"
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 6. "D3W,Domain 3 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 4. "D2W,Domain 2 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 2. "D1W,Domain 1 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 0. "D0W,Domain 0 Write Access" "0: No Write Access,1: Write Access Allowed"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x480)++0x03
line.long 0x00 "PDAP$1,Peripheral Domain Access Permissions"
bitfld.long 0x00 31. "LCK,Peripheral Permissions Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 30. "SREQ,Semaphore Required" "0: Semaphores have no effect,1: Semaphores are enforced"
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 6. "D3W,Domain 3 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 4. "D2W,Domain 2 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 2. "D1W,Domain 1 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 0. "D0W,Domain 0 Write Access" "0: No Write Access,1: Write Access Allowed"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x4C0)++0x03
line.long 0x00 "PDAP$1,Peripheral Domain Access Permissions"
bitfld.long 0x00 31. "LCK,Peripheral Permissions Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 30. "SREQ,Semaphore Required" "0: Semaphores have no effect,1: Semaphores are enforced"
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 6. "D3W,Domain 3 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 4. "D2W,Domain 2 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 2. "D1W,Domain 1 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 0. "D0W,Domain 0 Write Access" "0: No Write Access,1: Write Access Allowed"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x500)++0x03
line.long 0x00 "PDAP$1,Peripheral Domain Access Permissions"
bitfld.long 0x00 31. "LCK,Peripheral Permissions Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 30. "SREQ,Semaphore Required" "0: Semaphores have no effect,1: Semaphores are enforced"
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 6. "D3W,Domain 3 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 4. "D2W,Domain 2 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 2. "D1W,Domain 1 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 0. "D0W,Domain 0 Write Access" "0: No Write Access,1: Write Access Allowed"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x540)++0x03
line.long 0x00 "PDAP$1,Peripheral Domain Access Permissions"
bitfld.long 0x00 31. "LCK,Peripheral Permissions Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 30. "SREQ,Semaphore Required" "0: Semaphores have no effect,1: Semaphores are enforced"
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 6. "D3W,Domain 3 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 4. "D2W,Domain 2 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 2. "D1W,Domain 1 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 0. "D0W,Domain 0 Write Access" "0: No Write Access,1: Write Access Allowed"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x580)++0x03
line.long 0x00 "PDAP$1,Peripheral Domain Access Permissions"
bitfld.long 0x00 31. "LCK,Peripheral Permissions Lock" "0: Not Locked,1: Locked"
bitfld.long 0x00 30. "SREQ,Semaphore Required" "0: Semaphores have no effect,1: Semaphores are enforced"
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 6. "D3W,Domain 3 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 4. "D2W,Domain 2 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 2. "D1W,Domain 1 Write Access" "0: No Write Access,1: Write Access Allowed"
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access" "0: No Read Access,1: Read Access Allowed"
bitfld.long 0x00 0. "D0W,Domain 0 Write Access" "0: No Write Access,1: Write Access Allowed"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x800)++0x03
line.long 0x00 "MRSA$1,Memory Region Start Address"
hexmask.long 0x00 7.--31. 1. "SADR,Start address for memory region"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x900)++0x03
line.long 0x00 "MRSA$1,Memory Region Start Address"
hexmask.long 0x00 7.--31. 1. "SADR,Start address for memory region"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xA00)++0x03
line.long 0x00 "MRSA$1,Memory Region Start Address"
hexmask.long 0x00 7.--31. 1. "SADR,Start address for memory region"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xB00)++0x03
line.long 0x00 "MRSA$1,Memory Region Start Address"
hexmask.long 0x00 7.--31. 1. "SADR,Start address for memory region"
repeat.end
repeat 13. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 )
group.long ($2+0xC00)++0x03
line.long 0x00 "MRSA$1,Memory Region Start Address"
hexmask.long 0x00 7.--31. 1. "SADR,Start address for memory region"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x804)++0x03
line.long 0x00 "MREA$1,Memory Region End Address"
hexmask.long 0x00 7.--31. 1. "EADR,Upper bound for memory region"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x904)++0x03
line.long 0x00 "MREA$1,Memory Region End Address"
hexmask.long 0x00 7.--31. 1. "EADR,Upper bound for memory region"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xA04)++0x03
line.long 0x00 "MREA$1,Memory Region End Address"
hexmask.long 0x00 7.--31. 1. "EADR,Upper bound for memory region"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xB04)++0x03
line.long 0x00 "MREA$1,Memory Region End Address"
hexmask.long 0x00 7.--31. 1. "EADR,Upper bound for memory region"
repeat.end
repeat 13. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 )
group.long ($2+0xC04)++0x03
line.long 0x00 "MREA$1,Memory Region End Address"
hexmask.long 0x00 7.--31. 1. "EADR,Upper bound for memory region"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x808)++0x03
line.long 0x00 "MRC$1,Memory Region Control"
bitfld.long 0x00 31. "LCK,Region Lock" "0: No Lock,1: Locked"
bitfld.long 0x00 30. "ENA,Region Enable" "0: Memory region is not defined or restricted,1: Memory boundaries domain permissions and.."
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access to Region" "0: Processing Domain 3 does not have Read access..,1: Processing Domain 3 has Read access to the.."
bitfld.long 0x00 6. "D3W,Domain 3 Write Access to Region" "0: Processing Domain 3 does not have Write..,1: Processing Domain 3 has Read access to the.."
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access to Region" "0: Processing Domain 2 does not have Read access..,1: Processing Domain 2 has Read access to the.."
bitfld.long 0x00 4. "D2W,Domain 2 Write Access to Region" "0: Processing Domain 2 does not have Write..,1: Processing Domain 2 has Write access to the.."
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access to Region" "0: Processing Domain 1 does not have Read access..,1: Processing Domain 1 has Read access to the.."
bitfld.long 0x00 2. "D1W,Domain 1 Write Access to Region" "0: Processing Domain 1 does not have Write..,1: Processing Domain 1 has Write access to the.."
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access to Region" "0: Processing Domain 0 does not have Read access..,1: Processing Domain 0 has Read access to the.."
bitfld.long 0x00 0. "D0W,Domain 0 Write Access to Region" "0: Processing Domain 0 does not have Write..,1: Processing Domain 0 has Write access to the.."
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x908)++0x03
line.long 0x00 "MRC$1,Memory Region Control"
bitfld.long 0x00 31. "LCK,Region Lock" "0: No Lock,1: Locked"
bitfld.long 0x00 30. "ENA,Region Enable" "0: Memory region is not defined or restricted,1: Memory boundaries domain permissions and.."
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access to Region" "0: Processing Domain 3 does not have Read access..,1: Processing Domain 3 has Read access to the.."
bitfld.long 0x00 6. "D3W,Domain 3 Write Access to Region" "0: Processing Domain 3 does not have Write..,1: Processing Domain 3 has Read access to the.."
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access to Region" "0: Processing Domain 2 does not have Read access..,1: Processing Domain 2 has Read access to the.."
bitfld.long 0x00 4. "D2W,Domain 2 Write Access to Region" "0: Processing Domain 2 does not have Write..,1: Processing Domain 2 has Write access to the.."
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access to Region" "0: Processing Domain 1 does not have Read access..,1: Processing Domain 1 has Read access to the.."
bitfld.long 0x00 2. "D1W,Domain 1 Write Access to Region" "0: Processing Domain 1 does not have Write..,1: Processing Domain 1 has Write access to the.."
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access to Region" "0: Processing Domain 0 does not have Read access..,1: Processing Domain 0 has Read access to the.."
bitfld.long 0x00 0. "D0W,Domain 0 Write Access to Region" "0: Processing Domain 0 does not have Write..,1: Processing Domain 0 has Write access to the.."
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xA08)++0x03
line.long 0x00 "MRC$1,Memory Region Control"
bitfld.long 0x00 31. "LCK,Region Lock" "0: No Lock,1: Locked"
bitfld.long 0x00 30. "ENA,Region Enable" "0: Memory region is not defined or restricted,1: Memory boundaries domain permissions and.."
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access to Region" "0: Processing Domain 3 does not have Read access..,1: Processing Domain 3 has Read access to the.."
bitfld.long 0x00 6. "D3W,Domain 3 Write Access to Region" "0: Processing Domain 3 does not have Write..,1: Processing Domain 3 has Read access to the.."
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access to Region" "0: Processing Domain 2 does not have Read access..,1: Processing Domain 2 has Read access to the.."
bitfld.long 0x00 4. "D2W,Domain 2 Write Access to Region" "0: Processing Domain 2 does not have Write..,1: Processing Domain 2 has Write access to the.."
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access to Region" "0: Processing Domain 1 does not have Read access..,1: Processing Domain 1 has Read access to the.."
bitfld.long 0x00 2. "D1W,Domain 1 Write Access to Region" "0: Processing Domain 1 does not have Write..,1: Processing Domain 1 has Write access to the.."
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access to Region" "0: Processing Domain 0 does not have Read access..,1: Processing Domain 0 has Read access to the.."
bitfld.long 0x00 0. "D0W,Domain 0 Write Access to Region" "0: Processing Domain 0 does not have Write..,1: Processing Domain 0 has Write access to the.."
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xB08)++0x03
line.long 0x00 "MRC$1,Memory Region Control"
bitfld.long 0x00 31. "LCK,Region Lock" "0: No Lock,1: Locked"
bitfld.long 0x00 30. "ENA,Region Enable" "0: Memory region is not defined or restricted,1: Memory boundaries domain permissions and.."
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access to Region" "0: Processing Domain 3 does not have Read access..,1: Processing Domain 3 has Read access to the.."
bitfld.long 0x00 6. "D3W,Domain 3 Write Access to Region" "0: Processing Domain 3 does not have Write..,1: Processing Domain 3 has Read access to the.."
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access to Region" "0: Processing Domain 2 does not have Read access..,1: Processing Domain 2 has Read access to the.."
bitfld.long 0x00 4. "D2W,Domain 2 Write Access to Region" "0: Processing Domain 2 does not have Write..,1: Processing Domain 2 has Write access to the.."
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access to Region" "0: Processing Domain 1 does not have Read access..,1: Processing Domain 1 has Read access to the.."
bitfld.long 0x00 2. "D1W,Domain 1 Write Access to Region" "0: Processing Domain 1 does not have Write..,1: Processing Domain 1 has Write access to the.."
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access to Region" "0: Processing Domain 0 does not have Read access..,1: Processing Domain 0 has Read access to the.."
bitfld.long 0x00 0. "D0W,Domain 0 Write Access to Region" "0: Processing Domain 0 does not have Write..,1: Processing Domain 0 has Write access to the.."
repeat.end
repeat 13. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 )
group.long ($2+0xC08)++0x03
line.long 0x00 "MRC$1,Memory Region Control"
bitfld.long 0x00 31. "LCK,Region Lock" "0: No Lock,1: Locked"
bitfld.long 0x00 30. "ENA,Region Enable" "0: Memory region is not defined or restricted,1: Memory boundaries domain permissions and.."
newline
bitfld.long 0x00 7. "D3R,Domain 3 Read Access to Region" "0: Processing Domain 3 does not have Read access..,1: Processing Domain 3 has Read access to the.."
bitfld.long 0x00 6. "D3W,Domain 3 Write Access to Region" "0: Processing Domain 3 does not have Write..,1: Processing Domain 3 has Read access to the.."
newline
bitfld.long 0x00 5. "D2R,Domain 2 Read Access to Region" "0: Processing Domain 2 does not have Read access..,1: Processing Domain 2 has Read access to the.."
bitfld.long 0x00 4. "D2W,Domain 2 Write Access to Region" "0: Processing Domain 2 does not have Write..,1: Processing Domain 2 has Write access to the.."
newline
bitfld.long 0x00 3. "D1R,Domain 1 Read Access to Region" "0: Processing Domain 1 does not have Read access..,1: Processing Domain 1 has Read access to the.."
bitfld.long 0x00 2. "D1W,Domain 1 Write Access to Region" "0: Processing Domain 1 does not have Write..,1: Processing Domain 1 has Write access to the.."
newline
bitfld.long 0x00 1. "D0R,Domain 0 Read Access to Region" "0: Processing Domain 0 does not have Read access..,1: Processing Domain 0 has Read access to the.."
bitfld.long 0x00 0. "D0W,Domain 0 Write Access to Region" "0: Processing Domain 0 does not have Write..,1: Processing Domain 0 has Write access to the.."
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x80C)++0x03
line.long 0x00 "MRVS$1,Memory Region Violation Status"
hexmask.long 0x00 5.--31. 1. "VADR,Violating Address"
eventfld.long 0x00 4. "AD,Access Denied" "0,1"
newline
rbitfld.long 0x00 0.--1. "VDID,Violating Domain ID" "0: Processing Domain 0,1: Processing Domain 1,2: Processing Domain 2,3: Processing Domain 3"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0x90C)++0x03
line.long 0x00 "MRVS$1,Memory Region Violation Status"
hexmask.long 0x00 5.--31. 1. "VADR,Violating Address"
eventfld.long 0x00 4. "AD,Access Denied" "0,1"
newline
rbitfld.long 0x00 0.--1. "VDID,Violating Domain ID" "0: Processing Domain 0,1: Processing Domain 1,2: Processing Domain 2,3: Processing Domain 3"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xA0C)++0x03
line.long 0x00 "MRVS$1,Memory Region Violation Status"
hexmask.long 0x00 5.--31. 1. "VADR,Violating Address"
eventfld.long 0x00 4. "AD,Access Denied" "0,1"
newline
rbitfld.long 0x00 0.--1. "VDID,Violating Domain ID" "0: Processing Domain 0,1: Processing Domain 1,2: Processing Domain 2,3: Processing Domain 3"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 )
group.long ($2+0xB0C)++0x03
line.long 0x00 "MRVS$1,Memory Region Violation Status"
hexmask.long 0x00 5.--31. 1. "VADR,Violating Address"
eventfld.long 0x00 4. "AD,Access Denied" "0,1"
newline
rbitfld.long 0x00 0.--1. "VDID,Violating Domain ID" "0: Processing Domain 0,1: Processing Domain 1,2: Processing Domain 2,3: Processing Domain 3"
repeat.end
repeat 13. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" )(list 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 )
group.long ($2+0xC0C)++0x03
line.long 0x00 "MRVS$1,Memory Region Violation Status"
hexmask.long 0x00 5.--31. 1. "VADR,Violating Address"
eventfld.long 0x00 4. "AD,Access Denied" "0,1"
newline
rbitfld.long 0x00 0.--1. "VDID,Violating Domain ID" "0: Processing Domain 0,1: Processing Domain 1,2: Processing Domain 2,3: Processing Domain 3"
repeat.end
tree.end
tree "RDC_SEMAPHORE (Resources Domain Controller Semaphore)"
repeat 2. (list 1. 2.) (list ad:0x303B0000 ad:0x303C0000)
tree "RDC_SEMAPHORE$1"
base $2
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "GATE$1,Gate Register"
rbitfld.byte 0x00 4.--5. "LDOM,Read-only bits" "0: The gate is locked by domain 0,1: The gate has been locked by domain 1,2: The gate has been locked by domain 2,3: The gate has been locked by domain 3"
bitfld.byte 0x00 0.--3. "GTFSM,Gate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor with..,2: The gate has been locked by processor with..,3: The gate has been locked by processor with..,4: The gate has been locked by processor with..,5: The gate has been locked by processor with..,6: The gate has been locked by processor with..,7: The gate has been locked by processor with..,8: The gate has been locked by processor with..,9: The gate has been locked by processor with..,10: The gate has been locked by processor with..,11: The gate has been locked by processor with..,12: The gate has been locked by processor with..,13: The gate has been locked by processor with..,14: The gate has been locked by processor with..,15: The gate has been locked by processor with.."
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "GATE$1,Gate Register"
rbitfld.byte 0x00 4.--5. "LDOM,Read-only bits" "0: The gate is locked by domain 0,1: The gate has been locked by domain 1,2: The gate has been locked by domain 2,3: The gate has been locked by domain 3"
bitfld.byte 0x00 0.--3. "GTFSM,Gate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor with..,2: The gate has been locked by processor with..,3: The gate has been locked by processor with..,4: The gate has been locked by processor with..,5: The gate has been locked by processor with..,6: The gate has been locked by processor with..,7: The gate has been locked by processor with..,8: The gate has been locked by processor with..,9: The gate has been locked by processor with..,10: The gate has been locked by processor with..,11: The gate has been locked by processor with..,12: The gate has been locked by processor with..,13: The gate has been locked by processor with..,14: The gate has been locked by processor with..,15: The gate has been locked by processor with.."
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x20)++0x00
line.byte 0x00 "GATE$1,Gate Register"
rbitfld.byte 0x00 4.--5. "LDOM,Read-only bits" "0: The gate is locked by domain 0,1: The gate has been locked by domain 1,2: The gate has been locked by domain 2,3: The gate has been locked by domain 3"
bitfld.byte 0x00 0.--3. "GTFSM,Gate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor with..,2: The gate has been locked by processor with..,3: The gate has been locked by processor with..,4: The gate has been locked by processor with..,5: The gate has been locked by processor with..,6: The gate has been locked by processor with..,7: The gate has been locked by processor with..,8: The gate has been locked by processor with..,9: The gate has been locked by processor with..,10: The gate has been locked by processor with..,11: The gate has been locked by processor with..,12: The gate has been locked by processor with..,13: The gate has been locked by processor with..,14: The gate has been locked by processor with..,15: The gate has been locked by processor with.."
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x30)++0x00
line.byte 0x00 "GATE$1,Gate Register"
rbitfld.byte 0x00 4.--5. "LDOM,Read-only bits" "0: The gate is locked by domain 0,1: The gate has been locked by domain 1,2: The gate has been locked by domain 2,3: The gate has been locked by domain 3"
bitfld.byte 0x00 0.--3. "GTFSM,Gate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor with..,2: The gate has been locked by processor with..,3: The gate has been locked by processor with..,4: The gate has been locked by processor with..,5: The gate has been locked by processor with..,6: The gate has been locked by processor with..,7: The gate has been locked by processor with..,8: The gate has been locked by processor with..,9: The gate has been locked by processor with..,10: The gate has been locked by processor with..,11: The gate has been locked by processor with..,12: The gate has been locked by processor with..,13: The gate has been locked by processor with..,14: The gate has been locked by processor with..,15: The gate has been locked by processor with.."
repeat.end
group.word 0x42++0x01
line.word 0x00 "RSTGT_R,Reset Gate"
hexmask.word.byte 0x00 8.--15. 1. "RSTGTN,Reset Gate Number"
rbitfld.word 0x00 4.--5. "RSTGSM,Reset Gate Finite State Machine" "0: Idle waiting for the first data pattern,1: Waiting for the second data pattern,2: The 2-write sequence has completed,3: This state encoding is never used and.."
newline
rbitfld.word 0x00 0.--3. "RSTGMS,Reset Gate Bus Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x42++0x01
line.word 0x00 "RSTGT_W,Reset Gate"
hexmask.word.byte 0x00 8.--15. 1. "RSTGTN,Reset Gate Number"
hexmask.word.byte 0x00 0.--7. 1. "RSTGDP,Reset Gate Data Pattern"
tree.end
repeat.end
tree.end
tree "SDMAARM (Smart Direct Memory Access - Arm Platform)"
repeat 3. (list 1. 2. 3.) (list ad:0x30BD0000 ad:0x30E10000 ad:0x30E00000)
tree "SDMAARM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MC0PTR,Arm platform Channel 0 Pointer"
hexmask.long 0x00 0.--31. 1. "MC0PTR,Channel 0 Pointer contains the 32-bit address in Arm platform memory of channel 0 control block (the boot channel)"
group.long 0x04++0x03
line.long 0x00 "INTR,Channel Interrupts"
hexmask.long 0x00 0.--31. 1. "HI,The Arm platform Interrupts register contains the 32 HI[i] bits"
group.long 0x08++0x03
line.long 0x00 "STOP_STAT,Channel Stop/Channel Status"
hexmask.long 0x00 0.--31. 1. "HE,This 32-bit register gives access to the Arm platform Enable bits"
group.long 0x0C++0x03
line.long 0x00 "HSTART,Channel Start"
hexmask.long 0x00 0.--31. 1. "HSTART_HE,The HSTART_HE registers are 32 bits wide with one bit for every channel"
group.long 0x10++0x03
line.long 0x00 "EVTOVR,Channel Event Override"
hexmask.long 0x00 0.--31. 1. "EO,The Channel Event Override register contains the 32 EO[i] bits"
group.long 0x14++0x03
line.long 0x00 "DSPOVR,Channel BP Override"
hexmask.long 0x00 0.--31. 1. "DO,This register is reserved"
group.long 0x18++0x03
line.long 0x00 "HOSTOVR,Channel Arm platform Override"
hexmask.long 0x00 0.--31. 1. "HO,The Channel Arm platform Override register contains the 32 HO[i] bits"
group.long 0x1C++0x03
line.long 0x00 "EVTPEND,Channel Event Pending"
hexmask.long 0x00 0.--31. 1. "EP,The Channel Event Pending register contains the 32 EP[i] bits"
rgroup.long 0x24++0x03
line.long 0x00 "RESET,Reset Register"
bitfld.long 0x00 1. "RESCHED,When set this bit forces the SDMA to reschedule as if a script had executed a done instruction" "0,1"
bitfld.long 0x00 0. "RESET,When set this bit causes the SDMA to be held in a software reset" "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "EVTERR,DMA Request Error Register"
hexmask.long 0x00 0.--31. 1. "CHNERR,This register is used by the SDMA to warn the Arm platform when an incoming DMA request was detected and it triggers a channel that is already pending or being serviced"
group.long 0x2C++0x03
line.long 0x00 "INTRMASK,Channel Arm platform Interrupt Mask"
hexmask.long 0x00 0.--31. 1. "HIMASK,The Interrupt Mask Register contains 32 interrupt generation mask bits"
rgroup.long 0x30++0x03
line.long 0x00 "PSW,Schedule Status"
bitfld.long 0x00 13.--15. "NCP,The Next Channel Priority gives the next pending channel priority" "0: No running channel,1: Active channel priority,?..."
bitfld.long 0x00 8.--12. "NCR,The Next Channel Register indicates the number of the next scheduled pending channel with the highest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "CCP,The Current Channel Priority indicates the priority of the current active channel" "0: No running channel,1: Active channel priority,?..."
bitfld.long 0x00 0.--3. "CCR,The Current Channel Register indicates the number of the channel that is being executed by the SDMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x03
line.long 0x00 "EVTERRDBG,DMA Request Error Register"
hexmask.long 0x00 0.--31. 1. "CHNERR,This register is the same as EVTERR except reading it does not clear its contents"
group.long 0x38++0x03
line.long 0x00 "CONFIG,Configuration Register"
bitfld.long 0x00 12. "DSPDMA,This bit's function is reserved and should be configured as zero" "0: - Reset Value,1: - Reserved"
bitfld.long 0x00 11. "RTDOBS,Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power consumption" "0: RTD pins disabled,1: RTD pins enabled"
newline
bitfld.long 0x00 4. "ACR,Arm platform DMA / SDMA Core Clock Ratio" "0: Arm platform DMA interface frequency equals..,1: Arm platform DMA interface frequency equals.."
bitfld.long 0x00 0.--1. "CSM,Selects the Context Switch Mode" "0: static,1: dynamic low power,2: dynamic with no loop,3: dynamic"
group.long 0x3C++0x03
line.long 0x00 "SDMA_LOCK,SDMA LOCK"
bitfld.long 0x00 1. "SRESET_LOCK_CLR,The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing to the RESET register" "0: Software Reset does not clear the LOCK bit,1: Software Reset clears the LOCK bit"
bitfld.long 0x00 0. "LOCK,The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts and through the OnCE interface under Arm platform control" "0: LOCK disengaged,1: LOCK enabled"
group.long 0x40++0x03
line.long 0x00 "ONCE_ENB,OnCE Enable"
bitfld.long 0x00 0. "ENB,The OnCE Enable register selects the OnCE control source: When cleared (0) the OnCE registers are accessed through the JTAG interface when set (1) the OnCE registers may be accessed by the Arm platform through the addresses described as follows" "0,1"
group.long 0x44++0x03
line.long 0x00 "ONCE_DATA,OnCE Data Register"
hexmask.long 0x00 0.--31. 1. "DATA,Data register of the OnCE JTAG controller"
group.long 0x48++0x03
line.long 0x00 "ONCE_INSTR,OnCE Instruction Register"
hexmask.long.word 0x00 0.--15. 1. "INSTR,Instruction register of the OnCE JTAG controller"
rgroup.long 0x4C++0x03
line.long 0x00 "ONCE_STAT,OnCE Status Register"
bitfld.long 0x00 12.--15. "PST,The Processor Status bits reflect the state of the SDMA RISC engine" "0: Program,1: PST_1,2: Change of Flow,3: Change of Flow in Loop,4: PST_4,5: Functional Unit,6: PST_6,7: PST_7,8: Program in Sleep,9: Data in Sleep,?,?,12: Debug in Sleep,13: Functional Unit in Sleep,14: Sleep after Reset,15: Restore"
bitfld.long 0x00 11. "RCV,After each write access to the real time buffer (RTB) the RCV bit is set" "0,1"
newline
bitfld.long 0x00 10. "EDR,This flag is raised when the SDMA has entered debug mode after an external debug request" "0,1"
bitfld.long 0x00 9. "ODR,This flag is raised when the SDMA has entered debug mode after a OnCE debug request" "0,1"
newline
bitfld.long 0x00 8. "SWB,This flag is raised when the SDMA has entered debug mode after a software breakpoint" "0,1"
bitfld.long 0x00 7. "MST,This flag is raised when the OnCE is controlled from the Arm platform peripheral interface" "0: The JTAG interface controls the OnCE,1: The Arm platform peripheral interface.."
newline
bitfld.long 0x00 0.--2. "ECDR,Event Cell Debug Request" "0: 1 matched addra_cond,1: 1 matched addrb_cond,2: 1 matched data_cond,?..."
group.long 0x50++0x03
line.long 0x00 "ONCE_CMD,OnCE Command Register"
bitfld.long 0x00 0.--3. "CMD,Writing to this register will cause the OnCE to execute the command that is written" "0: rstatus,1: CMD_1,2: exec_once,3: run_core,4: exec_core,5: debug_rqst,6: rbuffer,?..."
group.long 0x58++0x03
line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address"
hexmask.long.word 0x00 0.--13. 1. "ILLINSTADDR,The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is executed"
group.long 0x5C++0x03
line.long 0x00 "CHN0ADDR,Channel 0 Boot Address"
bitfld.long 0x00 14. "SMSZ,The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel context" "0: 24 words per context,1: 32 words per context"
hexmask.long.word 0x00 0.--13. 1. "CHN0ADDR,This 14-bit register is used by the boot code of the SDMA"
rgroup.long 0x60++0x03
line.long 0x00 "EVT_MIRROR,DMA Requests"
hexmask.long 0x00 0.--31. 1. "EVENTS,This register reflects the DMA requests received by the SDMA for events 31-0"
rgroup.long 0x64++0x03
line.long 0x00 "EVT_MIRROR2,DMA Requests 2"
hexmask.long.word 0x00 0.--15. 1. "EVENTS,This register reflects the DMA requests received by the SDMA for events 47-32"
group.long 0x70++0x03
line.long 0x00 "XTRIG_CONF1,Cross-Trigger Events Configuration Register 1"
bitfld.long 0x00 30. "CNF3,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 24.--29. "NUM3,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 22. "CNF2,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 16.--21. "NUM2,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 14. "CNF1,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 8.--13. "NUM1,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6. "CNF0,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 0.--5. "NUM0,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x74++0x03
line.long 0x00 "XTRIG_CONF2,Cross-Trigger Events Configuration Register 2"
bitfld.long 0x00 30. "CNF7,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 24.--29. "NUM7,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 22. "CNF6,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 16.--21. "NUM6,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 14. "CNF5,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 8.--13. "NUM5,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6. "CNF4,Configuration of the SDMA event line number i that is connected to the cross-trigger" "0: channel,1: DMA request"
bitfld.long 0x00 0.--5. "NUM4,Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "SDMA_CHNPRI$1,Channel Priority Registers"
bitfld.long 0x00 0.--2. "CHNPRIn,This contains the priority of channel number n" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x140)++0x03
line.long 0x00 "SDMA_CHNPRI$1,Channel Priority Registers"
bitfld.long 0x00 0.--2. "CHNPRIn,This contains the priority of channel number n" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "CHNENBL$1,Channel Enable RAM"
hexmask.long 0x00 0.--31. 1. "ENBLn,This 32-bit value selects the channels that are triggered by the DMA request number n"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "CHNENBL$1,Channel Enable RAM"
hexmask.long 0x00 0.--31. 1. "ENBLn,This 32-bit value selects the channels that are triggered by the DMA request number n"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "CHNENBL$1,Channel Enable RAM"
hexmask.long 0x00 0.--31. 1. "ENBLn,This 32-bit value selects the channels that are triggered by the DMA request number n"
repeat.end
group.long 0x1000++0x03
line.long 0x00 "DONE0_CONFIG,SDMA DONE0 Configuration"
bitfld.long 0x00 31. "DONE_SEL3,Select Done from SW or HW for channel 3" "0: DONE_SEL3_0,1: DONE_SEL3_1"
bitfld.long 0x00 30. "SW_DONE_DIS3,Disable SW Done for channel 3" "0: SW_DONE_DIS3_0,1: SW_DONE_DIS3_1"
newline
bitfld.long 0x00 24.--28. "CH_SEL3,Select event for channel 3 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "DONE_SEL2,Select Done from SW or HW for channel 2" "0: DONE_SEL2_0,1: DONE_SEL2_1"
newline
bitfld.long 0x00 22. "SW_DONE_DIS2,Disable SW Done for channel 2" "0: SW_DONE_DIS2_0,1: SW_DONE_DIS2_1"
bitfld.long 0x00 16.--20. "CH_SEL2,Select event for channel 2 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "DONE_SEL1,Select Done from SW or HW for channel 1" "0: DONE_SEL1_0,1: DONE_SEL1_1"
bitfld.long 0x00 14. "SW_DONE_DIS1,Disable SW Done for channel 1" "0: SW_DONE_DIS1_0,1: SW_DONE_DIS1_1"
newline
bitfld.long 0x00 8.--12. "CH_SEL1,Select event for channel 1 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "DONE_SEL0,Select Done from SW or HW for channel 0" "0: DONE_SEL0_0,1: DONE_SEL0_1"
newline
bitfld.long 0x00 6. "SW_DONE_DIS0,Disable SW Done for channel 0" "0: SW_DONE_DIS0_0,1: SW_DONE_DIS0_1"
bitfld.long 0x00 0.--4. "CH_SEL0,Select event for channel 0 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1004++0x03
line.long 0x00 "DONE1_CONFIG,SDMA DONE1 Configuration"
bitfld.long 0x00 31. "DONE_SEL7,Select Done from SW or HW for channel 7" "0: DONE_SEL7_0,1: DONE_SEL7_1"
bitfld.long 0x00 30. "SW_DONE_DIS7,Disable SW Done for channel 7" "0: SW_DONE_DIS7_0,1: SW_DONE_DIS7_1"
newline
bitfld.long 0x00 24.--28. "CH_SEL7,Select event for channel 7 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "DONE_SEL6,Select Done from SW or HW for channel 6" "0: DONE_SEL6_0,1: DONE_SEL6_1"
newline
bitfld.long 0x00 22. "SW_DONE_DIS6,Disable SW Done for channel 6" "0: SW_DONE_DIS6_0,1: SW_DONE_DIS6_1"
bitfld.long 0x00 16.--20. "CH_SEL6,Select event for channel 6 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "DONE_SEL5,Select Done from SW or HW for channel 5" "0: DONE_SEL5_0,1: DONE_SEL5_1"
bitfld.long 0x00 14. "SW_DONE_DIS5,Disable SW Done for channel 5" "0: SW_DONE_DIS5_0,1: SW_DONE_DIS5_1"
newline
bitfld.long 0x00 8.--12. "CH_SEL5,Select event for channel 5 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "DONE_SEL4,Select Done from SW or HW for channel 4" "0: DONE_SEL4_0,1: DONE_SEL4_1"
newline
bitfld.long 0x00 6. "SW_DONE_DIS4,Disable SW Done for channel 4" "0: SW_DONE_DIS4_0,1: SW_DONE_DIS4_1"
bitfld.long 0x00 0.--4. "CH_SEL4,Select event for channel 4 when Done is selected from HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
repeat.end
tree.end
tree "SEMA4 (Semaphore)"
base ad:0x30AC0000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "Gate$1,Semaphores Gate 0 Register"
bitfld.byte 0x00 0.--1. "GTFSM,Gate Finite State Machine" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,3: This state encoding is never used and.."
repeat.end
group.word 0x40++0x01
line.word 0x00 "CP0INE,Semaphores Processor n IRQ Notification Enable"
bitfld.word 0x00 15. "INE8,Interrupt Request Notification Enable 8" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 14. "INE9,Interrupt Request Notification Enable 9" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 13. "INE10,Interrupt Request Notification Enable 10" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 12. "INE11,Interrupt Request Notification Enable 11" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 11. "INE12,Interrupt Request Notification Enable 12" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 10. "INE13,Interrupt Request Notification Enable 13" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 9. "INE14,Interrupt Request Notification Enable 14" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 8. "INE15,Interrupt Request Notification Enable 15" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 7. "INE0,Interrupt Request Notification Enable 0" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 6. "INE1,Interrupt Request Notification Enable 1" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 5. "INE2,Interrupt Request Notification Enable 2" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 4. "INE3,Interrupt Request Notification Enable 3" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 3. "INE4,Interrupt Request Notification Enable 4" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 2. "INE5,Interrupt Request Notification Enable 5" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 1. "INE6,Interrupt Request Notification Enable 6" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 0. "INE7,Interrupt Request Notification Enable 7" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
group.word 0x48++0x01
line.word 0x00 "CP1INE,Semaphores Processor n IRQ Notification Enable"
bitfld.word 0x00 15. "INE8,Interrupt Request Notification Enable 8" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 14. "INE9,Interrupt Request Notification Enable 9" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 13. "INE10,Interrupt Request Notification Enable 10" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 12. "INE11,Interrupt Request Notification Enable 11" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 11. "INE12,Interrupt Request Notification Enable 12" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 10. "INE13,Interrupt Request Notification Enable 13" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 9. "INE14,Interrupt Request Notification Enable 14" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 8. "INE15,Interrupt Request Notification Enable 15" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 7. "INE0,Interrupt Request Notification Enable 0" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 6. "INE1,Interrupt Request Notification Enable 1" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 5. "INE2,Interrupt Request Notification Enable 2" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 4. "INE3,Interrupt Request Notification Enable 3" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 3. "INE4,Interrupt Request Notification Enable 4" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 2. "INE5,Interrupt Request Notification Enable 5" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
newline
bitfld.word 0x00 1. "INE6,Interrupt Request Notification Enable 6" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
bitfld.word 0x00 0. "INE7,Interrupt Request Notification Enable 7" "0: The generation of the notification interrupt..,1: The generation of the notification interrupt.."
rgroup.word 0x80++0x01
line.word 0x00 "CP0NTF,Semaphores Processor n IRQ Notification"
bitfld.word 0x00 15. "GN8,Gate 8 Notification" "0,1"
bitfld.word 0x00 14. "GN9,Gate 9 Notification" "0,1"
newline
bitfld.word 0x00 13. "GN10,Gate 10 Notification" "0,1"
bitfld.word 0x00 12. "GN11,Gate 11 Notification" "0,1"
newline
bitfld.word 0x00 11. "GN12,Gate 12 Notification" "0,1"
bitfld.word 0x00 10. "GN13,Gate 13 Notification" "0,1"
newline
bitfld.word 0x00 9. "GN14,Gate 14 Notification" "0,1"
bitfld.word 0x00 8. "GN15,Gate 15 Notification" "0,1"
newline
bitfld.word 0x00 7. "GN0,Gate 0 Notification" "0,1"
bitfld.word 0x00 6. "GN1,Gate 1 Notification" "0,1"
newline
bitfld.word 0x00 5. "GN2,Gate 2 Notification" "0,1"
bitfld.word 0x00 4. "GN3,Gate 3 Notification" "0,1"
newline
bitfld.word 0x00 3. "GN4,Gate 4 Notification" "0,1"
bitfld.word 0x00 2. "GN5,Gate 5 Notification" "0,1"
newline
bitfld.word 0x00 1. "GN6,Gate 6 Notification" "0,1"
bitfld.word 0x00 0. "GN7,Gate 7 Notification" "0,1"
rgroup.word 0x88++0x01
line.word 0x00 "CP1NTF,Semaphores Processor n IRQ Notification"
bitfld.word 0x00 15. "GN8,Gate 8 Notification" "0,1"
bitfld.word 0x00 14. "GN9,Gate 9 Notification" "0,1"
newline
bitfld.word 0x00 13. "GN10,Gate 10 Notification" "0,1"
bitfld.word 0x00 12. "GN11,Gate 11 Notification" "0,1"
newline
bitfld.word 0x00 11. "GN12,Gate 12 Notification" "0,1"
bitfld.word 0x00 10. "GN13,Gate 13 Notification" "0,1"
newline
bitfld.word 0x00 9. "GN14,Gate 14 Notification" "0,1"
bitfld.word 0x00 8. "GN15,Gate 15 Notification" "0,1"
newline
bitfld.word 0x00 7. "GN0,Gate 0 Notification" "0,1"
bitfld.word 0x00 6. "GN1,Gate 1 Notification" "0,1"
newline
bitfld.word 0x00 5. "GN2,Gate 2 Notification" "0,1"
bitfld.word 0x00 4. "GN3,Gate 3 Notification" "0,1"
newline
bitfld.word 0x00 3. "GN4,Gate 4 Notification" "0,1"
bitfld.word 0x00 2. "GN5,Gate 5 Notification" "0,1"
newline
bitfld.word 0x00 1. "GN6,Gate 6 Notification" "0,1"
bitfld.word 0x00 0. "GN7,Gate 7 Notification" "0,1"
group.word 0x100++0x01
line.word 0x00 "RSTGT,Semaphores (Secure) Reset Gate n"
hexmask.word.byte 0x00 8.--15. 1. "RSTGTN,Reset Gate Number"
hexmask.word.byte 0x00 0.--7. 1. "RSTGSM_RSTGMS_RSTGDP,This field contains sub-fields that vary depending on whether it is being read or written"
group.word 0x104++0x01
line.word 0x00 "RSTNTF,Semaphores (Secure) Reset IRQ Notification"
hexmask.word.byte 0x00 8.--15. 1. "RSTNTN,Reset Notification Number"
hexmask.word.byte 0x00 0.--7. 1. "RSTNSM_RSTNMS_RSTNDP,This field contains sub-fields that vary depending on whether it is being read or written"
tree.end
tree "SVNS (Secure Non-Volatile Storage)"
base ad:0x30370000
group.long 0x04++0x03
line.long 0x00 "HPCOMR,SNVS_HP Command Register"
bitfld.long 0x00 31. "NPSWA_EN,Non-Privileged Software Access Enable When set allows non-privileged software to access all SNVS registers including those that are privileged software read/write access only" "0,1"
bitfld.long 0x00 5. "LP_SWR_DIS,LP Software Reset Disable When set disables the LP software reset" "0: LP software reset is enabled,1: LP software reset is disabled"
newline
bitfld.long 0x00 4. "LP_SWR,LP Software Reset When set to 1 the registers in the SNVS_LP section are reset" "0: NO_ACTION,1: Reset LP section"
group.long 0x08++0x03
line.long 0x00 "HPCR,SNVS_HP Control Register"
bitfld.long 0x00 27. "BTN_MASK,Button interrupt mask" "0,1"
bitfld.long 0x00 24.--26. "BTN_CONFIG,Button Configuration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--14. "HPCALB_VAL,HP Calibration Value Defines signed calibration value for the HP Real Time Counter" "0: +0 counts per each 32768 ticks of the counter,1: +1 counts per each 32768 ticks of the counter,2: +2 counts per each 32768 ticks of the counter,?,?,?,?,?,?,?,?,?,?,?,?,15: +15 counts per each 32768 ticks of the counter,16: -16 counts per each 32768 ticks of the counter,17: -15 counts per each 32768 ticks of the counter,?,?,?,?,?,?,?,?,?,?,?,?,30: -2 counts per each 32768 ticks of the counter,31: -1 counts per each 32768 ticks of the counter"
bitfld.long 0x00 8. "HPCALB_EN,HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled" "0: HP Timer calibration disabled,1: HP Timer calibration enabled"
newline
bitfld.long 0x00 1. "HPTA_EN,HP Time Alarm Enable When set the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter" "0: HP Time Alarm Interrupt is disabled,1: HP Time Alarm Interrupt is enabled"
bitfld.long 0x00 0. "RTC_EN,HP Real Time Counter Enable" "0: RTC is disabled,1: RTC is enabled"
group.long 0x14++0x03
line.long 0x00 "HPSR,SNVS_HP Status Register"
eventfld.long 0x00 7. "BI,Button Interrupt Signal ipi_snvs_btn_int_b was asserted" "0,1"
rbitfld.long 0x00 6. "BTN,Button Value of the BTN input" "0,1"
newline
rbitfld.long 0x00 4. "LPDIS,Low Power Disable If 1 the low power section has been disabled by means of an input signal to SNVS" "0,1"
eventfld.long 0x00 0. "HPTA,HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared" "0: No time alarm interrupt occurred,1: A time alarm interrupt occurred"
group.long 0x24++0x03
line.long 0x00 "HPRTCMR,SNVS_HP Real Time Counter MSB Register"
hexmask.long.word 0x00 0.--14. 1. "RTC,HP Real Time Counter The most-significant 15 bits of the RTC"
group.long 0x28++0x03
line.long 0x00 "HPRTCLR,SNVS_HP Real Time Counter LSB Register"
hexmask.long 0x00 0.--31. 1. "RTC,HP Real Time Counter least-significant 32 bits"
group.long 0x2C++0x03
line.long 0x00 "HPTAMR,SNVS_HP Time Alarm MSB Register"
hexmask.long.word 0x00 0.--14. 1. "HPTA_MS,HP Time Alarm most-significant 15 bits"
group.long 0x30++0x03
line.long 0x00 "HPTALR,SNVS_HP Time Alarm LSB Register"
hexmask.long 0x00 0.--31. 1. "HPTA_LS,HP Time Alarm 32 least-significant bits"
group.long 0x34++0x03
line.long 0x00 "LPLR,SNVS_LP Lock Register"
bitfld.long 0x00 5. "GPR_HL,General Purpose Register Hard Lock When set prevents any writes to the GPR" "0: Write access is allowed,1: Write access is not allowed"
bitfld.long 0x00 4. "MC_HL,Monotonic Counter Hard Lock When set prevents any writes (increments) to the MC Registers and MC_ENV bit" "0: Write access (increment) is allowed,1: Write access (increment) is not allowed"
group.long 0x38++0x03
line.long 0x00 "LPCR,SNVS_LP Control Register"
bitfld.long 0x00 23. "PK_OVERRIDE,PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override" "0,1"
bitfld.long 0x00 22. "PK_EN,PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en" "0,1"
newline
bitfld.long 0x00 20.--21. "ON_TIME,The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power" "0,1,2,3"
bitfld.long 0x00 18.--19. "DEBOUNCE,This field configures the amount of debounce time for the BTN input signal" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "BTN_PRESS_TIME,This field configures the button press time out values for the PMIC Logic" "0,1,2,3"
bitfld.long 0x00 7. "PWR_GLITCH_EN,Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted" "0,1"
newline
bitfld.long 0x00 6. "TOP,Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power" "0: Leave system power on,1: Turn off system power"
bitfld.long 0x00 5. "DP_EN,Dumb PMIC Enabled When set software can control the system power" "0: Smart PMIC enabled,1: Dumb PMIC enabled"
newline
bitfld.long 0x00 3. "LPWUI_EN,LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (MC rollover SRTC rollover or time alarm )" "0,1"
bitfld.long 0x00 2. "MC_ENV,Monotonic Counter Enabled and Valid When set the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)" "0: MC is disabled or invalid,1: MC is enabled and valid"
group.long 0x4C++0x03
line.long 0x00 "LPSR,SNVS_LP Status Register"
eventfld.long 0x00 18. "SPOF,Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time" "0: Set Power Off was not detected,1: Set Power Off was detected"
eventfld.long 0x00 17. "EO,Emergency Off This bit is set when a power off is requested" "0: Emergency off was not detected,1: Emergency off was detected"
newline
eventfld.long 0x00 2. "MCR,Monotonic Counter Rollover" "0: MC has not reached its maximum value,1: MC has reached its maximum value"
group.long 0x5C++0x03
line.long 0x00 "LPSMCMR,SNVS_LP Secure Monotonic Counter MSB Register"
hexmask.long.word 0x00 16.--31. 1. "MC_ERA_BITS,Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses"
hexmask.long.word 0x00 0.--15. 1. "MON_COUNTER,Monotonic Counter most-significant 16 Bits Note that writing to this register does not change the value of this field to the value that was written"
group.long 0x60++0x03
line.long 0x00 "LPSMCLR,SNVS_LP Secure Monotonic Counter LSB Register"
hexmask.long 0x00 0.--31. 1. "MON_COUNTER,Monotonic Counter bits Note that writing to this register does not change the value of this field to the value that was written"
group.long 0x64++0x03
line.long 0x00 "LPPGDR,SNVS_LP Power Glitch Detector Register"
hexmask.long 0x00 0.--31. 1. "PGD,Power Glitch Detector Value"
group.long 0x68++0x03
line.long 0x00 "LPGPR0_legacy_alias,SNVS_LP General Purpose Register 0 (legacy alias)"
hexmask.long 0x00 0.--31. 1. "GPR,General Purpose Register When GPR_SL or GPR_HL bit is set the register cannot be programmed"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x90)++0x03
line.long 0x00 "LPGPR_alias[$1],SNVS_LP General Purpose Registers 0"
hexmask.long 0x00 0.--31. 1. "GPR,General Purpose Register When GPR_SL or GPR_HL bit is set the register cannot be programmed"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "LPGPR[$1],SNVS_LP General Purpose Registers 0"
hexmask.long 0x00 0.--31. 1. "GPR,General Purpose Register When GPR_SL or GPR_HL bit is set the register cannot be programmed"
repeat.end
rgroup.long 0xBF8++0x03
line.long 0x00 "HPVIDR1,SNVS_HP Version ID Register 1"
hexmask.long.word 0x00 16.--31. 1. "IP_ID,SNVS block ID"
hexmask.long.byte 0x00 8.--15. 1. "MAJOR_REV,SNVS block major version number"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_REV,SNVS block minor version number"
rgroup.long 0xBFC++0x03
line.long 0x00 "HPVIDR2,SNVS_HP Version ID Register 2"
abitfld.long 0x00 24.--31. "IP_ERA,IP Era" "0x00=0: Era 1 or 2,0x03=3: Era 3,0x04=4: Era 4,0x05=5: Era 5"
hexmask.long.byte 0x00 16.--23. 1. "INTG_OPT,SNVS Integration Options"
newline
hexmask.long.byte 0x00 8.--15. 1. "ECO_REV,SNVS ECO Revision"
hexmask.long.byte 0x00 0.--7. 1. "CONFIG_OPT,SNVS Configuration Options"
tree.end
tree "SPBA (Shared Peripheral Bus Arbiter)"
repeat 2. (list 1. 2.) (list ad:0x308F0000 ad:0x30CF0000)
tree "SPBA$1"
base $2
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x00)++0x03
line.long 0x00 "PRR$1,Peripheral Rights Register"
rbitfld.long 0x00 30.--31. "RMO,Requesting Master Owner" "0: The resource is unowned,?,2: The resource is owned by another master,3: The resource is owned by the requesting master"
rbitfld.long 0x00 16.--17. "ROI,Resource Owner ID" "0: Unowned resource,1: The resource is owned by master A port,2: The resource is owned by master B port,3: The resource is owned by master C port"
newline
bitfld.long 0x00 2. "RARC,Resource Access Right" "0: Access to peripheral is not allowed,1: Access to peripheral is granted"
bitfld.long 0x00 1. "RARB,Resource Access Right" "0: Access to peripheral is not allowed,1: Access to peripheral is granted"
newline
bitfld.long 0x00 0. "RARA,Resource Access Right" "0: Access to peripheral is not allowed,1: Access to peripheral is granted"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x40)++0x03
line.long 0x00 "PRR$1,Peripheral Rights Register"
rbitfld.long 0x00 30.--31. "RMO,Requesting Master Owner" "0: The resource is unowned,?,2: The resource is owned by another master,3: The resource is owned by the requesting master"
rbitfld.long 0x00 16.--17. "ROI,Resource Owner ID" "0: Unowned resource,1: The resource is owned by master A port,2: The resource is owned by master B port,3: The resource is owned by master C port"
newline
bitfld.long 0x00 2. "RARC,Resource Access Right" "0: Access to peripheral is not allowed,1: Access to peripheral is granted"
bitfld.long 0x00 1. "RARB,Resource Access Right" "0: Access to peripheral is not allowed,1: Access to peripheral is granted"
newline
bitfld.long 0x00 0. "RARA,Resource Access Right" "0: Access to peripheral is not allowed,1: Access to peripheral is granted"
repeat.end
tree.end
repeat.end
tree.end
tree "SRC (System Reset Controller)"
base ad:0x30390000
group.long 0x00++0x03
line.long 0x00 "SCR,SRC Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 4.--7. "MASK_TEMPSENSE_RESET,Mask tempsense_reset source" "?,?,?,?,?,5: tempsense_reset is masked,?,?,?,?,10: tempsense_reset is not masked,?..."
group.long 0x04++0x03
line.long 0x00 "A53RCR0,A53 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 21. "A53_L2RESET,Software reset for A53 Snoop Control Unit (SCU)" "0: do not assert SCU reset,1: assert SCU reset"
newline
bitfld.long 0x00 20. "A53_SOC_DBG_RESET,Software reset for system level debug reset" "0: do not assert system level debug reset,1: assert system level debug reset"
newline
bitfld.long 0x00 16.--19. "MASK_WDOG1_RST,Mask wdog1_rst_b source" "?,?,?,?,?,5: wdog1_rst_b is masked,?,?,?,?,10: wdog1_rst_b is not masked,?..."
newline
bitfld.long 0x00 15. "A53_ETM_RESET3,Software reset for core3 ETM only" "0: do not assert core3 ETM reset,1: assert core3 ETM reset"
newline
bitfld.long 0x00 14. "A53_ETM_RESET2,Software reset for core2 ETM only" "0: do not assert core2 ETM reset,1: assert core2 ETM reset"
newline
bitfld.long 0x00 13. "A53_ETM_RESET1,Software reset for core1 ETM only" "0: do not assert core1 ETM reset,1: assert core1 ETM reset"
newline
bitfld.long 0x00 12. "A53_ETM_RESET0,Software reset for core0 ETM only" "0: do not assert core0 ETM reset,1: assert core0 ETM reset"
newline
bitfld.long 0x00 11. "A53_DBG_RESET3,Software reset for core3 debug only" "0: do not assert core3 debug reset,1: assert core3 debug reset"
newline
bitfld.long 0x00 10. "A53_DBG_RESET2,Software reset for core2 debug only" "0: do not assert core2 debug reset,1: assert core2 debug reset"
newline
bitfld.long 0x00 9. "A53_DBG_RESET1,Software reset for core1 debug only" "0: do not assert core1 debug reset,1: assert core1 debug reset"
newline
bitfld.long 0x00 8. "A53_DBG_RESET0,Software reset for core0 debug only" "0: do not assert core0 debug reset,1: assert core0 debug reset"
newline
bitfld.long 0x00 7. "A53_CORE_RESET3,Software reset for core3 only" "0: do not assert core3 reset,1: assert core3 reset"
newline
bitfld.long 0x00 6. "A53_CORE_RESET2,Software reset for core2 only" "0: do not assert core2 reset,1: assert core2 reset"
newline
bitfld.long 0x00 5. "A53_CORE_RESET1,Software reset for core1 only" "0: do not assert core1 reset,1: assert core1 reset"
newline
bitfld.long 0x00 4. "A53_CORE_RESET0,Software reset for core0 only" "0: do not assert core0 reset,1: assert core0 reset"
newline
bitfld.long 0x00 3. "A53_CORE_POR_RESET3,POR reset for A53 core3 only" "0: do not assert core3 reset,1: A53_CORE_POR_RESET3_1"
newline
bitfld.long 0x00 2. "A53_CORE_POR_RESET2,POR reset for A53 core2 only" "0: do not assert core2 reset,1: A53_CORE_POR_RESET2_1"
newline
bitfld.long 0x00 1. "A53_CORE_POR_RESET1,POR reset for A53 core1 only" "0: do not assert core1 reset,1: A53_CORE_POR_RESET1_1"
newline
bitfld.long 0x00 0. "A53_CORE_POR_RESET0,POR reset for A53 core0 only" "0: do not assert core0 reset,1: A53_CORE_POR_RESET0_1"
group.long 0x08++0x03
line.long 0x00 "A53RCR1,A53 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 4.--6. "A53_RST_SLOW,A53_RST_SLOW" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "A53_CORE3_ENABLE,core 3 enable" "0: A53_CORE3_ENABLE_0,1: A53_CORE3_ENABLE_1"
newline
bitfld.long 0x00 2. "A53_CORE2_ENABLE,core 2 enable" "0: A53_CORE2_ENABLE_0,1: A53_CORE2_ENABLE_1"
newline
bitfld.long 0x00 1. "A53_CORE1_ENABLE,core 1 enable" "0: A53_CORE1_ENABLE_0,1: A53_CORE1_ENABLE_1"
newline
rbitfld.long 0x00 0. "A53_CORE0_ENABLE,Always 1 can't be changed" "0,1"
group.long 0x0C++0x03
line.long 0x00 "M7RCR,M7 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 9. "WDOG3_RST_OPTION,Wdog3_rst_b option" "0: Wdog3_rst_b asserts M7 reset,1: Wdog3_rst_b asserts global reset"
newline
bitfld.long 0x00 8. "WDOG3_RST_OPTION_M7,Wdog3_rst_b option for M7" "0: wdgo3_rst_b Reset M7 core only,1: Reset both M7 core and platform"
newline
bitfld.long 0x00 4.--7. "MASK_WDOG3_RST,Mask wdog3_rst_b source" "?,?,?,?,?,5: wdog3_rst_b is masked,?,?,?,?,10: wdog3_rst_b is not masked,?..."
newline
bitfld.long 0x00 3. "ENABLE_M7,Enable M7" "0: M7 is disabled,1: M7 is enabled"
newline
bitfld.long 0x00 1. "SW_M7C_RST,Self-clearing SW reset for M7 core This is a self clearing bit" "0: do not assert M7 core reset,1: assert M7 core reset"
newline
bitfld.long 0x00 0. "SW_M7C_NON_SCLR_RST,Non-self-clearing SW reset for M7 core" "0: do not assert M7 core reset,1: SW_M7C_NON_SCLR_RST_1"
group.long 0x18++0x03
line.long 0x00 "SUPERMIX_RCR,SUPERMIX Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "SUPERMIX_RESET,Self-clearing SW reset for SUPERMIX" "0: Do not assert SUPERMIX reset,1: Assert SUPERMIX reset"
group.long 0x1C++0x03
line.long 0x00 "AUDIOMIX_RCR,AUDIOMIX Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
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bitfld.long 0x00 0. "AUDIOMIX_RESET,Self-clearing SW reset for AUDIOMIX" "0: Do not assert AUDIOMIX reset,1: Assert AUDIOMIX reset"
group.long 0x20++0x03
line.long 0x00 "USBPHY1_RCR,USB PHY1 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
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bitfld.long 0x00 0. "USB1_PHY_RESET,Self-clearing SW reset for USB 1 PHY" "0: Don't reset USB 1 PHY,1: USB1_PHY_RESET_1"
group.long 0x24++0x03
line.long 0x00 "USBPHY2_RCR,USB PHY2 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "USB2_PHY_RESET,no description available" "0: Don't reset USB 2 PHY,1: USB2_PHY_RESET_1"
group.long 0x28++0x03
line.long 0x00 "MLMIX_RCR,MLMIX Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "MLMIX_RESET,Self-clearing SW reset for MLMIX" "0: Do not assert MLMIX reset,1: Assert MLMIX reset"
group.long 0x2C++0x03
line.long 0x00 "PCIEPHY_RCR,PCIE PHY Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 16. "PCIE_CTRL_APP_XFER_PENDING,PCIE_CTRL_APP_XFER_PENDING" "0,1"
newline
bitfld.long 0x00 15. "PCIE_CTRL_APP_UNLOCK_MSG,PCIE_CTRL_APP_UNLOCK_MSG" "0,1"
newline
bitfld.long 0x00 14. "PCIE_CTRL_SYS_INT,PCIE_CTRL_SYS_INT" "0,1"
newline
bitfld.long 0x00 12. "PCIE_CTRL_CFG_L1_AUX,Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en" "0,1"
newline
bitfld.long 0x00 11. "PCIE_CTRL_APPS_TURNOFF,Pcie_ctrl_apps_pm_xmt_turnoff" "0,1"
newline
bitfld.long 0x00 10. "PCIE_CTRL_APPS_PME,Pcie_ctrl_apps_pm_xmt_pme" "0,1"
newline
bitfld.long 0x00 9. "PCIE_CTRL_APPS_EXIT,Pcie_ctrl_app_req_exit_l1" "0,1"
newline
bitfld.long 0x00 8. "PCIE_CTRL_APPS_ENTER,Pcie_ctrl_app_req_entr_l1" "0,1"
newline
bitfld.long 0x00 7. "PCIE_CTRL_APPS_READY,Pcie_ctrl_app_ready_entr_l23" "0,1"
newline
bitfld.long 0x00 6. "PCIE_CTRL_APPS_EN,Pcie_ctrl_app_ltssm_enable" "0,1"
newline
bitfld.long 0x00 5. "PCIE_CTRL_APPS_RST,Pcie_ctrl_app_init_rst" "0,1"
newline
bitfld.long 0x00 4. "PCIE_CTRL_APPS_CLK_REQ,Pcie_ctrl_app_clk_req_n" "0,1"
newline
bitfld.long 0x00 3. "PCIEPHY_PERST,Pciephy_perst" "0,1"
newline
bitfld.long 0x00 2. "PCIEPHY_BTNRST,PCIE PHY button" "0,1"
newline
bitfld.long 0x00 0. "PCIE_PHY_POWER_ON_RESET,PCIE_PHY_POWER_ON_RESET" "0,1"
group.long 0x30++0x03
line.long 0x00 "HDMI_RCR,HDMI Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "HDMI_PHY_APB_RESET,Active 1" "0,1"
group.long 0x34++0x03
line.long 0x00 "MEDIA_RCR,MEDIAMIX Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "MEDIAMIX_RESET,MEDIAMIX reset for MEDIAMIX expect ISP/Dewrap" "0: Don't reset MEDIAMIX,1: MEDIAMIX_RESET_1"
group.long 0x38++0x03
line.long 0x00 "GPU2D_RCR,GPU2D Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "GPU2D_RESET,GPU shared logic reset active 1" "0,1"
group.long 0x3C++0x03
line.long 0x00 "GPU3D_RCR,GPU3D Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "GPU3D_RESET,GPU3D reset active 1" "0,1"
group.long 0x40++0x03
line.long 0x00 "GPU_RCR,GPU Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "GPU_RESET,GPU shared logic reset" "0,1"
group.long 0x44++0x03
line.long 0x00 "VPU_RCR,VPU Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "VPU_RESET,VPU shared logic reset" "0,1"
group.long 0x48++0x03
line.long 0x00 "VPU_G1_RCR,VPU G1 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "VPU_G1_RESET,VPU G1 reset active 1" "0,1"
group.long 0x4C++0x03
line.long 0x00 "VPU_G2_RCR,VPU G2 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "VPU_G2_RESET,VPU G2 reset active 1" "0,1"
group.long 0x50++0x03
line.long 0x00 "VPUVC8KE_RCR,VPU VC8000E Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "VPU_VPUVC8KE_RESET,VPU VC8000E reset active 1" "0,1"
group.long 0x54++0x03
line.long 0x00 "NOC_RCR,NOC Wrapper Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "NOC_RESET,NOC reset active 1" "0,1"
rgroup.long 0x58++0x03
line.long 0x00 "SBMR1,SRC Boot Mode Register 1"
hexmask.long.tbyte 0x00 0.--19. 1. "BOOT_CFG,Refer to fusemap"
group.long 0x5C++0x03
line.long 0x00 "SRSR,SRC Reset Status Register"
bitfld.long 0x00 9. "tempsense_rst_b,Temper Sensor software reset" "0: Reset is not a result of software reset from..,1: Reset is a result of software reset from.."
newline
eventfld.long 0x00 8. "wdog2_rst_b,IC Watchdog2 Time-out reset" "0: Reset is not a result of the watchdog4..,1: Reset is a result of the watchdog4 time-out.."
newline
eventfld.long 0x00 7. "wdog3_rst_b,IC Watchdog3 Time-out reset" "0: Reset is not a result of the watchdog3..,1: Reset is a result of the watchdog3 time-out.."
newline
eventfld.long 0x00 6. "jtag_sw_rst,JTAG software reset" "0: Reset is not a result of software reset from..,1: Reset is a result of software reset from JTAG"
newline
eventfld.long 0x00 5. "jtag_rst_b,HIGH - Z JTAG reset" "0: Reset is not a result of HIGH-Z reset from JTAG,1: Reset is a result of HIGH-Z reset from JTAG"
newline
eventfld.long 0x00 4. "wdog1_rst_b,IC Watchdog1 Time-out reset" "0: Reset is not a result of the watchdog1..,1: Reset is a result of the watchdog1 time-out.."
newline
eventfld.long 0x00 3. "ipp_user_reset_b,Indicates whether the reset was the result of the ipp_user_reset_b qualified reset" "0: Reset is not a result of the ipp_user_reset_b..,1: Reset is a result of the ipp_user_reset_b.."
newline
eventfld.long 0x00 2. "csu_reset_b,Indicates whether the reset was the result of the csu_reset_b input" "0: Reset is not a result of the csu_reset_b event,1: Reset is a result of the csu_reset_b event"
newline
eventfld.long 0x00 0. "ipp_reset_b,Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)" "0: Reset is not a result of ipp_reset_b pin,1: Reset is a result of ipp_reset_b pin"
group.long 0x68++0x03
line.long 0x00 "SISR,SRC Interrupt Status Register"
eventfld.long 0x00 11. "VPU_PASSED_RESET,Interrupt generated to indicate that VPU passed software reset and is ready to be used" "0: interrupt generated not due to VPU reset,1: interrupt generated due to VPU reset"
newline
eventfld.long 0x00 10. "GPU_PASSED_RESET,Interrupt generated to indicate that GPU passed software reset and is ready to be used" "0: interrupt generated not due to GPU reset,1: interrupt generated due to GPU reset"
newline
eventfld.long 0x00 9. "M7P_PASSED_RESET,Interrupt generated to indicate that m7 platform passed software reset and is ready to be used" "0: interrupt generated not due to m7 platform..,1: interrupt generated due to m7 platform reset"
newline
eventfld.long 0x00 8. "M7C_PASSED_RESET,Interrupt generated to indicate that m7 core passed software reset and is ready to be used" "0: interrupt generated not due to m7core reset,1: interrupt generated due to m7core reset"
newline
eventfld.long 0x00 7. "DISPLAY_PASSED_RESET,Interrupt generated to indicate that DISPLAY passed software reset and is ready to be used" "0: Interrupt generated not due to DISPLAY passed..,1: Interrupt generated due to DISPLAY passed reset"
newline
eventfld.long 0x00 5. "PCIE1_PHY_PASSED_RESET,Interrupt generated to indicate that PCIE1 PHY passed software reset and is ready to be used" "0: Interrupt generated not due to PCIE1 PHY..,1: Interrupt generated due to PCIE1 PHY passed.."
newline
eventfld.long 0x00 3. "USBPHY2_PASSED_RESET,Interrupt generated to indicate that USB PHY2 passed software reset and is ready to be used" "0: Interrupt generated not due to USB PHY2..,1: Interrupt generated due to USB PHY2 passed.."
newline
eventfld.long 0x00 2. "USBPHY1_PASSED_RESET,Interrupt generated to indicate that USB PHY1 passed software reset and is ready to be used" "0: Interrupt generated not due to USB PHY1..,1: Interrupt generated due to USB PHY1 passed.."
group.long 0x6C++0x03
line.long 0x00 "SIMR,SRC Interrupt Mask Register"
bitfld.long 0x00 11. "MASK_VPU_PASSED_RESET,Mask interrupt generation due to VPU passed reset" "0: do not mask interrupt due to VPU passed reset..,1: mask interrupt due to VPU passed reset"
newline
bitfld.long 0x00 10. "MASK_GPU_PASSED_RESET,Mask interrupt generation due to GPU passed reset" "0: do not mask interrupt due to GPU passed reset..,1: mask interrupt due to GPU passed reset"
newline
bitfld.long 0x00 9. "MASK_M7P_PASSED_RESET,mask interrupt generation due to m7 platform passed reset" "0: do not mask interrupt due to m7 platform..,1: mask interrupt due to m7 platform passed reset"
newline
bitfld.long 0x00 8. "MASK_M7C_PASSED_RESET,mask interrupt generation due to m7 core passed reset" "0: do not mask interrupt due to m7 core passed..,1: mask interrupt due to m7 core passed reset"
newline
bitfld.long 0x00 7. "MASK_DISPLAY_PASSED_RESET,Mask interrupt generation due to display passed reset" "0: do not mask interrupt due to display passed..,1: mask interrupt due to display passed reset"
newline
bitfld.long 0x00 5. "MASK_PCIE_PHY_PASSED_RESET,Mask interrupt generation due to PCIE PHY passed reset" "0: do not mask interrupt due to PCIE PHY passed..,1: mask interrupt due to PCIE PHY passed reset"
newline
bitfld.long 0x00 3. "MASK_USBPHY2_PASSED_RESET,mask interrupt generation due to USB PHY2 passed reset" "0: do not mask interrupt due to USB PHY2 passed..,1: mask interrupt due to USB PHY2 passed reset"
newline
bitfld.long 0x00 2. "MASK_USBPHY1_PASSED_RESET,mask interrupt generation due to USB PHY1 passed reset" "0: do not mask interrupt due to USB PHY1 passed..,1: mask interrupt due to USB PHY1 passed reset"
rgroup.long 0x70++0x03
line.long 0x00 "SBMR2,SRC Boot Mode Register 2"
bitfld.long 0x00 24.--27. "IPP_BOOT_MODE,IPP_BOOT_MODE shows the latched state of the BOOT_MODE3 BOOT_MODE2 BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--7. "FORCE_COLD_BOOT,See Fusemap for additional information" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "BT_FUSE_SEL,BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse" "0,1"
newline
bitfld.long 0x00 0.--1. "SEC_CONFIG,SEC_CONFIG[1] shows the state of the SEC_CONFIG[1] fuse and SEC_CONFIG[0] shows the state of the SEC_CONFIG[0] fuse" "0,1,2,3"
group.long 0x74++0x03
line.long 0x00 "GPR1,SRC General Purpose Register 1"
hexmask.long.word 0x00 0.--15. 1. "C0_START_ADDRH,Core0 start reset address: RVBARADDR0 = {SRC_GPR1[15:0] SRC_GPR2[21:2]}"
group.long 0x78++0x03
line.long 0x00 "GPR2,SRC General Purpose Register 2"
hexmask.long.tbyte 0x00 0.--21. 1. "C0_START_ADDRL,Core0 start reset address: RVBARADDR0 = {SRC_GPR1[15:0] SRC_GPR2[21:2]}"
group.long 0x7C++0x03
line.long 0x00 "GPR3,SRC General Purpose Register 3"
hexmask.long.word 0x00 0.--15. 1. "C1_START_ADDRH,Core1 start reset address: RVBARADDR1 = {SRC_GPR3[15:0] SRC_GPR4[21:2]}"
group.long 0x80++0x03
line.long 0x00 "GPR4,SRC General Purpose Register 4"
hexmask.long.tbyte 0x00 0.--21. 1. "C1_START_ADDRL,Core1 start reset address: RVBARADDR1 = {SRC_GPR3[15:0] SRC_GPR4[21:2]}"
group.long 0x84++0x03
line.long 0x00 "GPR5,SRC General Purpose Register 5"
hexmask.long.word 0x00 0.--15. 1. "C2_START_ADDRH,Core2 start reset address: RVBARADDR2 = {SRC_GPR5[15:0] SRC_GPR6[21:2]}"
group.long 0x88++0x03
line.long 0x00 "GPR6,SRC General Purpose Register 6"
hexmask.long.tbyte 0x00 0.--21. 1. "C2_START_ADDRL,Core2 start reset address: RVBARADDR2 = {SRC_GPR5[15:0] SRC_GPR6[21:2]}"
group.long 0x8C++0x03
line.long 0x00 "GPR7,SRC General Purpose Register 7"
hexmask.long.word 0x00 0.--15. 1. "C3_START_ADDRH,Core3 start reset address: RVBARADDR3 = {SRC_GPR7[15:0] SRC_GPR8[21:2]}"
group.long 0x90++0x03
line.long 0x00 "GPR8,SRC General Purpose Register 8"
hexmask.long.tbyte 0x00 0.--21. 1. "C3_START_ADDRL,Core3 start reset address: RVBARADDR3 = {SRC_GPR7[15:0] SRC_GPR8[21:2]}"
repeat 2. (strings "9" "10" )(list 0x0 0x4 )
rgroup.long ($2+0x94)++0x03
line.long 0x00 "GPR$1,SRC General Purpose Register $1"
repeat.end
group.long 0x1000++0x03
line.long 0x00 "DDRC_RCR,SRC DDR Controller Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 5. "DDRC1_PHY_WRST,Active 1" "0,1"
newline
bitfld.long 0x00 4. "DDRC1_SYS_RST,Active 1" "0,1"
newline
bitfld.long 0x00 3. "DDRC1_PHY_PWROKIN,no description available" "0: De-assert DDR controller,1: Assert DDR Controller"
newline
bitfld.long 0x00 2. "DDRC1_PHY_RESET,no description available" "0: De-assert DDR controller,1: Assert DDR Controller"
newline
bitfld.long 0x00 1. "DDRC1_CORE_RST,DDR Controller core_ddrc_rstn and aresetn" "0: De-assert DDR controller aresetn and..,1: Assert DDR Controller preset and DDR PHY reset"
newline
bitfld.long 0x00 0. "DDRC1_PRST,DDR Controller preset and DDR PHY reset" "0: De-assert DDR Controller preset and DDR PHY..,1: Assert DDR Controller preset and DDR PHY reset"
group.long 0x1008++0x03
line.long 0x00 "HDMIPHY_RCR,HDMIPHY Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "HDMIPHY_RESET,Self-clearing SW reset for HDMI PHY" "0: Do not assert HDMI PHY reset,1: Assert HDMI PHY reset"
group.long 0x100C++0x03
line.long 0x00 "MIPIPHY1_RCR,MIPI PHY1 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "MIPIPHY1_RESET,Self-clearing SW reset for MIPI PHY1" "0: Do not assert MIPI PHY1 reset,1: Assert MIPI PHY1 reset"
group.long 0x1010++0x03
line.long 0x00 "MIPIPHY2_RCR,MIPI PHY2 Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "MIPIPHY2_RESET,Self-clearing SW reset for MIPI PHY2" "0: Do not assert MIPI PHY2 reset,1: Assert MIPI PHY2 reset"
group.long 0x1014++0x03
line.long 0x00 "HSIO_RCR,HSIO Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "HSIO_RESET,Self-clearing SW reset for HSIOMIX" "0: Do not assert HSIOMIX reset,1: Assert HSIOMIX reset"
group.long 0x1018++0x03
line.long 0x00 "MEDIAISPDWP_RCR,MEDIAMIX ISP and Dewarp Reset Control Register"
bitfld.long 0x00 31. "DOM_EN,Domain Control enable for this register" "0: Disables domain control,1: Enables domain control"
newline
bitfld.long 0x00 30. "LOCK,Domain control bits lock Lock bit is a write-once register once it is set to 1 it can't be write to 0" "0: [31] and [27:24] bits can be modified,1: [31] and [27:24] bits cannot be modified"
newline
bitfld.long 0x00 27. "DOMAIN3,Domain3 assignment control" "0: This register is not assigned to domain3,1: This register is assigned to domain3"
newline
bitfld.long 0x00 26. "DOMAIN2,Domain2 assignment control" "0: This register is not assigned to domain2,1: This register is assigned to domain2"
newline
bitfld.long 0x00 25. "DOMAIN1,Domain1 assignment control" "0: This register is not assigned to domain1,1: This register is assigned to domain1"
newline
bitfld.long 0x00 24. "DOMAIN0,Domain0 assignment control" "0: This register is not assigned to domain0,1: This register is assigned to domain0"
newline
bitfld.long 0x00 0. "MEDIAISPDWP_RESET,Self-clearing SW reset for MEDIAMIX ISP and Dewarp" "0: Do not assert MEDIAMIX ISP and Dewarp reset,1: Assert MEDIAMIX ISP and Dewarp reset"
tree.end
tree "SYS_CTR_COMPARE (SYS_CTR_COMPARE Registers)"
base ad:0x306B0000
repeat 2. (strings "0" "1" )(list 0x0 0x100 )
rgroup.long ($2+0x20)++0x03
line.long 0x00 "CMPCVL$1,Compare Count Value Low Register"
hexmask.long 0x00 0.--31. 1. "CMPCV0,Compare Count Value bits [31:0]"
repeat.end
repeat 2. (strings "0" "1" )(list 0x0 0x100 )
rgroup.long ($2+0x24)++0x03
line.long 0x00 "CMPCVH$1,Compare Count Value High Register"
hexmask.long 0x00 0.--24. 1. "CMPCV1,Compare Count Value bits [55:32]"
repeat.end
repeat 2. (strings "0" "1" )(list 0x0 0x100 )
group.long ($2+0x2C)++0x03
line.long 0x00 "CMPCR$1,Compare Control Register"
rbitfld.long 0x00 2. "ISTAT,Compare (interrupt) status" "0: Counter value is less than the compare value..,1: Counter value is greater than or equal to the.."
bitfld.long 0x00 1. "IMASK,Interrupt request mask" "0: Interrupt output signal is not masked,1: Interrupt output signal is masked"
newline
bitfld.long 0x00 0. "EN,Enable the compare function" "0: Compare disabled,1: Compare enabled"
repeat.end
rgroup.long 0xFD0++0x03
line.long 0x00 "CNTID0,Counter ID Register"
hexmask.long 0x00 0.--31. 1. "CNTID,Counter Identification"
tree.end
tree "SYS_CTR_CONTROL (SYS_CTR_CONTROL Registers)"
base ad:0x306C0000
group.long 0x00++0x03
line.long 0x00 "CNTCR,Counter Control Register"
bitfld.long 0x00 9. "FCR1,Frequency Change Request ID 1" "0: No change,1: Select frequency modes table entry 1 the base.."
bitfld.long 0x00 8. "FCR0,Frequency Change Request ID 0" "0: No change,1: Select frequency modes table entry 0 the base.."
newline
bitfld.long 0x00 1. "HDBG,Enable Debug" "0: The assertion of the debug input is ignored,1: The assertion of the debug input causes the.."
bitfld.long 0x00 0. "EN,Enable Counting" "0: Counter disabled,1: Counter enabled"
rgroup.long 0x04++0x03
line.long 0x00 "CNTSR,Counter Status Register"
bitfld.long 0x00 9. "FCA1,Frequency Change Acknowledge ID 1" "0: Base frequency is not selected,1: Base frequency is selected"
bitfld.long 0x00 8. "FCA0,Frequency Change Acknowledge ID 0" "0: Base frequency is not selected,1: Base frequency is selected"
newline
bitfld.long 0x00 0. "DBGH,Debug Halt" "0: Counter is not halted by debug,1: Counter is halted by debug"
group.long 0x08++0x03
line.long 0x00 "CNTCV0,Counter Count Value Low Register"
hexmask.long 0x00 0.--31. 1. "CNTCV0,Counter Count Value bits [31:0]"
group.long 0x0C++0x03
line.long 0x00 "CNTCV1,Counter Count Value High Register"
hexmask.long 0x00 0.--24. 1. "CNTCV1,Counter Count Value bits [55:32]"
rgroup.long 0x20++0x03
line.long 0x00 "CNTFID0,Frequency Modes Table 0 Register"
hexmask.long 0x00 0.--31. 1. "CNTFID0,Base Frequency (24 MHz /3 = 8 MHz)"
rgroup.long 0x24++0x03
line.long 0x00 "CNTFID1,Frequency Modes Table 1 Register"
hexmask.long 0x00 0.--31. 1. "CNTFID1,Alternate Frequency (32 kHz /64 = 512 Hz)"
rgroup.long 0x28++0x03
line.long 0x00 "CNTFID2,Frequency Modes Table 2 Register"
hexmask.long 0x00 0.--31. 1. "CNTFID2,End Marker"
rgroup.long 0xFD0++0x03
line.long 0x00 "CNTID0,Counter ID Register"
hexmask.long 0x00 0.--31. 1. "CNTID,Counter Identification"
tree.end
tree "SYS_CTR_READ (SYS_CTR_READ Registers)"
base ad:0x306A0000
rgroup.long 0x00++0x03
line.long 0x00 "CNTCV0,Counter Count Value Low Register"
hexmask.long 0x00 0.--31. 1. "CNTCV0,Counter Count Value bits [31:0]"
rgroup.long 0x04++0x03
line.long 0x00 "CNTCV1,Counter Count Value High Register"
hexmask.long 0x00 0.--24. 1. "CNTCV1,Counter Count Value bits [55:32]"
rgroup.long 0xFD0++0x03
line.long 0x00 "CNTID0,Counter ID Register"
hexmask.long 0x00 0.--31. 1. "CNTID,Counter Identification"
tree.end
tree "TMU (Thermal Monitoring Unit)"
base ad:0x30260000
group.long 0x00++0x03
line.long 0x00 "TER,TMU Enable register"
bitfld.long 0x00 31. "EN,Enable the temperature sensor" "0: Disable,1: Enable"
bitfld.long 0x00 30. "ADC_PD,ADC power down controll bit This bit needs to be 0 to enable TMU" "0: normal operating mode,1: power down mode"
newline
bitfld.long 0x00 0.--1. "ALPF,Average low pass filter setting" "0: ALPF_0,1: ALPF_1,2: ALPF_2,3: ALPF_3"
group.long 0x04++0x03
line.long 0x00 "TPS,TMU Probe Select register"
bitfld.long 0x00 30.--31. "PROBE_SEL,Probe selection bit This field should only change when TER.EN=1'b0" "0: select the main probe only,1: select the remote probe(near A53) only,2: select both 2 probes,3: select both 2 probes"
group.long 0x08++0x03
line.long 0x00 "TIER,TMU Interrupt Enable register"
bitfld.long 0x00 31. "ITTEIE1,Immediate temperature threshold exceeded interrupt enable of probe1" "0: ITTEIE1_0,1: Interrupt enabled"
bitfld.long 0x00 30. "ATTEIE1,Average temperature threshold exceeded interrupt enable of probe1" "0: ATTEIE1_0,1: Interrupt enabled"
newline
bitfld.long 0x00 29. "ATCTEIE1,Average temperature critical threshold exceeded interrupt enable of probe1" "0: ATCTEIE1_0,1: Interrupt enabled"
bitfld.long 0x00 27. "ITTEIE0,Immediate temperature threshold exceeded interrupt enable of probe0" "0: ITTEIE0_0,1: Interrupt enabled"
newline
bitfld.long 0x00 26. "ATTEIE0,Average temperature threshold exceeded interrupt enable of probe0" "0: ATTEIE0_0,1: Interrupt enabled"
bitfld.long 0x00 25. "ATCTEIE0,Average temperature critical threshold exceeded interrupt enable of probe0" "0: ATCTEIE0_0,1: Interrupt enabled"
group.long 0x0C++0x03
line.long 0x00 "TIDR,TMU Interrupt Detect register"
eventfld.long 0x00 31. "ITTE1,Immediate temperature threshold exceeded of probe1" "0: No threshold exceeded,1: Immediate temperature threshold as defined by.."
eventfld.long 0x00 30. "ATTE1,Average temperature threshold exceeded of probe1" "0: No threshold exceeded,1: Average temperature threshold as defined by.."
newline
eventfld.long 0x00 29. "ATCTE1,Average temperature critical threshold exceeded of probe1" "0: No threshold exceeded,1: Average temperature critical threshold as.."
eventfld.long 0x00 27. "ITTE0,Immediate temperature threshold exceeded of probe0" "0: No threshold exceeded,1: Immediate temperature threshold as defined by.."
newline
eventfld.long 0x00 26. "ATTE0,Average temperature threshold exceeded of probe0" "0: No threshold exceeded,1: Average temperature threshold as defined by.."
eventfld.long 0x00 25. "ATCTE0,Average temperature critical threshold exceeded of probe0" "0: No threshold exceeded,1: Average temperature critical threshold as.."
group.long 0x10++0x03
line.long 0x00 "TMHTITR,TMU Monitor High Temperature Immediate Threshold register"
bitfld.long 0x00 31. "EN1,Enable threshold for probe1" "0: Disabled,1: Threshold enabled"
bitfld.long 0x00 30. "EN0,Enable threshold for probe0" "0: Disabled,1: Threshold enabled"
newline
hexmask.long.byte 0x00 16.--23. 1. "TEMP1,High temperature immediate threshold value"
hexmask.long.byte 0x00 0.--7. 1. "TEMP0,High temperature immediate threshold value"
group.long 0x14++0x03
line.long 0x00 "TMHTATR,TMU Monitor High Temperature Average threshold register"
bitfld.long 0x00 31. "EN1,Enable threshold for probe1" "0: Disabled,1: Threshold enabled"
bitfld.long 0x00 30. "EN0,Enable threshold for probe0" "0: Disabled,1: Threshold enabled"
newline
hexmask.long.byte 0x00 16.--23. 1. "TEMP1,High temperature average threshold value"
hexmask.long.byte 0x00 0.--7. 1. "TEMP0,High temperature average threshold value"
group.long 0x18++0x03
line.long 0x00 "TMHTACTR,TMU Monitor High Temperature Average Critical Threshold register"
bitfld.long 0x00 31. "EN1,Enable threshold for probe1" "0: Disabled,1: Threshold enabled"
bitfld.long 0x00 30. "EN0,Enable threshold for probe0" "0: Disabled,1: Threshold enabled"
newline
hexmask.long.byte 0x00 16.--23. 1. "TEMP1,High temperature average critical threshold value for probe1"
hexmask.long.byte 0x00 0.--7. 1. "TEMP0,High temperature average critical threshold value for probe0"
rgroup.long 0x1C++0x03
line.long 0x00 "TSCR,TMU Sensor Calibration register"
bitfld.long 0x00 31. "V1,Measured temperature ready of probe1" "0: Not ready,1: Ready"
bitfld.long 0x00 30. "V0,Measured temperature ready of probe0" "0: Not ready,1: Ready"
newline
hexmask.long.word 0x00 16.--27. 1. "SNSR1,Raw sensor value of probe1"
hexmask.long.word 0x00 0.--11. 1. "SNSR0,Raw sensor value of probe0"
rgroup.long 0x20++0x03
line.long 0x00 "TRITSR,TMU Report Immediate Temperature Site register n"
bitfld.long 0x00 31. "V1,Measured temperature ready of probe1" "0: Not ready,1: Ready"
bitfld.long 0x00 30. "V0,Measured temperature ready of probe0" "0: Not ready,1: Ready"
newline
hexmask.long.byte 0x00 16.--23. 1. "TEMP1,Last calibratied temperature of probe1 reading at site when V=1"
hexmask.long.byte 0x00 0.--7. 1. "TEMP0,Last calibratied temperature of probe0 reading at site when V=1"
rgroup.long 0x24++0x03
line.long 0x00 "TRATSR,TMU Report Average Temperature Site register n"
bitfld.long 0x00 31. "V1,Measured temperature ready of probe1" "0: Not ready,1: Ready"
bitfld.long 0x00 30. "V0,Measured temperature ready of probe0" "0: Not ready,1: Ready"
newline
hexmask.long.byte 0x00 16.--23. 1. "TEMP1,Average temperature of probe1 reading at site when V=1"
hexmask.long.byte 0x00 0.--7. 1. "TEMP0,Average temperature of probe0 reading at site when V=1"
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
repeat 4. (list 1. 2. 3. 4.) (list ad:0x30860000 ad:0x30890000 ad:0x30880000 ad:0x30A60000)
tree "UART$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "URXD,UART Receiver Register"
bitfld.long 0x00 15. "CHARRDY,Character Ready" "0: Character in RX_DATA field and associated..,1: Character in RX_DATA field and associated.."
bitfld.long 0x00 14. "ERR,Error Detect" "0: No error status was detected,1: An error status was detected"
newline
bitfld.long 0x00 13. "OVRRUN,Receiver Overrun" "0: No RxFIFO overrun was detected,1: A RxFIFO overrun was detected"
bitfld.long 0x00 12. "FRMERR,Frame Error" "0: The current character has no framing error,1: The current character has a framing error"
newline
bitfld.long 0x00 11. "BRK,BREAK Detect" "0: The current character is not a BREAK character,1: The current character is a BREAK character"
bitfld.long 0x00 10. "PRERR,In RS-485 mode it holds the ninth data bit (bit [8]) of received 9-bit RS-485 data In RS232/IrDA mode it is the Parity Error flag" "0: = No parity error was detected for data in..,1: = A parity error was detected for data in the.."
newline
hexmask.long.byte 0x00 0.--7. 1. "RX_DATA,Received Data"
wgroup.long 0x40++0x03
line.long 0x00 "UTXD,UART Transmitter Register"
hexmask.long.byte 0x00 0.--7. 1. "TX_DATA,Transmit Data"
group.long 0x80++0x03
line.long 0x00 "UCR1,UART Control Register 1"
bitfld.long 0x00 15. "ADEN,Automatic Baud Rate Detection Interrupt Enable" "0: Disable the automatic baud rate detection..,1: Enable the automatic baud rate detection.."
bitfld.long 0x00 14. "ADBR,Automatic Detection of Baud Rate" "0: Disable automatic detection of baud rate,1: Enable automatic detection of baud rate"
newline
bitfld.long 0x00 13. "TRDYEN,Transmitter Ready Interrupt Enable" "0: Disable the transmitter ready interrupt,1: Enable the transmitter ready interrupt"
bitfld.long 0x00 12. "IDEN,Idle Condition Detected Interrupt Enable" "0: Disable the IDLE interrupt,1: Enable the IDLE interrupt"
newline
bitfld.long 0x00 10.--11. "ICD,Idle Condition Detect" "0: Idle for more than 4 frames,1: Idle for more than 8 frames,2: Idle for more than 16 frames,3: Idle for more than 32 frames"
bitfld.long 0x00 9. "RRDYEN,Receiver Ready Interrupt Enable" "0: Disables the RRDY interrupt,1: Enables the RRDY interrupt"
newline
bitfld.long 0x00 8. "RXDMAEN,Receive Ready DMA Enable" "0: Disable DMA request,1: Enable DMA request"
bitfld.long 0x00 7. "IREN,Infrared Interface Enable" "0: Disable the IR interface,1: Enable the IR interface"
newline
bitfld.long 0x00 6. "TXMPTYEN,Transmitter Empty Interrupt Enable" "0: Disable the transmitter FIFO empty interrupt,1: Enable the transmitter FIFO empty interrupt"
bitfld.long 0x00 5. "RTSDEN,RTS Delta Interrupt Enable" "0: Disable RTSD interrupt,1: Enable RTSD interrupt"
newline
bitfld.long 0x00 4. "SNDBRK,Send BREAK" "0: Do not send a BREAK character,1: Send a BREAK character (continuous 0s)"
bitfld.long 0x00 3. "TXDMAEN,Transmitter Ready DMA Enable" "0: Disable transmit DMA request,1: Enable transmit DMA request"
newline
bitfld.long 0x00 2. "ATDMAEN,Aging DMA Timer Enable" "0: Disable AGTIM DMA request,1: Enable AGTIM DMA request"
bitfld.long 0x00 1. "DOZE,DOZE" "0: The UART is enabled when in DOZE state,1: The UART is disabled when in DOZE state"
newline
bitfld.long 0x00 0. "UARTEN,UART Enable" "0: Disable the UART,1: Enable the UART"
group.long 0x84++0x03
line.long 0x00 "UCR2,UART Control Register 2"
bitfld.long 0x00 15. "ESCI,Escape Sequence Interrupt Enable" "0: Disable the escape sequence interrupt,1: Enable the escape sequence interrupt"
bitfld.long 0x00 14. "IRTS,Ignore RTS Pin" "0: Transmit only when the RTS pin is asserted,1: Ignore the RTS pin"
newline
bitfld.long 0x00 13. "CTSC,CTS Pin Control" "0: The CTS_B pin is controlled by the CTS bit,1: The CTS_B pin is controlled by the receiver"
bitfld.long 0x00 12. "CTS,Clear to Send" "0: The CTS_B pin is high (inactive),1: The CTS_B pin is low (active)"
newline
bitfld.long 0x00 11. "ESCEN,Escape Enable" "0: Disable escape sequence detection,1: Enable escape sequence detection"
bitfld.long 0x00 9.--10. "RTEC,Request to Send Edge Control" "0: Trigger interrupt on a rising edge,1: Trigger interrupt on a falling edge,2: Trigger interrupt on any edge,3: Trigger interrupt on any edge"
newline
bitfld.long 0x00 8. "PREN,Parity Enable" "0: Disable parity generator and checker,1: Enable parity generator and checker"
bitfld.long 0x00 7. "PROE,Parity Odd/Even" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x00 6. "STPB,Stop" "0: The transmitter sends 1 stop bit,1: The transmitter sends 2 stop bits"
bitfld.long 0x00 5. "WS,Word Size" "0: 7-bit transmit and receive character length..,1: 8-bit transmit and receive character length.."
newline
bitfld.long 0x00 4. "RTSEN,Request to Send Interrupt Enable" "0: Disable request to send interrupt,1: Enable request to send interrupt"
bitfld.long 0x00 3. "ATEN,Aging Timer Enable" "0: AGTIM interrupt disabled,1: AGTIM interrupt enabled"
newline
bitfld.long 0x00 2. "TXEN,Transmitter Enable" "0: Disable the transmitter,1: Enable the transmitter"
bitfld.long 0x00 1. "RXEN,Receiver Enable" "0: Disable the receiver,1: Enable the receiver"
newline
bitfld.long 0x00 0. "SRST,Software Reset" "0: Reset the transmit and receive state machines..,1: No reset"
group.long 0x88++0x03
line.long 0x00 "UCR3,UART Control Register 3"
bitfld.long 0x00 14.--15. "DPEC,This bit is not used in this chip" "0,1,2,3"
bitfld.long 0x00 13. "DTREN,This bit is not used in this chip" "0,1"
newline
bitfld.long 0x00 12. "PARERREN,Parity Error Interrupt Enable" "0: Disable the parity error interrupt,1: Enable the parity error interrupt"
bitfld.long 0x00 11. "FRAERREN,Frame Error Interrupt Enable" "0: Disable the frame error interrupt,1: Enable the frame error interrupt"
newline
bitfld.long 0x00 10. "DSR,This bit is not used in this chip" "0,1"
bitfld.long 0x00 9. "DCD,This bit is not used in this chip" "0,1"
newline
bitfld.long 0x00 8. "RI,This bit is not used in this chip" "0,1"
bitfld.long 0x00 7. "ADNIMP,Autobaud Detection Not Improved" "0: Autobaud detection new features selected,1: Keep old autobaud detection mechanism"
newline
bitfld.long 0x00 6. "RXDSEN,Receive Status Interrupt Enable" "0: Disable the RXDS interrupt,1: Enable the RXDS interrupt"
bitfld.long 0x00 5. "AIRINTEN,Asynchronous IR WAKE Interrupt Enable" "0: Disable the AIRINT interrupt,1: Enable the AIRINT interrupt"
newline
bitfld.long 0x00 4. "AWAKEN,Asynchronous WAKE Interrupt Enable" "0: Disable the AWAKE interrupt,1: Enable the AWAKE interrupt"
bitfld.long 0x00 3. "DTRDEN,This bit is not used in this chip" "0,1"
newline
bitfld.long 0x00 2. "RXDMUXSEL,RXD Muxed Input Selected" "0,1"
bitfld.long 0x00 1. "INVT,Invert TXD output in RS-232/RS-485 mode set TXD active level in IrDA mode" "0: TXD is not inverted,1: TXD is inverted"
newline
bitfld.long 0x00 0. "ACIEN,Autobaud Counter Interrupt Enable" "0: ACST interrupt disabled,1: ACST interrupt enabled"
group.long 0x8C++0x03
line.long 0x00 "UCR4,UART Control Register 4"
bitfld.long 0x00 10.--15. "CTSTL,CTS Trigger Level" "0: 0 characters received,1: 1 characters in the RxFIFO,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: 32 characters in the RxFIFO (maximum),?..."
bitfld.long 0x00 9. "INVR,Invert RXD input in RS-232/RS-485 Mode determine RXD input logic level being sampled in In IrDA mode" "0: RXD input is not inverted,1: RXD input is inverted"
newline
bitfld.long 0x00 8. "ENIRI,Serial Infrared Interrupt Enable" "0: Serial infrared Interrupt disabled,1: Serial infrared Interrupt enabled"
bitfld.long 0x00 7. "WKEN,WAKE Interrupt Enable" "0: Disable the WAKE interrupt,1: Enable the WAKE interrupt"
newline
bitfld.long 0x00 6. "IDDMAEN,DMA IDLE Condition Detected Interrupt Enable Enables/Disables the receive DMA request dma_req_rx for the IDLE interrupt (triggered with IDLE flag in USR2[12])" "0: DMA IDLE interrupt disabled,1: DMA IDLE interrupt enabled"
bitfld.long 0x00 5. "IRSC,IR Special Case" "0: The vote logic uses the sampling clock (16x..,1: The vote logic uses the UART reference clock"
newline
bitfld.long 0x00 4. "LPBYP,Low Power Bypass" "0: Low power features enabled,1: Low power features disabled"
bitfld.long 0x00 3. "TCEN,Transmit Complete Interrupt Enable" "0: Disable TXDC interrupt,1: Enable TXDC interrupt"
newline
bitfld.long 0x00 2. "BKEN,BREAK Condition Detected Interrupt Enable" "0: Disable the BRCD interrupt,1: Enable the BRCD interrupt"
bitfld.long 0x00 1. "OREN,Receiver Overrun Interrupt Enable" "0: Disable ORE interrupt,1: Enable ORE interrupt"
newline
bitfld.long 0x00 0. "DREN,Receive Data Ready Interrupt Enable" "0: Disable RDR interrupt,1: Enable RDR interrupt"
group.long 0x90++0x03
line.long 0x00 "UFCR,UART FIFO Control Register"
bitfld.long 0x00 10.--15. "TXTL,Transmitter Trigger Level" "?,?,2: TxFIFO has 2 or fewer characters,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: TxFIFO has 31 or fewer characters,32: TxFIFO has 32 characters (maximum),?..."
bitfld.long 0x00 7.--9. "RFDIV,Reference Frequency Divider" "0: Divide input clock by 6,1: Divide input clock by 5,2: Divide input clock by 4,3: Divide input clock by 3,4: Divide input clock by 2,5: Divide input clock by 1,6: Divide input clock by 7,?..."
newline
bitfld.long 0x00 6. "DCEDTE,DCE/DTE mode select" "0: DCE mode selected,1: DTE mode selected"
bitfld.long 0x00 0.--5. "RXTL,Receiver Trigger Level" "0: 0 characters received,1: RxFIFO has 1 character,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: RxFIFO has 31 characters,32: RxFIFO has 32 characters (maximum),?..."
group.long 0x94++0x03
line.long 0x00 "USR1,UART Status Register 1"
eventfld.long 0x00 15. "PARITYERR,Parity Error Interrupt Flag" "0: No parity error detected,1: Parity error detected (write 1 to clear)"
rbitfld.long 0x00 14. "RTSS,RTS_B Pin Status" "0: The RTS_B module input is high (inactive),1: The RTS_B module input is low (active)"
newline
rbitfld.long 0x00 13. "TRDY,Transmitter Ready Interrupt / DMA Flag" "0: The transmitter does not require data,1: The transmitter requires data (interrupt.."
eventfld.long 0x00 12. "RTSD,RTS Delta" "0: RTS_B pin did not change state since last..,1: RTS_B pin changed state (write 1 to clear)"
newline
eventfld.long 0x00 11. "ESCF,Escape Sequence Interrupt Flag" "0: No escape sequence detected,1: Escape sequence detected (write 1 to clear)"
eventfld.long 0x00 10. "FRAMERR,Frame Error Interrupt Flag" "0: No frame error detected,1: Frame error detected (write 1 to clear)"
newline
rbitfld.long 0x00 9. "RRDY,Receiver Ready Interrupt / DMA Flag" "0: No character ready,1: Character(s) ready (interrupt posted)"
eventfld.long 0x00 8. "AGTIM,Ageing Timer Interrupt Flag" "0: AGTIM is not active,1: AGTIM is active (write 1 to clear)"
newline
eventfld.long 0x00 7. "DTRD,This bit is not used in this chip" "0,1"
rbitfld.long 0x00 6. "RXDS,Receiver IDLE Interrupt Flag" "0: Receive in progress,1: Receiver is IDLE"
newline
eventfld.long 0x00 5. "AIRINT,Asynchronous IR WAKE Interrupt Flag" "0: No pulse was detected on the RXD IrDA pin,1: A pulse was detected on the RXD IrDA pin"
eventfld.long 0x00 4. "AWAKE,Asynchronous WAKE Interrupt Flag" "0: No falling edge was detected on the RXD..,1: A falling edge was detected on the RXD Serial.."
newline
eventfld.long 0x00 3. "SAD,RS-485 Slave Address Detected Interrupt Flag" "0: No slave address detected,1: Slave address detected"
group.long 0x98++0x03
line.long 0x00 "USR2,UART Status Register 2"
eventfld.long 0x00 15. "ADET,Automatic Baud Rate Detect Complete" "0: ASCII A or a was not received,1: ASCII A or a was received (write 1 to clear)"
rbitfld.long 0x00 14. "TXFE,Transmit Buffer FIFO Empty" "0: The transmit buffer (TxFIFO) is not empty,1: The transmit buffer (TxFIFO) is empty"
newline
eventfld.long 0x00 13. "DTRF,This bit is not used in this chip" "0,1"
eventfld.long 0x00 12. "IDLE,Idle Condition" "0: No idle condition detected,1: Idle condition detected (write 1 to clear)"
newline
eventfld.long 0x00 11. "ACST,Autobaud Counter Stopped" "0: Measurement of bit length not finished (in..,1: Measurement of bit length finished (in.."
eventfld.long 0x00 10. "RIDELT,This bit is not used in this chip" "0,1"
newline
rbitfld.long 0x00 9. "RIIN,This bit is not used in this chip" "0,1"
eventfld.long 0x00 8. "IRINT,Serial Infrared Interrupt Flag" "0: no edge detected,1: valid edge detected (write 1 to clear)"
newline
eventfld.long 0x00 7. "WAKE,Wake" "0: start bit not detected,1: start bit detected (write 1 to clear)"
eventfld.long 0x00 6. "DCDDELT,This bit is not used in this chip" "0,1"
newline
rbitfld.long 0x00 5. "DCDIN,This bit is not used in this chip" "0,1"
eventfld.long 0x00 4. "RTSF,RTS Edge Triggered Interrupt Flag" "0: Programmed edge not detected on RTS_B,1: Programmed edge detected on RTS_B (write 1 to.."
newline
rbitfld.long 0x00 3. "TXDC,Transmitter Complete" "0: Transmit is incomplete,1: Transmit is complete"
eventfld.long 0x00 2. "BRCD,BREAK Condition Detected" "0: No BREAK condition was detected,1: A BREAK condition was detected (write 1 to.."
newline
eventfld.long 0x00 1. "ORE,Overrun Error" "0: No overrun error,1: Overrun error (write 1 to clear)"
rbitfld.long 0x00 0. "RDR,Receive Data Ready-Indicates that at least 1 character is received and written to the RxFIFO" "0: No receive data ready,1: Receive data ready"
group.long 0x9C++0x03
line.long 0x00 "UESC,UART Escape Character Register"
hexmask.long.byte 0x00 0.--7. 1. "ESC_CHAR,UART Escape Character"
group.long 0xA0++0x03
line.long 0x00 "UTIM,UART Escape Timer Register"
hexmask.long.word 0x00 0.--11. 1. "TIM,UART Escape Timer"
group.long 0xA4++0x03
line.long 0x00 "UBIR,UART BRM Incremental Register"
hexmask.long.word 0x00 0.--15. 1. "INC,Incremental Numerator"
group.long 0xA8++0x03
line.long 0x00 "UBMR,UART BRM Modulator Register"
hexmask.long.word 0x00 0.--15. 1. "MOD,Modulator Denominator"
rgroup.long 0xAC++0x03
line.long 0x00 "UBRC,UART Baud Rate Count Register"
hexmask.long.word 0x00 0.--15. 1. "BCNT,Baud Rate Count Register"
group.long 0xB0++0x03
line.long 0x00 "ONEMS,UART One Millisecond Register"
hexmask.long.tbyte 0x00 0.--23. 1. "ONEMS,One Millisecond Register"
group.long 0xB4++0x03
line.long 0x00 "UTS,UART Test Register"
bitfld.long 0x00 13. "FRCPERR,Force Parity Error" "0: Generate normal parity,1: Generate inverted parity (error)"
bitfld.long 0x00 12. "LOOP,Loop TX and RX for Test" "0: Normal receiver operation,1: Internally connect the transmitter output to.."
newline
bitfld.long 0x00 11. "DBGEN,This bit is not used in this chip" "0: UART will go into debug mode when debug_req..,1: UART will not go into debug mode even if.."
bitfld.long 0x00 10. "LOOPIR,Loop TX and RX for IR Test (LOOPIR)" "0: No IR loop,1: Connect IR transmitter to IR receiver"
newline
bitfld.long 0x00 9. "RXDBG,This bit is not used in this chip" "0: rx fifo read pointer does not increment,1: rx_fifo read pointer increments as normal"
bitfld.long 0x00 6. "TXEMPTY,TxFIFO Empty" "0: The TxFIFO is not empty,1: The TxFIFO is empty"
newline
bitfld.long 0x00 5. "RXEMPTY,RxFIFO Empty" "0: The RxFIFO is not empty,1: The RxFIFO is empty"
bitfld.long 0x00 4. "TXFULL,TxFIFO FULL" "0: The TxFIFO is not full,1: The TxFIFO is full"
newline
bitfld.long 0x00 3. "RXFULL,RxFIFO FULL" "0: The RxFIFO is not full,1: The RxFIFO is full"
bitfld.long 0x00 0. "SOFTRST,Software Reset" "0: Software reset inactive,1: Software reset active"
group.long 0xB8++0x03
line.long 0x00 "UMCR,UART RS-485 Mode Control Register"
hexmask.long.byte 0x00 8.--15. 1. "SLADDR,RS-485 Slave Address Character"
bitfld.long 0x00 3. "SADEN,RS-485 Slave Address Detected Interrupt Enable" "0: Disable RS-485 Slave Address Detected Interrupt,1: Enable RS-485 Slave Address Detected Interrupt"
newline
bitfld.long 0x00 2. "TXB8,Transmit RS-485 bit 8 (the ninth bit or 9th bit)" "0: 0 will be transmitted as the RS485 9th data bit,1: 1 will be transmitted as the RS485 9th data bit"
bitfld.long 0x00 1. "SLAM,RS-485 Slave Address Detect Mode Selection" "0: Select Normal Address Detect mode,1: Select Automatic Address Detect mode"
newline
bitfld.long 0x00 0. "MDEN,9-bit data or Multidrop Mode (RS-485) Enable" "0: Normal RS-232 or IrDA mode see for detail,1: Enable RS-485 mode see for detail"
tree.end
repeat.end
tree.end
tree "USB (Universal Serial Bus)"
repeat 2. (list 1. 2.) (list ad:0x38100000 ad:0x38200000)
tree "USB$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "CAPLENGTH,Capability registers length and Host Controller Operational Registers"
hexmask.long.word 0x00 16.--31. 1. "HCIVERSION,HC Interface Version Number (HCIVERSION)"
newline
hexmask.long.byte 0x00 0.--7. 1. "CAPLENGTH,Capability Registers Length (CAPLENGTH)"
rgroup.long 0x04++0x03
line.long 0x00 "HCSPARAMS1,Structural Parameters 1 Register"
hexmask.long.byte 0x00 24.--31. 1. "MAXPORTS,Number of Ports (MaxPorts) - Number of ports implemented is defined by the parameter (`DWC_USB3_HOST_NUM_U2_ROOT_PORTS + `DWC_USB3_HOST_NUM_U3_ROOT_PORTS) - Number of ports enabled is controlled by the core input signals.."
newline
hexmask.long.word 0x00 8.--18. 1. "MAXINTRS,Number of Interrupters (MaxIntrs) Defined by the configurable parameter `DWC_USB3_HOST_NUM_INTERRUPTER_SUPT"
newline
hexmask.long.byte 0x00 0.--7. 1. "MAXSLOTS,Number of device slots (MaxSlots) Defined by configurable parameter `DWC_USB3_NUM_DEVICE_SUPT"
rgroup.long 0x08++0x03
line.long 0x00 "HCSPARAMS2,Structural Parameters 2 Register"
bitfld.long 0x00 27.--31. "MAXSCRATCHPADBUFS,Max Scratchpad Bufs Lo The value is calculated based on chosen configuration parameter values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 26. "SPR,Scratchpad Restore (SPR)" "0,1"
newline
bitfld.long 0x00 21.--25. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Bufs HI The core automatically updates this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "ERSTMAX,Event Ring Segment Table Max (ERST Max)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "IST,Isochronous Scheduling Threshold (IST)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x0C++0x03
line.long 0x00 "HCSPARAMS3,Structural Parameters 3 Register"
hexmask.long.word 0x00 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 Device Exit Latency"
newline
hexmask.long.byte 0x00 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 Device Exit Latency"
rgroup.long 0x10++0x03
line.long 0x00 "HCCPARAMS1,Capability Parameters 1 Register"
hexmask.long.word 0x00 16.--31. 1. "XECP,xHCI Extended Capabilities Pointer (xECP) Based on configuration core automatically updates it"
newline
bitfld.long 0x00 12.--15. "MAXPSASIZE,Maximum Primary Stream Array Size (MaxPSASize) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "CFC,Contiguous Frame ID Capability (CFC)" "0,1"
newline
bitfld.long 0x00 10. "SEC,Stopped EDLTA Capability (SEC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 9. "SPC,Short Packet Capability (SPC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 8. "PAE,Parse All Event Data (PAE) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 7. "NSS,No Secondary SID Support (NSS) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 6. "LTC,Latency Tolerance Messaging Capability (LTC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 5. "LHRC,Light HC Reset Capability For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 4. "PIND,Port Indicators (PIND) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 3. "PPC,Port Power Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 2. "CSZ,Context Size (CSZ) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 1. "BNC,BW Negotiation Capability (BNC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
newline
bitfld.long 0x00 0. "AC64,64-bit Addressing Capability (AC64) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "DBOFF,Doorbell Offset Register"
hexmask.long 0x00 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Doorbell Array Offset - RO Based on configuration core automatically updates it"
rgroup.long 0x18++0x03
line.long 0x00 "RTSOFF,Runtime Register Space Offset Register"
hexmask.long 0x00 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Runtime Register Space Offset Based on configuration core automatically updates it"
rgroup.long 0x1C++0x03
line.long 0x00 "HCCPARAMS2,Host Controller Capability Parameters 2"
bitfld.long 0x00 5. "CIC,Configuration Information Capability (CIC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 4. "LEC,Large ESIT Payload Capability (LEC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 3. "CTC,Compliance Transition Capability (CTC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 2. "FSC,Force Save Context Capability (FSC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 1. "CMC,Configure Endpoint Command Max Exit Latency Too Large Capability (CMC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 0. "U3C,U3 Entry Capability (U3C) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3" "0,1"
group.long 0x20++0x03
line.long 0x00 "USBCMD,USB Command Register"
bitfld.long 0x00 13. "CME,CEM Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 11. "EU3S,EU3S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 10. "EWE,EWE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 9. "CRS,Controller Restore State This command is similar to the USBCMD" "0,1"
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bitfld.long 0x00 8. "CSS,Controller Save State This command is similar to the USBCMD" "0,1"
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bitfld.long 0x00 7. "LHCRST,Light Host Controller Reset For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 3. "HSEE,HSEE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 2. "INTE,INTE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 1. "HCRST,HCRST The following bits reset the internal logic of the host controller" "0,1"
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bitfld.long 0x00 0. "R_S,R_S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
group.long 0x24++0x03
line.long 0x00 "USBSTS,USB Status Register"
rbitfld.long 0x00 12. "HCE,Host Controller Error (HCE) - RO Default = 0" "0,1"
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rbitfld.long 0x00 11. "CNR,Controller Not Ready (CNR) - RO Default = '1'" "0,1"
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bitfld.long 0x00 10. "SRE,Save/Restore Error This bit is currently not supported" "0,1"
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rbitfld.long 0x00 9. "RSS,Restore State Status This bit is similar to the USBSTS" "0,1"
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rbitfld.long 0x00 8. "SSS,Save State Status This bit is similar to the USBSTS" "0,1"
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bitfld.long 0x00 4. "PCD,Reset Value for PCD" "0,1"
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bitfld.long 0x00 3. "EINT,Reset Value for EINT" "0,1"
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bitfld.long 0x00 2. "HSE,HSE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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rbitfld.long 0x00 0. "HCH,HCH For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "PAGESIZE,Page Size Register"
hexmask.long.word 0x00 0.--15. 1. "PAGE_SIZE,PAGE_SIZE"
group.long 0x34++0x03
line.long 0x00 "DNCTRL,Device Notification Register"
hexmask.long.word 0x00 0.--15. 1. "N0_N15,N0_N15 For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x38++0x03
line.long 0x00 "CRCR_LO,CRCR_LO"
hexmask.long 0x00 6.--31. 1. "CMD_RING_PNTR,CMD_RING_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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rbitfld.long 0x00 3. "CRR,CRR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 2. "CA,CA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 1. "CS,CS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 0. "RCS,RCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
group.long 0x3C++0x03
line.long 0x00 "CRCR_HI,CRCR_HI"
hexmask.long 0x00 0.--31. 1. "CMD_RING_PNTR,COMMAND_RING_POINTER Reading this field always returns '0'"
group.long 0x50++0x03
line.long 0x00 "DCBAAP_LO,DCBAAP_LO"
hexmask.long 0x00 6.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x54++0x03
line.long 0x00 "DCBAAP_HI,DCBAAP_HI"
hexmask.long 0x00 0.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP"
group.long 0x58++0x03
line.long 0x00 "CONFIG,Configuration Register"
bitfld.long 0x00 9. "CIE,Configuration Information Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 8. "U3E,U3 Entry Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "MAXSLOTSEN,MAXSLOTSEN For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x420++0x03
line.long 0x00 "PORTSC_20,Port Status and Control Register"
rbitfld.long 0x00 30. "DR,Reset value" "0,1"
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bitfld.long 0x00 27. "WOE,WOE" "0,1"
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bitfld.long 0x00 26. "WDE,WDE" "0,1"
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bitfld.long 0x00 25. "WCE,WCE" "0,1"
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rbitfld.long 0x00 24. "CAS,CAS" "0,1"
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eventfld.long 0x00 22. "PLC,PLC" "0,1"
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eventfld.long 0x00 21. "PRC,PRC" "0,1"
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eventfld.long 0x00 20. "OCC,OCC" "0,1"
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eventfld.long 0x00 18. "PEC,For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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eventfld.long 0x00 17. "CSC,CSC" "0,1"
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bitfld.long 0x00 16. "LWS,LWS" "0,1"
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bitfld.long 0x00 14.--15. "PIC,PIC" "0,1,2,3"
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rbitfld.long 0x00 10.--13. "PORTSPEED,PORTSPEED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 9. "PP,PP" "0,1"
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bitfld.long 0x00 5.--8. "PLS,PLS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4. "PR,PR" "0,1"
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rbitfld.long 0x00 3. "OCA,OCA" "0,1"
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eventfld.long 0x00 1. "PED,PED" "0,1"
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rbitfld.long 0x00 0. "CCS,For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
group.long 0x424++0x03
line.long 0x00 "PORTPMSC_20,USB3 Port Power Management Status and Control Register"
bitfld.long 0x00 28.--31. "PRTTSTCTRL,Port Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16. "HLE,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "L1DSLOT,L1DSLOT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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bitfld.long 0x00 4.--7. "HIRD,Host Initiated Resume Duration (HIRD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "RWE,RWE Port Test Control" "0,1"
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rbitfld.long 0x00 0.--2. "L1S,L1 Status (L1S)" "0,1,2,3,4,5,6,7"
rgroup.long 0x428++0x03
line.long 0x00 "PORTLI_20,Port Link Info Register Programming this field with random data will cause side effect i"
group.long 0x42C++0x03
line.long 0x00 "PORTHLPMC_20,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0 Reset Mask:0xFFFFC000"
bitfld.long 0x00 10.--13. "HIRDD,PORTHLPMC_20 HIRDD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 2.--9. 1. "L1_TIMEOUT,PORTHLPMC_20 L1_TIMEOUT"
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bitfld.long 0x00 0.--1. "HIRDM,Host Initiated Resume Duration Mode (HIRDM) - RWS" "0,1,2,3"
group.long 0x430++0x03
line.long 0x00 "PORTSC_30,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted"
bitfld.long 0x00 31. "WPR,For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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rbitfld.long 0x00 30. "DR,For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 27. "WOE,WOE" "0,1"
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bitfld.long 0x00 26. "WDE,WDE" "0,1"
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bitfld.long 0x00 25. "WCE,WCE" "0,1"
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rbitfld.long 0x00 24. "CAS,Cold Attach Status" "0,1"
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eventfld.long 0x00 23. "CEC,CEC" "0,1"
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eventfld.long 0x00 22. "PLC,PLC" "0,1"
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eventfld.long 0x00 21. "PRC,PRC" "0,1"
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eventfld.long 0x00 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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eventfld.long 0x00 19. "WRC,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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eventfld.long 0x00 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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eventfld.long 0x00 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1,2,3"
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rbitfld.long 0x00 10.--13. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 5.--8. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_30_REGS/PORTSC_30/PR VolatileMemory 1 Programming this field with random data will cause side effect" "0,1"
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rbitfld.long 0x00 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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eventfld.long 0x00 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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rbitfld.long 0x00 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
group.long 0x434++0x03
line.long 0x00 "PORTPMSC_30,USB3 Port Power Management Status and Control Register"
bitfld.long 0x00 16. "FLA,FLA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "U2_TIMEOUT,U2_TIMEOUT"
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hexmask.long.byte 0x00 0.--7. 1. "U1_TIMEOUT,U1_TIMEOUT"
rgroup.long 0x438++0x03
line.long 0x00 "PORTLI_30,Port Link Info Register"
hexmask.long.word 0x00 0.--15. 1. "LINK_ERROR_COUNT,LINK_ERROR_COUNT"
rgroup.long 0x43C++0x03
line.long 0x00 "PORTHLPMC_30,USB2 Port Hardware LPM Control Register"
rgroup.long 0x440++0x03
line.long 0x00 "MFINDEX,Microframe Index Register"
hexmask.long.word 0x00 0.--13. 1. "MICROFRAME_INDEX,MICROFRAME_INDEX For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x460++0x03
line.long 0x00 "IMAN,Interrupter Management Register"
bitfld.long 0x00 1. "IE,For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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eventfld.long 0x00 0. "IP,IP Interrupt Pending" "0,1"
group.long 0x464++0x03
line.long 0x00 "IMOD,Interrupter Moderation Register"
hexmask.long.word 0x00 16.--31. 1. "IMODC,Interrupt Moderation Counter (IMODC) - RW"
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hexmask.long.word 0x00 0.--15. 1. "IMODI,Interrupt Moderation Interval (IMODI) - RW"
group.long 0x468++0x03
line.long 0x00 "ERSTSZ,ERSTSZ"
hexmask.long.word 0x00 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x470++0x03
line.long 0x00 "ERSTBA_LO,ERSTBA_LO"
hexmask.long 0x00 6.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR"
group.long 0x474++0x03
line.long 0x00 "ERSTBA_HI,ERSTBA_HI"
hexmask.long 0x00 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x478++0x03
line.long 0x00 "ERDP_LO,ERDP_LO"
hexmask.long 0x00 4.--31. 1. "ERD_PNTR,ERD_PNTR"
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eventfld.long 0x00 3. "EHB,EHB" "0,1"
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bitfld.long 0x00 0.--2. "DESI,DESI - For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1,2,3,4,5,6,7"
group.long 0x47C++0x03
line.long 0x00 "ERDP_HI,ERDP_HI"
hexmask.long 0x00 0.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x480++0x03
line.long 0x00 "DB,Doorbell Register"
hexmask.long.word 0x00 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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hexmask.long.byte 0x00 0.--7. 1. "DB_TARGET,DB_TARGET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
group.long 0x880++0x03
line.long 0x00 "USBLEGSUP,USBLEGSUP"
bitfld.long 0x00 24. "HC_OS_OWNED,HC_OS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 16. "HC_BIOS_OWNED,HC_BIOS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID set_register_field_attribute DWC_usb3_map/DWC_usb3_block_HC_Extended_Capability_Register/USBLEGSUP/CAPABILITY_ID RegisterResetValue 0x1 For a description of this standard USB register field see the eXtensible Host Controller.."
group.long 0x884++0x03
line.long 0x00 "USBLEGCTLSTS,USBLEGCTLSTS"
bitfld.long 0x00 31. "SMI_ON_BAR,SMI_ON_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 30. "SMI_ON_PCI,SMI_ON_PCI COMMAND For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 29. "SMI_ON_OS,SMI_ON_OS OWNERSHIP CHANGE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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rbitfld.long 0x00 20. "SMI_ON_HOST,SMI_ON_HOST SYSTEM ERROR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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rbitfld.long 0x00 16. "SMI_ON_EVENT,SMI_ON_EVENT INTERRUPT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 15. "SMI_ON_BAR_E,SMI_ON_BAR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 14. "SMI_ON_PCI_E,SMI_ON_PCI COMMAND ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 13. "SMI_ON_OS_E,SMI_ON_OS OWNERSHIP ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 4. "SMI_ON_HOST_E,SMI_ON_HOST SYSTEM ERROR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
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bitfld.long 0x00 0. "USB_SMI_ENABLE,USB_SMI_ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3" "0,1"
rgroup.long 0x890++0x03
line.long 0x00 "SUPTPRT2_DW0,SUPTPRT2_DW0"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION"
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hexmask.long.byte 0x00 16.--23. 1. "MINOR_REVISION,MINOR_REVISION"
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hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER"
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hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
rgroup.long 0x894++0x03
line.long 0x00 "SUPTPRT2_DW1,SUPTPRT2_DW1 Register"
hexmask.long 0x00 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
rgroup.long 0x898++0x03
line.long 0x00 "SUPTPRT2_DW2,xHCI Supported Protocol Capability_ Data Word 2"
bitfld.long 0x00 28.--31. "PSIC,PSIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 25.--27. "MHD,Hub Depth" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "BLC,BESL LPM Capability" "0,1"
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bitfld.long 0x00 19. "HLC,Compatible Port Offset" "0,1"
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bitfld.long 0x00 18. "IHI,IHI" "0,1"
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bitfld.long 0x00 17. "HSO,HSO" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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hexmask.long.byte 0x00 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
rgroup.long 0x89C++0x03
line.long 0x00 "SUPTPRT2_DW3,SUPTPRT2_DW3 Register"
bitfld.long 0x00 0.--4. "PROTCL_SLT_TY,Protocol Slot Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x8A0++0x03
line.long 0x00 "SUPTPRT3_DW0,Register SUPTPRT3_DW0"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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hexmask.long.byte 0x00 16.--23. 1. "MINOR_REVISION,MINOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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hexmask.long.byte 0x00 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
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hexmask.long.byte 0x00 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3"
rgroup.long 0x8A4++0x03
line.long 0x00 "SUPTPRT3_DW1,SUPTPRT3_DW1 Register"
hexmask.long 0x00 0.--31. 1. "NAME_STRING,NAME_STRING"
rgroup.long 0x8A8++0x03
line.long 0x00 "SUPTPRT3_DW2,SUPTPRT3_DW2"
bitfld.long 0x00 28.--31. "PSIC,PSIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 25.--27. "MHD,Hub Depth" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT"
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hexmask.long.byte 0x00 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET"
rgroup.long 0x8AC++0x03
line.long 0x00 "SUPTPRT3_DW3,SUPTPRT3_DW3"
bitfld.long 0x00 0.--4. "PROTCL_SLT_TY,Protocol Slot Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC100++0x03
line.long 0x00 "GSBUSCFG0,Global SoC Bus Configuration Register 0"
bitfld.long 0x00 28.--31. "DATRDREQINFO,DATRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Read (DatRdReqInfo) Input to BUS-GM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "DESRDREQINFO,DESRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read (DesRdReqInfo)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "DATWRREQINFO,DATWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Write (DatWrReqInfo)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DESWRREQINFO,DESWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write (DesWrReqInfo) Input to BUS-GM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "DATBIGEND,Data Access is Big Endian This bit controls the endian mode for data accesses" "0,1"
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bitfld.long 0x00 10. "DESBIGEND,Descriptor Access is Big Endian This bit controls the endian mode for descriptor accesses" "0,1"
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bitfld.long 0x00 7. "INCR256BRSTENA,INCR256 Burst Type Enable Input to BUS-GM" "0,1"
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bitfld.long 0x00 6. "INCR128BRSTENA,INCR128 Burst Type Enable Input to BUS-GM For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 128-beat burst" "0,1"
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bitfld.long 0x00 5. "INCR64BRSTENA,INCR64 Burst Type Enable - Input to BUS-GM For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 64-beat burst" "0,1"
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bitfld.long 0x00 4. "INCR32BRSTENA,INCR32BRSTENA" "0,1"
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bitfld.long 0x00 3. "INCR16BRSTENA,INCR16BRSTENA" "0,1"
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bitfld.long 0x00 2. "INCR8BRSTENA,INCR8BRSTENA" "0,1"
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bitfld.long 0x00 1. "INCR4BRSTENA,INCR4BRSTENA" "0,1"
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bitfld.long 0x00 0. "INCRBRSTENA,INCRBRSTENA" "0,1"
group.long 0xC104++0x03
line.long 0x00 "GSBUSCFG1,Global SoC Bus Configuration Register 1"
bitfld.long 0x00 12. "EN1KPAGE,1k Page Boundary Enable By default (this bit is disabled) the AXI breaks transfers at the 4k page boundary" "0,1"
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bitfld.long 0x00 8.--11. "PipeTransLimit,AXI Pipelined Transfers Burst Request Limit The field controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC108++0x03
line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register"
bitfld.long 0x00 29. "UsbTxPktCntSel,USB Transmit Packet Count Enable This field enables/disables the USB transmission multi-packet thresholding" "0,1"
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bitfld.long 0x00 24.--27. "UsbTxPktCnt,USB Transmit Packet Count This field specifies the number of packets that must be in the TXFIFO before the core can start transmission for the corresponding USB transaction (burst)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 16.--23. 1. "UsbMaxTxBurstSize,USB Maximum TX Burst Size When UsbTxPktCntSel is one this field specifies the Maximum Bulk OUT burst the core can do"
group.long 0xC10C++0x03
line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register"
bitfld.long 0x00 29. "UsbRxPktCntSel,USB Receive Packet Count Enable This field enables/disables the USB reception multi-packet thresholding" "0,1"
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bitfld.long 0x00 24.--27. "UsbRxPktCnt,USB Receive Packet Count In host mode this field specifies the space (in terms of the number of packets) that must be available in the RX FIFO before the core can start the corresponding USB RX transaction (burst)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19.--23. "UsbMaxRxBurstSize,USB Maximum Receive Burst Size In host mode this field specifies the Maximum Bulk IN burst the DWC_usb3 core can perform" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--12. 1. "ResvISOCOUTSpc,Space reserved in Rx FIFO for ISOC OUT In host mode this field is not applicable and must be programmed to 0"
group.long 0xC110++0x03
line.long 0x00 "GCTL,Global Core Control Register"
hexmask.long.word 0x00 19.--31. 1. "PWRDNSCALE,Power Down Scale (PwrDnScale) The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to a small part of the USB3 core that operates when the SS PHY is in its lowest power (P3) state and therefore does not provide a clock"
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bitfld.long 0x00 18. "MASTERFILTBYPASS,Master Filter Bypass When this bit is set to 1'b1 irrespective of the parameter `DWC_USB3_EN_BUS_FILTERS chosen all the filters in the DWC_usb3_filter module are bypassed" "0,1"
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bitfld.long 0x00 17. "BYPSSETADDR,Bypass SetAddress in Device Mode" "0,1"
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bitfld.long 0x00 16. "U2RSTECN,U2RSTECN If the SuperSpeed connection fails during POLL or LMP exchange the device connects at non-SS mode" "0,1"
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bitfld.long 0x00 14.--15. "FRMSCLDWN,FRMSCLDWN This field scales down device view of a SOF/USOF/ITP duration" "0,1,2,3"
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bitfld.long 0x00 12.--13. "PRTCAPDIR,PRTCAPDIR: Port Capability Direction (PrtCapDir)" "?,1: for Host configurations,2: for Device configurations,?..."
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bitfld.long 0x00 11. "CORESOFTRESET,Core Soft Reset (CoreSoftReset)" "0: No soft reset,1: Soft reset to core Clears the interrupts"
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bitfld.long 0x00 10. "SOFITPSYNC,SOFITPSYNC If this bit is set to '0' operating in host mode the core keeps the UTMI/ULPI PHY on the first port in a non-suspended state whenever there is a SuperSpeed port that is not in Rx" "0,1"
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bitfld.long 0x00 9. "U1U2TimerScale,Disable U1/U2 timer Scaledown (U1U2TimerScale)" "0,1"
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bitfld.long 0x00 8. "DEBUGATTACH,Debug Attach When this bit is set - SS Link proceeds directly to the Polling link state (after RUN/STOP in the DCTL register is asserted) without checking remote termination - Link LFPS polling timeout is infinite - Polling timeout during.." "0,1"
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bitfld.long 0x00 6.--7. "RAMCLKSEL,RAM Clock Select (RAMClkSel)" "0: bus clock,1: pipe clock (Only used in device mode),2: In device mode pipe/2 clock,?..."
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bitfld.long 0x00 4.--5. "SCALEDOWN,Scale-Down Mode (ScaleDown) When Scale-Down mode is enabled for simulation the core uses scaled-down timing values resulting in faster simulations" "0,1,2,3"
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bitfld.long 0x00 3. "DISSCRAMBLE,Disable Scrambling (DisScramble) Transmit request to Link Partner on next transition to Recovery or Polling" "0,1"
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bitfld.long 0x00 2. "U2EXIT_LFPS,U2EXIT_LFPS If this bit is" "0,1"
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rbitfld.long 0x00 1. "GblHibernationEn,GblHibernationEn This bit enables hibernation at the global level" "0,1"
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bitfld.long 0x00 0. "DSBLCLKGTNG,Disable Clock Gating (DsblClkGtng) This bit is set to 1 and the core is in Low Power mode internal clock gating is disabled" "0,1"
group.long 0xC118++0x03
line.long 0x00 "GSTS,Global Status Register"
hexmask.long.word 0x00 20.--31. 1. "CBELT,Current BELT Value In Host mode this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command"
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rbitfld.long 0x00 11. "SSIC_IP,SSIC interrupt pending (SSIC_IP) This field indicates that there is a pending interrupt related to SSIC in the SEVT register" "0,1"
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rbitfld.long 0x00 9. "BC_IP,Battery Charger Interrupt Pending This field indicates that there is a pending interrupt pertaining to BC in BCEVT register" "0,1"
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rbitfld.long 0x00 7. "Host_IP,Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue" "0,1"
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rbitfld.long 0x00 6. "Device_IP,Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue" "0,1"
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bitfld.long 0x00 5. "CSRTimeout,CSR Timeout When this bit is 1'b1 it indicates that the software performed a write or read to a core register that could not be completed within `DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: h1FFFF)" "0,1"
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bitfld.long 0x00 4. "BUSERRADDRVLD,Bus Error Address Valid (BusErrAddrVld) Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error" "0,1"
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rbitfld.long 0x00 0.--1. "CURMOD,Current Mode of Operation (CurMod) Indicates the current mode of operation" "0: Device mode,1: Host mode,?..."
group.long 0xC11C++0x03
line.long 0x00 "GUCTL1,Global User Control Register 1"
bitfld.long 0x00 31. "DEV_DECOUPLE_L1L2_EVT,DEV_DECOUPLE_L1L2_EVT" "0,1"
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bitfld.long 0x00 30. "DS_RXDET_MAX_TOUT_CTRL,DS_RXDET_MAX_TOUT_CTRL This bit is used to control the tRxDetectTimeoutDFP timer for the SuperSpeed link" "0,1"
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bitfld.long 0x00 29. "FILTER_SE0_FSLS_EOP,FILTER_SE0_FSLS_EOP" "0: Default behavior no change in Linestate check,1: Feature enabled FS/LS SE0 is filtered for 2"
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bitfld.long 0x00 28. "TX_IPGAP_LINECHECK_DIS,TX_IPGAP_LINECHECK_DIS" "0: Default behavior no change in Linestate check,1: Feature enabled 2"
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bitfld.long 0x00 27. "DEV_TRB_OUT_SPR_IND,DEV_TRB_OUT_SPR_IND" "0: Default behavior no change in TRB status dword,1: Feature enabled OUT TRB status indicates Short"
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bitfld.long 0x00 26. "DEV_FORCE_20_CLK_FOR_30_CLK,DEV_FORCE_20_CLK_FOR_30_CLK" "0,1"
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bitfld.long 0x00 25. "P3_IN_U2,P3_IN_U2" "0,1"
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bitfld.long 0x00 24. "DEV_L1_EXIT_BY_HW,DEV_L1_EXIT_BY_HW" "0: Default behavior disables device L1 hardware,1: feature enabled This bit is applicable for"
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bitfld.long 0x00 21.--23. "IP_GAP_ADD_ON,This register field is used to add on to the default inter packet gap setting in the USB 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "DEV_LSP_TAIL_LOCK_DIS,DEV_LSP_TAIL_LOCK_DIS" "0: Default behavior enables device lsp lock logic,1: Fix disabled This is a bug fix for STAR"
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bitfld.long 0x00 19. "NAK_PER_ENH_FS,NAK_PER_ENH_FS" "0: Enhancement not applied If a periodic endpoint,1: Enables performance enhancement for FS async"
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bitfld.long 0x00 18. "NAK_PER_ENH_HS,NAK_PER_ENH_HS" "0: Enhancement not applied If a periodic endpoint,1: Enables performance enhancement for HS async"
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bitfld.long 0x00 17. "PARKMODE_DISABLE_SS,PARKMODE_DISABLE_SS This bit is used only in host mode and is for debug purpose only" "0,1"
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bitfld.long 0x00 16. "PARKMODE_DISABLE_HS,PARKMODE_DISABLE_HS This bit is used only in host mode" "0,1"
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bitfld.long 0x00 15. "PARKMODE_DISABLE_FSLS,PARKMODE_DISABLE_FSLS This bit is used only in host mode and is for debug purpose only" "0,1"
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bitfld.long 0x00 10. "RESUME_OPMODE_HS_HOST,RESUME_OPMODE_HS_HOST This bit is used only in host mode and is for USB 2" "0,1"
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bitfld.long 0x00 9. "DEV_HS_NYET_BULK_SPR,DEV_HS_NYET_BULK_SPR" "0: Default behavior no change in device response,1: Feature enabled HS bulk OUT short packet gets"
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bitfld.long 0x00 8. "L1_SUSP_THRLD_EN_FOR_HOST,L1_SUSP_THRLD_EN_FOR_HOST This bit is used only in host mode" "0,1"
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bitfld.long 0x00 4.--7. "L1_SUSP_THRLD_FOR_HOST,L1_SUSP_THRLD_FOR_HOST This field is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "HC_ERRATA_ENABLE,Host ELD Enable (HELDEn) When this bit is set to 1 it enables the Exit Latency Delta (ELD) support defined in the xHCI 1" "0,1"
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bitfld.long 0x00 2. "HC_PARCHK_DISABLE,Host Parameter Check Disable (HParChkDisable) When this bit is set to '0' (by default) the xHC checks that the input slot/EP context fields comply to the xHCI Specification" "0,1"
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bitfld.long 0x00 1. "OVRLD_L1_SUSP_COM,OVRLD_L1_SUSP_COM If this bit is set the utmi_l1_suspend_com_n is overloaded with the utmi_sleep_n signal" "0,1"
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bitfld.long 0x00 0. "LOA_FILTER_EN,LOA_FILTER_EN If this bit is set the USB 2" "0,1"
group.long 0xC128++0x03
line.long 0x00 "GUID,Global User ID Register"
hexmask.long 0x00 0.--31. 1. "USERID,USERID Application-programmable ID field"
group.long 0xC12C++0x03
line.long 0x00 "GUCTL,Global User Control Register"
hexmask.long.word 0x00 22.--31. 1. "REFCLKPER,REFCLKPER This field indicates in terms of nano seconds the period of ref_clk"
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bitfld.long 0x00 21. "NoExtrDl,No Extra Delay Between SOF and the First Packet(NoExtrDl) Some HS devices misbehave when the host sends a packet immediately after a SOF" "0,1"
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bitfld.long 0x00 17. "SprsCtrlTransEn,Sparse Control Transaction Enable Some devices are slow in responding to Control transfers" "0,1"
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bitfld.long 0x00 16. "ResBwHSEPS,Reserving 85% Bandwidth for HS Periodic EPs (ResBwHSEPS) By default HC reserves 80% of the bandwidth for periodic EPs" "0,1"
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bitfld.long 0x00 14. "USBHstInAutoRetryEn,Host IN Auto Retry (USBHstInAutoRetryEn) When set this field enables the Auto Retry feature" "0,1"
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bitfld.long 0x00 13. "EnOverlapChk,Enable Check for LFPS Overlap During Remote Ux Exit: If this bit is set to" "0,1"
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bitfld.long 0x00 12. "ExtCapSupptEN,External Extended Capability Support Enable (ExtCapSuptEN) When set this field enables extended capabilities to be implemented outside the core" "0,1"
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bitfld.long 0x00 11. "InsrtExtrFSBODI,Insert Extra Delay Between FS Bulk OUT Transactions (InsrtExtrFSBODl)" "0,1"
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bitfld.long 0x00 9.--10. "DTCT,Device Timeout Coarse Tuning (DTCT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout" "0,1,2,3"
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hexmask.long.word 0x00 0.--8. 1. "DTFT,Device Timeout Fine Tuning (DTFT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout"
rgroup.long 0xC130++0x03
line.long 0x00 "GBUSERRADDRLO,Gobal SoC Bus Error Address Register - Low"
hexmask.long 0x00 0.--31. 1. "BUSERRADDR,Bus Address - Low (BusAddrLo) This register contains the lower 32 bits of the first bus address that encountered a SoC bus error"
rgroup.long 0xC134++0x03
line.long 0x00 "GBUSERRADDRHI,Gobal SoC Bus Error Address Register - High"
hexmask.long 0x00 0.--31. 1. "BUSERRADDR,Bus Address - High (BusAddrHi) This register contains the higher 32 bits of the first bus address that encountered a SoC bus error"
group.long 0xC138++0x03
line.long 0x00 "GPRTBIMAPLO,Global SS Port to Bus Instance Mapping Register - Low"
bitfld.long 0x00 28.--31. "BINUM8,BINUM8: SS USB Instance Number for Port 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "BINUM7,BINUM7: SS USB Instance Number for Port 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "BINUM6,BINUM6: SS USB Instance Number for Port 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "BINUM5,BINUM5: SS USB Instance Number for Port 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "BINUM4,BINUM4: SS USB Instance Number for Port 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "BINUM3,BINUM3: SS USB Instance Number for Port 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "BINUM2,BINUM2: SS USB Instance Number for Port 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "BINUM1,BINUM1: SS USB Instance Number for Port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC13C++0x03
line.long 0x00 "GPRTBIMAPHI,Global SS Port to Bus Instance Mapping Register - High"
bitfld.long 0x00 24.--27. "BINUM15,BINUM15: SS USB Instance Number for Port 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "BINUM14,BINUM14: SS USB Instance Number for Port 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "BINUM13,BINUM13: SS USB Instance Number for Port 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "BINUM12,BINUM12: SS USB Instance Number for Port 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "BINUM11,BINUM11: SS USB Instance Number for Port 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "BINUM10,BINUM10: SS USB Instance Number for Port 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "BINUM9,BINUM9: SS USB Instance Number for Port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xC140++0x03
line.long 0x00 "GHWPARAMS0,Global Hardware Parameters Register 0"
hexmask.long.byte 0x00 24.--31. 1. "ghwparams0_31_24,`DWC_USB3_AWIDTH"
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hexmask.long.byte 0x00 16.--23. 1. "ghwparams0_23_16,`DWC_USB3_SDWIDTH"
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hexmask.long.byte 0x00 8.--15. 1. "ghwparams0_15_8,`DWC_USB3_MDWIDTH"
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bitfld.long 0x00 6.--7. "ghwparams0_7_6,`DWC_USB3_SBUS_TYPE" "0,1,2,3"
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bitfld.long 0x00 3.--5. "ghwparams0_5_3,`DWC_USB3_MBUS_TYPE" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "ghwparams0_2_0,`DWC_USB3_MODE" "0,1,2,3,4,5,6,7"
rgroup.long 0xC144++0x03
line.long 0x00 "GHWPARAMS1,Global Hardware Parameters Register 1"
bitfld.long 0x00 31. "ghwparams1_31,`DWC_USB3_EN_DBC" "0,1"
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bitfld.long 0x00 30. "ghwparams1_30,`DWC_USB3_RM_OPT_FEATURES" "0,1"
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bitfld.long 0x00 28. "ghwparams1_28,`DWC_USB3_RAM_BUS_CLKS_SYNC" "0,1"
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bitfld.long 0x00 27. "ghwparams1_27,`DWC_USB3_MAC_RAM_CLKS_SYNC" "0,1"
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bitfld.long 0x00 26. "ghwparams1_26,`DWC_USB3_MAC_PHY_CLKS_SYNC" "0,1"
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bitfld.long 0x00 24.--25. "ghwparams1_25_24,`DWC_USB3_EN_PWROPT" "0,1,2,3"
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bitfld.long 0x00 23. "ghwparams1_23,`DWC_USB3_SPRAM_TYP" "0,1"
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bitfld.long 0x00 21.--22. "ghwparams1_22_21,`DWC_USB3_NUM_RAMS" "0,1,2,3"
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bitfld.long 0x00 15.--20. "ghwparams1_20_15,`DWC_USB3_DEVICE_NUM_INT For details on `DWC_USB3_DEVICE_NUM_INT refer to <workspace>/src/DWC_usb3_params" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 12.--14. "ghwparams1_14_12,`DWC_USB3_ASPACEWIDTH" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "ghwparams1_11_9,`DWC_USB3_REQINFOWIDTH" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--8. "ghwparams1_8_6,`DWC_USB3_DATAINFOWIDTH" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--5. "ghwparams1_5_3,`DWC_USB3_BURSTWIDTH-1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "ghwparams1_2_0,`DWC_USB3_IDWIDTH-1" "0,1,2,3,4,5,6,7"
rgroup.long 0xC148++0x03
line.long 0x00 "GHWPARAMS2,Global Hardware Parameters Register 2"
hexmask.long 0x00 0.--31. 1. "ghwparams2_31_0,`DWC_USB3_USERID"
rgroup.long 0xC14C++0x03
line.long 0x00 "GHWPARAMS3,Global Hardware Parameters Register 3"
hexmask.long.byte 0x00 23.--30. 1. "ghwparams3_30_23,`DWC_USB3_CACHE_TOTAL_XFER_RESOURCES"
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bitfld.long 0x00 18.--22. "ghwparams3_22_18,`DWC_USB3_NUM_IN_EPS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--17. "ghwparams3_17_12,`DWC_USB3_NUM_EPS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 11. "ghwparams3_11,`DWC_USB3_ULPI_CARKIT" "0,1"
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bitfld.long 0x00 10. "ghwparams3_10,`DWC_USB3_VENDOR_CTL_INTERFACE" "0,1"
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bitfld.long 0x00 6.--7. "ghwparams3_7_6,`DWC_USB3_HSPHY_DWIDTH" "0,1,2,3"
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bitfld.long 0x00 4.--5. "ghwparams3_5_4,`DWC_USB3_FSPHY_INTERFACE" "0,1,2,3"
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bitfld.long 0x00 2.--3. "ghwparams3_3_2,`DWC_USB3_HSPHY_INTERFACE" "0,1,2,3"
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bitfld.long 0x00 0.--1. "ghwparams3_1_0,`DWC_USB3_SSPHY_INTERFACE" "0,1,2,3"
rgroup.long 0xC150++0x03
line.long 0x00 "GHWPARAMS4,Global Hardware Parameters Register 4"
bitfld.long 0x00 28.--31. "ghwparams4_31_28,`DWC_USB3_BMU_LSP_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "ghwparams4_27_24,`DWC_USB3_BMU_PTL_DEPTH-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "ghwparams4_23,`DWC_USB3_EN_ISOC_SUPT" "0,1"
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bitfld.long 0x00 21. "ghwparams4_21,`DWC_USB3_EXT_BUFF_CONTROL" "0,1"
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bitfld.long 0x00 17.--20. "ghwparams4_20_17,`DWC_USB3_NUM_SS_USB_INSTANCES" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 13.--16. "ghwparams4_16_13,`DWC_USB3_HIBER_SCRATCHBUFS Number of external scratchpad buffers the core requires to save its internal state in the device mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "ghwparams4_12,`DWC_USB3_EN_SSIC" "0: if DWC_USB3_EN_SSIC ==,1: if DWC_USB3_EN_SSIC != 0"
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bitfld.long 0x00 11. "ghwparams4_11,`DWC_USB3_SSIC_NON_SNPS_MPHY This field indicates whether Synopsys M-PHY or a third-party M-PHY is used with SSIC ports" "0,1"
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bitfld.long 0x00 9.--10. "ghwparams4_10_9,`DWC_USB3_SSIC_GEAR This field indicates DWC_USB3_SSIC_GEAR parameter value chosen by the user" "0: Reserved,1: HS-G1,2: HS-G2,3: HS-G3"
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bitfld.long 0x00 7.--8. "ghwparams4_8_7,`DWC_USB3_NUM_SSIC_NUM_LANE This bit indicates `DWC_USB3_SSIC_NUM_LANE parameter value chosen by the user" "0: 4 lane,1: 1 lane,2: 2 lane,3: Reserved"
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bitfld.long 0x00 0.--5. "ghwparams4_5_0,`DWC_USB3_CACHE_TRBS_PER_TRANSFER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xC154++0x03
line.long 0x00 "GHWPARAMS5,Global Hardware Parameters Register 5"
bitfld.long 0x00 22.--27. "ghwparams5_27_22,`DWC_USB3_DFQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "ghwparams5_21_16,`DWC_USB3_DWQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 10.--15. "ghwparams5_15_10,`DWC_USB3_TXQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--9. "ghwparams5_9_4,`DWC_USB3_RXQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--3. "ghwparams5_3_0,`DWC_USB3_BMU_BUSGM_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xC158++0x03
line.long 0x00 "GHWPARAMS6,Global Hardware Parameters Register 6"
hexmask.long.word 0x00 16.--31. 1. "ghwparams6_31_16,`DWC_USB3_RAM0_DEPTH"
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bitfld.long 0x00 15. "BusFltrsSupport,`DWC_USB3_EN_BUS_FILTERS" "0,1"
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bitfld.long 0x00 14. "BCSupport,`DWC_USB3_EN_BC" "0,1"
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bitfld.long 0x00 8.--9. "ghwparams6_9_8,Reserved" "0,1,2,3"
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bitfld.long 0x00 7. "ghwparams6_7,`DWC_USB3_EN_FPGA" "0,1"
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bitfld.long 0x00 6. "ghwparams6_6,`DWC_USB3_EN_DBG_PORTS" "0,1"
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bitfld.long 0x00 0.--5. "ghwparams6_5_0,`DWC_USB3_PSQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xC15C++0x03
line.long 0x00 "GHWPARAMS7,Global Hardware Parameters Register 7"
hexmask.long.word 0x00 16.--31. 1. "ghwparams7_31_16,`DWC_USB3_RAM2_DEPTH"
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hexmask.long.word 0x00 0.--15. 1. "ghwparams7_15_0,`DWC_USB3_RAM1_DEPTH"
group.long 0xC180++0x03
line.long 0x00 "GPRTBIMAP_HSLO,Global High-Speed Port to Bus Instance Mapping Register - Low"
bitfld.long 0x00 28.--31. "BINUM8,BINUM8: HS USB Instance Number for Port 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "BINUM7,BINUM7: HS USB Instance Number for Port 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "BINUM6,BINUM6 USB Instance Number for Port 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "BINUM5,BINUM5: HS USB Instance Number for Port 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "BINUM4,BINUM4: HS USB Instance Number for Port 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "BINUM3,BINUM3: HS USB Instance Number for Port 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "BINUM2,BINUM2: HS USB Instance Number for Port 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "BINUM1,BINUM1: HS USB Instance Number for Port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC184++0x03
line.long 0x00 "GPRTBIMAP_HSHI,Global High-Speed Port to Bus Instance Mapping Register - High"
bitfld.long 0x00 24.--27. "BINUM15,BINUM15: HS USB Instance Number for Port 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "BINUM14,BINUM14: HS USB Instance Number for Port 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "BINUM13,BINUM13: HS USB Instance Number for Port 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "BINUM12,BINUM12: HS USB Instance Number for Port 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "BINUM11,BINUM11: HS USB Instance Number for 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "BINUM10,BINUM10: HS USB Instance Number for Port 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "BINUM9,BINUM9: HS USB Instance Number for Port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC188++0x03
line.long 0x00 "GPRTBIMAP_FSLO,Global Full-Speed Port to Bus Instance Mapping Register - Low"
bitfld.long 0x00 28.--31. "BINUM8,BINUM8: FS USB Instance Number for Port 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "BINUM7,BINUM7: FS USB Instance Number for Port 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "BINUM6,BINUM6: FS USB Instance Number for Port 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "BINUM5,BINUM5: FS USB Instance Number for Port 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "BINUM4,BINUM4: FS USB Instance Number for Port 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "BINUM3,BINUM3: FS USB Instance Number for Port 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "BINUM2,BINUM2: FS USB Instance Number for Port 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "BINUM1,BINUM1: FS USB Instance Number for Port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC18C++0x03
line.long 0x00 "GPRTBIMAP_FSHI,Global Full-Speed Port to Bus Instance Mapping Register - High"
bitfld.long 0x00 24.--27. "BINUM15,BINUM15: FS USB Instance Number for Port 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "BINUM14,BINUM14: FS USB Instance Number for Port 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "BINUM13,BINUM13: FS USB Instance Number for Port 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "BINUM12,BINUM12: FS USB Instance Number for Port 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "BINUM11,BINUM11: FS USB Instance Number for Port 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "BINUM10,BINUM10: FS USB Instance Number for Port 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "BINUM9,BINUM9: FS USB Instance Number for Port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC19C++0x03
line.long 0x00 "GUCTL2,Global User Control Register 2"
hexmask.long.byte 0x00 19.--25. 1. "EN_HP_PM_TIMER,This register field is used to set new HP and PM timers"
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bitfld.long 0x00 15.--18. "NOLOWPWRDUR,No Low Power Duration (NOLOWPWRDUR) This bit is applicable for device mode only and is ignored in host mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 14. "Rst_actbitlater,Enable clearing of the command active bit for the ENDXFER command after the command execution is completed" "0,1"
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bitfld.long 0x00 12. "EnableEpCacheEvict,Enable Evicting Endpoint cache after Flow Control for bulk endpoints" "0,1"
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bitfld.long 0x00 11. "DisableCFC,Disable xHCI Errata Feature Contiguous Frame ID Capability This field controls the xHCI Errata feature Contiguous FrameID capability" "0,1"
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bitfld.long 0x00 5.--10. "RxPingDuration,Recieve Ping Maximum Duration This field is relevant to Host mode and controls the maximum duration of received LFPS to be treated as a Ping LFPS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--4. "TxPingDuration,Transmit Ping Maximum Duration This field is relevant to Device mode and controls the maximum duration for which the controller should instruct the PHY to transmit a Ping LFPS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC200++0x03
line.long 0x00 "GUSB2PHYCFG,Global USB2 PHY Configuration Register"
bitfld.long 0x00 31. "PHYSOFTRST,UTMI PHY Soft Reset (PHYSoftRst) Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY" "0,1"
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bitfld.long 0x00 30. "U2_FREECLK_EXISTS,U2_FREECLK_EXISTS Specifies whether your USB 2" "0,1"
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bitfld.long 0x00 29. "ULPI_LPM_WITH_OPMODE_CHK,ULPI_LPM_WITH_OPMODE_CHK Support the LPM over ULPI without NOPID token to the ULPI PHY" "0,1"
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rbitfld.long 0x00 27.--28. "HSIC_CON_WIDTH_ADJ,HSIC_CON_WIDTH_ADJ This bit is used in the HSIC device mode of operation" "0,1,2,3"
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rbitfld.long 0x00 26. "INV_SEL_HSIC,INV_SEL_HSIC The application driver uses this bit to control the HSIC enable/disable function" "0,1"
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bitfld.long 0x00 22.--24. "LSTRD,LS Turnaround Time (LSTRDTIM) This field indicates the value of the Rx-to-Tx packet gap for LS devices" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--21. "LSIPD,LS Inter-Packet Time (LSIPD) This field indicates the value of Tx-to-Tx packet gap for LS devices" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18. "ULPIEXTVBUSINDIACTOR,ULPI External VBUS Indicator (ULPIExtVbusIndicator) Indicates the ULPI PHY VBUS over-current indicator" "0,1"
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bitfld.long 0x00 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive 5V on VBUS in the ULPI PHY" "0,1"
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bitfld.long 0x00 15. "ULPIAUTORES,ULPI Auto Resume (ULPIAutoRes) Sets the AutoResume bit in Interface Control register on the ULPI PHY" "0,1"
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bitfld.long 0x00 10.--13. "USBTRDTIM,USB 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 9. "XCVRDLY,Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp" "0,1"
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bitfld.long 0x00 8. "ENBLSLPM,Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state" "0,1"
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bitfld.long 0x00 7. "PHYSEL,USB 2" "0,1"
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bitfld.long 0x00 6. "SUSPENDUSB20,Suspend USB2" "0,1"
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rbitfld.long 0x00 5. "FSINTF,Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1" "0,1"
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rbitfld.long 0x00 4. "ULPI_UTMI_Sel,ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface" "0,1"
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bitfld.long 0x00 3. "PHYIF,PHY Interface (PHYIf) If UTMI+ is selected the application uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "0,1"
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bitfld.long 0x00 0.--2. "TOutCal,HS/FS Timeout Calibration (TOutCal) The number of PHY clocks as indicated by the application in this field is multiplied by a bit-time factor this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account.." "0,1,2,3,4,5,6,7"
rgroup.long 0xC280++0x03
line.long 0x00 "GUSB2PHYACC_ULPI,Global USB 2.0 UTMI PHY vendor control register"
bitfld.long 0x00 26. "DISUIPIDRVR,DISUIPIDRVR" "0,1"
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bitfld.long 0x00 25. "NEWREGREQ,New Register Request The application sets this bit for a new vendor control access" "0,1"
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bitfld.long 0x00 24. "VSTSDONE,VSTSDONE" "0,1"
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bitfld.long 0x00 23. "VSTSBSY,VSTSBSY" "0,1"
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bitfld.long 0x00 22. "REGWR,Register Write The application sets this bit for register writes and clears it for register reads" "0,1"
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bitfld.long 0x00 16.--21. "REGADDR,Register Address The 6-bit PHY register address for immediate PHY Register Set access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 8.--15. 1. "EXTREGADDR,EXTREGADDR"
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hexmask.long.byte 0x00 0.--7. 1. "REGDATA,REGDATA"
group.long 0xC2C0++0x03
line.long 0x00 "GUSB3PIPECTL,Global USB 3.0 PIPE control register"
bitfld.long 0x00 31. "PHYSoftRst,USB3 PHY Soft Reset After setting this bit to '1' the software needs to clear this bit" "0,1"
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bitfld.long 0x00 30. "HstPrtCmpl,HstPrtCmpl This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3" "0,1"
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bitfld.long 0x00 29. "U2P3ok,P3 OK for U2 (u2P3ok)" "0,1"
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bitfld.long 0x00 28. "DisRxDetP3,Disabled receiver detection in P3 (DisRxDetP3)" "0,1"
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bitfld.long 0x00 27. "Ux_exit_in_Px,Ux Exit in Px (Ux_exit_in_Px)" "0,1"
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bitfld.long 0x00 26. "ping_enhancement_en,Ping Enhancement Enable (ping_enhancement_en) When set the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms" "0,1"
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bitfld.long 0x00 25. "u1u2exitfail_to_recov,U1U2exitfail to Recovery (u1u2exitfail_to_recov) When set and U1/U2 LFPS handshake fails the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive" "0,1"
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bitfld.long 0x00 24. "request_p1p2p3,Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3) When set the core always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition" "0,1"
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bitfld.long 0x00 23. "StartRxDetU3RxDet,Start Receiver Detection in U3/Rx" "0,1"
newline
bitfld.long 0x00 22. "DisRxDetU3RxDet,Disable Receiver Detection in U3/Rx" "0,1"
newline
bitfld.long 0x00 19.--21. "DelayP1P2P3,Delay P1P2P3 Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8) 8B10B error occurs or Pipe3_RxValid drops to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 18. "DELAYP1TRANS,Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively" "0,1"
newline
bitfld.long 0x00 17. "SUSPENDENABLE,Suspend USB3" "0,1"
newline
rbitfld.long 0x00 15.--16. "DATWIDTH,PIPE Data Width (DatWidth)" "0: 32 bits,1: 16 bits,2: 8 bits One clock after,?..."
newline
bitfld.long 0x00 14. "AbortRxDetInU2,Abort Rx Detect in U2 (AbortRxDetInU2) When set and the link state is U2 then the core will abort receiver detection if it receives U2 exit LFPS from the remote link partner" "0,1"
newline
bitfld.long 0x00 13. "SkipRxDet,Skip Rx Detect: When set the core skips Rx Detection if pipe3_RxElecIdle is low" "0,1"
newline
bitfld.long 0x00 12. "LFPSP0Algn,LFPS P0 Align: When set - The core deasserts LFPS transmission on the clock edge that it requests Phy power state 0 when exiting U1 U2 or U3 low power states" "0,1"
newline
bitfld.long 0x00 11. "P3P2TranOK,P3 P2 Transitions OK (P3P2TranOK) When set the core transitions directly from Phy power state P2 to P3 or from state P3 to P2" "0,1"
newline
bitfld.long 0x00 10. "P3ExSigP2,P3 Exit Signal in P2 (P3ExSigP2) When this bit is set the core always changes the PHY power state to P2 before attempting a U3 exit handshake" "0,1"
newline
bitfld.long 0x00 9. "LFPSFILTER,LFPS Filter (LFPSFilt) When set filter LFPS reception with pipe3_RxValid in PHY power state P0 that is ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are deasserted" "0,1"
newline
bitfld.long 0x00 8. "RX_DETECT_to_Polling_LFPS_Control,RX_DETECT to Polling" "0,1"
newline
bitfld.long 0x00 7. "SSICEn,USB3 SSIC Enable (SSICEn) This bit is valid only when coreConsultant parameter DWC_USB3_EN_SSIC=1 else this bit needs to be set to 1'b0" "0,1"
newline
bitfld.long 0x00 6. "TX_SWING,Tx Swing (TxSwing) Refer to the PIPE3 specification" "0,1"
newline
bitfld.long 0x00 3.--5. "TX_MARGIN,Tx Margin[2:0] (TxMargin) Refer to Table 5-3 of the PIPE3 Specification" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 1.--2. "SS_TX_DE_EMPHASIS,Tx Deemphasis (TxDeemphasis) The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode" "0,1,2,3"
newline
bitfld.long 0x00 0. "ELASTIC_BUFFER_MODE,Elastic Buffer Mode (ElasticBufferMode) (Refer to Table 5-3 of the PIPE3 specification" "0,1"
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0xC300)++0x03
line.long 0x00 "GTXFIFOSIZ[$1],Global transmit FIFO size register $1"
hexmask.long.word 0x00 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words"
newline
hexmask.long.word 0x00 0.--15. 1. "TXFDEP_N,TXFIFO depth"
repeat.end
repeat 3. (increment 0 1) (increment 0 0x04)
group.long ($2+0xC380)++0x03
line.long 0x00 "GRXFIFOSIZ[$1],Global receive FIFO size register $1"
hexmask.long.word 0x00 16.--31. 1. "RXFSTADDR_N,RxFIFOn RAM Start Address (RxFStAddr_n) This field contains the memory start address for RxFIFOn in MDWIDTH-bit words"
newline
hexmask.long.word 0x00 0.--15. 1. "RXFDEP_N,RxFIFO Depth (RxFDep_n) This field contains the depth of RxFIFOn in MDWIDTH-bit words"
repeat.end
group.long 0xC400++0x03
line.long 0x00 "GEVNTADRLO,Global Event Buffer Address (Low) Register"
hexmask.long 0x00 0.--31. 1. "EVNTADRLO,Event Buffer Address (EvntAdrLo) Holds the lower 32 bits of start address of the external memory for the Event Buffer"
group.long 0xC404++0x03
line.long 0x00 "GEVNTADRHI,Global Event Buffer Address (High) Register"
hexmask.long 0x00 0.--31. 1. "EVNTADRHI,Event Buffer Address (EvntAdrHi) Holds the higher 32 bits of start address of the external memory for the Event Buffer"
group.long 0xC408++0x03
line.long 0x00 "GEVNTSIZ,Global event buffer size register"
bitfld.long 0x00 31. "EVNTINTRPTMASK,Event Interrupt Mask (EvntIntMask)" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "EVENTSIZ,Event Buffer Size in bytes (EVNTSiz) Holds the size of the Event Buffer in bytes must be a multiple of four"
group.long 0xC40C++0x03
line.long 0x00 "GEVNTCOUNT,Global event buffer count register"
bitfld.long 0x00 31. "EVNT_HANDLER_BUSY,Event Handler Busy Device software event handler busy indication" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "EVNTCOUNT,Event Count (EVNTCount) When read returns the number of valid events in the Event Buffer (in bytes)"
rgroup.long 0xC600++0x03
line.long 0x00 "GHWPARAMS8,Global Hardware Parameters Register 8"
hexmask.long 0x00 0.--31. 1. "ghwparams8_32_0,`DWC_USB3_DCACHE_DEPTH_INFO"
group.long 0xC610++0x03
line.long 0x00 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "gtxfifopridev,Device TxFIFO priority"
group.long 0xC618++0x03
line.long 0x00 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register"
bitfld.long 0x00 0.--3. "gtxfifoprihst,Host TxFIFO priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC61C++0x03
line.long 0x00 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register"
bitfld.long 0x00 0.--2. "grxfifoprihst,Host RxFIFO priority" "0,1,2,3,4,5,6,7"
group.long 0xC620++0x03
line.long 0x00 "GFIFOPRIDBC,Global Host Debug Capability DMA Priority Register"
bitfld.long 0x00 0.--1. "gfifopridbc,Host DbC DMA priority" "0,1,2,3"
group.long 0xC624++0x03
line.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs"
bitfld.long 0x00 8.--12. "hstrxfifo,Host RXFIFO DMA High-Low Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "hsttxfifo,Host TXFIFO DMA High-Low Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC630++0x03
line.long 0x00 "GFLADJ,Global Frame Length Adjustment Register"
bitfld.long 0x00 31. "GFLADJ_REFCLK_240MHZDECR_PLS1,GFLADJ_REFCLK_240MHZDECR_PLS1 This field indicates that the decrement value that the controller applies for each ref_clk must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk" "0,1"
newline
hexmask.long.byte 0x00 24.--30. 1. "GFLADJ_REFCLK_240MHZ_DECR,This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock"
newline
bitfld.long 0x00 23. "GFLADJ_REFCLK_LPM_SEL,This bit enables the functionality of running SOF/ITP counters on the ref_clk" "0,1"
newline
hexmask.long.word 0x00 8.--21. 1. "GFLADJ_REFCLK_FLADJ,This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk"
newline
bitfld.long 0x00 7. "GFLADJ_30MHZ_SDBND_SEL,GFLADJ_30MHZ_SDBND_SEL This field selects whether to use the input signal fladj_30mhz_reg or the GFLADJ" "0,1"
newline
bitfld.long 0x00 0.--5. "GFLADJ_30MHZ,GFLADJ_30MHZ This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC700++0x03
line.long 0x00 "DCFG,Device Configuration Register"
bitfld.long 0x00 23. "IgnStrmPP,IgnoreStreamPP This bit only affects stream-capable bulk endpoints" "0,1"
newline
bitfld.long 0x00 22. "LPMCAP,LPM Capable The application uses this bit to control the DWC_usb3 core LPM capabilities" "0,1"
newline
bitfld.long 0x00 17.--21. "NUMP,Number of Receive Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12.--16. "INTRNUM,Interrupt number Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 3.--9. 1. "DEVADDR,Device Address"
newline
bitfld.long 0x00 0.--2. "DEVSPD,Device Speed" "0: no description available,1: no description available,?,?,4: no description available,?..."
group.long 0xC704++0x03
line.long 0x00 "DCTL,Device control register"
bitfld.long 0x00 31. "RUN_STOP,Run/Stop The software writes 1 to this bit to start the device controller operation" "0,1"
newline
bitfld.long 0x00 30. "CSFTRST,Core Soft Reset Resets the all clock domains as follows: - This bit clears the interrupts and all the CSRs except GSTS GSNPSID GGPIO GUID GUSB2PHYCFGn registers GUSB3PIPECTLn registers DCFG DCTL DEVTEN and DSTS registers" "0,1"
newline
bitfld.long 0x00 24.--28. "HIRDTHRES,HIRD Threshold (HIRD_Thres) The core asserts output signals utmi_l1_suspend_n and utmi_sleep_n (see LPM Interface Signals table in the Databook) on the basis of this signal: The core asserts utmi_l1_suspend_n to put the PHY into Deep Low-Power.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 20.--23. "LPM_NYET_thres,LPM NYET Threshold When LPM Errata is enabled: Bits [23:20]: LPM NYET Response Threshold (LPM_NYET_thres) Handshake response to LPM token specified by device application" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "KeepConnect,Keep Connect When '1' this bit enables the save and restore programming model by preventing the core from disconnecting from the host when DCTL" "0,1"
newline
bitfld.long 0x00 18. "L1HibernationEn,L1HibernationEn When this bit is set along with KeepConnect the device core generates a Hibernation Request Event if L1 is enabled and the HIRD value in the LPM token is larger than the threshold programmed in DCTL" "0,1"
newline
bitfld.long 0x00 17. "CRS,Controller Restore State (CRS) This command is similar to the USBCMD" "0,1"
newline
bitfld.long 0x00 16. "CSS,Controller Save State (CSS) This command is similar to the USBCMD" "0,1"
newline
bitfld.long 0x00 12. "INITU2ENA,Initiate U2 Enable" "0: May not initiate U2 (default),1: May initiate U2 On USB reset hardware clears"
newline
bitfld.long 0x00 11. "ACCEPTU2ENA,Accept U2 Enable" "0: Reject U2 except when Force_LinkPM_Accept bit..,1: Core accepts transition to U2 state if nothing"
newline
bitfld.long 0x00 10. "INITU1ENA,Initiate U1 Enable" "0: May not initiate U1 (default),1: May initiate U1"
newline
bitfld.long 0x00 9. "ACCEPTU1ENA,Accept U1 Enable" "0: Core rejects U1 except when Force_LinkPM_Accept,1: Core accepts transition to U1 state if nothing"
newline
bitfld.long 0x00 5.--8. "ULSTCHNGREQ,ULSTCHNGREQ Software writes this field to issue a USB/Link state change request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--4. "TSTCTL,Test Control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable - Others: Reserved,?..."
group.long 0xC708++0x03
line.long 0x00 "DEVTEN,Device Event Enable Register"
rbitfld.long 0x00 16. "ECCERREN,ECC Error Enable" "0,1"
newline
bitfld.long 0x00 14. "L1WKUPEVTEN,L1 Resume Detected Event Enable" "0,1"
newline
bitfld.long 0x00 12. "VENDEVTSTRCVDEN,Vendor Device Test LMP Received Event (VndrDevTstRcvedEn)" "0,1"
newline
bitfld.long 0x00 9. "ERRTICERREVTEN,Erratic Error Event Enable" "0,1"
newline
bitfld.long 0x00 8. "L1SUSPEN,L1 Suspend Event Enable Note: Only if GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled this bit is for L1 Suspend Event Enable" "0,1"
newline
bitfld.long 0x00 7. "SOFTEVTEN,Start of (u)frame" "0,1"
newline
bitfld.long 0x00 6. "U3L2L1SuspEn,U3/L2 or U3/L2L1 Suspend Event Enable" "0,1"
newline
bitfld.long 0x00 5. "HibernationReqEvtEn,This bit enables/disables the generation of the Hibernation Request Event" "0,1"
newline
bitfld.long 0x00 4. "WKUPEVTEN,U3/L2 or U3/L2L1 Resume Detected Event Enable" "0,1"
newline
bitfld.long 0x00 3. "ULSTCNGEN,USB/Link State Change Event Enable" "0,1"
newline
bitfld.long 0x00 2. "CONNECTDONEEVTEN,Connection Done Enable" "0,1"
newline
bitfld.long 0x00 1. "USBRSTEVTEN,USB Reset Enable" "0,1"
newline
bitfld.long 0x00 0. "DISSCONNEVTEN,Disconnect Detected Event Enable" "0,1"
group.long 0xC70C++0x03
line.long 0x00 "DSTS,Device Status Register"
rbitfld.long 0x00 29. "DCNRD,Device Controller Not Ready The bit indicates that the core is in the process of completing the state transitions after exiting from hibernation" "0,1"
newline
bitfld.long 0x00 28. "SRE,Save Restore Error" "0,1"
newline
rbitfld.long 0x00 25. "RSS,RSS Restore State Status This bit is similar to the USBSTS" "0,1"
newline
rbitfld.long 0x00 24. "SSS,SSS Save State Status This bit is similar to the USBSTS" "0,1"
newline
rbitfld.long 0x00 23. "COREIDLE,Core Idle The bit indicates that the core finished transferring all RxFIFO data to system memory writing out all completed descriptors and all Event Counts are zero" "0,1"
newline
rbitfld.long 0x00 22. "DEVCTRLHLT,Device Controller Halted This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1" "0,1"
newline
rbitfld.long 0x00 18.--21. "USBLNKST,USBLNKST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 17. "RXFIFOEMPTY,RxFIFO Empty" "0,1"
newline
hexmask.long.word 0x00 3.--16. 1. "SOFFN,Frame/Microframe Number of the Received SOF"
newline
rbitfld.long 0x00 0.--2. "CONNECTSPD,Connected Speed (ConnectSpd) Indicates the speed at which the DWC_usb3 core has come up after speed detection through a chirp sequence" "0: no description available,1: no description available,?,?,4: no description available,?..."
group.long 0xC710++0x03
line.long 0x00 "DGCMDPAR,Device Generic Command Parameter Register"
hexmask.long 0x00 0.--31. 1. "PARAMETER,PARAMETER"
group.long 0xC714++0x03
line.long 0x00 "DGCMD,Device Generic Command Register This register enables software to program the core using a single generic command interface to send link management packets and notifications.Reset Mask:0xFFFF0A00"
rbitfld.long 0x00 12.--15. "CMDSTATUS,Command Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10. "CMDACT,Command Active The software sets this bit to 1 to enable the device controller to execute the generic command" "0,1"
newline
bitfld.long 0x00 8. "CMDIOC,Command Interrupt on Complete When this bit is set the device controller issues a Generic Command Completion event after executing the command" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "CMDTYP,CMDTYP Generic Command Type Specifies the type of generic command the software driver is requesting the controller to perform"
group.long 0xC720++0x03
line.long 0x00 "DALEPENA,Device Active USB Endpoint Enable Register"
hexmask.long 0x00 0.--31. 1. "USBACTEP,USB active endpoints This bit indicates if a USB endpoint is active in the current configuration and interface"
group.long 0xC800++0x03
line.long 0x00 "DEPCMDPAR2,Device physical endpoint-n command parameter 2 register"
hexmask.long 0x00 0.--31. 1. "PARAMETER,PARAMETER"
group.long 0xC804++0x03
line.long 0x00 "DEPCMDPAR1,Device Physical Endpoint-n Command Parameter 1 Register"
hexmask.long 0x00 0.--31. 1. "PARAMETER,PARAMETER"
group.long 0xC808++0x03
line.long 0x00 "DEPCMDPAR0,Device Physical Endpoint-n Command Parameter 0 Register"
hexmask.long 0x00 0.--31. 1. "PARAMETER,PARAMETER"
group.long 0xC80C++0x03
line.long 0x00 "DEPCMD,Device Physical Endpoint-n Command Register"
hexmask.long.word 0x00 16.--31. 1. "COMMANDPARAM,Command Parameters or Event Parameters Command Parameters (CommandParam) when this register is written: For Start Transfer command: - [31:16]: StreamID"
newline
bitfld.long 0x00 12.--15. "CMDSTATUS,Command Completion Status (CmdStatus) Additional information about the completion of this command is available in this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 11. "HIPRI_FORCERM,HighPriority/ForceRM (HiPri_ForceRM) - HighPriority: Only valid for Start Transfer command - ForceRM: Only valid for End Transfer command - ClearPendIN: Only valid for Clear Stall command" "0,1"
newline
bitfld.long 0x00 10. "CMDACT,Command Active (CmdAct) Software sets this bit to 1 to enable the device endpoint controller to execute the generic command" "0,1"
newline
bitfld.long 0x00 8. "CMDIOC,CMDIOC Command Interrupt on Complete (CmdIOC) When this bit is set the device controller issues a generic Endpoint Command Complete event after executing the command" "0,1"
newline
bitfld.long 0x00 0.--3. "CMDTYP,Command Type Specifies the type of command the software driver is requesting the core to perform" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xCA00++0x03
line.long 0x00 "DEV_IMOD,Device Interrupt Moderation Register"
hexmask.long.word 0x00 16.--31. 1. "DEVICE_IMODC,Interrupt Moderation Down Counter Loaded with the DEVICE_IMODI value whenever the hardware interrupt(n) line is de-asserted from the asserted state counts down to 0 and stops"
newline
hexmask.long.word 0x00 0.--15. 1. "DEVICE_IMODI,Moderation Interval (DEVICE_IMODI) This field holds the minimum inter-interrupt interval between events"
group.long 0xCC30++0x03
line.long 0x00 "BCFG,BCFG"
bitfld.long 0x00 1. "IDDIG_SEL,IDDIG Select: When this bit is programmed as" "0,1"
newline
bitfld.long 0x00 0. "CHIRP_EN,Chirp Enable When this bit is 1'b1 the core asserts the bc_chirp_on output signal to indicate an imminent chirp" "0,1"
group.long 0xCC38++0x03
line.long 0x00 "BCEVT,BCEVT"
bitfld.long 0x00 24. "MV_ChngEvnt,Multi-Valued input changed Event: This event indicates that there is a change in the value of at least one ACA pin value" "0,1"
newline
rbitfld.long 0x00 0.--4. "MultValIdBc,Multi Valued ID pin Indicates the Battery Charger ACA inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xCC3C++0x03
line.long 0x00 "BCEVTEN,BCEVTEN"
bitfld.long 0x00 24. "MV_ChngEvntEna,BCEvtInfoEna[0] Multi-Valued input changed Event Enable (MV_ChngEvntEn) When this bit is set MV_ChngEvnt in BCEVT register is enabled" "0,1"
tree.end
repeat.end
tree.end
tree "USDHC (Ultra Secured Digital Host Controller)"
repeat 3. (list 1. 2. 3.) (list ad:0x30B40000 ad:0x30B50000 ad:0x30B60000)
tree "USDHC$1"
base $2
group.long 0x00++0x03
line.long 0x00 "DS_ADDR,DMA System Address"
hexmask.long 0x00 0.--31. 1. "DS_ADDR,System address"
group.long 0x04++0x03
line.long 0x00 "BLK_ATT,Block Attributes"
hexmask.long.word 0x00 16.--31. 1. "BLKCNT,Blocks count for current transfer"
newline
hexmask.long.word 0x00 0.--12. 1. "BLKSIZE,Transfer block size"
group.long 0x08++0x03
line.long 0x00 "CMD_ARG,Command Argument"
hexmask.long 0x00 0.--31. 1. "CMDARG,Command argument"
group.long 0x0C++0x03
line.long 0x00 "CMD_XFR_TYP,Command Transfer Type"
bitfld.long 0x00 24.--29. "CMDINX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 22.--23. "CMDTYP,Command type" "0: Normal other commands,1: Suspend CMD52 for writing bus suspend in CCCR,2: Resume CMD52 for writing function select in..,3: Abort CMD12 CMD52 for writing I/O Abort in CCCR"
newline
bitfld.long 0x00 21. "DPSEL,Data present select" "0: No data present,1: Data present"
newline
bitfld.long 0x00 20. "CICEN,Command index check enable" "0: Disable command index check,1: Enables command index check"
newline
bitfld.long 0x00 19. "CCCEN,Command CRC check enable" "0: Disables command CRC check,1: Enables command CRC check"
newline
bitfld.long 0x00 16.--17. "RSPTYP,Response type select" "0: No response,1: Response length 136,2: Response length 48,3: Response length 48 check busy after response"
rgroup.long 0x10++0x03
line.long 0x00 "CMD_RSP0,Command Response0"
hexmask.long 0x00 0.--31. 1. "CMDRSP0,Command response 0"
rgroup.long 0x14++0x03
line.long 0x00 "CMD_RSP1,Command Response1"
hexmask.long 0x00 0.--31. 1. "CMDRSP1,Command response 1"
rgroup.long 0x18++0x03
line.long 0x00 "CMD_RSP2,Command Response2"
hexmask.long 0x00 0.--31. 1. "CMDRSP2,Command response 2"
rgroup.long 0x1C++0x03
line.long 0x00 "CMD_RSP3,Command Response3"
hexmask.long 0x00 0.--31. 1. "CMDRSP3,Command response 3"
group.long 0x20++0x03
line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port"
hexmask.long 0x00 0.--31. 1. "DATCONT,Data content"
rgroup.long 0x24++0x03
line.long 0x00 "PRES_STATE,Present State"
hexmask.long.byte 0x00 24.--31. 1. "DLSL,DATA[7:0] line signal level"
newline
bitfld.long 0x00 23. "CLSL,CMD line signal level" "0,1"
newline
bitfld.long 0x00 19. "WPSPL,Write protect switch pin level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)"
newline
bitfld.long 0x00 18. "CDPL,Card detect pin level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)"
newline
bitfld.long 0x00 16. "CINST,Card inserted" "0: Power on reset or no card,1: Card inserted"
newline
bitfld.long 0x00 15. "TSCD,Tap select change done" "0: Delay cell select change is not finished,1: Delay cell select change is finished"
newline
bitfld.long 0x00 12. "RTR,Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning"
newline
bitfld.long 0x00 11. "BREN,Buffer read enable" "0: Read disable,1: Read enable"
newline
bitfld.long 0x00 10. "BWEN,Buffer write enable" "0: Write disable,1: Write enable"
newline
bitfld.long 0x00 9. "RTA,Read transfer active" "0: No valid data,1: Transferring data"
newline
bitfld.long 0x00 8. "WTA,Write transfer active" "0: No valid data,1: Transferring data"
newline
bitfld.long 0x00 7. "SDOFF,SD clock gated off internally" "0: SD clock is active,1: SD clock is gated off"
newline
bitfld.long 0x00 6. "PEROFF,IPG_PERCLK gated off internally" "0: IPG_PERCLK is active,1: IPG_PERCLK is gated off"
newline
bitfld.long 0x00 5. "HCKOFF,HCLK gated off internally" "0: HCLK is active,1: HCLK is gated off"
newline
bitfld.long 0x00 4. "IPGOFF,Peripheral clock gated off internally" "0: Peripheral clock is active,1: Peripheral clock is gated off"
newline
bitfld.long 0x00 3. "SDSTB,SD clock stable" "0: Clock is changing frequency and not stable,1: Clock is stable"
newline
bitfld.long 0x00 2. "DLA,Data line active" "0: DATA line inactive,1: DATA line active"
newline
bitfld.long 0x00 1. "CDIHB,Command Inhibit Data (DATA)" "0: Can issue command that uses the DATA line,1: Cannot issue command that uses the DATA line"
newline
bitfld.long 0x00 0. "CIHB,Command inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
group.long 0x28++0x03
line.long 0x00 "PROT_CTRL,Protocol Control"
bitfld.long 0x00 30. "NON_EXACT_BLK_RD,Non-exact block" "0: The block read is exact block,1: The block read is non-exact block"
newline
bitfld.long 0x00 26. "WECRM,Wakeup event enable on SD card removal" "0: Disables wakeup event enable on SD card removal,1: Enables wakeup event enable on SD card removal"
newline
bitfld.long 0x00 25. "WECINS,Wakeup event enable on SD card insertion" "0: Disable wakeup event enable on SD card..,1: Enable wakeup event enable on SD card insertion"
newline
bitfld.long 0x00 24. "WECINT,Wakeup event enable on card interrupt" "0: Disables wakeup event enable on card interrupt,1: Enables wakeup event enable on card interrupt"
newline
bitfld.long 0x00 20. "RD_DONE_NO_8CLK,Read performed number 8 clock" "0,1"
newline
bitfld.long 0x00 19. "IABG,Interrupt at block gap" "0: Disables interrupt at block gap,1: Enables interrupt at block gap"
newline
bitfld.long 0x00 18. "RWCTL,Read wait control" "0: Disables read wait control and stop SD clock..,1: Enables read wait control and assert read.."
newline
bitfld.long 0x00 17. "CREQ,Continue request" "0: No effect,1: Restart"
newline
bitfld.long 0x00 16. "SABGREQ,Stop at block gap request" "0: SABGREQ_0,1: SABGREQ_1"
newline
bitfld.long 0x00 8.--9. "DMASEL,DMA select" "0: No DMA or simple DMA is selected,1: ADMA1 is selected,2: ADMA2 is selected,?..."
newline
bitfld.long 0x00 7. "CDSS,Card detect signal selection" "0: Card detection level is selected (for normal..,1: Card detection test level is selected (for.."
newline
bitfld.long 0x00 6. "CDTL,Card detect test level" "0: Card detect test level is 0 no card inserted,1: Card detect test level is 1 card inserted"
newline
bitfld.long 0x00 4.--5. "EMODE,Endian mode" "0: Big endian mode,1: Half word big endian mode,2: Little endian mode,?..."
newline
bitfld.long 0x00 3. "D3CD,DATA3 as card detection pin" "0: DATA3 does not monitor card insertion,1: DATA3 as card detection pin"
newline
bitfld.long 0x00 1.--2. "DTW,Data transfer width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,?..."
group.long 0x2C++0x03
line.long 0x00 "SYS_CTRL,System Control"
bitfld.long 0x00 28. "RSTT,Reset tuning" "0,1"
newline
bitfld.long 0x00 27. "INITA,Initialization active" "0,1"
newline
bitfld.long 0x00 26. "RSTD,Software reset for data line" "0: No reset,1: RSTD_1"
newline
bitfld.long 0x00 25. "RSTC,Software reset for CMD line" "0: No reset,1: RSTC_1"
newline
bitfld.long 0x00 24. "RSTA,Software reset for all" "0: No reset,1: RSTA_1"
newline
bitfld.long 0x00 23. "IPP_RST_N,Hardware reset" "0,1"
newline
bitfld.long 0x00 16.--19. "DTOCV,Data timeout counter value" "0: SDCLK x 2 32,1: SDCLK x 2 33,2: SDCLK x 2 18,3: SDCLK x 2 19,?,?,?,?,?,?,?,?,?,13: SDCLK x 2 29 recommend to use for other..,14: SDCLK x 2 30 recommend to use for..,15: SDCLK x 2 31 recommend to use for HS400 mode"
newline
hexmask.long.byte 0x00 8.--15. 1. "SDCLKFS,SDCLK frequency select"
newline
bitfld.long 0x00 4.--7. "DVS,Divisor" "0: Divide-by-1,1: Divide-by-2,?,?,?,?,?,?,?,?,?,?,?,?,14: Divide-by-15,15: Divide-by-16"
group.long 0x30++0x03
line.long 0x00 "INT_STATUS,Interrupt Status"
eventfld.long 0x00 28. "DMAE,DMA error" "0: No error,1: DMAE_1"
newline
eventfld.long 0x00 26. "TNE,Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
newline
eventfld.long 0x00 24. "AC12E,Auto CMD12 error" "0: No error,1: AC12E_1"
newline
eventfld.long 0x00 22. "DEBE,Data end bit error" "0: No error,1: DEBE_1"
newline
eventfld.long 0x00 21. "DCE,Data CRC error" "0: No error,1: DCE_1"
newline
eventfld.long 0x00 20. "DTOE,Data timeout error" "0: No error,1: Time out"
newline
eventfld.long 0x00 19. "CIE,Command index error" "0: No error,1: CIE_1"
newline
eventfld.long 0x00 18. "CEBE,Command end bit error" "0: No error,1: End bit error generated"
newline
eventfld.long 0x00 17. "CCE,Command CRC error" "0: No error,1: CRC error generated"
newline
eventfld.long 0x00 16. "CTOE,Command timeout error" "0: No error,1: Time out"
newline
eventfld.long 0x00 14. "CQI,Command queuing interrupt" "0,1"
newline
eventfld.long 0x00 13. "TP,Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
newline
eventfld.long 0x00 12. "RTE,Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Re-tuning is not required,1: Re-tuning should be performed"
newline
eventfld.long 0x00 8. "CINT,Card interrupt" "0: No card interrupt,1: Generate card interrupt"
newline
eventfld.long 0x00 7. "CRM,Card removal" "0: Card state unstable or inserted,1: Card removed"
newline
eventfld.long 0x00 6. "CINS,Card insertion" "0: Card state unstable or removed,1: Card inserted"
newline
eventfld.long 0x00 5. "BRR,Buffer read ready" "0: Not ready to read buffer,1: Ready to read buffer"
newline
eventfld.long 0x00 4. "BWR,Buffer write ready" "0: Not ready to write buffer,1: Ready to write buffer"
newline
eventfld.long 0x00 3. "DINT,DMA interrupt" "0: No DMA interrupt,1: DMA interrupt is generated"
newline
eventfld.long 0x00 2. "BGE,Block gap event" "0: No block gap event,1: Transaction stopped at block gap"
newline
eventfld.long 0x00 1. "TC,Transfer complete" "0: Transfer does not complete,1: Transfer complete"
newline
eventfld.long 0x00 0. "CC,Command complete" "0: Command not complete,1: Command complete"
group.long 0x34++0x03
line.long 0x00 "INT_STATUS_EN,Interrupt Status Enable"
bitfld.long 0x00 28. "DMAESEN,DMA error status enable" "0: DMAESEN_0,1: DMAESEN_1"
newline
bitfld.long 0x00 26. "TNESEN,Tuning error status enable" "0: TNESEN_0,1: TNESEN_1"
newline
bitfld.long 0x00 24. "AC12ESEN,Auto CMD12 error status enable" "0: AC12ESEN_0,1: AC12ESEN_1"
newline
bitfld.long 0x00 22. "DEBESEN,Data end bit error status enable" "0: DEBESEN_0,1: DEBESEN_1"
newline
bitfld.long 0x00 21. "DCESEN,Data CRC error status enable" "0: DCESEN_0,1: DCESEN_1"
newline
bitfld.long 0x00 20. "DTOESEN,Data timeout error status enable" "0: DTOESEN_0,1: DTOESEN_1"
newline
bitfld.long 0x00 19. "CIESEN,Command index error status enable" "0: CIESEN_0,1: CIESEN_1"
newline
bitfld.long 0x00 18. "CEBESEN,Command end bit error status enable" "0: CEBESEN_0,1: CEBESEN_1"
newline
bitfld.long 0x00 17. "CCESEN,Command CRC error status enable" "0: CCESEN_0,1: CCESEN_1"
newline
bitfld.long 0x00 16. "CTOESEN,Command timeout error status enable" "0: CTOESEN_0,1: CTOESEN_1"
newline
bitfld.long 0x00 14. "CQISEN,Command queuing status enable" "0: CQISEN_0,1: CQISEN_1"
newline
bitfld.long 0x00 13. "TPSEN,Tuning pass status enable" "0: TPSEN_0,1: TPSEN_1"
newline
bitfld.long 0x00 12. "RTESEN,Re-tuning event status enable" "0: RTESEN_0,1: RTESEN_1"
newline
bitfld.long 0x00 8. "CINTSEN,Card interrupt status enable" "0: CINTSEN_0,1: CINTSEN_1"
newline
bitfld.long 0x00 7. "CRMSEN,Card removal status enable" "0: CRMSEN_0,1: CRMSEN_1"
newline
bitfld.long 0x00 6. "CINSSEN,Card insertion status enable" "0: CINSSEN_0,1: CINSSEN_1"
newline
bitfld.long 0x00 5. "BRRSEN,Buffer read ready status enable" "0: BRRSEN_0,1: BRRSEN_1"
newline
bitfld.long 0x00 4. "BWRSEN,Buffer write ready status enable" "0: BWRSEN_0,1: BWRSEN_1"
newline
bitfld.long 0x00 3. "DINTSEN,DMA interrupt status enable" "0: DINTSEN_0,1: DINTSEN_1"
newline
bitfld.long 0x00 2. "BGESEN,Block gap event status enable" "0: BGESEN_0,1: BGESEN_1"
newline
bitfld.long 0x00 1. "TCSEN,Transfer complete status enable" "0: TCSEN_0,1: TCSEN_1"
newline
bitfld.long 0x00 0. "CCSEN,Command complete status enable" "0: CCSEN_0,1: CCSEN_1"
group.long 0x38++0x03
line.long 0x00 "INT_SIGNAL_EN,Interrupt Signal Enable"
bitfld.long 0x00 28. "DMAEIEN,DMA error interrupt enable" "0: DMAEIEN_0,1: DMAEIEN_1"
newline
bitfld.long 0x00 26. "TNEIEN,Tuning error interrupt enable" "0: TNEIEN_0,1: TNEIEN_1"
newline
bitfld.long 0x00 24. "AC12EIEN,Auto CMD12 error interrupt enable" "0: AC12EIEN_0,1: AC12EIEN_1"
newline
bitfld.long 0x00 22. "DEBEIEN,Data end bit error interrupt enable" "0: DEBEIEN_0,1: DEBEIEN_1"
newline
bitfld.long 0x00 21. "DCEIEN,Data CRC error interrupt enable" "0: DCEIEN_0,1: DCEIEN_1"
newline
bitfld.long 0x00 20. "DTOEIEN,Data timeout error interrupt enable" "0: DTOEIEN_0,1: DTOEIEN_1"
newline
bitfld.long 0x00 19. "CIEIEN,Command index error interrupt enable" "0: CIEIEN_0,1: CIEIEN_1"
newline
bitfld.long 0x00 18. "CEBEIEN,Command end bit error interrupt enable" "0: CEBEIEN_0,1: CEBEIEN_1"
newline
bitfld.long 0x00 17. "CCEIEN,Command CRC error interrupt enable" "0: CCEIEN_0,1: CCEIEN_1"
newline
bitfld.long 0x00 16. "CTOEIEN,Command timeout error interrupt enable" "0: CTOEIEN_0,1: CTOEIEN_1"
newline
bitfld.long 0x00 14. "CQIIEN,Command queuing signal enable" "0: CQIIEN_0,1: CQIIEN_1"
newline
bitfld.long 0x00 13. "TPIEN,Tuning pass interrupt enable" "0: TPIEN_0,1: TPIEN_1"
newline
bitfld.long 0x00 12. "RTEIEN,Re-tuning event interrupt enable" "0: RTEIEN_0,1: RTEIEN_1"
newline
bitfld.long 0x00 8. "CINTIEN,Card interrupt enable" "0: CINTIEN_0,1: CINTIEN_1"
newline
bitfld.long 0x00 7. "CRMIEN,Card removal interrupt enable" "0: CRMIEN_0,1: CRMIEN_1"
newline
bitfld.long 0x00 6. "CINSIEN,Card insertion interrupt enable" "0: CINSIEN_0,1: CINSIEN_1"
newline
bitfld.long 0x00 5. "BRRIEN,Buffer read ready interrupt enable" "0: BRRIEN_0,1: BRRIEN_1"
newline
bitfld.long 0x00 4. "BWRIEN,Buffer write ready interrupt enable" "0: BWRIEN_0,1: BWRIEN_1"
newline
bitfld.long 0x00 3. "DINTIEN,DMA interrupt enable" "0: DINTIEN_0,1: DINTIEN_1"
newline
bitfld.long 0x00 2. "BGEIEN,Block gap event interrupt enable" "0: BGEIEN_0,1: BGEIEN_1"
newline
bitfld.long 0x00 1. "TCIEN,Transfer complete interrupt enable" "0: TCIEN_0,1: TCIEN_1"
newline
bitfld.long 0x00 0. "CCIEN,Command complete interrupt enable" "0: CCIEN_0,1: CCIEN_1"
group.long 0x3C++0x03
line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status"
bitfld.long 0x00 23. "SMP_CLK_SEL,Sample clock select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
newline
bitfld.long 0x00 22. "EXECUTE_TUNING,Execute tuning" "0: Tuning procedure is aborted,1: Start tuning procedure"
newline
rbitfld.long 0x00 7. "CNIBAC12E,Command not issued by Auto CMD12 error" "0: CNIBAC12E_0,1: CNIBAC12E_1"
newline
rbitfld.long 0x00 4. "AC12IE,Auto CMD12 / 23 index error" "0: AC12IE_0,1: Error the CMD index in response is not CMD12/23"
newline
rbitfld.long 0x00 3. "AC12CE,Auto CMD12 / 23 CRC error" "0: No CRC error,1: CRC error met in Auto CMD12/23 response"
newline
rbitfld.long 0x00 2. "AC12EBE,Auto CMD12 / 23 end bit error" "0: AC12EBE_0,1: End bit error generated"
newline
rbitfld.long 0x00 1. "AC12TOE,Auto CMD12 / 23 timeout error" "0: AC12TOE_0,1: AC12TOE_1"
newline
rbitfld.long 0x00 0. "AC12NE,Auto CMD12 not executed" "0: AC12NE_0,1: Not executed"
group.long 0x40++0x03
line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities"
rbitfld.long 0x00 26. "VS18,Voltage support 1.8 V" "0: 1.8 V not supported,1: 1.8 V supported"
newline
rbitfld.long 0x00 25. "VS30,Voltage support 3.0 V" "0: 3.0 V not supported,1: 3.0 V supported"
newline
rbitfld.long 0x00 24. "VS33,Voltage support 3.3 V" "0: 3.3 V not supported,1: 3.3 V supported"
newline
rbitfld.long 0x00 23. "SRS,Suspend / resume support" "0: Not supported,1: Supported"
newline
rbitfld.long 0x00 22. "DMAS,DMA support" "0: DMA not supported,1: DMA supported"
newline
rbitfld.long 0x00 21. "HSS,High speed support" "0: High speed not supported,1: High speed supported"
newline
rbitfld.long 0x00 20. "ADMAS,ADMA support" "0: Advanced DMA not supported,1: Advanced DMA supported"
newline
rbitfld.long 0x00 16.--18. "MBL,Max block length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,?..."
newline
bitfld.long 0x00 13. "USE_TUNING_SDR50,Use Tuning for SDR50" "0: SDR50 does not support tuning,1: SDR50 supports tuning"
newline
rbitfld.long 0x00 2. "DDR50_SUPPORT,DDR50 support" "0,1"
newline
rbitfld.long 0x00 1. "SDR104_SUPPORT,SDR104 support" "0,1"
newline
rbitfld.long 0x00 0. "SDR50_SUPPORT,SDR50 support" "0,1"
group.long 0x44++0x03
line.long 0x00 "WTMK_LVL,Watermark Level"
hexmask.long.byte 0x00 16.--23. 1. "WR_WML,Write watermark level"
newline
hexmask.long.byte 0x00 0.--7. 1. "RD_WML,Read watermark level"
group.long 0x48++0x03
line.long 0x00 "MIX_CTRL,Mixer Control"
bitfld.long 0x00 27. "EN_HS400_MODE,Enable enhance HS400 mode" "0,1"
newline
bitfld.long 0x00 26. "HS400_MODE,Enable HS400 mode" "0,1"
newline
bitfld.long 0x00 25. "FBCLK_SEL,Feedback clock source selection (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Feedback clock comes from the loopback CLK,1: Feedback clock comes from the ipp_card_clk_out"
newline
bitfld.long 0x00 24. "AUTO_TUNE_EN,Auto tuning enable (Only used for SD3.0 SDR104 mode and and EMMC HS200 mode)" "0: Disable auto tuning,1: Enable auto tuning"
newline
bitfld.long 0x00 23. "SMP_CLK_SEL,Clock selection" "0: Fixed clock is used to sample data / cmd,1: Tuned clock is used to sample data / cmd"
newline
bitfld.long 0x00 22. "EXE_TUNE,Execute tuning: (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Not tuned or tuning completed,1: Execute tuning"
newline
bitfld.long 0x00 7. "AC23EN,Auto CMD23 enable" "0,1"
newline
bitfld.long 0x00 6. "NIBBLE_POS,Nibble position indication" "0,1"
newline
bitfld.long 0x00 5. "MSBSEL,Multi / Single block select" "0: Single block,1: Multiple blocks"
newline
bitfld.long 0x00 4. "DTDSEL,Data transfer direction select" "0: Write (Host to card),1: Read (Card to host)"
newline
bitfld.long 0x00 3. "DDR_EN,Dual data rate mode selection" "0,1"
newline
bitfld.long 0x00 2. "AC12EN,Auto CMD12 enable" "0: AC12EN_0,1: AC12EN_1"
newline
bitfld.long 0x00 1. "BCEN,Block count enable" "0: Disable,1: BCEN_1"
newline
bitfld.long 0x00 0. "DMAEN,DMA enable" "0: DMAEN_0,1: DMAEN_1"
group.long 0x50++0x03
line.long 0x00 "FORCE_EVENT,Force Event"
bitfld.long 0x00 31. "FEVTCINT,Force event card interrupt" "0,1"
newline
bitfld.long 0x00 28. "FEVTDMAE,Force event DMA error" "0,1"
newline
bitfld.long 0x00 26. "FEVTTNE,Force tuning error" "0,1"
newline
bitfld.long 0x00 24. "FEVTAC12E,Force event Auto Command 12 error" "0,1"
newline
bitfld.long 0x00 22. "FEVTDEBE,Force event data end bit error" "0,1"
newline
bitfld.long 0x00 21. "FEVTDCE,Force event data CRC error" "0,1"
newline
bitfld.long 0x00 20. "FEVTDTOE,Force event data time out error" "0,1"
newline
bitfld.long 0x00 19. "FEVTCIE,Force event command index error" "0,1"
newline
bitfld.long 0x00 18. "FEVTCEBE,Force event command end bit error" "0,1"
newline
bitfld.long 0x00 17. "FEVTCCE,Force event command CRC error" "0,1"
newline
bitfld.long 0x00 16. "FEVTCTOE,Force event command time out error" "0,1"
newline
bitfld.long 0x00 7. "FEVTCNIBAC12E,Force event command not executed by Auto Command 12 error" "0,1"
newline
bitfld.long 0x00 4. "FEVTAC12IE,Force event Auto Command 12 index error" "0,1"
newline
bitfld.long 0x00 3. "FEVTAC12EBE,Force event Auto Command 12 end bit error" "0,1"
newline
bitfld.long 0x00 2. "FEVTAC12CE,Force event auto command 12 CRC error" "0,1"
newline
bitfld.long 0x00 1. "FEVTAC12TOE,Force event auto command 12 time out error" "0,1"
newline
bitfld.long 0x00 0. "FEVTAC12NE,Force event auto command 12 not executed" "0,1"
rgroup.long 0x54++0x03
line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status"
bitfld.long 0x00 3. "ADMADCE,ADMA descriptor error" "0: ADMADCE_0,1: ADMADCE_1"
newline
bitfld.long 0x00 2. "ADMALME,ADMA length mismatch error" "0: ADMALME_0,1: ADMALME_1"
newline
bitfld.long 0x00 0.--1. "ADMAES,ADMA error state (when ADMA error is occurred)" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address"
hexmask.long 0x00 2.--31. 1. "ADS_ADDR,ADMA system address"
group.long 0x60++0x03
line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control"
bitfld.long 0x00 28.--31. "DLL_CTRL_REF_UPDATE_INT,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 20.--27. 1. "DLL_CTRL_SLV_UPDATE_INT,Slave delay line update interval"
newline
bitfld.long 0x00 16.--18. "DLL_CTRL_SLV_DLY_TARGET1,DLL slave delay target1" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 9.--15. 1. "DLL_CTRL_SLV_OVERRIDE_VAL,DLL slave override val"
newline
bitfld.long 0x00 8. "DLL_CTRL_SLV_OVERRIDE,DLL slave override" "0,1"
newline
bitfld.long 0x00 7. "DLL_CTRL_GATE_UPDATE,DLL gate update" "0,1"
newline
bitfld.long 0x00 3.--6. "DLL_CTRL_SLV_DLY_TARGET0,DLL slave delay target0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "DLL_CTRL_SLV_FORCE_UPD,DLL slave delay line" "0,1"
newline
bitfld.long 0x00 1. "DLL_CTRL_RESET,DLL reset" "0,1"
newline
bitfld.long 0x00 0. "DLL_CTRL_ENABLE,DLL and delay chain" "0,1"
rgroup.long 0x64++0x03
line.long 0x00 "DLL_STATUS,DLL Status"
hexmask.long.byte 0x00 9.--15. 1. "DLL_STS_REF_SEL,Reference delay line select taps"
newline
hexmask.long.byte 0x00 2.--8. 1. "DLL_STS_SLV_SEL,Slave delay line select status"
newline
bitfld.long 0x00 1. "DLL_STS_REF_LOCK,Reference DLL lock status" "0,1"
newline
bitfld.long 0x00 0. "DLL_STS_SLV_LOCK,Slave delay-line lock status" "0,1"
group.long 0x68++0x03
line.long 0x00 "CLK_TUNE_CTRL_STATUS,CLK Tuning Control and Status"
rbitfld.long 0x00 31. "PRE_ERR,PRE error" "0,1"
newline
hexmask.long.byte 0x00 24.--30. 1. "TAP_SEL_PRE,TAP_SEL_PRE"
newline
rbitfld.long 0x00 20.--23. "TAP_SEL_OUT,Delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TAP_SEL_POST,Delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 15. "NXT_ERR,NXT error" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "DLY_CELL_SET_PRE,delay cells on the feedback clock between the feedback clock and CLK_PRE"
newline
bitfld.long 0x00 4.--7. "DLY_CELL_SET_OUT,Delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DLY_CELL_SET_POST,Delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x03
line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL control"
bitfld.long 0x00 28.--31. "STROBE_DLL_CTRL_REF_UPDATE_INT,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 20.--27. 1. "STROBE_DLL_CTRL_SLV_UPDATE_INT,Strobe DLL control slave update interval"
newline
hexmask.long.byte 0x00 9.--15. 1. "STROBE_DLL_CTRL_SLV_OVERRIDE_VAL,Strobe DLL control slave Override value"
newline
bitfld.long 0x00 8. "STROBE_DLL_CTRL_SLV_OVERRIDE,Strobe DLL control slave override" "0,1"
newline
bitfld.long 0x00 7. "STROBE_DLL_CTRL_GATE_UPDATE,Strobe DLL control gate update" "0,1"
newline
bitfld.long 0x00 3.--6. "STROBE_DLL_CTRL_SLV_DLY_TARGET,Strobe DLL Control Slave Delay Target" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "STROBE_DLL_CTRL_SLV_FORCE_UPD,Strobe DLL control slave force updated" "0,1"
newline
bitfld.long 0x00 1. "STROBE_DLL_CTRL_RESET,Strobe DLL control reset" "0,1"
newline
bitfld.long 0x00 0. "STROBE_DLL_CTRL_ENABLE,Strobe DLL control enable" "0,1"
rgroup.long 0x74++0x03
line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL status"
hexmask.long.byte 0x00 9.--15. 1. "STROBE_DLL_STS_REF_SEL,Strobe DLL status reference select"
newline
hexmask.long.byte 0x00 2.--8. 1. "STROBE_DLL_STS_SLV_SEL,Strobe DLL status slave select"
newline
bitfld.long 0x00 1. "STROBE_DLL_STS_REF_LOCK,Strobe DLL status reference lock" "0,1"
newline
bitfld.long 0x00 0. "STROBE_DLL_STS_SLV_LOCK,Strobe DLL status slave lock" "0,1"
group.long 0xC0++0x03
line.long 0x00 "VEND_SPEC,Vendor Specific Register"
bitfld.long 0x00 31. "CMD_BYTE_EN,Byte access" "0: CMD_BYTE_EN_0,1: CMD_BYTE_EN_1"
newline
bitfld.long 0x00 15. "CRC_CHK_DIS,CRC Check Disable" "0: Check CRC16 for every read data packet and..,1: Ignore CRC16 check for every read data packet.."
newline
bitfld.long 0x00 8. "FRC_SDCLK_ON,Force CLK" "0: CLK active or inactive is fully controlled by..,1: Force CLK active"
newline
bitfld.long 0x00 3. "AC12_WR_CHKBUSY_EN,Check busy enable" "0: Do not check busy after auto CMD12 for write..,1: Check busy after auto CMD12 for write data.."
newline
bitfld.long 0x00 2. "CONFLICT_CHK_EN,Conflict check enable" "0: Conflict check disable,1: Conflict check enable"
newline
bitfld.long 0x00 1. "VSELECT,Voltage selection" "0: Change the voltage to high voltage range..,1: Change the voltage to low voltage range.."
newline
bitfld.long 0x00 0. "EXT_DMA_EN,External DMA request enable" "0: In any scenario uSDHC does not send out..,1: When internal DMA is not active the external.."
group.long 0xC4++0x03
line.long 0x00 "MMC_BOOT,MMC Boot"
hexmask.long.word 0x00 16.--31. 1. "BOOT_BLK_CNT,Stop At Block Gap value of automatic mode"
newline
bitfld.long 0x00 8. "DISABLE_TIME_OUT,Time out" "0: DISABLE_TIME_OUT_0,1: DISABLE_TIME_OUT_1"
newline
bitfld.long 0x00 7. "AUTO_SABG_EN,Auto stop at block gap" "0,1"
newline
bitfld.long 0x00 6. "BOOT_EN,Boot enable" "0: Fast boot disable,1: Fast boot enable"
newline
bitfld.long 0x00 5. "BOOT_MODE,Boot mode" "0: BOOT_MODE_0,1: Alternative boot"
newline
bitfld.long 0x00 4. "BOOT_ACK,BOOT ACK" "0: BOOT_ACK_0,1: BOOT_ACK_1"
newline
bitfld.long 0x00 0.--3. "DTOCV_ACK,DTOCV_ACK" "0: SDCLK x 2^32,1: SDCLK x 2^33,2: SDCLK x 2^18,3: SDCLK x 2^19,4: SDCLK x 2^20,5: SDCLK x 2^21,6: SDCLK x 2^22,7: SDCLK x 2^23,?,?,?,?,?,?,14: DTOCV_ACK_14,15: DTOCV_ACK_15"
group.long 0xC8++0x03
line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register"
hexmask.long.word 0x00 16.--31. 1. "FBCLK_TAP_SEL,Enable extra delay on internal feedback clock"
newline
bitfld.long 0x00 15. "EN_32K_CLK,Enable 32khz clock for card detection" "0,1"
newline
bitfld.long 0x00 12. "ACMD23_ARGU2_EN,Argument2 register enable for ACMD23" "0: ACMD23_ARGU2_EN_0,1: Argument2 register enable for ACMD23 sharing.."
newline
bitfld.long 0x00 11. "HS400_RD_CLK_STOP_EN,HS400 read clock stop enable" "0,1"
newline
bitfld.long 0x00 10. "HS400_WR_CLK_STOP_EN,HS400 write clock stop enable" "0,1"
newline
bitfld.long 0x00 6. "TUNING_CMD_EN,Tuning command enable" "0: Auto tuning circuit does not check the CMD line,1: Auto tuning circuit checks the CMD line"
newline
bitfld.long 0x00 5. "TUNING_1bit_EN,Tuning 1bit enable" "0,1"
newline
bitfld.long 0x00 4. "TUNING_8bit_EN,Tuning 8bit enable" "0,1"
newline
bitfld.long 0x00 3. "CARD_INT_D3_TEST,Card interrupt detection test" "0: Check the card interrupt only when DATA3 is..,1: Check the card interrupt by ignoring the.."
group.long 0xCC++0x03
line.long 0x00 "TUNING_CTRL,Tuning Control"
bitfld.long 0x00 24. "STD_TUNING_EN,Standard tuning circuit and procedure enable" "0,1"
newline
bitfld.long 0x00 20.--22. "TUNING_WINDOW,Data window" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "TUNING_STEP,TUNING_STEP" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 8.--15. 1. "TUNING_COUNTER,Tuning counter"
newline
bitfld.long 0x00 7. "DIS_CMD_CHK_FOR_STD_TUNING,Disable command check for standard tuning" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "TUNING_START_TAP,Tuning start"
rgroup.long 0x100++0x03
line.long 0x00 "CQVER,Command Queuing Version"
bitfld.long 0x00 8.--11. "MAJOR_VN,e MMC major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "MINOR_VN,e MMC minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "VERSION_SUFFIX,e MMC version suffix" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x104++0x03
line.long 0x00 "CQCAP,Command Queuing Capabilities"
bitfld.long 0x00 12.--15. "ITCFMUL,Internal timer clock frequency multiplier" "?,1: ITCFMUL_1,2: ITCFMUL_2,3: ITCFMUL_3,4: ITCFMUL_4,5: ITCFMUL_5,?..."
newline
hexmask.long.word 0x00 0.--9. 1. "ITCFVAL,Internal timer clock frequency value"
group.long 0x108++0x03
line.long 0x00 "CQCFG,Command Queuing Configuration"
bitfld.long 0x00 12. "DCMDE,Direct command (DCMD) enable" "0: Task descriptor in slot #31 is a Data..,1: Task descriptor in slot #31 is a DCMD Task.."
newline
bitfld.long 0x00 8. "TDS,Task descriptor size" "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits"
newline
bitfld.long 0x00 0. "CQUE,Command queuing enable" "0,1"
group.long 0x10C++0x03
line.long 0x00 "CQCTL,Command Queuing Control"
bitfld.long 0x00 8. "CLEAR,Clear all tasks" "0,1"
newline
bitfld.long 0x00 0. "HALT,Halt" "0,1"
group.long 0x110++0x03
line.long 0x00 "CQIS,Command Queuing Interrupt Status"
eventfld.long 0x00 3. "TCL,Task cleared" "0,1"
newline
eventfld.long 0x00 2. "RED,Response error detected interrupt" "0,1"
newline
eventfld.long 0x00 1. "TCC,Task complete interrupt" "0,1"
newline
eventfld.long 0x00 0. "HAC,Halt complete interrupt" "0,1"
group.long 0x114++0x03
line.long 0x00 "CQISTE,Command Queuing Interrupt Status Enable"
bitfld.long 0x00 3. "TCL_STE,Task cleared status enable" "0: CQIS[TCL] is disabled,1: CQIS[TCL] is set when its interrupt condition.."
newline
bitfld.long 0x00 2. "RED_STE,Response error detected status enable" "0: CQIS[RED] is disabled,1: CQIS[RED] is set when its interrupt condition.."
newline
bitfld.long 0x00 1. "TCC_STE,Task complete status enable" "0: CQIS[TCC] is disabled,1: CQIS[TCC] is set when its interrupt condition.."
newline
bitfld.long 0x00 0. "HAC_STE,Halt complete status enable" "0: CQIS[HAC] is disabled,1: CQIS[HAC] is set when its interrupt condition.."
group.long 0x118++0x03
line.long 0x00 "CQISGE,Command Queuing Interrupt Signal Enable"
bitfld.long 0x00 3. "TCL_SGE,Task cleared signal enable" "0,1"
newline
bitfld.long 0x00 2. "RED_SGE,Response error detected signal enable" "0,1"
newline
bitfld.long 0x00 1. "TCC_SGE,Task complete signal enable" "0,1"
newline
bitfld.long 0x00 0. "HAC_SGE,Halt complete signal enable" "0,1"
group.long 0x11C++0x03
line.long 0x00 "CQIC,Command Queuing Interrupt Coalescing"
bitfld.long 0x00 31. "ICENDIS,Interrupt coalescing enable/disable" "0,1"
newline
rbitfld.long 0x00 20. "ICSB,Interrupt coalescing status" "0: No task completions have occurred since last..,1: At least one task completion has been counted.."
newline
bitfld.long 0x00 16. "ICCTR,Counter and timer reset" "0,1"
newline
bitfld.long 0x00 15. "ICCTHWEN,Interrupt coalescing counter threshold write enable" "0,1"
newline
bitfld.long 0x00 8.--12. "ICCTH,Interrupt coalescing counter threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7. "ICTOVALWEN,Interrupt coalescing timeout value write enable" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "ICTOVAL,Interrupt coalescing timeout value"
group.long 0x120++0x03
line.long 0x00 "CQTDLBA,Command Queuing Task Descriptor List Base Address"
hexmask.long 0x00 0.--31. 1. "TDLBA,Task descriptor list base address"
group.long 0x124++0x03
line.long 0x00 "CQTDLBAU,Command Queuing Task Descriptor List Base Address Upper 32 Bits"
hexmask.long 0x00 0.--31. 1. "TDLBAU,Task descriptor list base address"
group.long 0x128++0x03
line.long 0x00 "CQTDBR,Command Queuing Task Doorbell"
hexmask.long 0x00 0.--31. 1. "TDBR,Task doorbell"
group.long 0x12C++0x03
line.long 0x00 "CQTCN,Command Queuing Task Completion Notification"
hexmask.long 0x00 0.--31. 1. "TCN,Task complete notification"
rgroup.long 0x130++0x03
line.long 0x00 "CQDQS,Command Queuing Device Queue Status"
hexmask.long 0x00 0.--31. 1. "DQS,Device queue status"
rgroup.long 0x134++0x03
line.long 0x00 "CQDPT,Command Queuing Device Pending Tasks"
hexmask.long 0x00 0.--31. 1. "DPT,Device pending tasks"
group.long 0x138++0x03
line.long 0x00 "CQTCLR,Command Queuing Task Clear"
hexmask.long 0x00 0.--31. 1. "TCLR,Task clear"
group.long 0x140++0x03
line.long 0x00 "CQSSC1,Command Queuing Send Status Configuration 1"
bitfld.long 0x00 16.--19. "CBC,Send status command block counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--15. 1. "CIT,Send status command idle timer"
group.long 0x144++0x03
line.long 0x00 "CQSSC2,Command Queuing Send Status Configuration 2"
hexmask.long.word 0x00 0.--15. 1. "SSC2,Send queue status RCA"
rgroup.long 0x148++0x03
line.long 0x00 "CQCRDCT,Command Queuing Command Response for Direct-Command Task"
hexmask.long 0x00 0.--31. 1. "CRDCT,Direct command last response"
group.long 0x150++0x03
line.long 0x00 "CQRMEM,Command Queuing Response Mode Error Mask"
hexmask.long 0x00 0.--31. 1. "RMEM,Response mode error mask"
rgroup.long 0x154++0x03
line.long 0x00 "CQTERRI,Command Queuing Task Error Information"
bitfld.long 0x00 31. "DTEFV,Data transfer error fields valid" "0,1"
newline
bitfld.long 0x00 24.--28. "DTETID,Data transfer error task ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--21. "DTECI,Data transfer error command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. "RMEFV,Response mode error fields valid" "0,1"
newline
bitfld.long 0x00 8.--12. "RMETID,Response mode error task ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--5. "RMECI,Response mode error command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x158++0x03
line.long 0x00 "CQCRI,Command Queuing Command Response Index"
bitfld.long 0x00 0.--5. "LCMDRI,Last command response index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x15C++0x03
line.long 0x00 "CQCRA,Command Queuing Command Response Argument"
hexmask.long 0x00 0.--31. 1. "LCMDRA,Last command response argument"
tree.end
repeat.end
tree.end
tree "VIDEOPACKETIZER (VideoPacketizer)"
base ad:0x32FD8800
rgroup.byte 0x00++0x00
line.byte 0x00 "vp_status,Video Packetizer Packing Phase Status Register"
bitfld.byte 0x00 0.--3. "packing_phase,Read only register that holds the packing phase output of the Video Packetizer block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x01++0x00
line.byte 0x00 "vp_pr_cd,Video Packetizer Pixel Repetition and Color Depth Register"
bitfld.byte 0x00 4.--7. "color_depth,The Color depth configuration is described as the following with the action stated corresponding to color_depth[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "desired_pr_factor,Desired pixel repetition factor configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x02++0x00
line.byte 0x00 "vp_stuff,Video Packetizer Stuffing and Default Packing Phase Register"
bitfld.byte 0x00 5. "idefault_phase,Controls the default phase packing machine used according to HDMI 1" "0,1"
bitfld.byte 0x00 4. "ifix_pp_to_last,Reserved" "0,1"
newline
bitfld.byte 0x00 3. "icx_goto_p0_st,Reserved" "0,1"
bitfld.byte 0x00 2. "ycc422_stuffing,YCbCr 422 remap stuffing control" "0,1"
newline
bitfld.byte 0x00 1. "pp_stuffing,Pixel packing stuffing control" "0,1"
bitfld.byte 0x00 0. "pr_stuffing,Pixel repeater stuffing control" "0,1"
group.byte 0x03++0x00
line.byte 0x00 "vp_remap,Video Packetizer YCbCr 422 Remapping Register"
bitfld.byte 0x00 0.--1. "ycc422_size,YCbCr 422 remap input video size ycc422_size[1:0]" "0: YCbCr 422 16-bit input video (8 bits per,1: YCbCr 422 20-bit input video (10 bits per,2: YCbCr 422 24-bit input video (12 bits per,3: Reserved"
group.byte 0x04++0x00
line.byte 0x00 "vp_conf,Video Packetizer Output and Enable Configuration Register"
bitfld.byte 0x00 6. "bypass_en,When set to 1'b1 Pixel packing enable" "0,1"
bitfld.byte 0x00 5. "pp_en,Pixel packing enable" "0,1"
newline
bitfld.byte 0x00 4. "pr_en,Pixel repeater enable" "0,1"
bitfld.byte 0x00 3. "ycc422_en,YCbCr 422 select enable" "0,1"
newline
bitfld.byte 0x00 2. "bypass_select,bypass_select" "0: Data from pixel repeater block,1: Data from input of Video Packetizer block"
bitfld.byte 0x00 1. "output_selector_1,When set to 1'b1 Data from pixel packing block Note: the use of this field is deprecated" "0,1"
newline
bitfld.byte 0x00 0. "output_selector_0,Video Packetizer output selection" "0: Data from pixel packing block,1: Data from YCbCr 422 remap block"
group.byte 0x07++0x00
line.byte 0x00 "vp_mask,Video Packetizer Interrupt Mask Register"
bitfld.byte 0x00 7. "ointfullrepet,Mask bit for Video Packetizer pixel repeater FIFO full" "0,1"
bitfld.byte 0x00 6. "ointemptyrepet,Mask bit for Video Packetizer pixel repeater FIFO empty" "0,1"
newline
bitfld.byte 0x00 5. "ointfullpp,Mask bit for Video Packetizer pixel packing FIFO full" "0,1"
bitfld.byte 0x00 4. "ointemptypp,Mask bit for Video Packetizer pixel packing FIFO empty" "0,1"
newline
bitfld.byte 0x00 3. "ointfullremap,Mask bit for Video Packetizer pixel YCbCr 422 re-mapper FIFO full" "0,1"
bitfld.byte 0x00 2. "ointemptyremap,Mask bit for Video Packetizer pixel YCbCr 422 re-mapper FIFO empty" "0,1"
newline
bitfld.byte 0x00 1. "spare_2,Reserved as spare bit with no associated functionality" "0,1"
bitfld.byte 0x00 0. "spare_1,Reserved as spare bit with no associated functionality" "0,1"
tree.end
tree "VIDEOSAMPLER (VideoSampler)"
base ad:0x32FD8200
group.byte 0x00++0x00
line.byte 0x00 "tx_invid0,Video Input Mapping and Internal Data Enable Configuration Register"
bitfld.byte 0x00 7. "internal_de_generator,Internal data enable (DE) generator enable" "0,1"
bitfld.byte 0x00 0.--4. "video_mapping,Video Input mapping (color space/color depth)" "?,1: RGB 4:4:4/8 bits,?,3: RGB 4:4:4/10 bits,?,5: RGB 4:4:4/12 bits,?,7: RGB 4:4:4/16 bits,?,9: YCbCr 4:4:4 or 4:2:0/8 bits,?,11: YCbCr 4:4:4 or 4:2:0/10 bits,?,13: YCbCr 4:4:4 or 4:2:0/12 bits,?,15: YCbCr 4:4:4 or 4:2:0/16 bits,?,?,18: YCbCr 4:2:2/12 bits,?,20: YCbCr 4:2:2/10 bits,?,22: YCbCr 4:2:2/8 bits,23: YCbCr 4:4:4 (IPI)/8 bits,24: YCbCr 4:4:4 (IPI)/10 bits,25: YCbCr 4:4:4 (IPI)/12 bits,26: YCbCr 4:4:4 (IPI)/16 bits,27: YCbCr 4:2:2 (IPI)/12 bits,28: YCbCr 4:2:0 (IPI)/8 bits,29: YCbCr 4:2:0 (IPI)/10 bits,30: YCbCr 4:2:0 (IPI)/12 bits,31: YCbCr 4:2:0 (IPI)/16 bits"
group.byte 0x01++0x00
line.byte 0x00 "tx_instuffing,Video Input Stuffing Enable Register"
bitfld.byte 0x00 2. "bcbdata_stuffing," "0,1"
bitfld.byte 0x00 1. "rcrdata_stuffing," "0,1"
newline
bitfld.byte 0x00 0. "gydata_stuffing," "0,1"
group.byte 0x02++0x00
line.byte 0x00 "tx_gydata0,Video Input gy Data Channel Stuffing Register 0"
hexmask.byte 0x00 0.--7. 1. "gydata,This register defines the value of gydata[7:0] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b"
group.byte 0x03++0x00
line.byte 0x00 "tx_gydata1,Video Input gy Data Channel Stuffing Register 1"
hexmask.byte 0x00 0.--7. 1. "gydata,This register defines the value of gydata[15:8] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b"
group.byte 0x04++0x00
line.byte 0x00 "tx_rcrdata0,Video Input rcr Data Channel Stuffing Register 0"
hexmask.byte 0x00 0.--7. 1. "rcrdata,This register defines the value of rcrydata[7:0] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b"
group.byte 0x05++0x00
line.byte 0x00 "tx_rcrdata1,Video Input rcr Data Channel Stuffing Register 1"
hexmask.byte 0x00 0.--7. 1. "rcrdata,This register defines the value of rcrydata[15:8] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b"
group.byte 0x06++0x00
line.byte 0x00 "tx_bcbdata0,Video Input bcb Data Channel Stuffing Register 0"
hexmask.byte 0x00 0.--7. 1. "bcbdata,This register defines the value of bcbdata[7:0] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b"
group.byte 0x07++0x00
line.byte 0x00 "tx_bcbdata1,Video Input bcb Data Channel Stuffing Register 1"
hexmask.byte 0x00 0.--7. 1. "bcbdata,This register defines the value of bcbdata[15:8] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b"
tree.end
tree "VPU_BLK_CTL"
base ad:0x38330000
group.long 0x00++0x03
line.long 0x00 "BLK_SFT_RSTN_CSR,VPUMIX block soft reset control"
bitfld.long 0x00 2. "VC8000E_SFT_RSTN,Soft reset for VC8000E active low" "0: VC8000E_SFT_RSTN_0,1: VC8000E_SFT_RSTN_1"
bitfld.long 0x00 1. "G1_SFT_RSTN,Soft reset for G1 active low" "0: G1_SFT_RSTN_0,1: G1_SFT_RSTN_1"
newline
bitfld.long 0x00 0. "G2_SFT_RSTN,Soft reset for G2 active low" "0: G2_SFT_RSTN_0,1: G2_SFT_RSTN_1"
group.long 0x04++0x03
line.long 0x00 "BLK_CLK_EN_CSR,VPUMIX block clock enable control"
bitfld.long 0x00 3. "MAIN_CLK_EN,Clock enable for noc main bus active high" "0: MAIN_CLK_EN_0,1: MAIN_CLK_EN_1"
bitfld.long 0x00 2. "VC8000E_CLK_EN,Clock enable for VC8000E active high" "0: VC8000E_CLK_EN_0,1: VC8000E_CLK_EN_1"
newline
bitfld.long 0x00 1. "G1_CLK_EN,Clock enable for G1 active high" "0: G1_CLK_EN_0,1: G1_CLK_EN_1"
bitfld.long 0x00 0. "G2_CLK_EN,Clock enable for G2 active high" "0: G2_CLK_EN_0,1: G2_CLK_EN_1"
group.long 0x08++0x03
line.long 0x00 "G1_FUSE_DEC_CSR,VPUMIX G1 fuse_dec control"
hexmask.long 0x00 0.--31. 1. "G1_FUSE_DEC,G1 fuse decoder enable active high for each bit"
group.long 0x0C++0x03
line.long 0x00 "G1_FUSE_PP_CSR,VPUMIX G1 fuse_pp control"
hexmask.long 0x00 0.--31. 1. "G1_FUSE_PP,G1 fuse post process enable active high for each bit"
group.long 0x10++0x03
line.long 0x00 "G2_FUSE_DEC_CSR,VPUMIX G2 fuse_dec control"
hexmask.long 0x00 0.--31. 1. "G2_FUSE_DEC,G2 fuse decoder enable active high for each bit"
group.long 0x14++0x03
line.long 0x00 "VC8000E_FUSE_ENC_CSR,VPUMIX VC8000E fuse_enc control"
hexmask.long 0x00 0.--31. 1. "VC8000E_FUSE_ENC,VC8000E fuse encoder enable active high for each bit"
group.long 0x18++0x03
line.long 0x00 "VPU_CACHE_EN_CSR,VPUMIX block cache enable control"
bitfld.long 0x00 5. "VC8000E_AWCACHE_EN,VC8000E AXI AW cacheable enable active high" "0: VC8000E_AWCACHE_EN_0,1: VC8000E_AWCACHE_EN_1"
bitfld.long 0x00 4. "VC8000E_ARCACHE_EN,VC8000E AXI AR cacheable enable active high" "0: VC8000E_ARCACHE_EN_0,1: VC8000E_ARCACHE_EN_1"
newline
bitfld.long 0x00 3. "G2_AWCACHE_EN,G2 AXI AW cacheable enable active high" "0: G2_AWCACHE_EN_0,1: G2_AWCACHE_EN_1"
bitfld.long 0x00 2. "G2_ARCACHE_EN,G2 AXI AR cacheable enable active high" "0: G2_ARCACHE_EN_0,1: G2_ARCACHE_EN_1"
newline
bitfld.long 0x00 1. "G1_AWCACHE_EN,G1 AXI AW cacheable enable active high" "0: G1_AWCACHE_EN_0,1: G1_AWCACHE_EN_1"
bitfld.long 0x00 0. "G1_ARCACHE_EN,G1 AXI AR cacheable enable active high" "0: G1_ARCACHE_EN_0,1: G1_ARCACHE_EN_1"
rgroup.long 0x1C++0x03
line.long 0x00 "VPU_NO_PENDING_CSR,VPUMIX block pending transaction status"
bitfld.long 0x00 2. "VC8000E_NO_PENDING,pending transaction status of NOC AXI port connected with VC8000E" "0,1"
bitfld.long 0x00 1. "G2_NO_PENDING,pending transaction status of NOC AXI port connected with G2" "0,1"
newline
bitfld.long 0x00 0. "G1_NO_PENDING,pending transaction status of NOC AXI port connected with G1" "0,1"
group.long 0x20++0x03
line.long 0x00 "G1_OTR_BEAT_LIMIT_CSR,VPUMIX G1 outstanding read beat limit control"
bitfld.long 0x00 16. "G1_BEAT_LIMIT_ENABLE,G1 AXI outstanding read beat limit enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "G1_BEAT_LIMIT_NUM,G1 AXI outstanding read beat limit number"
group.long 0x24++0x03
line.long 0x00 "G2_OTR_BEAT_LIMIT_CSR,VPUMIX G2 outstanding read beat limit control"
bitfld.long 0x00 16. "G2_BEAT_LIMIT_ENABLE,G2 AXI outstanding read beat limit enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "G2_BEAT_LIMIT_NUM,G2 AXI outstanding read beat limit number"
group.long 0x28++0x03
line.long 0x00 "VC8000E_OTR_BEAT_LIMIT_CSR,VPUMIX VC8000E outstanding read beat limit control"
bitfld.long 0x00 16. "VC8000E_BEAT_LIMIT_ENABLE,VC8000E AXI outstanding read beat limit enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "VC8000E_BEAT_LIMIT_NUM,VC8000E AXI outstanding read beat limit number"
tree.end
tree "VPU_G1"
base ad:0x38300000
group.long 0x04++0x03
line.long 0x00 "SWREG1,Interrupt register decoder"
bitfld.long 0x00 24. "SW_DEC_PIC_INF,B slice detected" "0,1"
bitfld.long 0x00 18. "SW_DEC_TIMEOUT,Interrupt status bit decoder timeout" "0,1"
newline
bitfld.long 0x00 17. "SW_DEC_SLICE_INT,Interrupt status bit dec_slice_decoded" "0,1"
bitfld.long 0x00 16. "SW_DEC_ERROR_INT,Interrupt status bit input stream error" "0,1"
newline
bitfld.long 0x00 15. "SW_DEC_ASO_INT,H264: Interrupt status bit ASO (Arbitrary Slice Ordering) detected" "0,1"
bitfld.long 0x00 14. "SW_DEC_BUFFER_INT,Interrupt status bit input buffer empty" "0,1"
newline
bitfld.long 0x00 13. "SW_DEC_BUS_INT,Interrupt status bit bus" "0,1"
bitfld.long 0x00 12. "SW_DEC_RDY_INT,Interrupt status bit decoder" "0,1"
newline
bitfld.long 0x00 8. "SW_DEC_IRQ,Decoder IRQ" "0,1"
bitfld.long 0x00 5. "SW_DEC_ABORT_E,Abort decoding enable" "0,1"
newline
bitfld.long 0x00 4. "SW_DEC_IRQ_DIS,Decoder IRQ disable" "0,1"
bitfld.long 0x00 0. "SW_DEC_E,Decoder enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SWREG2,Device configuration register decoder"
hexmask.long.byte 0x00 24.--31. 1. "SW_DEC_AXI_RD_ID,Read ID used for decoder reading services in AXI bus (if connected to AXI)"
bitfld.long 0x00 23. "SW_DEC_TIMEOUT_E,Timeout interrupt enable" "0,1"
newline
bitfld.long 0x00 22. "SW_DEC_STRSWAP32_E,Decoder input 32bit data swap for stream data (may be used for 64 bit environment)" "0: no swapping of 32 bit words,1: 32 bit data words are swapped (needed in 64.."
bitfld.long 0x00 21. "SW_DEC_STRENDIAN_E,Decoder input endian mode for stream data" "0: Big endian (0-1-2-3 order),1: Little endian (3-2-1-0 order)"
newline
bitfld.long 0x00 20. "SW_DEC_INSWAP32_E,Decoder input 32bit data swap for other than stream data (may be used for 64 bit environment)" "0: no swapping of 32 bit words,1: 32 bit data words are swapped (needed in 64.."
bitfld.long 0x00 19. "SW_DEC_OUTSWAP32_E,Decoder output 32bit data swap (may be used for 64 bit environment)" "0: no swapping of 32 bit words,1: 32 bit data words are swapped (needed in 64.."
newline
bitfld.long 0x00 18. "SW_DEC_DATA_DISC_E,Data discard enable" "0,1"
bitfld.long 0x00 17. "SW_TILED_MODE_MSB,Tiled mode msb" "0: Tiled mode not enabled,1: Tiled mode enabled for 8x4 tile size"
newline
bitfld.long 0x00 11.--16. "SW_DEC_LATENCY,Decoder master interface additional latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 10. "SW_DEC_CLK_GATE_E,Decoder dynamic clock gating enable" "0: Clock is running for all structures,1: Clock is gated for decoder structures that.."
newline
bitfld.long 0x00 9. "SW_DEC_IN_ENDIAN,Decoder input endian mode for other than stream data" "0: Big endian (0-1-2-3 order),1: Little endian (3-2-1-0 order)"
bitfld.long 0x00 8. "SW_DEC_OUT_ENDIAN,Decoder output endian mode" "0: Big endian (0-1-2-3 order),1: Little endian (3-2-1-0 order)"
newline
bitfld.long 0x00 7. "SW_TILED_MODE_LSB,Tiled mode lsb" "0,1"
bitfld.long 0x00 6. "SW_DEC_ADV_PRE_DIS,Advanced PREFETCH mode disable (advanced reference picture reading mode for video)" "0,1"
newline
bitfld.long 0x00 5. "SW_DEC_SCMD_DIS,9170 decoder and later->: AXI Single Command Multiple Data disable" "0,1"
bitfld.long 0x00 0.--4. "SW_DEC_MAX_BURST,Maximum burst length for decoder bus transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x0C++0x03
line.long 0x00 "SWREG3,Decoder control register 0 (decmode picture type etc)"
bitfld.long 0x00 28.--31. "SW_DEC_MODE,Decoding mode" "0: SW_DEC_MODE_0,?,?,?,?,?,?,?,?,?,10: SW_DEC_MODE_10,?..."
bitfld.long 0x00 27. "SW_RLC_MODE_E,RLC mode enable" "0: HW decodes video from bit stream (VLC mode) +..,1: HW decodes video from RLC input data + side.."
newline
bitfld.long 0x00 26. "SW_SKIP_MODE,VP8" "0: HW decodes mb_coeff_skip -flag,1: HW does not decode mb_coeff_skip -flag"
bitfld.long 0x00 23. "SW_PIC_INTERLACE_E,Coding mode of the current picture" "0: SW_PIC_INTERLACE_E_0,1: SW_PIC_INTERLACE_E_1"
newline
bitfld.long 0x00 22. "SW_PIC_FIELDMODE_E,Structure of the current picture (residual structure)" "0: Frame structure,1: SW_PIC_FIELDMODE_E_1"
bitfld.long 0x00 21. "SW_PIC_B_E,B picture enable for current picture" "0: picture type is I or P depending on..,1: picture type is B depending on sw_pic_inter_e.."
newline
bitfld.long 0x00 20. "SW_PIC_INTER_E,Picture type" "0: SW_PIC_INTER_E_0,1: SW_PIC_INTER_E_1"
bitfld.long 0x00 19. "SW_PIC_TOPFIELD_E,If field structure is enabled this bit informs which one of the fields is being decoded" "0: SW_PIC_TOPFIELD_E_0,1: SW_PIC_TOPFIELD_E_1"
newline
bitfld.long 0x00 18. "SW_FWD_INTERLACE_E,Coding mode of forward reference picture" "0: SW_FWD_INTERLACE_E_0,1: SW_FWD_INTERLACE_E_1"
bitfld.long 0x00 16. "SW_REF_TOPFIELD_E,Indicates which field should be used as reference if sw_ref_frames = '0'" "0: SW_REF_TOPFIELD_E_0,1: SW_REF_TOPFIELD_E_1"
newline
bitfld.long 0x00 15. "SW_DEC_OUT_DIS,Disable decoder output picture writing" "0: Decoder output picture is written to external..,1: Decoder output picture is not written to.."
bitfld.long 0x00 14. "SW_FILTERING_DIS,De-block filtering disable" "0: filtering is enabled for current picture,1: filtering is disabled for current picture"
newline
bitfld.long 0x00 13. "SW_WEBP_E,SW_WEBP_E: Webp enable for VP8:'0' = Normal VP8 '1' = WEBP picture SW_MVC_E: Multi View Coding enable" "0,1"
bitfld.long 0x00 12. "SW_WRITE_MVS_E,Direct mode motion vector write enable for current picture / VPX motion vector write enable for error concealment purposes" "0: Writing disabled for current picture,1: The direct mode motion vectors are written to.."
newline
bitfld.long 0x00 11. "SW_REFTOPFIRST_E,Indicates which FWD reference field has been decoded first" "0: FWD reference bottom field,1: FWD reference top field"
bitfld.long 0x00 10. "SW_SEQ_MBAFF_E,Sequence includes MBAFF coded pictures" "0,1"
newline
bitfld.long 0x00 9. "SW_PICORD_COUNT_E,h264_high config: Picture order count table read enable" "0,1"
bitfld.long 0x00 8. "SW_DEC_AHB_HLOCK_E,AHB master HLOCK enable" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_DEC_AXI_WR_ID,Write ID used for decoder writing services in AXI bus (if connected to AXI)"
group.long 0x30++0x03
line.long 0x00 "SWREG12,Base address for RLC data (RLC) / stream start address/decoded end addr register (VLC)"
hexmask.long 0x00 0.--31. 1. "SW_RLC_VLC_BASE,RLC mode: Base address for RLC data (swreg3"
group.long 0x34++0x03
line.long 0x00 "SWREG13,Base address for decoded picture"
hexmask.long 0x00 2.--31. 1. "SW_DEC_OUT_BASE,Video: Base address for decoder output picture"
bitfld.long 0x00 1. "SW_DPB_ILACE_MODE,DPB ilaced mode: '0' : DPB consist of ilaced/progressive frames '1' : DPB consist of progressive frames / separate fields" "0,1"
group.long 0xA0++0x03
line.long 0x00 "SWREG40,Base address for standard dependent tables"
hexmask.long 0x00 2.--31. 1. "SW_QTABLE_BASE,Base address for standard dependent tables"
group.long 0xA4++0x03
line.long 0x00 "SWREG41,Base address for direct mode motion vectors"
hexmask.long 0x00 2.--31. 1. "SW_DIR_MV_BASE,Direct mode motion vector write/read base address"
group.long 0xC0++0x03
line.long 0x00 "SWREG48,Error concealment register"
hexmask.long.word 0x00 23.--31. 1. "SW_STARTMB_X,Start MB from SW for X dimension"
hexmask.long.word 0x00 14.--22. 1. "SW_STARTMB_Y,Start MB from SW for Y dimension"
newline
bitfld.long 0x00 12.--13. "SW_ERROR_CONC_MODE,Error concealment mode" "0: disabled (normal decoding mode),1: enabled for direct mode MV usage starting..,?..."
group.long 0xC4++0x03
line.long 0x00 "SWREG49,Prediction filter tap register for H264"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_0_0,Prediction filter set 0 tap 0"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_0_1,Prediction filter set 0 tap 1"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_0_2,Prediction filter set 0 tap 2"
rgroup.long 0xC8++0x03
line.long 0x00 "SWREG50,Synthesis configuration register decoder 0"
bitfld.long 0x00 24.--25. "SW_DEC_H264_PROF,Decoding format support H.264" "0: SW_DEC_H264_PROF_0,1: supported up to baseline profile,2: supported up to high profile labeled stream..,3: supported up to high profile"
bitfld.long 0x00 21. "SW_DEC_OBUFF_LEVEL,Decoder output buffer level" "0: 1 MB buffering is used,1: 4 MB buffering is used"
newline
bitfld.long 0x00 20. "SW_REF_BUFF_EXIST,Reference picture buffer usage" "0: SW_REF_BUFF_EXIST_0,1: reference buffer is used"
bitfld.long 0x00 16.--19. "SW_DEC_BUS_STRD,Connected to standard bus" "0: SW_DEC_BUS_STRD_0,1: AHB master AHB slave,2: OCP master OCP slave,3: AXI master AXI slave,4: AXI master APB slave,5: AXI master AHB slave,?..."
newline
bitfld.long 0x00 14.--15. "SW_DEC_SYNTH_LAN,no description available" "0: SW_DEC_SYNTH_LAN_0,1: SW_DEC_SYNTH_LAN_1,2: SW_DEC_SYNTH_LAN_2,?..."
bitfld.long 0x00 12.--13. "SW_DEC_BUS_WIDTH,no description available" "0: SW_DEC_BUS_WIDTH_0,1: SW_DEC_BUS_WIDTH_1,2: SW_DEC_BUS_WIDTH_2,3: SW_DEC_BUS_WIDTH_3"
newline
bitfld.long 0x00 11. "SW_DEC_SOREN_PROF,Decoding format support Sorenson" "0: SW_DEC_SOREN_PROF_0,1: SW_DEC_SOREN_PROF_1"
hexmask.long.word 0x00 0.--10. 1. "SW_DEC_MAX_OWIDTH,Max configured decoder video resolution that can be decoded"
group.long 0xCC++0x03
line.long 0x00 "SWREG51,Reference picture buffer control register"
bitfld.long 0x00 31. "SW_REFBU_E,Refer picture buffer enable" "0: refer picture buffer disabled,1: refer picture buffer enabled"
hexmask.long.word 0x00 19.--30. 1. "SW_REFBU_THR,Reference buffer disable threshold value (cache miss amount)"
newline
bitfld.long 0x00 14.--18. "SW_REFBU_PICID,The used reference picture ID for reference buffer usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 13. "SW_REFBU_EVAL_E,Enable for HW internal reference ID calculation" "0,1"
newline
bitfld.long 0x00 12. "SW_REFBU_FPARMOD_E,Field parity mode enable" "0: use the result field of the evaluation,1: use the parity mode field"
hexmask.long.word 0x00 0.--8. 1. "SW_REFBU_Y_OFFSET,Y offset for refbufferd"
rgroup.long 0xD0++0x03
line.long 0x00 "SWREG52,Reference picture buffer information register 1"
hexmask.long.word 0x00 16.--31. 1. "SW_REFBU_HIT_SUM,The sum of the refbufferd hits of the picture"
hexmask.long.word 0x00 0.--15. 1. "SW_REFBU_INTRA_SUM,The sum of the luminance 8x8 intra partitions of the picture"
rgroup.long 0xD4++0x03
line.long 0x00 "SWREG53,Reference picture buffer information register 2"
hexmask.long.tbyte 0x00 0.--21. 1. "SW_REFBU_Y_MV_SUM,The sum of the decoded motion vector y-components of the picture"
rgroup.long 0xD8++0x03
line.long 0x00 "SWREG54,Synthesis configuration register decoder 1"
bitfld.long 0x00 30. "SW_DEC_REFBU_ILACE,Refbufferd support for interlaced content" "0: SW_DEC_REFBU_ILACE_0,1: SW_DEC_REFBU_ILACE_1"
bitfld.long 0x00 29. "SW_DEC_DIVX_PROF,DIVX Support" "0: SW_DEC_DIVX_PROF_0,1: SW_DEC_DIVX_PROF_1"
newline
bitfld.long 0x00 28. "SW_REF_BUFF2_EXIST,Reference picture buffer 2 usage" "0: SW_REF_BUFF2_EXIST_0,1: reference buffer 2 is used"
bitfld.long 0x00 25. "SW_DEC_RTL_ROM,ROM implementation type (If design includes ROMs)" "0: ROMs are implemented from actual ROM units,1: ROMs are implemented from RTL"
newline
bitfld.long 0x00 23. "SW_DEC_VP8_PROF,Decoding format support VP8" "0: SW_DEC_VP8_PROF_0,1: SW_DEC_VP8_PROF_1"
bitfld.long 0x00 20. "SW_DEC_MVC_PROF,Decoding format support MVC" "0: SW_DEC_MVC_PROF_0,1: SW_DEC_MVC_PROF_1"
newline
bitfld.long 0x00 19. "SW_DEC_WEBP_E,Decoding format support Web-p" "0: not supported bigger than 1080p resolution,1: supported upto 16kx16k pixel resolution.."
bitfld.long 0x00 17.--18. "SW_DEC_TILED_L,Tiled mode support level" "0: SW_DEC_TILED_L_0,1: supported with 8x4 tile size for progressive..,2: supported with 8x4 tile size for..,?..."
newline
bitfld.long 0x00 16. "SW_DEC_VP8S_ARCH,VP8 Architecture type (for prediction)" "0: Same prediction architecture as for other..,1: Dedicated small architecture for VP8.."
bitfld.long 0x00 14.--15. "SW_DEC_MAX_OW_EXT,Max configured decoder video resolution that can be decoded" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "SW_DEC_ERRCO_LEVEL,Decoder error concealment support level" "0: Error concealment not supported (only error..,1: VP8 direct mode motion vector error..,?..."
bitfld.long 0x00 11. "SW_VP8_STRIDE_E,Decoder output stride support for VP8" "0: not supported Y and C tables attached,1: supported Y and C tables can be set freely"
newline
bitfld.long 0x00 10. "SW_DPB_FIELD_E,DPB field separate mode support for ilaced content" "0: Not supported,1: Supported"
bitfld.long 0x00 7.--9. "SW_DEC_CORE_AM,Decoder core amount" "0: single core decoder,1: dual core decoder,2: SW_DEC_CORE_AM_2,3: SW_DEC_CORE_AM_3,4: SW_DEC_CORE_AM_4,5: SW_DEC_CORE_AM_5,6: SW_DEC_CORE_AM_6,7: SW_DEC_CORE_AM_7"
group.long 0xDC++0x03
line.long 0x00 "SWREG55,Reference picture buffer 2 / Advanced prefetch control register"
bitfld.long 0x00 31. "SW_REFBU2_BUF_E,Refer picture buffer 2 enable" "0: refer picture buffer disabled,1: refer picture buffer enabled"
hexmask.long.word 0x00 19.--30. 1. "SW_REFBU2_THR,Reference buffer disable threshold value (buffer miss amount)"
newline
bitfld.long 0x00 14.--18. "SW_REFBU2_PICID,The used reference picture ID for reference buffer usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--13. 1. "SW_APF_THRESHOLD,G1 decoder and later :Advanced prefetch threshold value"
rgroup.long 0xE0++0x03
line.long 0x00 "SWREG56,Reference buffer information register 3"
hexmask.long.word 0x00 16.--31. 1. "SW_REFBU_TOP_SUM,The sum of the top partitions of the picture"
hexmask.long.word 0x00 0.--15. 1. "SW_REFBU_BOT_SUM,The sum of the bottom partitions of the picture"
rgroup.long 0xE4++0x03
line.long 0x00 "SWREG57,Decoder fuse register"
bitfld.long 0x00 31. "FUSE_DEC_H264," "0,1"
bitfld.long 0x00 20. "FUSE_DEC_VP8," "0,1"
newline
bitfld.long 0x00 18. "FUSE_DEC_MVC," "0,1"
bitfld.long 0x00 16. "FUSE_DEC_MAXW_4K," "0,1"
newline
bitfld.long 0x00 15. "FUSE_DEC_MAXW_1920," "0,1"
bitfld.long 0x00 14. "FUSE_DEC_MAXW_1280," "0,1"
newline
bitfld.long 0x00 13. "FUSE_DEC_MAXW_720," "0,1"
bitfld.long 0x00 12. "FUSE_DEC_MAXW_352," "0,1"
newline
bitfld.long 0x00 7. "FUSE_DEC_REFBUFFER," "0,1"
group.long 0xE8++0x03
line.long 0x00 "SWREG58,Device configuration register decoder 2 + Multi core control register"
bitfld.long 0x00 31. "SW_SERV_MERGE_DIS,Decoder service merge disable" "0: HW merges simultaneous sub-block requests..,1: decoder serves one sub-block per service and.."
bitfld.long 0x00 30. "SW_DEC_MULTICORE_E,Decoder multi core enable" "0: Multi core disabled or only one core exists..,1: Multi core enable"
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bitfld.long 0x00 29. "SW_DEC_WRITESTAT_E,Decoder write statusword enable" "0,1"
bitfld.long 0x00 27.--28. "SW_DEC_MC_POLLMODE,Decoder multicore status reading mode" "0: HW internal status polling mechanism is used,1: Dummy status polling mechanism is used for..,?..."
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hexmask.long.word 0x00 17.--26. 1. "SW_DEC_MC_POLLTIME,sw_dec_mc_polltime definition depends on sw_dec_mc_mode"
group.long 0xEC++0x03
line.long 0x00 "SWREG59,H264 Chrominance 8 pixel interleaved data base"
hexmask.long 0x00 2.--31. 1. "SW_DEC_CH8PIX_BASE,Base address for additional chrominance data format where chrominance is interleaved in group of 8 pixels"
group.long 0xF0++0x03
line.long 0x00 "SWREG60,Interrupt register post-processor"
bitfld.long 0x00 13. "SW_PP_BUS_INT,Interrupt status bit bus" "0,1"
bitfld.long 0x00 12. "SW_PP_RDY_INT,Interrupt status bit pp" "0,1"
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bitfld.long 0x00 8. "SW_PP_IRQ,Post-processor IRQ" "0,1"
bitfld.long 0x00 4. "SW_PP_IRQ_DIS,Post-processor IRQ disable" "0,1"
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bitfld.long 0x00 1. "SW_PP_PIPELINE_E,Decoder - post-processing pipeline enable" "0: Post-processing is processing different..,1: Post-processing is performed in pipeline with.."
bitfld.long 0x00 0. "SW_PP_E,External mode post-processing enable" "0,1"
group.long 0xF4++0x03
line.long 0x00 "SWREG61,Device configuration register post-processor"
hexmask.long.byte 0x00 24.--31. 1. "SW_PP_AXI_RD_ID,Read ID used for AXI PP read services (if connected to AXI)"
hexmask.long.byte 0x00 16.--23. 1. "SW_PP_AXI_WR_ID,Write ID used for AXI PP write services (if connected to AXI)"
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bitfld.long 0x00 15. "SW_PP_AHB_HLOCK_E,AHB master HLOCK enable" "0,1"
bitfld.long 0x00 14. "SW_PP_SCMD_DIS,9170 decoder: AXI Single Command Multiple Data disable" "0,1"
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bitfld.long 0x00 13. "SW_PP_IN_A2_ENDSEL,Endian/swap select for Alpha blend input source 2" "0: Use PP in endian/swap definitions..,1: Use Ablend source 1 endian/swap definitions.."
bitfld.long 0x00 12. "SW_PP_IN_A1_SWAP32,Alpha blend source 1 input 32bit data swap (may be used for 64 bit environment)" "0: no swapping of 32 bit words,1: 32 bit data words are swapped (needed in 64.."
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bitfld.long 0x00 11. "SW_PP_IN_A1_ENDIAN,Alpha blend source 1 input data byte endian mode" "0: Big endian (0-1-2-3 order),1: Little endian (3-2-1-0 order)"
bitfld.long 0x00 10. "SW_PP_IN_SWAP32_E,PP input 32bit data swap (may be used for 64 bit environment)" "0: no swapping of 32 bit words,1: 32 bit data words are swapped (needed in 64.."
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bitfld.long 0x00 9. "SW_PP_DATA_DISC_E,PP data discard enable" "0,1"
bitfld.long 0x00 8. "SW_PP_CLK_GATE_E,PP dynamic clock gating enable" "0: Clock is running for all PP structures,1: Clock is gated from PP structures that are.."
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bitfld.long 0x00 7. "SW_PP_IN_ENDIAN,PP input picture byte endian mode" "0: Big endian (0-1-2-3 order),1: Little endian (3-2-1-0 order)"
bitfld.long 0x00 6. "SW_PP_OUT_ENDIAN,PP output picture endian mode for YCbCr data or for any data if config value SW_PP_OEN_VERSION = 1" "0: Big endian (0-1-2-3 order),1: Little endian (3-2-1-0 order)"
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bitfld.long 0x00 5. "SW_PP_OUT_SWAP32_E,PP output data word swap (may be used for 64 bit environment)" "0: no swapping of 32 bit words,1: 32 bit data words are swapped (needed in 64.."
bitfld.long 0x00 0.--4. "SW_PP_MAX_BURST,Maximum burst length for PP bus transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF8++0x03
line.long 0x00 "SWREG62,Deinterlace control register"
bitfld.long 0x00 31. "SW_DEINT_E,De-interlace enable" "0,1"
hexmask.long.word 0x00 16.--29. 1. "SW_DEINT_THRESHOLD,Threshold value used in deinterlacing"
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bitfld.long 0x00 15. "SW_DEINT_BLEND_E,Blend enable for de-interlacing" "0,1"
hexmask.long.word 0x00 0.--14. 1. "SW_DEINT_EDGE_DET,Edge detect value used for deinterlacing"
group.long 0xFC++0x03
line.long 0x00 "SWREG63,Base address for reading post-processing input picture luminance (top field/frame)"
hexmask.long 0x00 2.--31. 1. "SW_PP_IN_LU_BASE,Base address for post-processing input luminance picture"
group.long 0x100++0x03
line.long 0x00 "SWREG64,Base address for reading post-processing input picture Cb/Ch (top field/frame)"
hexmask.long 0x00 2.--31. 1. "SW_PP_IN_CB_BASE,Base address for post-processing input Cb picture or for both chrominance pictures (if chrominances interleaved)"
group.long 0x104++0x03
line.long 0x00 "SWREG65,Base address for reading post-processing input picture Cr"
hexmask.long 0x00 2.--31. 1. "SW_PP_IN_CR_BASE,Base address for post-processing input cr picture"
group.long 0x108++0x03
line.long 0x00 "SWREG66,Base address for writing post-processed picture luminance/RGB"
hexmask.long 0x00 0.--31. 1. "SW_PP_OUT_LU_BASE,Base address for post-processing output picture (luminance/YUYV/RGB)"
group.long 0x10C++0x03
line.long 0x00 "SWREG67,Base address for writing post-processed picture Ch"
hexmask.long 0x00 0.--31. 1. "SW_PP_OUT_CH_BASE,Base address for post-processing output chrominance picture (interleaved chrominance)"
group.long 0x110++0x03
line.long 0x00 "SWREG68,Register for contrast adjusting"
hexmask.long.byte 0x00 24.--31. 1. "SW_CONTRAST_THR1,Threshold value 1 used with contrast adjusting"
hexmask.long.word 0x00 10.--19. 1. "SW_CONTRAST_OFF2,Offset value 2 used with contrast adjusting"
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hexmask.long.word 0x00 0.--9. 1. "SW_CONTRAST_OFF1,Offset value 1 used with contrast adjusting"
group.long 0x114++0x03
line.long 0x00 "SWREG69,Register for colour conversion and contrast adjusting/YUYV 422 channel orders"
bitfld.long 0x00 31. "SW_PP_IN_START_CH,For YUYV 422 input format" "0: the order is Y0CbY0Cr or Y0CrY0Cb,1: the order is CbY0CrY0 or CrY0CbY0"
bitfld.long 0x00 30. "SW_PP_IN_CR_FIRST,For YUYV 422 input format" "0: the order is Y0CbY0Cr or CbY0CrY0 (if 420..,1: the order is Y0CrY0Cb or CrY0CbY0 (if 420.."
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bitfld.long 0x00 29. "SW_PP_OUT_START_CH,For YUYV 422 output format" "0: the order is Y0CbY0Cr or Y0CrY0Cb,1: the order is CbY0CrY0 or CrY0CbY0"
bitfld.long 0x00 28. "SW_PP_OUT_CR_FIRST,For YUYV 422 output format" "0: the order is Y0CbY0Cr or CbY0CrY0,1: the order is Y0CrY0Cb or CrY0CbY0"
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hexmask.long.word 0x00 18.--27. 1. "SW_COLOR_COEFFA2,Coefficient a2 used with Y pixel to calculate all color components"
hexmask.long.word 0x00 8.--17. 1. "SW_COLOR_COEFFA1,Coefficient a1 used with Y pixel to calculate all color components"
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hexmask.long.byte 0x00 0.--7. 1. "SW_CONTRAST_THR2,Threshold value 2 used with contrast adjusting"
group.long 0x118++0x03
line.long 0x00 "SWREG70,Register for colour conversion 0"
bitfld.long 0x00 30.--31. "SW_PP_OUT_H_EXT,Extended output height for 4k resolution" "0,1,2,3"
hexmask.long.word 0x00 20.--29. 1. "SW_COLOR_COEFFD,Coefficient d used with Cb to calculate green component value"
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hexmask.long.word 0x00 10.--19. 1. "SW_COLOR_COEFFC,Coefficient c used with Cr to calculate green component value"
hexmask.long.word 0x00 0.--9. 1. "SW_COLOR_COEFFB,Coefficient b used with Cr to calculate red component value"
group.long 0x11C++0x03
line.long 0x00 "SWREG71,Register for colour conversion 1 + rotation mode"
bitfld.long 0x00 30.--31. "SW_PP_OUT_W_EXT,Extended output width for 4k resolution" "0,1,2,3"
hexmask.long.word 0x00 21.--29. 1. "SW_CROP_STARTX,Start coordinate x for the cropped area in macroblocks"
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bitfld.long 0x00 18.--20. "SW_ROTATION_MODE,Rotation mode" "0: SW_ROTATION_MODE_0,1: SW_ROTATION_MODE_1,2: SW_ROTATION_MODE_2,3: horizontal flip (mirror),4: SW_ROTATION_MODE_4,5: SW_ROTATION_MODE_5,?..."
hexmask.long.byte 0x00 10.--17. 1. "SW_COLOR_COEFFF,Coefficient f used with Y to adjust brightness"
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hexmask.long.word 0x00 0.--9. 1. "SW_COLOR_COEFFE,Coefficient e used with Cb to calculate blue component value"
group.long 0x120++0x03
line.long 0x00 "SWREG72,PP input size and -cropping register"
hexmask.long.byte 0x00 24.--31. 1. "SW_CROP_STARTY,Start coordinate y for the cropped area in macroblocks"
bitfld.long 0x00 18.--22. "SW_RANGEMAP_COEF_Y,Range map value for Y component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 9.--16. 1. "SW_PP_IN_HEIGHT,PP input picture height in MBs"
hexmask.long.word 0x00 0.--8. 1. "SW_PP_IN_WIDTH,PP input picture width in MBs"
group.long 0x124++0x03
line.long 0x00 "SWREG73,PP input picture base address for Y bottom field"
hexmask.long 0x00 2.--31. 1. "SW_PP_BOT_YIN_BASE,PP input Y base for bottom field"
group.long 0x128++0x03
line.long 0x00 "SWREG74,PP input picture base for Ch bottom field"
hexmask.long 0x00 2.--31. 1. "SW_PP_BOT_CIN_BASE,PP input C base for bottom field (mixed chrominance)"
group.long 0x13C++0x03
line.long 0x00 "SWREG79,Scaling register 0 ratio and padding for R and G"
bitfld.long 0x00 31. "SW_RANGEMAP_Y_E,Range map enable for Y component" "0,1"
bitfld.long 0x00 30. "SW_RANGEMAP_C_E,Range map enable for chrominance component" "0,1"
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bitfld.long 0x00 29. "SW_YCBCR_RANGE,Defines the YCbCr range in RGB conversion" "0: 16...235 for Y 16...240 for Chrominance,1: 0...255 for all components"
bitfld.long 0x00 28. "SW_RGB_PIX_IN32,RGB pixel amount/ 32 bit word" "0: 1 RGB pixel/32 bit,1: 2 RGB pixels/32 bit"
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bitfld.long 0x00 23.--27. "SW_RGB_R_PADD,Amount of ones that will be padded in front of the R-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18.--22. "SW_RGB_G_PADD,Amount of ones that will be padded in front of the G-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.tbyte 0x00 0.--17. 1. "SW_SCALE_WRATIO,Scaling ratio for width (outputw-1/inputw-1)"
group.long 0x140++0x03
line.long 0x00 "SWREG80,Scaling ratio register 1 and padding for B"
bitfld.long 0x00 30. "SW_PP_FAST_SCALE_E,no description available" "0: fast downscaling is not enabled,1: fast downscaling is enabled"
bitfld.long 0x00 27.--29. "SW_PP_IN_STRUCT,PP input data picture structure" "0: Top field / progressive frame structure,1: Bottom field structure,2: Interlaced field structure,3: Interlaced frame structure,4: Ripped top field structure,5: Ripped bottom field structure,?..."
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bitfld.long 0x00 25.--26. "SW_HOR_SCALE_MODE,Horizontal scaling mode" "0: SW_HOR_SCALE_MODE_0,1: SW_HOR_SCALE_MODE_1,2: SW_HOR_SCALE_MODE_2,?..."
bitfld.long 0x00 23.--24. "SW_VER_SCALE_MODE,Vertical scaling mode" "0: SW_VER_SCALE_MODE_0,1: SW_VER_SCALE_MODE_1,2: SW_VER_SCALE_MODE_2,?..."
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bitfld.long 0x00 18.--22. "SW_RGB_B_PADD,Amount of ones that will be padded in front of the B-component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.tbyte 0x00 0.--17. 1. "SW_SCALE_HRATIO,Scaling ratio for height (outputh-1/inputh-1)"
group.long 0x144++0x03
line.long 0x00 "SWREG81,Scaling ratio register 2"
hexmask.long.word 0x00 16.--31. 1. "SW_WSCALE_INVRA,Inverse scaling ratio for width or ch (inputw-1 / outputw-1)"
hexmask.long.word 0x00 0.--15. 1. "SW_HSCALE_INVRA,Inverse scaling ratio for height or cv (inputh-1 / outputh-1)"
group.long 0x148++0x03
line.long 0x00 "SWREG82,Rmask register"
hexmask.long 0x00 0.--31. 1. "SW_R_MASK,Bit mask for R component (and alpha channel)"
group.long 0x14C++0x03
line.long 0x00 "SWREG83,Gmask register"
hexmask.long 0x00 0.--31. 1. "SW_G_MASK,Bit mask for G component (and alpha channel)"
group.long 0x150++0x03
line.long 0x00 "SWREG84,Bmask register"
hexmask.long 0x00 0.--31. 1. "SW_B_MASK,Bit mask for B component (and alpha channel)"
group.long 0x154++0x03
line.long 0x00 "SWREG85,Post-processor control register"
bitfld.long 0x00 29.--31. "SW_PP_IN_FORMAT,PP input picture data format" "0: YUYV 4:2:2 interleaved (supported only in..,1: YCbCr 4:2:0 Semi-planar in linear raster-scan..,2: YCbCr 4:2:0 planar (supported only in..,3: YCbCr 4:0:0 (supported only in pipelined mode),4: YCbCr 4:2:2 Semi-planar (supported only in..,5: YCbCr 4:2:0 Semi-planar in tiled format..,?,7: Escape pp input data format"
bitfld.long 0x00 26.--28. "SW_PP_OUT_FORMAT,PP output picture data format" "0: SW_PP_OUT_FORMAT_0,1: YCbCr 4:2:0 planar (Not supported),2: YCbCr 4:2:2 planar (Not supported),3: YUYV 4:2:2 interleaved,4: YCbCr 4:4:4 planar (Not supported),5: YCh 4:2:0 chrominance interleaved,6: YCh 4:2:2 (Not supported),7: YCh 4:4:4 (Not supported)"
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hexmask.long.word 0x00 15.--25. 1. "SW_PP_OUT_HEIGHT,Scaled picture height in pixels (Must be dividable by 2 or by any if Pixel Accurate PP output configuration is enabled) Max scaled picture height is 1920 pixels or maximum three times the input source height minus 8 pixels"
hexmask.long.word 0x00 4.--14. 1. "SW_PP_OUT_WIDTH,Scaled picture width in pixels"
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bitfld.long 0x00 3. "SW_PP_OUT_TILED_E,Tiled mode enable for PP output" "0,1"
bitfld.long 0x00 2. "SW_PP_OUT_SWAP16_E,PP output swap 16 swaps 16 bit half inside of 32 bit word" "0,1"
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bitfld.long 0x00 1. "SW_PP_CROP8_R_E,PP input picture width is not 16 pixels multiple" "0,1"
bitfld.long 0x00 0. "SW_PP_CROP8_D_E,PP input picture height is not 16 pixels multiple" "0,1"
group.long 0x158++0x03
line.long 0x00 "SWREG86,Mask 1 start coordinate register"
bitfld.long 0x00 29.--31. "SW_PP_IN_FORMAT_ES,Escape PP in format" "0: SW_PP_IN_FORMAT_ES_0,1: SW_PP_IN_FORMAT_ES_1,?..."
bitfld.long 0x00 23.--27. "SW_RANGEMAP_COEF_C,Range map value for chrominance component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 22. "SW_MASK1_ABLEND_E,Mask 1 alpha blending enable" "0,1"
hexmask.long.word 0x00 11.--21. 1. "SW_MASK1_STARTY,Vertical start pixel for mask area 1"
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hexmask.long.word 0x00 0.--10. 1. "SW_MASK1_STARTX,Horizontal start pixel for mask area 1"
group.long 0x15C++0x03
line.long 0x00 "SWREG87,Mask 2 start coordinate register + Mask extensions"
bitfld.long 0x00 29.--30. "SW_MASK1_STARTX_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
bitfld.long 0x00 27.--28. "SW_MASK1_STARTY_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
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bitfld.long 0x00 25.--26. "SW_MASK2_STARTX_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
bitfld.long 0x00 23.--24. "SW_MASK2_STARTY_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
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bitfld.long 0x00 22. "SW_MASK2_ABLEND_E,Mask 2 alpha blending enable" "0,1"
hexmask.long.word 0x00 11.--21. 1. "SW_MASK2_STARTY,Vertical start pixel for mask area 2"
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hexmask.long.word 0x00 0.--10. 1. "SW_MASK2_STARTX,Horizontal start pixel for mask area 2"
group.long 0x160++0x03
line.long 0x00 "SWREG88,Mask 1 size and PP original width register"
hexmask.long.word 0x00 23.--31. 1. "SW_EXT_ORIG_WIDTH,PP input picture original width in macro blocks"
bitfld.long 0x00 22. "SW_MASK1_E,Mask 1 enable" "0,1"
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hexmask.long.word 0x00 11.--21. 1. "SW_MASK1_ENDY,Mask 1 end coordinate y in pixels (inside of PPD output picture)"
hexmask.long.word 0x00 0.--10. 1. "SW_MASK1_ENDX,Mask 1 end coordinate x in pixels (inside of PPD output picture)"
group.long 0x164++0x03
line.long 0x00 "SWREG89,Mask 2 size register + mask extensions"
bitfld.long 0x00 29.--30. "SW_MASK1_ENDX_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
bitfld.long 0x00 27.--28. "SW_MASK1_ENDY_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
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bitfld.long 0x00 25.--26. "SW_MASK2_ENDX_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
bitfld.long 0x00 23.--24. "SW_MASK2_ENDY_EXT,Extended coordinate upto 4k resolution" "0,1,2,3"
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bitfld.long 0x00 22. "SW_MASK2_E,Mask 2 enable" "0,1"
hexmask.long.word 0x00 11.--21. 1. "SW_MASK2_ENDY,Mask 2 end coordinate y in pixels (inside of PP output picture)"
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hexmask.long.word 0x00 0.--10. 1. "SW_MASK2_ENDX,Mask 2 end coordinate x in pixels (inside of PP output picture)"
group.long 0x168++0x03
line.long 0x00 "SWREG90,PiP register 0"
bitfld.long 0x00 29. "SW_RIGHT_CROSS_E,Right side overcross enable" "0: No right side overcross,1: Right side overcross"
bitfld.long 0x00 28. "SW_LEFT_CROSS_E,Left side overcross enable" "0: No left side overcross,1: Left side overcross"
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bitfld.long 0x00 27. "SW_UP_CROSS_E,Upward overcross enable" "0: No upward overcross,1: Upward overcross"
bitfld.long 0x00 26. "SW_DOWN_CROSS_E,Downward overcross enable" "0: No downward overcross,1: Downward overcross"
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hexmask.long.word 0x00 15.--25. 1. "SW_UP_CROSS,Amount of upward overcross (vertical pixels outside of display from the upper side)"
bitfld.long 0x00 11.--12. "SW_DOWN_CROSS_EXT,Extended coordinate for 4k resolution" "0,1,2,3"
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hexmask.long.word 0x00 0.--10. 1. "SW_DOWN_CROSS,Amount of downward overcross (vertical pixels outside of display from the down side)"
group.long 0x16C++0x03
line.long 0x00 "SWREG91,PiP register 1 and dithering control"
bitfld.long 0x00 30.--31. "SW_DITHER_SELECT_R,Dithering control for R channel" "0: SW_DITHER_SELECT_R_0,1: use four-bit dither matrix,2: use five-bit dither matrix,3: use six-bit dither matrix"
bitfld.long 0x00 28.--29. "SW_DITHER_SELECT_G,Dithering control for G channel" "0: SW_DITHER_SELECT_G_0,1: use four-bit dither matrix,2: use five-bit dither matrix,3: use six-bit dither matrix"
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bitfld.long 0x00 26.--27. "SW_DITHER_SELECT_B,Dithering control for B channel" "0: SW_DITHER_SELECT_B_0,1: use four-bit dither matrix,2: use five-bit dither matrix,3: use six-bit dither matrix"
bitfld.long 0x00 22.--23. "SW_PP_TILED_MODE,Input data is in tiled mode (at the moment valid only for YCbCr 420 data pipeline or external mode)" "0: Tiled mode not used,1: Tiled mode enabled for 8x4 sized tiles,?..."
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hexmask.long.word 0x00 11.--21. 1. "SW_RIGHT_CROSS,Amount of right side overcross (Horizontal pixels outside of display from the right side)"
hexmask.long.word 0x00 0.--10. 1. "SW_LEFT_CROSS,Amount of left side overcross (Horizontal pixels outside of display from the left side)"
group.long 0x170++0x03
line.long 0x00 "SWREG92,Display width and PP input size extension register"
bitfld.long 0x00 29.--31. "SW_PP_IN_H_EXT,Extended PP input height" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "SW_PP_IN_W_EXT,Extended PP input width" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 23.--25. "SW_CROP_STARTY_EXT,Extended PP input crop start coordinate x" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "SW_CROP_STARTX_EXT,Extended PP input crop start coordinate y" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18.--19. "SW_RIGHT_CROSS_EXT,Extended coordinate for 4k resolution" "0,1,2,3"
bitfld.long 0x00 16.--17. "SW_LEFT_CROSS_EXT,Extended coordinate for 4k resolution" "0,1,2,3"
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bitfld.long 0x00 14.--15. "SW_UP_CROSS_EXT,Extended coordinate for 4k resolution" "0,1,2,3"
hexmask.long.word 0x00 0.--12. 1. "SW_DISPLAY_WIDTH,Width of the display in pixels"
group.long 0x174++0x03
line.long 0x00 "SWREG93,Base address for alpha blend 1 gui component"
hexmask.long 0x00 0.--31. 1. "SW_ABLEND1_BASE,Base address for alpha blending input 1 (if mask1 is used in alpha blending mode)"
group.long 0x178++0x03
line.long 0x00 "SWREG94,Base address for alpha blend 2 gui component"
hexmask.long 0x00 0.--31. 1. "SW_ABLEND2_BASE,Base address for alpha blending input 2 (if mask2 is used in alpha blending mode)"
group.long 0x17C++0x03
line.long 0x00 "SWREG95,Alpha blend input cropping register (scanline for cropping)"
hexmask.long.word 0x00 13.--25. 1. "SW_ABLEND2_SCANL,Scanline width in pixels for Ablend 2"
hexmask.long.word 0x00 0.--12. 1. "SW_ABLEND1_SCANL,Scanline width in pixels for Ablend 1"
rgroup.long 0x18C++0x03
line.long 0x00 "SWREG99,PP fuse register"
bitfld.long 0x00 31. "FUSE_PP_PP," "0,1"
bitfld.long 0x00 30. "FUSE_PP_DEINT," "0,1"
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bitfld.long 0x00 29. "FUSE_PP_ABLEND," "0,1"
bitfld.long 0x00 16. "FUSE_PP_MAXW_4K," "0,1"
newline
bitfld.long 0x00 15. "FUSE_PP_MAXW_1920," "0,1"
bitfld.long 0x00 14. "FUSE_PP_MAXW_1280," "0,1"
newline
bitfld.long 0x00 13. "FUSE_PP_MAXW_720," "0,1"
bitfld.long 0x00 12. "FUSE_PP_MAXW_352," "0,1"
rgroup.long 0x190++0x03
line.long 0x00 "SWREG100,Synthesis configuration register post-processor"
bitfld.long 0x00 31. "SW_ABLEND_CROP_E,Alpha blending support for input cropping" "0: Not supported,1: Supported"
bitfld.long 0x00 30. "SW_PPD_PIXAC_E,Pixel Accurate PP output mode exists" "0: PIP Scaling and masks can be adjusted by..,1: PIP Scaling and masks can be adjusted by.."
newline
bitfld.long 0x00 29. "SW_PPD_TILED_EXIST,PP output YCbYCr 422 tiled support (4x4 pixel tiles)" "0: SW_PPD_TILED_EXIST_0,1: SW_PPD_TILED_EXIST_1"
bitfld.long 0x00 28. "SW_PPD_DITH_EXIST,Dithering exists" "0: SW_PPD_DITH_EXIST_0,1: SW_PPD_DITH_EXIST_1"
newline
bitfld.long 0x00 26.--27. "SW_PPD_SCALE_LEVEL,Scaling support" "0: SW_PPD_SCALE_LEVEL_0,1: Scaling with lo performance architecture,2: Scaling with high performance architecture,3: Scaling with high performance architecture +.."
bitfld.long 0x00 25. "SW_PPD_DEINT_EXIST,De-interlacing exits" "0: SW_PPD_DEINT_EXIST_0,1: SW_PPD_DEINT_EXIST_1"
newline
bitfld.long 0x00 24. "SW_PPD_BLEND_EXIST,Alpha blending exists" "0: SW_PPD_BLEND_EXIST_0,1: SW_PPD_BLEND_EXIST_1"
bitfld.long 0x00 23. "SW_PPD_IBUFF_LEVEL,PP input buffering level" "0: 1 MB input buffering is used,1: 4 MB input buffering is used"
newline
bitfld.long 0x00 18. "SW_PPD_OEN_VERSION,PP output endian version" "0: Endian mode supported for other than RGB,1: Endian mode supported for any output format"
bitfld.long 0x00 17. "SW_PPD_OBUFF_LEVEL,PP output buffering level" "0: 1 unit output buffering is used,1: 4 unit output buffering is used"
newline
bitfld.long 0x00 16. "SW_PPD_PP_EXIST,PPD exists" "0: SW_PPD_PP_EXIST_0,1: SW_PPD_PP_EXIST_1"
bitfld.long 0x00 14.--15. "SW_PPD_IN_TILED_L,PPD input tiled mode support level" "0: SW_PPD_IN_TILED_L_0,1: 8x4 tile size supported,?..."
newline
hexmask.long.word 0x00 0.--12. 1. "SW_PPD_MAX_OWIDTH,Max supported PP output width in pixels"
group.long 0x198++0x03
line.long 0x00 "SWREG102,Base address for H264 decoded chroma picture"
hexmask.long 0x00 2.--31. 1. "SW_DEC_CH_BASE,Valid only if chroma address separate mode is enabled"
bitfld.long 0x00 0. "SW_CH_BASE_E,chroma address separate mode enable" "0: HW outputs decoded chroma picture to the end..,1: HW outputs decoded chroma picture to.."
group.long 0x19C++0x03
line.long 0x00 "SWREG103,Base address for reference chroma picture index 0"
hexmask.long 0x00 2.--31. 1. "SW_REFER0_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1A0++0x03
line.long 0x00 "SWREG104,Base address for reference chroma picture index 1"
hexmask.long 0x00 2.--31. 1. "SW_REFER1_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1A4++0x03
line.long 0x00 "SWREG105,Base address for reference chroma picture index 2"
hexmask.long 0x00 2.--31. 1. "SW_REFER2_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1A8++0x03
line.long 0x00 "SWREG106,Base address for reference chroma picture index 3"
hexmask.long 0x00 2.--31. 1. "SW_REFER3_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1AC++0x03
line.long 0x00 "SWREG107,Base address for reference chroma picture index 4"
hexmask.long 0x00 2.--31. 1. "SW_REFER4_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1B0++0x03
line.long 0x00 "SWREG108,Base address for reference chroma picture index 5"
hexmask.long 0x00 2.--31. 1. "SW_REFER5_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1B4++0x03
line.long 0x00 "SWREG109,Base address for reference chroma picture index 6"
hexmask.long 0x00 2.--31. 1. "SW_REFER6_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1B8++0x03
line.long 0x00 "SWREG110,Base address for reference chroma picture index 7"
hexmask.long 0x00 2.--31. 1. "SW_REFER7_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1BC++0x03
line.long 0x00 "SWREG111,Base address for reference chroma picture index 8"
hexmask.long 0x00 2.--31. 1. "SW_REFER8_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1C0++0x03
line.long 0x00 "SWREG112,Base address for reference chroma picture index 9"
hexmask.long 0x00 2.--31. 1. "SW_REFER9_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1C4++0x03
line.long 0x00 "SWREG113,Base address for reference chroma picture index 10"
hexmask.long 0x00 2.--31. 1. "SW_REFER10_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1C8++0x03
line.long 0x00 "SWREG114,Base address for reference chroma picture index 11"
hexmask.long 0x00 2.--31. 1. "SW_REFER11_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1CC++0x03
line.long 0x00 "SWREG115,Base address for reference chroma picture index 12"
hexmask.long 0x00 2.--31. 1. "SW_REFER12_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1D0++0x03
line.long 0x00 "SWREG116,Base address for reference chroma picture index 13"
hexmask.long 0x00 2.--31. 1. "SW_REFER13_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1D4++0x03
line.long 0x00 "SWREG117,Base address for reference chroma picture index 14"
hexmask.long 0x00 2.--31. 1. "SW_REFER14_CH_BASE,Valid only if chroma address separate mode is enabled"
group.long 0x1D8++0x03
line.long 0x00 "SWREG118,Base address for reference chroma picture index 15"
hexmask.long 0x00 2.--31. 1. "SW_REFER15_CH_BASE,Valid only if chroma address separate mode is enabled"
tree.end
tree "VPU_G1_H264 (VPU_G1)"
base ad:0x38300000
group.long 0x10++0x03
line.long 0x00 "SWREG4,Decoder control register 1 (picture parameters)"
hexmask.long.word 0x00 23.--31. 1. "SW_PIC_MB_WIDTH,Picture width in macroblocks = ((width in pixels + 15) /16)"
bitfld.long 0x00 19.--22. "SW_MB_WIDTH_OFF,The amount of meaningfull horizontal pixels in last MB (width offset) 0 if exactly 16 pixels multiple picture and all the horizontal pixels in last MB are meaningfull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 11.--18. 1. "SW_PIC_MB_HEIGHT_P,Picture height in macroblocks =((height in pixels+15)/16)"
bitfld.long 0x00 7.--10. "SW_MB_HEIGHT_OFF,The amount of meaningful vertical pixels in last MB (height offset 0 if exactly 16 pixels multiple picture and all the vertical pixels in last MB are meaningfull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "SW_ALT_SCAN_E,indicates alternative vertical scan method used for interlaced frames" "0,1"
bitfld.long 0x00 0.--4. "SW_REF_FRAMES,H.264: num_ref_frames maximum number of short and long term reference frames in decoded picture buffer VC-1: num_ref semantics" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "SWREG5,Decoder control register 2 (stream decoding table selects)"
bitfld.long 0x00 26.--31. "SW_STRM_START_BIT,Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "SW_SYNC_MARKER_E,Sync markers enable" "0: synch markers are not used,1: synch markers are used"
newline
bitfld.long 0x00 24. "SW_TYPE1_QUANT_E,MPEG4: Type 1 quantization enable'0' = type 2 inverse Q method '1' = type 1 inverse Q method (Q-tables used) H264 (h264_high config): scaling matrix enable'0' = normal transform '1' = use scaling matrix for transform (read from external.." "0,1"
bitfld.long 0x00 19.--23. "SW_CH_QP_OFFSET,Chroma Qp filter offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 14.--18. "SW_CH_QP_OFFSET2,Chroma Qp filter offset for cr type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "SW_FIELDPIC_FLAG_E,Flag for streamd that field_pic_flag exists in stream" "0,1"
group.long 0x18++0x03
line.long 0x00 "SWREG6,Decoder control register 3 (stream buffer information)"
bitfld.long 0x00 31. "SW_START_CODE_E,Bit for indicating stream start code existence" "0: stream doesn't contain start codes,1: stream contains start codes"
bitfld.long 0x00 25.--30. "SW_INIT_QP,Initial value for quantization parameter (picture quantizer)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "SW_CH_8PIX_ILEAV_E,Enable for additional chrominance data format writing where decoder writes chrominance in group of 8 pixels of Cb and then corresponding 8 pixels of Cr" "0,1"
hexmask.long.tbyte 0x00 0.--23. 1. "SW_STREAM_LEN,Amount of stream data bytes in input buffer"
group.long 0x1C++0x03
line.long 0x00 "SWREG7,Decoder control register 4 (H264 VC-1 VP6 and progressive JPEG control)"
bitfld.long 0x00 31. "SW_CABAC_E,CABAC enable" "0,1"
bitfld.long 0x00 30. "SW_BLACKWHITE_E,no description available" "0: 4:2:0 sampling format,1: 4:0:0 sampling format (H264 monochroma)"
newline
bitfld.long 0x00 29. "SW_DIR_8X8_INFER_E,Specifies the method to use to derive luma motion vectors in B_skip B_Direct_16x16 and B_direct_8x8_inference_flag (see direct_8x8_inference flag)" "0,1"
bitfld.long 0x00 28. "SW_WEIGHT_PRED_E,Weighted prediction enable for P slices" "0,1"
newline
bitfld.long 0x00 26.--27. "SW_WEIGHT_BIPR_IDC,weighted prediction specification for B slices" "0: default weighted prediction is applied to B..,1: explicit weighted prediction shall be applied..,2: implicit weighted prediction shall be applied..,?..."
bitfld.long 0x00 25. "SW_AVS_H264_H_EXT,Resolution extension to support 4k resolution for AVS/H264" "0,1"
newline
bitfld.long 0x00 16.--20. "SW_FRAMENUM_LEN,H.264: Bit length of frame_num in data stream RV: frame size length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "SW_FRAMENUM,current frame_num used to identify short-term reference frames"
group.long 0x20++0x03
line.long 0x00 "SWREG8,Decoder control register 5 (H264 VC-1 VP6 Progressive JPEG and RV control)"
bitfld.long 0x00 31. "SW_CONST_INTRA_E,constrained_intra_pred_flag equal to 1 specifies that intra prediction uses only neighbouring intra macroblocks in prediction" "0,1"
bitfld.long 0x00 30. "SW_FILT_CTRL_PRES,deblocking_filter_control_present_flag indicates whether extra variables controlling characteristics of the deblocking filter are present in the slice header" "0,1"
newline
bitfld.long 0x00 29. "SW_RDPIC_CNT_PRES,redundant_pic_cnt_present_flag specifies whether redundant_pic_cnt syntax elements are present in the slice header" "0,1"
bitfld.long 0x00 28. "SW_8X8TRANS_FLAG_E,8x8 transform flag enable for stream decoding" "0,1"
newline
hexmask.long.word 0x00 17.--27. 1. "SW_REFPIC_MK_LEN,Length of decoded reference picture marking bits"
bitfld.long 0x00 16. "SW_IDR_PIC_E,IDR (instantaneous decoding refresh) picture flag" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_IDR_PIC_ID,idr_pic_id identifies IDR (instantaneous decoding refresh) picture"
group.long 0x24++0x03
line.long 0x00 "SWREG9,Decoder control register 6 / base address for MB-control (RLC) / VC-1 intensity control 0/ VP6 VP7 VP8 ctrl-stream length/ RV pic slice amount"
hexmask.long.byte 0x00 24.--31. 1. "SW_PPS_ID,pic_parameter_set_id identifies the picture parameter set that is referred to in the slice header"
bitfld.long 0x00 19.--23. "SW_REFIDX1_ACTIVE,Specifies the maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 14.--18. "SW_REFIDX0_ACTIVE,Specifies the maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "SW_POC_LENGTH,Length of picture order count field in stream"
group.long 0x28++0x03
line.long 0x00 "SWREG10,Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register"
bitfld.long 0x00 25.--29. "SW_PINIT_RLIST_F9,Initial reference picture list for P forward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_PINIT_RLIST_F8,Initial reference picture list for P forward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_PINIT_RLIST_F7,Initial reference picture list for P forward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_PINIT_RLIST_F6,Initial reference picture list for P forward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_PINIT_RLIST_F5,Initial reference picture list for P forward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_PINIT_RLIST_F4,Initial reference picture list for P forward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2C++0x03
line.long 0x00 "SWREG11,Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2"
bitfld.long 0x00 25.--29. "SW_PINIT_RLIST_F15,Initial reference picture list for P forward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_PINIT_RLIST_F14,Initial reference picture list for P forward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_PINIT_RLIST_F13,Initial reference picture list for P forward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_PINIT_RLIST_F12,Initial reference picture list for P forward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_PINIT_RLIST_F11,Initial reference picture list for P forward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_PINIT_RLIST_F10,Initial reference picture list for P forward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x03
line.long 0x00 "SWREG14,Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture"
hexmask.long 0x00 2.--31. 1. "SW_REFER0_BASE,Base address for reference picture index 0"
bitfld.long 0x00 1. "SW_REFER0_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER0_TOPC_E,Which field of reference picture is closer to current picture" "0: Bottom field is closer to current picture,1: Top field is closer to current picture"
group.long 0x3C++0x03
line.long 0x00 "SWREG15,Base address for reference picture index 1 / JPEG control"
hexmask.long 0x00 2.--31. 1. "SW_REFER1_BASE,Base address for reference picture index 1"
bitfld.long 0x00 1. "SW_REFER1_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER1_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x40++0x03
line.long 0x00 "SWREG16,Base address for reference picture index 2 / List of VLC code lengths in first JPEG AC table"
hexmask.long 0x00 2.--31. 1. "SW_REFER2_BASE,Base address for reference picture index 2"
bitfld.long 0x00 1. "SW_REFER2_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER2_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x44++0x03
line.long 0x00 "SWREG17,Base address for reference picture index 3 / List of VLC code lengths in first JPEG AC table"
hexmask.long 0x00 2.--31. 1. "SW_REFER3_BASE,Base address for reference picture index 3"
bitfld.long 0x00 1. "SW_REFER3_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER3_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x48++0x03
line.long 0x00 "SWREG18,Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7 VP8 Golden refer picture base"
hexmask.long 0x00 2.--31. 1. "SW_REFER4_BASE,H264: Base address for reference picture index 4 VP6/VP7/VP8: Base address for Golden reference picture (corresponds picid 4)"
bitfld.long 0x00 1. "SW_REFER4_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER4_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x4C++0x03
line.long 0x00 "SWREG19,Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps"
hexmask.long 0x00 2.--31. 1. "SW_REFER5_BASE,H.264: Base address for reference picture index 5 VP8: Base address for alternate reference picture (corresponds picid 5)"
bitfld.long 0x00 1. "SW_REFER5_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER5_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x50++0x03
line.long 0x00 "SWREG20,Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps"
hexmask.long 0x00 2.--31. 1. "SW_REFER6_BASE,Base address for reference picture index 6"
bitfld.long 0x00 1. "SW_REFER6_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER6_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x54++0x03
line.long 0x00 "SWREG21,Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps"
hexmask.long 0x00 2.--31. 1. "SW_REFER7_BASE,Base address for reference picture index 7"
bitfld.long 0x00 1. "SW_REFER7_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER7_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x58++0x03
line.long 0x00 "SWREG22,Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7 VP8 DCT stream 1 base"
hexmask.long 0x00 2.--31. 1. "SW_REFER8_BASE,Base address for reference picture index 8"
bitfld.long 0x00 1. "SW_REFER8_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER8_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x5C++0x03
line.long 0x00 "SWREG23,Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 2 base"
hexmask.long 0x00 2.--31. 1. "SW_REFER9_BASE,Base address for reference picture index 9"
bitfld.long 0x00 1. "SW_REFER9_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER9_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x60++0x03
line.long 0x00 "SWREG24,Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 3 base"
hexmask.long 0x00 2.--31. 1. "SW_REFER10_BASE,Base address for reference picture index 10"
bitfld.long 0x00 1. "SW_REFER10_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER10_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x64++0x03
line.long 0x00 "SWREG25,Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 4 base"
hexmask.long 0x00 2.--31. 1. "SW_REFER11_BASE,Base address for reference picture index 11"
bitfld.long 0x00 1. "SW_REFER11_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER11_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x68++0x03
line.long 0x00 "SWREG26,Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 5 base"
hexmask.long 0x00 2.--31. 1. "SW_REFER12_BASE,Base address for reference picture index 12"
bitfld.long 0x00 1. "SW_REFER12_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER12_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x6C++0x03
line.long 0x00 "SWREG27,Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6 VP7 VP8 ctrl stream base /Progressive JPEG DC table"
hexmask.long 0x00 2.--31. 1. "SW_REFER13_BASE,Base address for reference picture index 13"
bitfld.long 0x00 1. "SW_REFER13_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER13_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x70++0x03
line.long 0x00 "SWREG28,Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7 VP8 DCT stream 6 base"
hexmask.long 0x00 2.--31. 1. "SW_REFER14_BASE,Base address for reference picture index 14"
bitfld.long 0x00 1. "SW_REFER14_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER14_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x74++0x03
line.long 0x00 "SWREG29,Base address for reference picture index 15 / VP6 scan maps / VP7 VP8 DCT stream 7 base"
hexmask.long 0x00 2.--31. 1. "SW_REFER15_BASE,Base address for reference picture index 15"
bitfld.long 0x00 1. "SW_REFER15_FIELD_E,Refer picture consist of single fields or frame" "0: reference picture consists of frame,1: reference picture consists of fields"
newline
bitfld.long 0x00 0. "SW_REFER15_TOPC_E,Which field of reference picture is closer to current picture" "0: bottom field is closer to current picture,1: top field is closer to current picture"
group.long 0x78++0x03
line.long 0x00 "SWREG30,Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7 VP8 loop filter mb level adjusts"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER1_NBR,Number for reference picture index 1"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER0_NBR,Number for reference picture index 0"
group.long 0x7C++0x03
line.long 0x00 "SWREG31,Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7 VP8 loop filter ref pic level adjusts"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER3_NBR,Number for reference picture index 3"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER2_NBR,Number for reference picture index 2"
group.long 0x80++0x03
line.long 0x00 "SWREG32,Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7 VP8 loop filter levels"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER5_NBR,Number for reference picture index 5"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER4_NBR,Number for reference picture index 4"
group.long 0x84++0x03
line.long 0x00 "SWREG33,Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7 VP8 quantization values"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER7_NBR,Number for reference picture index 7"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER6_NBR,Number for reference picture index 6"
group.long 0x88++0x03
line.long 0x00 "SWREG34,Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4 VC1 VPx prediction filter taps"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER9_NBR,Number for reference picture index 9"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER8_NBR,Number for reference picture index 8"
group.long 0x8C++0x03
line.long 0x00 "SWREG35,Reference picture numbers for index 10 and 11 (H264 VLC) / VC1 VPx prediction filter taps"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER11_NBR,Number for reference picture index 11"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER10_NBR,Number for reference picture index 10"
group.long 0x90++0x03
line.long 0x00 "SWREG36,Reference picture numbers for index 12 and 13 (H264 VLC) / VC1 VPx prediction filter taps"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER13_NBR,Number for reference picture index 13"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER12_NBR,Number for reference picture index 12"
group.long 0x94++0x03
line.long 0x00 "SWREG37,Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER15_NBR,Number for reference picture index 15"
hexmask.long.word 0x00 0.--15. 1. "SW_REFER14_NBR,Number for reference picture index 14"
group.long 0x98++0x03
line.long 0x00 "SWREG38,Reference picture long term flags (H264 VLC) / VPx prediction filter taps"
hexmask.long 0x00 0.--31. 1. "SW_REFER_LTERM_E,Long term flag for reference picture index [31:0]"
group.long 0x9C++0x03
line.long 0x00 "SWREG39,Reference picture valid flags (H264 VLC) / VPx prediction filter taps"
hexmask.long 0x00 0.--31. 1. "SW_REFER_VALID_E,Valid flag for reference picture index [31:0].Definition: If frame is being decoded the bits 31:15 are used Bit 31 for picture index 0 Bit 30 for picture index 1 etc"
group.long 0xA8++0x03
line.long 0x00 "SWREG42_H264,bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base"
bitfld.long 0x00 25.--29. "SW_BINIT_RLIST_B2_H264,Initial reference picture list for bi-direct backward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_BINIT_RLIST_F2_H264,Initial reference picture list for bi-direct forward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_BINIT_RLIST_B1_H264,Initial reference picture list for bi-direct backward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_BINIT_RLIST_F1_H264,Initial reference picture list for bi-direct forward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_BINIT_RLIST_B0_H264,Initial reference picture list for bi-direct backward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_BINIT_RLIST_F0_H264,Initial reference picture list for bi-direct forward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAC++0x03
line.long 0x00 "SWREG43_H264,bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base"
bitfld.long 0x00 25.--29. "SW_BINIT_RLIST_B5_H264,Initial reference picture list for bi-direct backward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_BINIT_RLIST_F5_H264,Initial reference picture list for bi-direct forward picid 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_BINIT_RLIST_B4_H264,Initial reference picture list for bi-direct backward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_BINIT_RLIST_F4_H264,Initial reference picture list for bi-direct forward picid 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_BINIT_RLIST_B3_H264,Initial reference picture list for bi-direct backward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_BINIT_RLIST_F3_H264,Initial reference picture list for bi-direct forward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB0++0x03
line.long 0x00 "SWREG44_H264,bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps"
bitfld.long 0x00 25.--29. "SW_BINIT_RLIST_B8_H264,Initial reference picture list for bi-direct backward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_BINIT_RLIST_F8_H264,Initial reference picture list for bi-direct forward picid 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_BINIT_RLIST_B7_H264,Initial reference picture list for bi-direct backward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_BINIT_RLIST_F7_H264,Initial reference picture list for bi-direct forward picid 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_BINIT_RLIST_B6_H264,Initial reference picture list for bi-direct backward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_BINIT_RLIST_F6_H264,Initial reference picture list for bi-direct forward picid 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB4++0x03
line.long 0x00 "SWREG45,bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps"
bitfld.long 0x00 25.--29. "SW_BINIT_RLIST_B11,Initial reference picture list for bi-direct backward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_BINIT_RLIST_F11,Initial reference picture list for bi-direct forward picid 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_BINIT_RLIST_B10,Initial reference picture list for bi-direct backward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_BINIT_RLIST_F10,Initial reference picture list for bi-direct forward picid 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_BINIT_RLIST_B9,Initial reference picture list for bi-direct backward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_BINIT_RLIST_F9,Initial reference picture list for bi-direct forward picid 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB8++0x03
line.long 0x00 "SWREG46,bi-dir initial ref pic list register (12-14) / VP7 VP8 quantization values"
bitfld.long 0x00 25.--29. "SW_BINIT_RLIST_B14,Initial reference picture list for bi-direct backward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_BINIT_RLIST_F14,Initial reference picture list for bi-direct forward picid 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_BINIT_RLIST_B13,Initial reference picture list for bi-direct backward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_BINIT_RLIST_F13,Initial reference picture list for bi-direct forward picid 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_BINIT_RLIST_B12,Initial reference picture list for bi-direct backward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_BINIT_RLIST_F12,Initial reference picture list for bi-direct forward picid 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xBC++0x03
line.long 0x00 "SWREG47,bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7 VP8 quantization values"
bitfld.long 0x00 25.--29. "SW_PINIT_RLIST_F3,Initial reference picture list for P forward picid 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "SW_PINIT_RLIST_F2,Initial reference picture list for P forward picid 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15.--19. "SW_PINIT_RLIST_F1,Initial reference picture list for P forward picid 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "SW_PINIT_RLIST_F0,Initial reference picture list for P forward picid 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "SW_BINIT_RLIST_B15,Initial reference picture list for bi-direct backward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SW_BINIT_RLIST_F15,Initial reference picture list for bi-direct forward picid 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "VPU_G1_VP7_VP8 (VPU_G1)"
base ad:0x38300000
group.long 0x10++0x03
line.long 0x00 "SWREG4_JPEG_VP7_VP8,Decoder control register 1 (picture parameters)"
hexmask.long.word 0x00 23.--31. 1. "SW_PIC_MB_WIDTH_JPEG_VP7_VP6,Picture width in macroblocks = ((width in pixels + 15) /16)"
bitfld.long 0x00 19.--22. "SW_MB_WIDTH_OFF_JPEG_VP7_VP6,The amount of meaningfull horizontal pixels in last MB (width offset) 0 if exactly 16 pixels multiple picture and all the horizontal pixels in last MB are meaningfull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 11.--18. 1. "SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6,Picture height in macroblocks =((height in pixels+15)/16)"
bitfld.long 0x00 7.--10. "SW_MB_HEIGHT_OFF_JPEG_VP7_VP6,The amount of meaningful vertical pixels in last MB (height offset 0 if exactly 16 pixels multiple picture and all the vertical pixels in last MB are meaningfull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "SW_ALT_SCAN_E_JPEG_VP7_VP6,indicates alternative vertical scan method used for interlaced frames" "0,1"
bitfld.long 0x00 3.--5. "SW_PIC_MB_W_EXT_JPEG_VP7_VP6,Picture mb width extension" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "SW_PIC_MB_H_EXT_JPEG_VP7_VP6,Picture mb height extension" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "SWREG5_VP7_VP8,Decoder control register 2 (stream decoding table selects)"
bitfld.long 0x00 26.--31. "SW_STRM_START_BIT_VP7_VP8,Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. "SW_STRM1_START_BIT_VP7_VP8,Start bit for ctrl-stream (needed if multistream is enabled assosiates with sw_bitpl_ctrl_base)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_BOOLEAN_VALUE_VP7_VP8,Initial value for boolean dec"
hexmask.long.byte 0x00 0.--7. 1. "SW_BOOLEAN_RANGE_VP7_VP8,Initial range for boolean dec"
group.long 0x18++0x03
line.long 0x00 "SWREG6_VP7_VP8,Decoder control register 3 (stream buffer information)"
hexmask.long.byte 0x00 24.--31. 1. "SW_STREAM_LEN_EXT_VP7_VP8,Extended stream length for WEBP/VP8"
hexmask.long.tbyte 0x00 0.--23. 1. "SW_STREAM_LEN_VP7_VP8,Amount of stream data bytes in input buffer"
group.long 0x1C++0x03
line.long 0x00 "SWREG7_VP7_VP8,Decoder control register 4 (H264 VC-1 VP6 and progressive JPEG control)"
bitfld.long 0x00 26.--31. "SW_DCT1_START_BIT_VP7_VP8,Start bit for VP7/VP8 DCT stream partition index 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20.--25. "SW_DCT2_START_BIT_VP7_VP8,Start bit for VP7/VP8 DCT stream partition index 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "SW_CH_MV_RES_VP7_VP8,VP7/VP8 Chrominance motion vector resolution" "0: SW_CH_MV_RES_VP7_VP8_0,1: SW_CH_MV_RES_VP7_VP8_1"
bitfld.long 0x00 12. "SW_BILIN_MC_E_VP7_VP8,Bilinear motion compensation enable" "0: Bicubic interpolation used,1: Bilinear interpolation used"
newline
bitfld.long 0x00 9.--11. "SW_INIT_DC_MATCH0_VP7_VP8,Initial DC prediction mach count 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "SW_INIT_DC_MATCH1_VP7_VP8,Initial DC prediction mach count 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5. "SW_VP7_VERSION_VP7_VP8,VP7 version information to streamd" "0: SW_VP7_VERSION_VP7_VP8_0,1: VP7 version 7.1 or better"
group.long 0x28++0x03
line.long 0x00 "SWREG10_VP7_VP8,Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register"
hexmask.long 0x00 2.--31. 1. "SW_SEGMENT_BASE_VP7_VP8,VP7/VP8: base address for segmentation map values"
bitfld.long 0x00 1. "SW_SEGMENT_UPD_E_VP7_VP8,VP7/VP8 Segmentation map update enable: '0': segmentation values are read from external memory (from segment_base) '1': segmentation update is included in stream" "0,1"
newline
bitfld.long 0x00 0. "SW_SEGMENT_E_VP7_VP8,Segmentation enable: '0': segmentation is not enabled '1': segmentation is enabled (sw_segment_upd_e value is used)" "0,1"
group.long 0x2C++0x03
line.long 0x00 "SWREG11_VP7_VP8,Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2"
bitfld.long 0x00 24.--29. "SW_DCT3_START_BIT_VP7_VP8,Start bit for VP7/VP8 DCT stream partition index 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. "SW_DCT4_START_BIT_VP7_VP8,Start bit for VP7/VP8 DCT stream partition index 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "SW_DCT5_START_BIT_VP7_VP8,Start bit for VP7/VP8 DCT stream partition index 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--11. "SW_DCT6_START_BIT_VP7_VP8,Start bit for VP7/VP8 DCT stream partition index 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "SW_DCT7_START_BIT_VP7_VP8,Start bit for VP7/VP8 DCT stream partition index 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "SWREG14_VP7_VP8,Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture"
hexmask.long 0x00 2.--31. 1. "SW_JPG_CH_OUT_BASE_VP7_VP8,Base address for decoder output chrominance picture"
group.long 0x3C++0x03
line.long 0x00 "SWREG15_VP7_VP8,Base address for reference picture index 1 / JPEG control"
hexmask.long.byte 0x00 0.--7. 1. "SW_JPEG_SLICE_H_VP7_VP8,JPEG/Web-p"
group.long 0x48++0x03
line.long 0x00 "SWREG18_VP7_VP8,Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7 VP8 Golden refer picture base"
hexmask.long 0x00 2.--31. 1. "SW_REFER4_BASE_VP7_VP8,H264: Base address for reference picture index 4 VP6/VP7/VP8: Base address for Golden reference picture (corresponds picid 4)"
bitfld.long 0x00 0. "SW_GREF_SIGN_BIAS_VP7_VP8,Reference picture sign bias for Golden reference frame" "0,1"
group.long 0x58++0x03
line.long 0x00 "SWREG22_VP7_VP8,Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7 VP8 DCT stream 1 base"
hexmask.long 0x00 2.--31. 1. "SW_DCT_STRM1_BASE,Base address for VP7/VP8 DCT stream MB row 1 2n+1"
group.long 0x5C++0x03
line.long 0x00 "SWREG23_VP7_VP8,Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 2 base"
hexmask.long 0x00 2.--31. 1. "SW_DCT_STRM2_BASE,Base address for VP7/VP8 DCT stream MB row 2 2n+2"
group.long 0x60++0x03
line.long 0x00 "SWREG24_VP7_VP8,Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 3 base"
hexmask.long 0x00 2.--31. 1. "SW_DCT_STRM3_BASE,Base address for VP7/VP8 DCT stream MB row 3 2n+3"
group.long 0x64++0x03
line.long 0x00 "SWREG25_VP7_VP8,Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 4 base"
hexmask.long 0x00 2.--31. 1. "SW_DCT_STRM4_BASE,Base address for VP7/VP8 DCT stream MB row 4 2n+4"
group.long 0x68++0x03
line.long 0x00 "SWREG26_VP7_VP8,Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7 VP8 DCT stream 5 base"
hexmask.long 0x00 2.--31. 1. "SW_DCT_STRM5_BASE,Base address for VP7/VP8 DCT stream MB row 5 2n+5"
group.long 0x6C++0x03
line.long 0x00 "SWREG27_VC1,Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6 VP7 VP8 ctrl stream base /Progressive JPEG DC table"
hexmask.long 0x00 2.--31. 1. "SW_BITPL_CTRL_BASE,VC-1: Base address for bitplane mb control VP6/VP7/VP8 : Base address for ctrl data stream"
group.long 0x70++0x03
line.long 0x00 "SWREG28_VP7_VP8,Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7 VP8 DCT stream 6 base"
hexmask.long 0x00 2.--31. 1. "SW_DCT_STRM6_BASE,Base address for VP7/VP8 DCT stream MB row 6 2n+6"
group.long 0x74++0x03
line.long 0x00 "SWREG29_VP7_VP8,Base address for reference picture index 15 / VP6 scan maps / VP7 VP8 DCT stream 7 base"
hexmask.long 0x00 2.--31. 1. "SW_DCT_STRM7_BASE,Base address for VP7/VP8 DCT stream MB row 7 2n+7"
group.long 0x78++0x03
line.long 0x00 "SWREG30_VP7_VP8,Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7 VP8 loop filter mb level adjusts"
bitfld.long 0x00 31. "SW_FILT_TYPE,VP7/VP8 loop filter type" "0,1"
bitfld.long 0x00 28.--30. "SW_FILT_SHARPNESS,VP7/VP8 loop filter sharpness" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 21.--27. 1. "SW_FILT_MB_ADJ_0,VP7/VP8 filter level adjustment for MB type 0"
hexmask.long.byte 0x00 14.--20. 1. "SW_FILT_MB_ADJ_1,VP7/VP8 filter level adjustment for MB type 1"
newline
hexmask.long.byte 0x00 7.--13. 1. "SW_FILT_MB_ADJ_2,VP7/VP8 filter level adjustment for MB type 2"
hexmask.long.byte 0x00 0.--6. 1. "SW_FILT_MB_ADJ_3,VP7/VP8 filter level adjustment for MB type 3"
group.long 0x7C++0x03
line.long 0x00 "SWREG31_VP7_VP8,Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7 VP8 loop filter ref pic level adjusts"
hexmask.long.byte 0x00 21.--27. 1. "SW_FILT_REF_ADJ_0,VP7/VP8 filter level adjustment for reference frame type 0"
hexmask.long.byte 0x00 14.--20. 1. "SW_FILT_REF_ADJ_1,VP7/VP8 filter level adjustment for reference frame type 1"
newline
hexmask.long.byte 0x00 7.--13. 1. "SW_FILT_REF_ADJ_2,VP7/VP8 filter level adjustment for reference frame type 2"
hexmask.long.byte 0x00 0.--6. 1. "SW_FILT_REF_ADJ_3,VP7/VP8 filter level adjustment for reference frame type 3"
group.long 0x80++0x03
line.long 0x00 "SWREG32_VP7_VP8,Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7 VP8 loop filter levels"
bitfld.long 0x00 18.--23. "SW_FILT_LEVEL_0,VP7/VP8 filter level value for reference frame type 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 12.--17. "SW_FILT_LEVEL_1,VP7/VP8 filter level value for reference frame type 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "SW_FILT_LEVEL_2,VP7/VP8 filter level value for reference frame type 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "SW_FILT_LEVEL_3,VP7/VP8 filter level value for reference frame type 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x84++0x03
line.long 0x00 "SWREG33_VP7_VP8,Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7 VP8 quantization values"
bitfld.long 0x00 27.--31. "SW_QUANT_DELTA_0,VP8 quantisizer delta 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22.--26. "SW_QUANT_DELTA_1,VP8 quantisizer delta 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 11.--21. 1. "SW_QUANT_0,VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)"
hexmask.long.word 0x00 0.--10. 1. "SW_QUANT_1,VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)"
group.long 0x88++0x03
line.long 0x00 "SWREG34_H263,Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4 VC1 VPx prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_0_3,Prediction filter set 0 tap 3"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_1_0,Prediction filter set 1 tap 0"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_1_1,Prediction filter set 1 tap 1"
group.long 0x8C++0x03
line.long 0x00 "SWREG35_VC1,Reference picture numbers for index 10 and 11 (H264 VLC) / VC1 VPx prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_1_2,Prediction filter set 1 tap 2"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_1_3,Prediction filter set 1 tap 3"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_2_0,Prediction filter set 2 tap 0"
group.long 0x90++0x03
line.long 0x00 "SWREG36_VC1,Reference picture numbers for index 12 and 13 (H264 VLC) / VC1 VPx prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_2_1,Prediction filter set 2 tap 1"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_2_2,Prediction filter set 2 tap 2"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_2_3,Prediction filter set 2 tap 3"
group.long 0x94++0x03
line.long 0x00 "SWREG37_VP6_VP7_VP8,Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_3_0,Prediction filter set 3 tap 0"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_3_1,Prediction filter set 3 tap 1"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_3_2,Prediction filter set 3 tap 2"
group.long 0x98++0x03
line.long 0x00 "SWREG38_VP6_VP7_VP8,Reference picture long term flags (H264 VLC) / VPx prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_3_3,Prediction filter set 3 tap 3"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_4_0,Prediction filter set 4 tap 0"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_4_1,Prediction filter set 4 tap 1"
group.long 0x9C++0x03
line.long 0x00 "SWREG39_VP6_VP7_VP8,Reference picture valid flags (H264 VLC) / VPx prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_4_2,Prediction filter set 4 tap 2"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_4_3,Prediction filter set 4 tap 3"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_5_0,Prediction filter set 5 tap 0"
group.long 0xA8++0x03
line.long 0x00 "SWREG42_VP6,bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_5_1_VP6,Prediction filter set 5 tap 1"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_5_2_VP6,Prediction filter set 5 tap 2"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_5_3_VP6,Prediction filter set 5 tap 3"
group.long 0xAC++0x03
line.long 0x00 "SWREG43_VP7_VP8,bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_6_0_VP7_VP8,Prediction filter set 6 tap 0"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_6_1_VP7_VP8,Prediction filter set 6 tap 1"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_6_2_VP7_VP8,Prediction filter set 6 tap 2"
group.long 0xB0++0x03
line.long 0x00 "SWREG44_VP7_VP8,bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_6_3_VP7_VP8,Prediction filter set 6 tap 3"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_7_0_VP7_VP8,Prediction filter set 7 tap 0"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_PRED_BC_TAP_7_1_VP7_VP8,Prediction filter set 7 tap 1"
group.long 0xB4++0x03
line.long 0x00 "SWREG45_VP7_VP8,bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps"
hexmask.long.word 0x00 22.--31. 1. "SW_PRED_BC_TAP_7_2_VP7_VP8,Prediction filter set 7 tap 2"
hexmask.long.word 0x00 12.--21. 1. "SW_PRED_BC_TAP_7_3_VP7_VP8,Prediction filter set 7 tap 3"
newline
bitfld.long 0x00 10.--11. "SW_PRED_TAP_2_M1_VP7_VP8,Additional Prediction filter tap -1 for set 2" "0,1,2,3"
bitfld.long 0x00 8.--9. "SW_PRED_TAP_2_4_VP7_VP8,Additional Prediction filter tap 4 for set 2" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "SW_PRED_TAP_4_M1_VP7_VP8,Additional Prediction filter tap -1 for set 4" "0,1,2,3"
bitfld.long 0x00 4.--5. "SW_PRED_TAP_4_4_VP7_VP8,Additional Prediction filter tap 4 for set 4" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "SW_PRED_TAP_6_M1_VP7_VP8,Additional Prediction filter tap -1 for set 6" "0,1,2,3"
bitfld.long 0x00 0.--1. "SW_PRED_TAP_6_4_VP7_VP8,Additional Prediction filter tap 4 for set 6" "0,1,2,3"
group.long 0xB8++0x03
line.long 0x00 "SWREG46_VP7_VP8,bi-dir initial ref pic list register (12-14) / VP7 VP8 quantization values"
bitfld.long 0x00 27.--31. "SW_QUANT_DELTA_2_VP7_VP8,VP8 quantisizer delta 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22.--26. "SW_QUANT_DELTA_3_VP7_VP8,VP8 quantisizer delta 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 11.--21. 1. "SW_QUANT_2_VP7_VP8,VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)"
hexmask.long.word 0x00 0.--10. 1. "SW_QUANT_3_VP7_VP8,VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)"
group.long 0xBC++0x03
line.long 0x00 "SWREG47_VP7_VP8,bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7 VP8 quantization values"
bitfld.long 0x00 27.--31. "SW_QUANT_DELTA_4_VP7_VP8,VP8 quantisizer delta 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 11.--21. 1. "SW_QUANT_4_VP7_VP8,VP7 QP (11 bit)"
newline
hexmask.long.word 0x00 0.--10. 1. "SW_QUANT_5_VP7_VP8,VP7 QP (11 bit)"
tree.end
tree "VPU_G1_VP8 (VPU_G1)"
base ad:0x38300000
group.long 0x4C++0x03
line.long 0x00 "SWREG19_VP8,Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps"
hexmask.long 0x00 2.--31. 1. "SW_REFER5_BASE_VP8,H.264: Base address for reference picture index 5 VP8: Base address for alternate reference picture (corresponds picid 5)"
bitfld.long 0x00 0. "SW_AREF_SIGN_BIAS,VP8 only: Reference picture sign bias for Alternate reference frame" "0,1"
group.long 0x50++0x03
line.long 0x00 "SWREG20_VP8,Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps"
hexmask.long 0x00 2.--31. 1. "SW_VP8_DEC_CH_BASE,VP8 video base address for decoder output chrominance data (if vp8 stride configuration is enabled)"
bitfld.long 0x00 1. "SW_VP8_STRIDE_E,VP8 stride enable" "0: SW_VP8_STRIDE_E_0,1: SW_VP8_STRIDE_E_1"
newline
bitfld.long 0x00 0. "SW_VP8_CH_BASE_E,VP8 separate chrominance enable" "0: Write/Read chrominance data from internal..,1: Write/Read chrominance data from separate.."
group.long 0x54++0x03
line.long 0x00 "SWREG21_VP8,Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps"
bitfld.long 0x00 27.--31. "SW_Y_STRIDE_POW2,VP8 Y stride length informed by 2^n (n=sw_y_stride_pow2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22.--26. "SW_C_STRIDE_POW2,VP8 C stride length informed by 2^n (n=sw_c_stride_pow2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "VPU_G2 (Video Processing Unit)"
base ad:0x38310000
rgroup.long 0x00++0x03
line.long 0x00 "SWREG0,ID register (read only)"
hexmask.long.word 0x00 16.--31. 1. "SW_PRODUCT_NUMBER,Product number (g2)"
newline
bitfld.long 0x00 12.--15. "SW_MAJOR_VERSION,Major version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 4.--11. 1. "SW_MINOR_VERSION,Minor version"
newline
bitfld.long 0x00 3. "SW_PRODUCT_ID_EN,ASCII type product ID enable" "0,1"
newline
bitfld.long 0x00 0.--2. "SW_BUILD_VERSION,Build version (core number)" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "SWREG1,Interrupt register decoder"
bitfld.long 0x00 18. "SW_DEC_TIMEOUT,Interrupt status bit decoder timeout" "0,1"
newline
bitfld.long 0x00 16. "SW_DEC_ERROR_INT,Interrupt status bit input stream error" "0,1"
newline
bitfld.long 0x00 14. "SW_DEC_BUFFER_INT,Interrupt status bit input buffer empty" "0,1"
newline
bitfld.long 0x00 13. "SW_DEC_BUS_INT,Interrupt status bit bus" "0,1"
newline
bitfld.long 0x00 12. "SW_DEC_RDY_INT,Interrupt status bit decoder" "0,1"
newline
bitfld.long 0x00 11. "SW_DEC_ABORT_INT,Interrupt status bit decoding aborted" "0,1"
newline
bitfld.long 0x00 8. "SW_DEC_IRQ,Decoder IRQ" "0,1"
newline
bitfld.long 0x00 5. "SW_DEC_ABORT_E,Abort decoding enable" "0,1"
newline
bitfld.long 0x00 4. "SW_DEC_IRQ_DIS,Decoder IRQ disable" "0,1"
newline
bitfld.long 0x00 0. "SW_DEC_E,Decoder enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SWREG2,Data configuration register decoder"
bitfld.long 0x00 28.--31. "SW_DEC_STRM_SWAP,Byte swap configuration for stream data 4 Bit byte order vector to control byte locations inside HW internal 128 bit data vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24.--27. "SW_DEC_PIC_SWAP,Byte swap configuration for decoder reference output picture data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "SW_DEC_DIRMV_SWAP,Byte swap configuration for direct mode MV data (read/write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "SW_DEC_TAB0_SWAP,Byte swap configuration for VP9 stream propability tables" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "SW_DEC_TAB1_SWAP,Byte swap configuration for HEVC scaling lists / VP9 segmentation map read/" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "SW_DEC_TAB2_SWAP,Byte swap configuration for VP9 CTX counter values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "SW_DEC_TAB3_SWAP,Byte swap configuration for tile sizes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SW_DEC_RSCAN_SWAP,Byte swap for raster scan output picture data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "SWREG3,Decoder control register 0"
bitfld.long 0x00 27.--31. "SW_DEC_MODE,Decoding mode" "?,?,?,?,?,?,?,?,?,?,?,?,12: SW_DEC_MODE_12,13: SW_DEC_MODE_13,?..."
newline
bitfld.long 0x00 20.--23. "SW_DEC_COMP_TABLE_SWAP,Byte swap configuration for compress table data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 17. "SW_DEC_OUT_EC_BYPASS,Compress bypass" "0,1"
newline
bitfld.long 0x00 16. "SW_DEC_OUT_RS_E,Raster scan output enable" "0,1"
newline
bitfld.long 0x00 15. "SW_DEC_OUT_DIS,Disable decoder output picture writing" "0: Decoder output picture is written to external..,1: Decoder output picture is not written to.."
newline
bitfld.long 0x00 14. "SW_FILTERING_DIS,De-block filtering disable" "0: Filtering is enabled for current picture,1: Filtering is disabled for current picture"
newline
bitfld.long 0x00 12. "SW_WRITE_MVS_E,Direct mode motion vector write enable for current picture" "0: Writing disabled for current picture,1: The direct mode motion vectors are written to.."
newline
bitfld.long 0x00 11. "SW_APF_ONE_PID,Prefetch partitions that have the same pic_id together" "0,1"
group.long 0x10++0x03
line.long 0x00 "SWREG4,Decoder control register 1"
hexmask.long.word 0x00 19.--31. 1. "SW_PIC_WIDTH_IN_CBS,Picture width in min coded blocks (min = 8pix)"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_PIC_HEIGHT_IN_CBS,Picture height in min coded blocks (min = 8pix)"
newline
bitfld.long 0x00 0.--4. "SW_REF_FRAMES,HEVC: num_ref_frames maximum number of short and long term reference frames in decoded picture buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "SWREG5,Decoder control register 2"
hexmask.long.byte 0x00 25.--31. 1. "SW_STRM_START_BIT,Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base)"
newline
bitfld.long 0x00 24. "SW_SCALING_LIST_E,Scaling matrix enable" "0: SW_SCALING_LIST_E_0,1: Use scaling matrix for transform (read from.."
newline
bitfld.long 0x00 19.--23. "SW_CH_QP_OFFSET,Chroma Qp filter offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 14.--18. "SW_CH_QP_OFFSET2,Chroma Qp filter offset for cr type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12. "SW_SIGN_DATA_HIDE,Flag for stream decoding" "0,1"
newline
bitfld.long 0x00 11. "SW_TEMPOR_MVP_E,Temporal mvp enable" "0,1"
newline
bitfld.long 0x00 5.--10. "SW_MAX_CU_QPD_DEPTH,Max CU qp delta depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "SW_CU_QPD_E,CU qp delta enable" "0,1"
group.long 0x18++0x03
line.long 0x00 "SWREG6,Decoder control register 3"
hexmask.long 0x00 0.--31. 1. "SW_STREAM_LEN,Amount of stream data bytes in input buffer"
group.long 0x1C++0x03
line.long 0x00 "SWREG7,Decoder control register 4"
bitfld.long 0x00 31. "SW_CABAC_INIT_PRESENT,CABAC init present enable for stream decoding" "0,1"
newline
bitfld.long 0x00 30. "SW_BLACKWHITE_E,Sampling" "0: 4:2:0 sampling format,1: 4:0:0 sampling format (H264 monochroma)"
newline
bitfld.long 0x00 28. "SW_WEIGHT_PRED_E,Weighted prediction enable for P slices" "0,1"
newline
bitfld.long 0x00 26.--27. "SW_WEIGHT_BIPR_IDC,Weighted prediction specification" "0: Default weighted prediction is applied to B..,1: Explicit weighted prediction shall be applied..,2: SW_WEIGHT_BIPR_IDC_2,3: SW_WEIGHT_BIPR_IDC_3"
newline
bitfld.long 0x00 25. "SW_FILT_SLICE_BORDER,Filter enable over slice border" "0,1"
newline
bitfld.long 0x00 24. "SW_FILT_TILE_BORDER,Filter enable over tile border" "0,1"
newline
bitfld.long 0x00 23. "SW_ASYM_PRED_E,Asymmetric prediction flag for stream decoding" "0,1"
newline
bitfld.long 0x00 22. "SW_SAO_E,Sample Adaptive Offset enable for stream decoding" "0,1"
newline
bitfld.long 0x00 21. "SW_PCM_FILT_DISABLE,Disable for PCM loop filtering" "0,1"
newline
bitfld.long 0x00 20. "SW_SLICE_CHQP_FLAG,Slice header flag for chroma QP present (if it is included in slice header)" "0,1"
newline
bitfld.long 0x00 19. "SW_DEPEND_SLICE_E,Dependent slice enable" "0,1"
newline
bitfld.long 0x00 18. "SW_FILT_OVERRIDE_E,Filter override enable" "0,1"
newline
bitfld.long 0x00 17. "SW_STRONG_SMOOTH_E,Strong smoothing enable" "0,1"
newline
bitfld.long 0x00 12.--16. "SW_FILT_OFFSET_BETA,Filter beta offset (declared as div2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7.--11. "SW_FILT_OFFSET_TC,Filter tc offset (declared as div2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6. "SW_SLICE_HDR_EXT_E,Slice header extension enable" "0,1"
newline
bitfld.long 0x00 3.--5. "SW_SLICE_HDR_EBITS,Number of extra slice header bits (if enabled slice header extension)" "0,1,2,3,4,5,6,7"
group.long 0x20++0x03
line.long 0x00 "SWREG8,Decoder control register 5"
bitfld.long 0x00 31. "SW_CONST_INTRA_E,constrained_intra_pred_flag equal to 1 specifies that intra prediction uses only neighbouring intra macroblocks in prediction" "0,1"
newline
bitfld.long 0x00 30. "SW_FILT_CTRL_PRES,deblocking_filter_control_present_flag indicates whether extra variables controlling characteristics of the deblocking filter are present in the slice header" "0,1"
newline
bitfld.long 0x00 16. "SW_IDR_PIC_E,IDR (instantaneous decoding refresh) picture flag" "0,1"
newline
bitfld.long 0x00 12.--15. "SW_PCM_BITDEPTH_Y,Bit depth for PCM Y data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "SW_PCM_BITDEPTH_C,Bit depth for PCM C data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6.--7. "SW_BIT_DEPTH_Y_MINUS8,Bit depth of luma samples minus 8" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "SW_BIT_DEPTH_C_MINUS8,Bit depth of chroma samples minus 8" "0,1,2,3"
newline
bitfld.long 0x00 3. "SW_OUTPUT_8_BITS,enable rasterscan output force to 8 bit(only for hevc main10 and vp9 10bit)" "0,1"
newline
bitfld.long 0x00 0.--2. "SW_OUTPUT_FORMAT,Raster scan and down scale output data format" "0: Each pixel in 10 bits when luma or chroma..,1: Store in P010 format when luma or chroma..,2: A customized format,?..."
group.long 0x24++0x03
line.long 0x00 "SWREG9,Decoder control register 6"
bitfld.long 0x00 19.--23. "SW_REFIDX1_ACTIVE,Specifies the maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 14.--18. "SW_REFIDX0_ACTIVE,Specifies the maximum reference index that can be used while decoding inter predicted macro blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--13. 1. "SW_HDR_SKIP_LENGTH,Length of slice header skip length (bytes used by sw)"
group.long 0x28++0x03
line.long 0x00 "SWREG10,Decoder control register 7"
bitfld.long 0x00 31. "SW_START_CODE_E,Bit for indicating stream start code existence" "0: Stream does not contain start codes,1: Stream contains start codes"
newline
hexmask.long.byte 0x00 24.--30. 1. "SW_INIT_QP,Initial value for quantization parameter (picture quantizer)"
newline
bitfld.long 0x00 19.--23. "SW_NUM_TILE_COLS,Number of tile columns in picture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 14.--18. "SW_NUM_TILE_ROWS,Number of tile rows in picture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1. "SW_TILE_ENABLE,Tile enable" "0,1"
newline
bitfld.long 0x00 0. "SW_ENTR_CODE_SYNCH_E,Entropy coding synchronization enable (Possible parallel cabac decoding)" "0,1"
group.long 0x2C++0x03
line.long 0x00 "SWREG11,Decoder control register 8"
bitfld.long 0x00 27.--29. "SW_TRANSFORM_MODE,Transform modes" "0: SW_TRANSFORM_MODE_0,1: SW_TRANSFORM_MODE_1,2: SW_TRANSFORM_MODE_2,3: SW_TRANSFORM_MODE_3,4: SW_TRANSFORM_MODE_4,?..."
newline
bitfld.long 0x00 21.--23. "SW_FILT_SHARPNESS,Filter sharpness value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19. "SW_FILT_TYPE,Filter Type" "0,1"
newline
bitfld.long 0x00 8.--10. "SW_MCOMP_FILT_TYPE,Inter prediction filter type to stream decoder" "0: SW_MCOMP_FILT_TYPE_0,1: SW_MCOMP_FILT_TYPE_1,2: SW_MCOMP_FILT_TYPE_2,3: SW_MCOMP_FILT_TYPE_3,4: SW_MCOMP_FILT_TYPE_4,?..."
newline
bitfld.long 0x00 7. "SW_HIGH_PREC_MV_E,High precision MV prediction enable" "0,1"
newline
bitfld.long 0x00 4.--5. "SW_COMP_PRED_MODE,Prediction Comp Type" "0: Single prediction only,1: COMP prediction only,2: SW_COMP_PRED_MODE_2,?..."
newline
bitfld.long 0x00 2. "SW_GREF_SIGN_BIAS,Golden reference picture sign bias used for motion vector decoding" "0,1"
newline
bitfld.long 0x00 0. "SW_AREF_SIGN_BIAS,Alternate reference picture sign bias used for motion vector decoding" "0,1"
group.long 0x30++0x03
line.long 0x00 "SWREG12,Decoder control register 9"
hexmask.long.word 0x00 16.--31. 1. "SW_REFER_LTERM_E,Long term flag for reference picture index Definition: Bit 31 for picture index 0 Bit 30 for picture index 1 etc"
newline
bitfld.long 0x00 13.--15. "SW_MIN_CB_SIZE,CodedBlock min size (2^N)" "?,?,?,3: SW_MIN_CB_SIZE_3,4: SW_MIN_CB_SIZE_4,5: SW_MIN_CB_SIZE_5,6: SW_MIN_CB_SIZE_6,?..."
newline
bitfld.long 0x00 10.--12. "SW_MAX_CB_SIZE,CodedBlock max size (2^N)" "?,?,?,3: SW_MAX_CB_SIZE_3,4: SW_MAX_CB_SIZE_4,5: SW_MAX_CB_SIZE_5,6: SW_MAX_CB_SIZE_6,?..."
newline
bitfld.long 0x00 7.--9. "SW_MIN_PCM_SIZE,PCM min size (2^N)" "?,?,?,3: SW_MIN_PCM_SIZE_3,4: SW_MIN_PCM_SIZE_4,5: SW_MIN_PCM_SIZE_5,6: SW_MIN_PCM_SIZE_6,?..."
newline
bitfld.long 0x00 4.--6. "SW_MAX_PCM_SIZE,PCM max size (2^N)" "?,?,?,3: SW_MAX_PCM_SIZE_3,4: SW_MAX_PCM_SIZE_4,5: SW_MAX_PCM_SIZE_5,6: SW_MAX_PCM_SIZE_6,?..."
newline
bitfld.long 0x00 3. "SW_PCM_E,IPCM MBs flag" "0,1"
newline
bitfld.long 0x00 2. "SW_TRANSFORM_SKIP_E,Transform skipping flag" "0,1"
newline
bitfld.long 0x00 1. "SW_TRANSQ_BYPASS_E,Transform bypass flag (lossless mode)" "0,1"
newline
bitfld.long 0x00 0. "SW_REFPICLIST_MOD_E,Refpic list reordering flag" "0,1"
group.long 0x34++0x03
line.long 0x00 "SWREG13,Decoder control register 10"
abitfld.long 0x00 0.--28. "DEC_CTRL_REG10_BF,For HEVC: [31:16] - Reserved - Not used [15:13] - sw_min_trb_size - Transform Block min size (2^N)" "0x00000003=3: 8 pix,0x00000004=4: 16 pix,0x00000005=5: 32 pix,0x00000006=6: 64 pix"
group.long 0x38++0x03
line.long 0x00 "SWREG14,Initial ref pic list register (0-2)"
hexmask.long 0x00 0.--31. 1. "INIT_REF_PIC_0_2_BF,For HEVC: [31:30] - Reserved - Not used [29:25] - sw_init_rlist_b2 - Initial reference picture list for backward picid 2 [24:20] - sw_init_rlist_f2 - Initial reference picture list for forward picid 2 [19:15] - sw_init_rlist_b1 -.."
group.long 0x3C++0x03
line.long 0x00 "SWREG15,Initial ref pic list register (3-5)"
hexmask.long 0x00 0.--31. 1. "INIT_REF_PIC_3_5_BF,For HEVC: [31:30] - Reserved - Not used [29:25] - sw_init_rlist_b5 - Initial reference picture list for backward picid 5 [24:20] - sw_init_rlist_f5 - Initial reference picture list for forward picid 5 [19:15] - sw_init_rlist_b4 -.."
group.long 0x40++0x03
line.long 0x00 "SWREG16,Initial ref pic list register (6-8)"
hexmask.long 0x00 0.--31. 1. "INIT_REF_PIC_6_8_BF,For HEVC: [31:30] - Reserved - Not used [29:25] - sw_init_rlist_b8 - Initial reference picture list for backward picid 8 [24:20] - sw_init_rlist_f8 - Initial reference picture list for forward picid 8 [19:15] - sw_init_rlist_b7 -.."
group.long 0x44++0x03
line.long 0x00 "SWREG17,Initial ref pic list register (9-11)"
hexmask.long 0x00 0.--31. 1. "INIT_REF_PIC_9_11_BF,For HEVC: [31:30] - Reserved - Not used [29:25] - sw_init_rlist_b11 - Initial reference picture list for backward picid 11 [24:20] - sw_init_rlist_f11 - Initial reference picture list for forward picid 11 [19:15] - sw_init_rlist_b10.."
group.long 0x48++0x03
line.long 0x00 "SWREG18,Initial ref pic list register (12-14)"
hexmask.long 0x00 0.--31. 1. "INIT_REF_PIC_12_14_BF,For HEVC: [31:30] - Reserved - Not used [29:25] - sw_init_rlist_b14 - Initial reference picture list for backward picid 14 [24:20] - sw_init_rlist_f14 - Initial reference picture list for forward picid 14 [19:15] -.."
group.long 0x4C++0x03
line.long 0x00 "SWREG19,Initial ref pic list register (15 and P 0-3)"
hexmask.long 0x00 0.--31. 1. "INIT_REF_PIC_15_BF,For HEVC: [31:10] - Reserved - Not used [9:5] - sw_init_rlist_b15 - Initial reference picture list for backward picid 15 [4:0] - sw_init_rlist_f15 - Initial reference picture list for forward picid 15 For VP9: [31:18] - Reserved - Not.."
group.long 0x50++0x03
line.long 0x00 "SWREG20,Decoder control register 11"
bitfld.long 0x00 31. "SW_PARTIAL_CTB_X,Picture width not multiple of CTB size" "0,1"
newline
bitfld.long 0x00 30. "SW_PARTIAL_CTB_Y,Picture height not multiple of CTB size" "0,1"
newline
hexmask.long.word 0x00 16.--27. 1. "SW_PIC_WIDTH_4X4,Current picture width in 4x4 blocks (Needed to reduce overlapping HW conditions in various blocks)"
newline
hexmask.long.word 0x00 0.--11. 1. "SW_PIC_HEIGHT_4X4,Current picture height in 4x4 blocks (Needed to reduce overlapping HW conditions in various blocks)"
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
rgroup.long ($2+0x54)++0x03
line.long 0x00 "SWREG$1,Not used"
repeat.end
rgroup.long 0x5C++0x03
line.long 0x00 "SWREG23,Decoder configure status register"
bitfld.long 0x00 12.--15. "SW_VP9_PROFILE,VP9 version" "0: SW_VP9_PROFILE_0,1: vp9 profile 2 - 10bits,?..."
newline
bitfld.long 0x00 8.--11. "SW_HEVC_VERSION,HEVC version" "0: SW_HEVC_VERSION_0,1: SW_HEVC_VERSION_1,?..."
newline
bitfld.long 0x00 7. "SW_MULTI_PREFETCH,Multi-Reference Blocks Prefetch" "0: SW_MULTI_PREFETCH_0,1: SW_MULTI_PREFETCH_1"
newline
bitfld.long 0x00 6. "SW_DEC_FORMAT_CUSTOMER1_E,Customized output format support" "0: SW_DEC_FORMAT_CUSTOMER1_E_0,1: SW_DEC_FORMAT_CUSTOMER1_E_1"
newline
bitfld.long 0x00 5. "SW_DEC_FORMAT_P010_E,P010 output format support" "0: SW_DEC_FORMAT_P010_E_0,1: SW_DEC_FORMAT_P010_E_1"
newline
bitfld.long 0x00 4. "SW_DEC_64BIT_AD_E,64 bit addressing of master interface support" "0: Not supported (32 bit addressing),1: SW_DEC_64BIT_AD_E_1"
newline
bitfld.long 0x00 3. "SW_DOWN_SUPPORT,Downscale support" "0: Do not support downscale,1: SW_DOWN_SUPPORT_1"
newline
bitfld.long 0x00 2. "SW_RFC_SUPPORT,RFC support" "0: Do not support RFC,1: SW_RFC_SUPPORT_1"
newline
bitfld.long 0x00 1. "SW_VP9_SUPPORT,VP9 support" "0: Do not support VP9,1: SW_VP9_SUPPORT_1"
newline
bitfld.long 0x00 0. "SW_HEVC_SUPPORT,HEVC support" "0: Do not support HEVC,1: SW_HEVC_SUPPORT_1"
repeat 7. (strings "24" "25" "26" "27" "28" "29" "30" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "SWREG$1,Not used"
repeat.end
group.long 0x7C++0x03
line.long 0x00 "SWREG31,VP9 segmentation values"
bitfld.long 0x00 15.--17. "SW_REFPIC_SEG6,Segment refer picture" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14. "SW_SKIP_SEG6,Segment skip enable" "0,1"
newline
bitfld.long 0x00 8.--13. "SW_FILT_LEVEL_SEG6,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_QUANT_SEG6,Segment quantization parameter"
group.long 0x80++0x03
line.long 0x00 "SWREG32,VP9 segmentation values"
bitfld.long 0x00 15.--17. "SW_REFPIC_SEG7,Segment refer picture" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14. "SW_SKIP_SEG7,Segment skip enable" "0,1"
newline
bitfld.long 0x00 8.--13. "SW_FILT_LEVEL_SEG7,Segment filter level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_QUANT_SEG7,Segment quantization parameter"
group.long 0x84++0x03
line.long 0x00 "SWREG33,VP9 reference picture scaling register 0"
hexmask.long.word 0x00 16.--31. 1. "SW_LREF_WIDTH,Accurate width of last (previous) reference picture in pixels"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_LREF_HEIGHT,Accurate height of last (previous) reference picture in pixels"
group.long 0x88++0x03
line.long 0x00 "SWREG34,VP9 reference picture scaling register 1"
hexmask.long.word 0x00 16.--31. 1. "SW_GREF_WIDTH,Accurate width of golden reference picture in pixels"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_GREF_HEIGHT,Accurate height of golden reference picture in pixels"
group.long 0x8C++0x03
line.long 0x00 "SWREG35,VP9 reference picture scaling register 2"
hexmask.long.word 0x00 16.--31. 1. "SW_AREF_WIDTH,Accurate width of alternate reference picture in pixels"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_AREF_HEIGHT,Accurate height of alternate reference picture in pixels"
group.long 0x90++0x03
line.long 0x00 "SWREG36,VP9 reference picture scaling register 3"
hexmask.long.word 0x00 16.--31. 1. "SW_LREF_HOR_SCALE,Horizontal scaling factor for last (previous) reference picture"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_LREF_VER_SCALE,Vertical scaling factor for last (previous) reference picture"
group.long 0x94++0x03
line.long 0x00 "SWREG37,VP9 reference picture scaling register 4"
hexmask.long.word 0x00 16.--31. 1. "SW_GREF_HOR_SCALE,Horizontal scaling factor for golden reference picture"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_GREF_VER_SCALE,Vertical scaling factor for golden reference picture"
group.long 0x98++0x03
line.long 0x00 "SWREG38,VP9 reference picture scaling register 5"
hexmask.long.word 0x00 16.--31. 1. "SW_AREF_HOR_SCALE,Horizontal scaling factor for alternate reference picture"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_AREF_VER_SCALE,Vertical scaling factor for alternate reference picture"
repeat 6. (strings "39" "40" "41" "42" "43" "44" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
rgroup.long ($2+0x9C)++0x03
line.long 0x00 "SWREG$1,Not used"
repeat.end
group.long 0xB4++0x03
line.long 0x00 "SWREG45,Timeout control register"
bitfld.long 0x00 31. "SW_TIMEOUT_OVERRIDE_E,Enable for SW controlled timeout" "0,1"
newline
hexmask.long 0x00 0.--30. 1. "SW_TIMEOUT_CYCLES,Amount of clock cycles to trigger timeout interrupt if no external master activity acknowledged"
group.long 0xB8++0x03
line.long 0x00 "SWREG46,Picture order count from current pictures for index 0-3"
hexmask.long 0x00 0.--31. 1. "PIC_ORD_0_3_BF,For HEVC: [31:24] - sw_cur_poc_00 - Picture order count from current picture 0 [23:16] - sw_cur_poc_01 - Picture order count from current picture 1 [15:8] - sw_cur_poc_02 - Picture order count from current picture 2 [7:0] - sw_cur_poc_03.."
group.long 0xBC++0x03
line.long 0x00 "SWREG47,Picture order count from current pictures for index 4-7"
hexmask.long 0x00 0.--31. 1. "PIC_ORD_4_7_BF,For HEVC: [31:24] - sw_cur_poc_04 - Picture order count from current picture 4 [23:16] - sw_cur_poc_05 - Picture order count from current picture 5 [15:8] - sw_cur_poc_06 - Picture order count from current picture 6 [7:0] - sw_cur_poc_07.."
group.long 0xC0++0x03
line.long 0x00 "SWREG48,Picture order count from current pictures for index 8-11"
hexmask.long.byte 0x00 24.--31. 1. "SW_CUR_POC_08,Picture order count from current picture 8"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_CUR_POC_09,Picture order count from current picture 9"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_CUR_POC_10,Picture order count from current picture 10"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_CUR_POC_11,Picture order count from current picture 11"
group.long 0xC4++0x03
line.long 0x00 "SWREG49,Picture order count from current pictures for index 12-15"
hexmask.long.byte 0x00 24.--31. 1. "SW_CUR_POC_12,Picture order count from current picture 12"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_CUR_POC_13,Picture order count from current picture 13"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_CUR_POC_14,Picture order count from current picture 14"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_CUR_POC_15,Picture order count from current picture 15"
rgroup.long 0xC8++0x03
line.long 0x00 "SWREG50,Synthesis configuration register decoder 0 (read only)"
hexmask.long.word 0x00 0.--10. 1. "SW_DEC_MAX_OWIDTH,Max configured decoder video resolution that can be decoded"
rgroup.long 0xCC++0x03
line.long 0x00 "SWREG51,Reference picture buffer control register"
rgroup.long 0xD0++0x03
line.long 0x00 "SWREG52,Reference picture buffer information register 1 (read only)"
rgroup.long 0xD4++0x03
line.long 0x00 "SWREG53,Reference picture buffer information register 2 (read only)"
rgroup.long 0xD8++0x03
line.long 0x00 "SWREG54,Synthesis configuration register decoder 1 (read only)"
bitfld.long 0x00 14.--15. "SW_DEC_MAX_OW_EXT,Max configured decoder video resolution that can be decoded" "0,1,2,3"
group.long 0xDC++0x03
line.long 0x00 "SWREG55,Advanced prefetch control register"
bitfld.long 0x00 31. "SW_APF_DISABLE,Advanced prefetch disable" "0,1"
newline
bitfld.long 0x00 30. "SW_APF_SINGLE_PU_MODE,APF amount of buffered Pus: can be restricted to buffer one PU at a time" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_APF_THRESHOLD,Advanced prefetch threshold"
rgroup.long 0xE0++0x03
line.long 0x00 "SWREG56,Synthesis configuration register decoder 2 (read only)"
hexmask.long.word 0x00 0.--12. 1. "SW_DEC_MAX_OHEIGHT,Max supported picture height in pixels"
rgroup.long 0xE4++0x03
line.long 0x00 "SWREG57,Decoder fuse register (read only)"
group.long 0xE8++0x03
line.long 0x00 "SWREG58,Device configuration register decoder 2 + Multi core control register"
bitfld.long 0x00 17. "SW_DEC_CLK_GATE_IDLE_E,Clock gating enable for decoder run-time" "0,1"
newline
bitfld.long 0x00 16. "SW_DEC_CLK_GATE_E,Clock gating enable for picture-wise/decoding format clock gating" "0,1"
newline
bitfld.long 0x00 15. "SW_DEC_REFER_DOUBLEBUFFER_E,HW internal double buffering enable for reference data" "0,1"
newline
bitfld.long 0x00 14. "SW_DEC_AXI_RD_ID_E,SW axi ID enable" "0,1"
newline
bitfld.long 0x00 13. "SW_DEC_AXI_WD_ID_E,SW axi ID enable" "0,1"
newline
bitfld.long 0x00 8.--10. "SW_DEC_BUSWIDTH,Decoder master interface buswidth" "0: SW_DEC_BUSWIDTH_0,1: SW_DEC_BUSWIDTH_1,2: SW_DEC_BUSWIDTH_2,?..."
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_DEC_MAX_BURST,Maximum burst length for decoder bus transactions"
group.long 0xEC++0x03
line.long 0x00 "SWREG59,Device configuration register AXI ID"
hexmask.long.word 0x00 16.--31. 1. "SW_DEC_AXI_WR_ID,Read ID base for HW write accesses"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_DEC_AXI_RD_ID,Write ID base for HW write accesses"
rgroup.long 0xF0++0x03
line.long 0x00 "SWREG60,Synthesis configuration register decoder 3 for PP (read only)"
bitfld.long 0x00 31. "SW_DEC_PP_E,Decoder include PP" "0: PP does not exist,1: SW_DEC_PP_E_1"
newline
bitfld.long 0x00 30. "SW_DEC_PP_RS_E,Decoder PP raster scan output support" "0: Raster scan output not supported,1: Raster scan output supported"
rgroup.long 0xF4++0x03
line.long 0x00 "SWREG61,Not used"
group.long 0xF8++0x03
line.long 0x00 "SWREG62,HW proceed register (CU location)"
hexmask.long.word 0x00 16.--31. 1. "SW_CU_LOCATION_X,Cu horizontal start location X in pixels (returned HW internal position during interrupt)"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_CU_LOCATION_Y,Cu vertical start location Y in pixels (returned HW internal position during interrupt)"
rgroup.long 0xFC++0x03
line.long 0x00 "SWREG63,HW performance register (cycles running)"
hexmask.long 0x00 0.--31. 1. "SW_PERF_CYCLE_COUNT,HW clock cycle counter return value"
group.long 0x100++0x03
line.long 0x00 "SWREG64,Base address MSB (bits 63:32) for decoded luminance picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_YBASE_MSB,Base address MSB (bits 63:32) for decoded luminance picture"
group.long 0x104++0x03
line.long 0x00 "SWREG65,Base address LSB (bits 31:0) for decoded luminance picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_YBASE_LSB,Base address LSB (bits 31:0) for decoded luminance picture"
group.long 0x108++0x03
line.long 0x00 "SWREG66,Base address MSB (bits 63:32) for reference luminance picture index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 0"
group.long 0x10C++0x03
line.long 0x00 "SWREG67,Base address LSB (bits 31:0) for reference luminance picture index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 0"
group.long 0x110++0x03
line.long 0x00 "SWREG68,Base address MSB (bits 63:32) for reference luminance picture index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 1"
group.long 0x114++0x03
line.long 0x00 "SWREG69,Base address LSB (bits 31:0) for reference luminance picture index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 1"
group.long 0x118++0x03
line.long 0x00 "SWREG70,Base address MSB (bits 63:32) for reference luminance picture index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 2"
group.long 0x11C++0x03
line.long 0x00 "SWREG71,Base address LSB (bits 31:0) for reference luminance picture index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 2"
group.long 0x120++0x03
line.long 0x00 "SWREG72,Base address MSB (bits 63:32) for reference luminance picture index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 3"
group.long 0x124++0x03
line.long 0x00 "SWREG73,Base address LSB (bits 31:0) for reference luminance picture index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 3"
group.long 0x128++0x03
line.long 0x00 "SWREG74,Base address MSB (bits 63:32) for reference luminance picture index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 4"
group.long 0x12C++0x03
line.long 0x00 "SWREG75,Base address LSB (bits 31:0) for reference luminance picture index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 4"
group.long 0x130++0x03
line.long 0x00 "SWREG76,Base address MSB (bits 63:32) for reference luminance picture index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 5"
group.long 0x134++0x03
line.long 0x00 "SWREG77,Base address LSB (bits 31:0) for reference luminance picture index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 5"
group.long 0x138++0x03
line.long 0x00 "SWREG78,Base address MSB (bits 63:32) for reference luminance picture index 6 /VP9 segment write base MSB"
hexmask.long 0x00 0.--31. 1. "BASE_ADDR_6_MSB_BF,For HEVC: [31:0] - sw_refer6_ybase_msb - Base address MSB (bits 63:32) for reference luminance picture index 6 For VP9: [31:0] - sw_segment_write_base_msb - VP9 segment write base MSB"
group.long 0x13C++0x03
line.long 0x00 "SWREG79,Base address LSB (bits 31:0) for reference luminance picture index 6 /VP9 segment write base LSB"
hexmask.long 0x00 0.--31. 1. "BASE_ADDR_6_LSB_BF,For HEVC: [31:0] - sw_refer6_ybase_lsb - Base address LSB (bits 31:0) for reference luminance picture index 6 For VP9: [31:0] - sw_segment_write_base_lsb - VP9 segment write base LSB"
group.long 0x140++0x03
line.long 0x00 "SWREG80,Base address MSB (bits 63:32) for reference luminance picture index 7 /VP9 segment read base MSB"
hexmask.long 0x00 0.--31. 1. "BASE_ADDR_7_MSB_BF,For HEVC: [31:0] - sw_refer7_ybase_msb - Base address MSB (bits 63:32) for reference luminance picture index 7 For VP9: [31:0] - sw_segment_read_base_msb - VP9 segment read base MSB"
group.long 0x144++0x03
line.long 0x00 "SWREG81,Base address LSB (bits 31:0) for reference luminance picture index 7 /VP9 segment read base LSB"
hexmask.long 0x00 0.--31. 1. "BASE_ADDR_7_LSB_BF,For HEVC: [31:0] - sw_refer7_ybase_lsb - Base address LSB (bits 31:0) for reference luminance picture index 7 For VP9: [31:0] - sw_segment_read_base_lsb - VP9 segment read base LSB"
group.long 0x148++0x03
line.long 0x00 "SWREG82,Base address MSB (bits 63:32) for reference luminance picture index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 8"
group.long 0x14C++0x03
line.long 0x00 "SWREG83,Base address LSB (bits 31:0) for reference luminance picture index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 8"
group.long 0x150++0x03
line.long 0x00 "SWREG84,Base address MSB (bits 63:32) for reference luminance picture index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 9"
group.long 0x154++0x03
line.long 0x00 "SWREG85,Base address LSB (bits 31:0) for reference luminance picture index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 9"
group.long 0x158++0x03
line.long 0x00 "SWREG86,Base address MSB (bits 63:32) for reference luminance picture index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 10"
group.long 0x15C++0x03
line.long 0x00 "SWREG87,Base address LSB (bits 31:0) for reference luminance picture index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 10"
group.long 0x160++0x03
line.long 0x00 "SWREG88,Base address MSB (bits 63:32) for reference luminance picture index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 11"
group.long 0x164++0x03
line.long 0x00 "SWREG89,Base address LSB (bits 31:0) for reference luminance picture index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 11"
group.long 0x168++0x03
line.long 0x00 "SWREG90,Base address MSB (bits 63:32) for reference luminance picture index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 12"
group.long 0x16C++0x03
line.long 0x00 "SWREG91,Base address LSB (bits 31:0) for reference luminance picture index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 12"
group.long 0x170++0x03
line.long 0x00 "SWREG92,Base address MSB (bits 63:32) for reference luminance picture index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 13"
group.long 0x174++0x03
line.long 0x00 "SWREG93,Base address LSB (bits 31:0) for reference luminance picture index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 13"
group.long 0x178++0x03
line.long 0x00 "SWREG94,Base address MSB (bits 63:32) for reference luminance picture index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 14"
group.long 0x17C++0x03
line.long 0x00 "SWREG95,Base address LSB (bits 31:0) for reference luminance picture index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 14"
group.long 0x180++0x03
line.long 0x00 "SWREG96,Base address MSB (bits 63:32) for reference luminance picture index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_YBASE_MSB,Base address MSB (bits 63:32) for reference luminance picture index 15"
group.long 0x184++0x03
line.long 0x00 "SWREG97,Base address LSB (bits 31:0) for reference luminance picture index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_YBASE_LSB,Base address LSB (bits 31:0) for reference luminance picture index 15"
group.long 0x188++0x03
line.long 0x00 "SWREG98,Base address MSB (bits 63:32) for decoded chrominance picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_CBASE_MSB,Base address MSB (bits 64:32) for decoded chrominance picture"
group.long 0x18C++0x03
line.long 0x00 "SWREG99,Base address LSB (bits 31:0) for decoded chrominance picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_CBASE_LSB,Base address LSB (bits 31:0) for decoded chrominance picture"
group.long 0x190++0x03
line.long 0x00 "SWREG100,Base address MSB (bits 63:32) for reference chrominance picture index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 0"
group.long 0x194++0x03
line.long 0x00 "SWREG101,Base address LSB (bits 31:0) for reference chrominance picture index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 0"
group.long 0x198++0x03
line.long 0x00 "SWREG102,Base address MSB (bits 63:32) for reference chrominance picture index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 1"
group.long 0x19C++0x03
line.long 0x00 "SWREG103,Base address LSB (bits 31:0) for reference chrominance picture index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 1"
group.long 0x1A0++0x03
line.long 0x00 "SWREG104,Base address MSB (bits 63:32) for reference chrominance picture index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 2"
group.long 0x1A4++0x03
line.long 0x00 "SWREG105,Base address LSB (bits 31:0) for reference chrominance picture index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 2"
group.long 0x1A8++0x03
line.long 0x00 "SWREG106,Base address MSB (bits 63:32) for reference chrominance picture index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 3"
group.long 0x1AC++0x03
line.long 0x00 "SWREG107,Base address LSB (bits 31:0) for reference chrominance picture index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 3"
group.long 0x1B0++0x03
line.long 0x00 "SWREG108,Base address MSB (bits 63:32) for reference chrominance picture index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 4"
group.long 0x1B4++0x03
line.long 0x00 "SWREG109,Base address LSB (bits 31:0) for reference chrominance picture index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 4"
group.long 0x1B8++0x03
line.long 0x00 "SWREG110,Base address MSB (bits 63:32) for reference chrominance picture index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 5"
group.long 0x1BC++0x03
line.long 0x00 "SWREG111,Base address LSB (bits 31:0) for reference chrominance picture index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 5"
group.long 0x1C0++0x03
line.long 0x00 "SWREG112,Base address MSB (bits 63:32) for reference chrominance picture index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 6"
group.long 0x1C4++0x03
line.long 0x00 "SWREG113,Base address LSB (bits 31:0) for reference chrominance picture index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 6"
group.long 0x1C8++0x03
line.long 0x00 "SWREG114,Base address MSB (bits 63:32) for reference chrominance picture index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 7"
group.long 0x1CC++0x03
line.long 0x00 "SWREG115,Base address LSB (bits 31:0) for reference chrominance picture index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 7"
group.long 0x1D0++0x03
line.long 0x00 "SWREG116,Base address MSB (bits 63:32) for reference chrominance picture index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 8"
group.long 0x1D4++0x03
line.long 0x00 "SWREG117,Base address LSB (bits 31:0) for reference chrominance picture index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 8"
group.long 0x1D8++0x03
line.long 0x00 "SWREG118,Base address MSB (bits 63:32) for reference chrominance picture index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 9"
group.long 0x1DC++0x03
line.long 0x00 "SWREG119,Base address LSB (bits 31:0) for reference chrominance picture index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 9"
group.long 0x1E0++0x03
line.long 0x00 "SWREG120,Base address MSB (bits 63:32) for reference chrominance picture index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 10"
group.long 0x1E4++0x03
line.long 0x00 "SWREG121,Base address LSB (bits 31:0) for reference chrominance picture index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 10"
group.long 0x1E8++0x03
line.long 0x00 "SWREG122,Base address MSB (bits 63:32) for reference chrominance picture index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 11"
group.long 0x1EC++0x03
line.long 0x00 "SWREG123,Base address LSB (bits 31:0) for reference chrominance picture index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 11"
group.long 0x1F0++0x03
line.long 0x00 "SWREG124,Base address MSB (bits 63:32) for reference chrominance picture index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 12"
group.long 0x1F4++0x03
line.long 0x00 "SWREG125,Base address LSB (bits 31:0) for reference chrominance picture index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 12"
group.long 0x1F8++0x03
line.long 0x00 "SWREG126,Base address MSB (bits 63:32) for reference chrominance picture index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 13"
group.long 0x1FC++0x03
line.long 0x00 "SWREG127,Base address LSB (bits 31:0) for reference chrominance picture index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 13"
group.long 0x200++0x03
line.long 0x00 "SWREG128,Base address MSB (bits 63:32) for reference chrominance picture index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 14"
group.long 0x204++0x03
line.long 0x00 "SWREG129,Base address LSB (bits 31:0) for reference chrominance picture index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 14"
group.long 0x208++0x03
line.long 0x00 "SWREG130,Base address MSB (bits 63:32) for reference chrominance picture index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_CBASE_MSB,Base address MSB (bits 63:32) for reference chrominance picture index 15"
group.long 0x20C++0x03
line.long 0x00 "SWREG131,Base address LSB (bits 31:0) for reference chrominance picture index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_CBASE_LSB,Base address LSB (bits 31:0) for reference chrominance picture index 15"
group.long 0x210++0x03
line.long 0x00 "SWREG132,Base address MSB (bits 63:32) for decoded direct mode MVS"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_DBASE_MSB,Base address MSB (bits 63:32) for decoded direct mode MVS"
group.long 0x214++0x03
line.long 0x00 "SWREG133,Base address LSB (bits 31:0) for decoded direct mode MVS"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_DBASE_LSB,Base address LSB (bits 31:0) for decoded direct mode MVS"
group.long 0x218++0x03
line.long 0x00 "SWREG134,Base address MSB (bits 63:32) for reference direct mode MVS index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 0"
group.long 0x21C++0x03
line.long 0x00 "SWREG135,Base address LSB (bits 31:0) for reference direct mode MVS index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 0"
group.long 0x220++0x03
line.long 0x00 "SWREG136,Base address MSB (bits 63:32) for reference direct mode MVS index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 1"
group.long 0x224++0x03
line.long 0x00 "SWREG137,Base address LSB (bits 31:0) for reference direct mode MVS index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 1"
group.long 0x228++0x03
line.long 0x00 "SWREG138,Base address MSB (bits 63:32) for reference direct mode MVS index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 2"
group.long 0x22C++0x03
line.long 0x00 "SWREG139,Base address LSB (bits 31:0) for reference direct mode MVS index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 2"
group.long 0x230++0x03
line.long 0x00 "SWREG140,Base address MSB (bits 63:32) for reference direct mode MVS index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 3"
group.long 0x234++0x03
line.long 0x00 "SWREG141,Base address LSB (bits 31:0) for reference direct mode MVS index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 3"
group.long 0x238++0x03
line.long 0x00 "SWREG142,Base address MSB (bits 63:32) for reference direct mode MVS index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 4"
group.long 0x23C++0x03
line.long 0x00 "SWREG143,Base address LSB (bits 31:0) for reference direct mode MVS index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 4"
group.long 0x240++0x03
line.long 0x00 "SWREG144,Base address MSB (bits 63:32) for reference direct mode MVS index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 5"
group.long 0x244++0x03
line.long 0x00 "SWREG145,Base address LSB (bits 31:0) for reference direct mode MVS index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 5"
group.long 0x248++0x03
line.long 0x00 "SWREG146,Base address MSB (bits 63:32) for reference direct mode MVS index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 6"
group.long 0x24C++0x03
line.long 0x00 "SWREG147,Base address LSB (bits 31:0) for reference direct mode MVS index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 6"
group.long 0x250++0x03
line.long 0x00 "SWREG148,Base address MSB (bits 63:32) for reference direct mode MVS index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 7"
group.long 0x254++0x03
line.long 0x00 "SWREG149,Base address LSB (bits 31:0) for reference direct mode MVS index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 7"
group.long 0x258++0x03
line.long 0x00 "SWREG150,Base address MSB (bits 63:32) for reference direct mode MVS index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 8"
group.long 0x25C++0x03
line.long 0x00 "SWREG151,Base address LSB (bits 31:0) for reference direct mode MVS index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode mode MVS index 8"
group.long 0x260++0x03
line.long 0x00 "SWREG152,Base address MSB (bits 63:32) for reference direct mode mode MVS index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 9"
group.long 0x264++0x03
line.long 0x00 "SWREG153,Base address LSB (bits 31:0) for reference direct mode mode MVS index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode mode MVS index 9"
group.long 0x268++0x03
line.long 0x00 "SWREG154,Base address MSB (bits 63:32) for reference direct mode MVS index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 10"
group.long 0x26C++0x03
line.long 0x00 "SWREG155,Base address LSB (bits 31:0) for reference direct mode MVS index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 10"
group.long 0x270++0x03
line.long 0x00 "SWREG156,Base address MSB (bits 63:32) for reference direct mode MVS index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 11"
group.long 0x274++0x03
line.long 0x00 "SWREG157,Base address LSB (bits 31:0) for reference direct mode MVS index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 11"
group.long 0x278++0x03
line.long 0x00 "SWREG158,Base address MSB (bits 63:32) for reference direct mode MVS index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 12"
group.long 0x27C++0x03
line.long 0x00 "SWREG159,Base address LSB (bits 31:0) for reference direct mode MVS index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 12"
group.long 0x280++0x03
line.long 0x00 "SWREG160,Base address MSB (bits 63:32) for reference direct mode MVS index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 13"
group.long 0x284++0x03
line.long 0x00 "SWREG161,Base address LSB (bits 31:0) for reference direct mode MVS index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 13"
group.long 0x288++0x03
line.long 0x00 "SWREG162,Base address MSB (bits 63:32) for reference direct mode MVS index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 14"
group.long 0x28C++0x03
line.long 0x00 "SWREG163,Base address LSB (bits 31:0) for reference direct mode MVS index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 14"
group.long 0x290++0x03
line.long 0x00 "SWREG164,Base address MSB (bits 63:32) for reference direct mode MVS index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_DBASE_MSB,Base address MSB (bits 63:32) for reference direct mode MVS index 15"
group.long 0x294++0x03
line.long 0x00 "SWREG165,Base address LSB (bits 31:0) for reference direct mode MVS index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_DBASE_LSB,Base address LSB (bits 31:0) for reference direct mode MVS index 15"
group.long 0x298++0x03
line.long 0x00 "SWREG166,Base address MSB (bits 63:32) for tile sizes"
hexmask.long 0x00 0.--31. 1. "SW_TILE_BASE_MSB,Base address MSB (bits 63:32) for tile sizes"
group.long 0x29C++0x03
line.long 0x00 "SWREG167,Base address LSB (bits 31:0) for tile sizes"
hexmask.long 0x00 0.--31. 1. "SW_TILE_BASE_LSB,Base address LSB (bits 31:0) for tile sizes"
group.long 0x2A0++0x03
line.long 0x00 "SWREG168,Base address MSB (bits 63:32) for / stream start address/decoded end addr register"
hexmask.long 0x00 0.--31. 1. "SW_STREAM_BASE_MSB,Base address MSB (bits 63:32) for / stream start address/decoded end addr register"
group.long 0x2A4++0x03
line.long 0x00 "SWREG169,Base address LSB (bits 31:0) for / stream start address/decoded end addr register"
hexmask.long 0x00 0.--31. 1. "SW_STREAM_BASE_LSB,Base address LSB (bits 31:0) for / stream start address/decoded end addr register"
group.long 0x2A8++0x03
line.long 0x00 "SWREG170,Base address MSB (bits 63:32) for scaling lists / VP9 CTX counter values"
hexmask.long 0x00 0.--31. 1. "SW_SCALE_LIST_CTX_COUNTER_BASE_MSB,HEVC: Base address MSB (bits 63:32) for scaling lists VP9: CTX counter values"
group.long 0x2AC++0x03
line.long 0x00 "SWREG171,Base address LSB (bits 31:0) for scaling lists / VP9 CTX counter values"
hexmask.long 0x00 0.--31. 1. "SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB,HEVC: Base address LSB (bits 31:0) for scaling lists VP9: CTX counter values"
group.long 0x2B0++0x03
line.long 0x00 "SWREG172,Base address MSB (bits 63:32) for stream propability tables"
hexmask.long 0x00 0.--31. 1. "SW_PROB_TAB_BASE_MSB,Base address MSB (bits 63:32) for stream propability tables"
group.long 0x2B4++0x03
line.long 0x00 "SWREG173,Base address LSB (bits 31:0) for stream propability tables"
hexmask.long 0x00 0.--31. 1. "SW_PROB_TAB_BASE_LSB,Base address LSB (bits 31:0) for stream propability tables"
group.long 0x2B8++0x03
line.long 0x00 "SWREG174,Base address MSB (bits 63:32) for decoder output raster scan Y picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_RSY_BASE_MSB,Base address MSB (bits 63:32) for decoder output raster scan Y picture"
group.long 0x2BC++0x03
line.long 0x00 "SWREG175,Base address LSB (bits 31:0) for decoder output raster scan Y picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_RSY_BASE_LSB,Base address LSB (bits 31:0) for decoder output raster scan Y picture"
group.long 0x2C0++0x03
line.long 0x00 "SWREG176,Base address MSB (bits 63:32) for decoder output raster scan C picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_RSC_BASE_MSB,Base address MSB (bits 63:32) for decoder output raster scan C picture"
group.long 0x2C4++0x03
line.long 0x00 "SWREG177,Base address LSB (bits 31:0) for decoder output raster scan C picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_RSC_BASE_LSB,Base address LSB (bits 31:0) for decoder output raster scan C picture"
group.long 0x2C8++0x03
line.long 0x00 "SWREG178,Base address MSB (bits 63:32) for tile border coeffients of filter"
hexmask.long 0x00 0.--31. 1. "SW_DEC_VERT_FILT_BASE_MSB,Base address MSB to store/read filtering coeffients of current picture at tile border"
group.long 0x2CC++0x03
line.long 0x00 "SWREG179,Base address LSB (bits 31:0) for tile border coeffients of filter"
hexmask.long 0x00 0.--31. 1. "SW_DEC_VERT_FILT_BASE_LSB,Base address LSB to store/read filtering coeffients of current picture at tile border"
group.long 0x2D0++0x03
line.long 0x00 "SWREG180,Base address MSB (bits 63:32) for tile border coeffients of sao"
hexmask.long 0x00 0.--31. 1. "SW_DEC_VERT_SAO_BASE_MSB,Base address MSB to store/read sao coeffients of current picture at tile border"
group.long 0x2D4++0x03
line.long 0x00 "SWREG181,Base address LSB (bits 31:0) for tile border coeffients of sao"
hexmask.long 0x00 0.--31. 1. "SW_DEC_VERT_SAO_BASE_LSB,Base address LSB to store/read sao coeffients of current picture at tile border"
group.long 0x2D8++0x03
line.long 0x00 "SWREG182,Base address MSB (bits 63:32) for tile border bsd control data"
hexmask.long 0x00 0.--31. 1. "SW_DEC_BSD_CTRL_BASE_MSB,Base address MSB to store/read BSD control data of current picture at tile border"
group.long 0x2DC++0x03
line.long 0x00 "SWREG183,Base address LSB (bits 31:0) for tile border bsd control data"
hexmask.long 0x00 0.--31. 1. "SW_DEC_BSD_CTRL_BASE_LSB,Base address LSB to store/read BSD control data of current picture at tile border"
group.long 0x2E0++0x03
line.long 0x00 "SWREG184,Raster scan down scale control register MSM"
bitfld.long 0x00 7. "SW_DEC_DS_E,Raster scan down scale enable" "0: SW_DEC_DS_E_0,1: SW_DEC_DS_E_1"
newline
bitfld.long 0x00 2.--3. "SW_DEC_DS_Y,Y coordinate down scale times for raster scan output picture data" "0: SW_DEC_DS_Y_0,1: SW_DEC_DS_Y_1,2: SW_DEC_DS_Y_2,?..."
newline
bitfld.long 0x00 0.--1. "SW_DEC_DS_X,X coordinate down scale times for raster scan output picture data" "0: SW_DEC_DS_X_0,1: SW_DEC_DS_X_1,2: SW_DEC_DS_X_2,?..."
group.long 0x2E4++0x03
line.long 0x00 "SWREG185,Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_DSY_BASE_MSB,Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture"
group.long 0x2E8++0x03
line.long 0x00 "SWREG186,Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_DSY_BASE_LSB,Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture"
group.long 0x2EC++0x03
line.long 0x00 "SWREG187,Base address MSB (bits 63:32) for decoder output raster scan down scale C picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_DSC_BASE_MSB,Base address MSB (bits 63:32) for decoder output raster scan down scale C picture"
group.long 0x2F0++0x03
line.long 0x00 "SWREG188,Base address LSB (bits 31:0) for decoder output raster scan down scale C picture"
hexmask.long 0x00 0.--31. 1. "SW_DEC_DSC_BASE_LSB,Base address LSB (bits 31:0) for decoder output raster scan down scale C picture"
group.long 0x2F4++0x03
line.long 0x00 "SWREG189,Base address MSB (bits 63:32) for decoder output compress luminance table"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_TYBASE_MSB,Base address MSB (bits 63:32) for decoder output compress luminance table"
group.long 0x2F8++0x03
line.long 0x00 "SWREG190,Base address LSB (bits 31:0) for decoder output compress luminance table"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_TYBASE_LSB,Base address LSB (bits 31:0) for decoder output compress luminance table"
group.long 0x2FC++0x03
line.long 0x00 "SWREG191,Base address MSB (bits 63:32) for reference compress luminance table index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 0"
group.long 0x300++0x03
line.long 0x00 "SWREG192,Base address LSB (bits 31:0) for reference compress luminance table index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 0"
group.long 0x304++0x03
line.long 0x00 "SWREG193,Base address MSB (bits 63:32) for reference compress luminance table index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 1"
group.long 0x308++0x03
line.long 0x00 "SWREG194,Base address LSB (bits 31:0) for reference compress luminance table index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 1"
group.long 0x30C++0x03
line.long 0x00 "SWREG195,Base address MSB (bits 63:32) for reference compress luminance table index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 2"
group.long 0x310++0x03
line.long 0x00 "SWREG196,Base address LSB (bits 31:0) for reference compress luminance table index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 2"
group.long 0x314++0x03
line.long 0x00 "SWREG197,Base address MSB (bits 63:32) for reference compress luminance table index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 3"
group.long 0x318++0x03
line.long 0x00 "SWREG198,Base address LSB (bits 31:0) for reference compress luminance table index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 3"
group.long 0x31C++0x03
line.long 0x00 "SWREG199,Base address MSB (bits 63:32) for reference compress luminance table index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 4"
group.long 0x320++0x03
line.long 0x00 "SWREG200,Base address LSB (bits 31:0) for reference compress luminance table index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 4"
group.long 0x324++0x03
line.long 0x00 "SWREG201,Base address MSB (bits 63:32) for reference compress luminance table index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 5"
group.long 0x328++0x03
line.long 0x00 "SWREG202,Base address LSB (bits 31:0) for reference compress luminance table index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 5"
group.long 0x32C++0x03
line.long 0x00 "SWREG203,Base address MSB (bits 63:32) for reference compress luminance table index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 6"
group.long 0x330++0x03
line.long 0x00 "SWREG204,Base address LSB (bits 31:0) for reference compress luminance table index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 6"
group.long 0x334++0x03
line.long 0x00 "SWREG205,Base address MSB (bits 63:32) for reference compress luminance table index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 7"
group.long 0x338++0x03
line.long 0x00 "SWREG206,Base address LSB (bits 31:0) for reference compress luminance table index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 7"
group.long 0x33C++0x03
line.long 0x00 "SWREG207,Base address MSB (bits 63:32) for reference compress luminance table index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 8"
group.long 0x340++0x03
line.long 0x00 "SWREG208,Base address LSB (bits 31:0) for reference compress luminance table index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 8"
group.long 0x344++0x03
line.long 0x00 "SWREG209,Base address MSB (bits 63:32) for reference compress luminance table index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 9"
group.long 0x348++0x03
line.long 0x00 "SWREG210,Base address LSB (bits 31:0) for reference compress luminance table index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 9"
group.long 0x34C++0x03
line.long 0x00 "SWREG211,Base address MSB (bits 63:32) for reference compress luminance table index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 10"
group.long 0x350++0x03
line.long 0x00 "SWREG212,Base address LSB (bits 31:0) for reference compress luminance table index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 10"
group.long 0x354++0x03
line.long 0x00 "SWREG213,Base address MSB (bits 63:32) for reference compress luminance table index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 11"
group.long 0x358++0x03
line.long 0x00 "SWREG214,Base address LSB (bits 31:0) for reference compress luminance table index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 11"
group.long 0x35C++0x03
line.long 0x00 "SWREG215,Base address MSB (bits 63:32) for reference compress luminance table index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 12"
group.long 0x360++0x03
line.long 0x00 "SWREG216,Base address LSB (bits 31:0) for reference compress luminance table index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 12"
group.long 0x364++0x03
line.long 0x00 "SWREG217,Base address MSB (bits 63:32) for reference compress luminance table index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 13"
group.long 0x368++0x03
line.long 0x00 "SWREG218,Base address LSB (bits 31:0) for reference compress luminance table index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 13"
group.long 0x36C++0x03
line.long 0x00 "SWREG219,Base address MSB (bits 63:32) for reference compress luminance table index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 14"
group.long 0x370++0x03
line.long 0x00 "SWREG220,Base address LSB (bits 31:0) for reference compress luminance table index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 14"
group.long 0x374++0x03
line.long 0x00 "SWREG221,Base address MSB (bits 63:32) for reference compress luminance table index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_TYBASE_MSB,Base address MSB (bits 63:32) for reference compress luminance table index 15"
group.long 0x378++0x03
line.long 0x00 "SWREG222,Base address LSB (bits 31:0) for reference compress luminance table index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_TYBASE_LSB,Base address LSB (bits 31:0) for reference compress luminance table index 15"
group.long 0x37C++0x03
line.long 0x00 "SWREG223,Base address MSB (bits 63:32) for decoder output compress chrominance table"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_TCBASE_MSB,Base address MSB (bits 63:32) for decoder output compress chrominance table"
group.long 0x380++0x03
line.long 0x00 "SWREG224,Base address LSB (bits 31:0) for decoder output compress chrominance table"
hexmask.long 0x00 0.--31. 1. "SW_DEC_OUT_TCBASE_LSB,Base address LSB (bits 31:0) for decoder output compress chrominance table"
group.long 0x384++0x03
line.long 0x00 "SWREG225,Base address MSB (bits 63:32) for reference compress chrominance table index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 0"
group.long 0x388++0x03
line.long 0x00 "SWREG226,Base address LSB (bits 31:0) for reference compress chrominance table index 0"
hexmask.long 0x00 0.--31. 1. "SW_REFER0_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 0"
group.long 0x38C++0x03
line.long 0x00 "SWREG227,Base address MSB (bits 63:32) for reference compress chrominance table index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 1"
group.long 0x390++0x03
line.long 0x00 "SWREG228,Base address LSB (bits 31:0) for reference compress chrominance table index 1"
hexmask.long 0x00 0.--31. 1. "SW_REFER1_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 1"
group.long 0x394++0x03
line.long 0x00 "SWREG229,Base address MSB (bits 63:32) for reference compress chrominance table index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 2"
group.long 0x398++0x03
line.long 0x00 "SWREG230,Base address LSB (bits 31:0) for reference compress chrominance table index 2"
hexmask.long 0x00 0.--31. 1. "SW_REFER2_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 2"
group.long 0x39C++0x03
line.long 0x00 "SWREG231,Base address MSB (bits 63:32) for reference compress chrominance table index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 3"
group.long 0x3A0++0x03
line.long 0x00 "SWREG232,Base address LSB (bits 31:0) for reference compress chrominance table index 3"
hexmask.long 0x00 0.--31. 1. "SW_REFER3_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 3"
group.long 0x3A4++0x03
line.long 0x00 "SWREG233,Base address MSB (bits 63:32) for reference compress chrominance table index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 4"
group.long 0x3A8++0x03
line.long 0x00 "SWREG234,Base address LSB (bits 31:0) for reference compress chrominance table index 4"
hexmask.long 0x00 0.--31. 1. "SW_REFER4_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 4"
group.long 0x3AC++0x03
line.long 0x00 "SWREG235,Base address MSB (bits 63:32) for reference compress chrominance table index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 5"
group.long 0x3B0++0x03
line.long 0x00 "SWREG236,Base address LSB (bits 31:0) for reference compress chrominance table index 5"
hexmask.long 0x00 0.--31. 1. "SW_REFER5_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 5"
group.long 0x3B4++0x03
line.long 0x00 "SWREG237,Base address MSB (bits 63:32) for reference compress chrominance table index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 6"
group.long 0x3B8++0x03
line.long 0x00 "SWREG238,Base address LSB (bits 31:0) for reference compress chrominance table index 6"
hexmask.long 0x00 0.--31. 1. "SW_REFER6_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 6"
group.long 0x3BC++0x03
line.long 0x00 "SWREG239,Base address MSB (bits 63:32) for reference compress chrominance table index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 7"
group.long 0x3C0++0x03
line.long 0x00 "SWREG240,Base address LSB (bits 31:0) for reference compress chrominance table index 7"
hexmask.long 0x00 0.--31. 1. "SW_REFER7_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 7"
group.long 0x3C4++0x03
line.long 0x00 "SWREG241,Base address MSB (bits 63:32) for reference compress chrominance table index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 8"
group.long 0x3C8++0x03
line.long 0x00 "SWREG242,Base address LSB (bits 31:0) for reference compress chrominance table index 8"
hexmask.long 0x00 0.--31. 1. "SW_REFER8_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 8"
group.long 0x3CC++0x03
line.long 0x00 "SWREG243,Base address MSB (bits 63:32) for reference compress chrominance table index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 9"
group.long 0x3D0++0x03
line.long 0x00 "SWREG244,Base address LSB (bits 31:0) for reference compress chrominance table index 9"
hexmask.long 0x00 0.--31. 1. "SW_REFER9_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 9"
group.long 0x3D4++0x03
line.long 0x00 "SWREG245,Base address MSB (bits 63:32) for reference compress chrominance table index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 10"
group.long 0x3D8++0x03
line.long 0x00 "SWREG246,Base address LSB (bits 31:0) for reference compress chrominance table index 10"
hexmask.long 0x00 0.--31. 1. "SW_REFER10_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 10"
group.long 0x3DC++0x03
line.long 0x00 "SWREG247,Base address MSB (bits 63:32) for reference compress chrominance table index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 11"
group.long 0x3E0++0x03
line.long 0x00 "SWREG248,Base address LSB (bits 31:0) for reference compress chrominance table index 11"
hexmask.long 0x00 0.--31. 1. "SW_REFER11_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 11"
group.long 0x3E4++0x03
line.long 0x00 "SWREG249,Base address MSB (bits 63:32) for reference compress chrominance table index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 12"
group.long 0x3E8++0x03
line.long 0x00 "SWREG250,Base address LSB (bits 31:0) for reference compress chrominance table index 12"
hexmask.long 0x00 0.--31. 1. "SW_REFER12_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 12"
group.long 0x3EC++0x03
line.long 0x00 "SWREG251,Base address MSB (bits 63:32) for reference compress chrominance table index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 13"
group.long 0x3F0++0x03
line.long 0x00 "SWREG252,Base address LSB (bits 31:0) for reference compress chrominance table index 13"
hexmask.long 0x00 0.--31. 1. "SW_REFER13_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 13"
group.long 0x3F4++0x03
line.long 0x00 "SWREG253,Base address MSB (bits 63:32) for reference compress chrominance table index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 14"
group.long 0x3F8++0x03
line.long 0x00 "SWREG254,Base address LSB (bits 31:0) for reference compress chrominance table index 14"
hexmask.long 0x00 0.--31. 1. "SW_REFER14_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 14"
group.long 0x3FC++0x03
line.long 0x00 "SWREG255,Base address MSB (bits 63:32) for reference compress chrominance table index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_TCBASE_MSB,Base address MSB (bits 63:32) for reference compress chrominance table index 15"
group.long 0x400++0x03
line.long 0x00 "SWREG256,Base address LSB (bits 31:0) for reference compress chrominance table index 15"
hexmask.long 0x00 0.--31. 1. "SW_REFER15_TCBASE_LSB,Base address LSB (bits 31:0) for reference compress chrominance table index 15"
rgroup.long 0x404++0x03
line.long 0x00 "SWREG257,Not used"
group.long 0x408++0x03
line.long 0x00 "SWREG258,input stream buffer length"
hexmask.long 0x00 0.--31. 1. "SW_STRM_BUFFER_LEN,input stream buffer length"
group.long 0x40C++0x03
line.long 0x00 "SWREG259,input stream buffer start offset"
hexmask.long 0x00 0.--31. 1. "SW_STRM_START_OFFSET,input stream buffer start offset"
tree.end
tree "VPU_H264 (DMA controller)"
base ad:0x38320000
group.long 0x04++0x03
line.long 0x00 "swreg1,Interrupt register encoder"
bitfld.long 0x00 12. "SW_ENC_STRM_SEGMENT_RDY_INT,Output stream segment IRQ" "0,1"
newline
bitfld.long 0x00 11. "SW_ENC_TIMEOUT_INT,enable timeout interrupt when 1" "0,1"
newline
bitfld.long 0x00 9. "SW_ENC_IRQ_FUSE_ERROR,Interrupt Interrupt status bit encoder" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_SLICE_RDY_STATUS,Interrupt status bit encoder" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_IRQ_LINE_BUFFER,Interrupt status bit encoder linebuffer empty" "0,1"
newline
bitfld.long 0x00 6. "SW_ENC_TIMEOUT,Interrupt status bit encoder timeout" "0,1"
newline
bitfld.long 0x00 5. "SW_ENC_BUFFER_FULL,IRQ buffer full status bit" "0,1"
newline
bitfld.long 0x00 4. "SW_ENC_SW_RESET,IRQ SW reset status bit" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_BUS_ERROR_STATUS,Interrupt status bit bus" "0,1"
newline
bitfld.long 0x00 2. "SW_ENC_FRAME_RDY_STATUS,Interrupt status bit encoder" "0,1"
newline
bitfld.long 0x00 1. "SW_ENC_IRQ_DIS,Encoder IRQ disable" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_IRQ,Encoder IRQ" "0,1"
group.long 0x08++0x03
line.long 0x00 "swreg2,Data configuration register0"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_AXI_WRITE_ID,AXI Write ID"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_AXI_READ_ID,AXI Read ID"
newline
bitfld.long 0x00 12.--15. "SW_ENC_STRM_SWAP,byte swap config for output stream data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "SW_ENC_PIC_SWAP,Byte swap configuration for picture data (encoder input)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP,Byte swap configuration for qp delta of ROI map" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SW_ENC_CTB_RC_MEM_OUT_SWAP,Byte swap configuration for ctb rate control memory out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "swreg3,Data configuration register1"
bitfld.long 0x00 31. "SW_ENC_CLOCK_GATE_ENCODER_E,ASIC encoder clock gating control" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 30. "SW_ENC_CLOCK_GATE_ENCODER_H265_E,ASIC encoder clock gating control for h265" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 29. "SW_ENC_CLOCK_GATE_ENCODER_H264_E,ASIC encoder clock gating control for h264" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 28. "SW_ENC_CLOCK_GATE_INTER_E,ASIC inter clock gating control" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 27. "SW_ENC_CLOCK_GATE_INTER_H265_E,ASIC inter clock gating control for h265" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 26. "SW_ENC_CLOCK_GATE_INTER_H264_E,ASIC inter clock gating control for h264" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 25. "SW_ENC_AXI_WR_ID_E,axi write enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 24. "SW_ENC_AXI_RD_ID_E,axi read enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 20.--23. "SW_ENC_CU_INFO_MEM_OUT_SWAP,Byte swap configuration for cu infomation memory out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SW_ENC_SLICE_INT,enable slice interrupt when 1" "0,1"
newline
bitfld.long 0x00 2. "SW_ENC_LINE_BUFFER_INT,enable line buffer interrupt when 1" "0,1"
newline
bitfld.long 0x00 1. "SW_ENC_STRM_SEGMENT_INT,enable stream segment interrupt when 1" "0,1"
group.long 0x10++0x03
line.long 0x00 "swreg4,control register 0"
bitfld.long 0x00 29.--31. "SW_ENC_MODE,Encoding mode" "?,1: bf_val_0,2: bf_val_1,?,4: bf_val_2,?..."
newline
bitfld.long 0x00 25.--26. "SW_ENC_MIN_CB_SIZE,min cb size (we only support 8x8)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 23.--24. "SW_ENC_MAX_CB_SIZE,max cb size (we only support 64x64)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 21.--22. "SW_ENC_MIN_TRB_SIZE,min tr block size (we only support 4x4)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 19.--20. "SW_ENC_MAX_TRB_SIZE,max tr block size (we only support 16x16)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 18. "SW_ENC_OUTPUT_STRM_MODE,output stream mode" "0: byte stream,1: Nal stream"
newline
bitfld.long 0x00 13.--17. "SW_ENC_CHROMA_QP_OFFSET,chroma qp offset[-12~12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 11. "SW_BW_LINEBUF_DISABLE,BW line buffer disable" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_SCALING_LIST_ENABLED_FLAG,scaling_list_enabled_flag" "0,1"
newline
bitfld.long 0x00 3.--5. "SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA,max transform hierarchy depth of intra" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER,max transform hierarchy depth of inter" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "swreg5,control register 1"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_PIC_WIDTH,Encoded width"
newline
hexmask.long.word 0x00 11.--21. 1. "SW_ENC_PIC_HEIGHT,Encoded height"
newline
bitfld.long 0x00 9. "SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG,deblocking filter override enable flag" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 8. "SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG,slice deblocking filter override flag" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 1.--2. "SW_ENC_FRAME_CODING_TYPE,Encoded picture type" "0,1,2,3"
newline
bitfld.long 0x00 0. "SW_ENC_E,encoder enable" "0,1"
group.long 0x18++0x03
line.long 0x00 "swreg6,control register 2"
hexmask.long.byte 0x00 25.--31. 1. "SW_ENC_SLICE_SIZE,slice size in ctu row for HEVC and MB row for H264"
newline
bitfld.long 0x00 15. "SW_ENC_DEBLOCKING_FILTER_CTRL,deblocking filter control.De-block filtering disable" "0: filtering is enabled for current picture,1: filtering is disabled for current picture"
newline
bitfld.long 0x00 11.--14. "SW_ENC_DEBLOCKING_TC_OFFSET,deblocking tc offset:-6~6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--10. "SW_ENC_DEBLOCKING_BETA_OFFSET,deblocking beta offset:-6~6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SW_ENC_NAL_SIZE_WRITE,Enable writing size of each NAL unit to BaseControl" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_CU_QP_DELTA_ENABLED,cu qp delta encoding is enabled:used for ROI" "0,1"
group.long 0x1C++0x03
line.long 0x00 "swreg7,control register 3"
bitfld.long 0x00 26.--31. "SW_ENC_PIC_INIT_QP,picture header qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 25. "SW_ENC_CABAC_INIT_FLAG,cabac init flag" "0,1"
newline
hexmask.long.byte 0x00 17.--24. 1. "SW_ENC_NUM_SLICES_READY,HEVC amount of completed slices"
newline
bitfld.long 0x00 14.--15. "SW_ENC_DIFF_CU_QP_DELTA_DEPTH,difference of cu qp delta depth" "0,1,2,3"
newline
bitfld.long 0x00 8.--13. "SW_ENC_PIC_QP,qp of current picture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4.--7. "SW_ENC_ROI1_DELTA_QP,ROI1 delta qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SW_ENC_ROI2_DELTA_QP,ROI2 delta qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "swreg8,stream output buffer0 address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BASE,stream output buffer0 base address"
group.long 0x24++0x03
line.long 0x00 "swreg9,stream output buffer0 limit size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BUFFER_LIMIT,Stream buffer0 limit / Output stream size (bytes)"
group.long 0x28++0x03
line.long 0x00 "swreg10,sizeTblBase"
hexmask.long 0x00 0.--31. 1. "SW_ENC_SIZE_TBL_BASE,sizeTblBase"
group.long 0x2C++0x03
line.long 0x00 "swreg11,encoded Picture order count"
hexmask.long 0x00 0.--31. 1. "SW_ENC_POC,encoded Picture order count"
group.long 0x30++0x03
line.long 0x00 "swreg12,input lum base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_INPUT_Y_BASE,input image lum base address"
group.long 0x34++0x03
line.long 0x00 "swreg13,input cb base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_INPUT_CB_BASE,input image cb base address"
group.long 0x38++0x03
line.long 0x00 "swreg14,input cr base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_INPUT_CR_BASE,input image cr base address"
group.long 0x3C++0x03
line.long 0x00 "swreg15,recon image luma base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_Y_BASE,recon image lum base address"
group.long 0x40++0x03
line.long 0x00 "swreg16,recon image chroma base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_CHROMA_BASE,recon image chroma base address"
group.long 0x48++0x03
line.long 0x00 "swreg18,reference picture reconstructed list0 luma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L0_Y0,reference picture reconstructed list0 luma0"
group.long 0x4C++0x03
line.long 0x00 "swreg19,reference picture reconstructed list0 chroma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L0_CHROMA0,reference picture reconstructed list0 chroma0"
group.long 0x58++0x03
line.long 0x00 "swreg22,Cyclic Intra"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_CIR_START,cir start"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_CIR_INTERVAL,Cyclic Intra Refresh"
newline
bitfld.long 0x00 0.--3. "SW_ENC_RCROI_ENABLE,bit3:RC enable bit2:Quatily adjustment enable bit1:roi map enable bit0:roi area enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "swreg23,intra Area"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_INTRA_AREA_LEFT,intra Area Left"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_INTRA_AREA_RIGHT,intra Area Right"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_INTRA_AREA_TOP,intra Area Top"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_INTRA_AREA_BOTTOM,intra Area Bottom"
group.long 0x60++0x03
line.long 0x00 "swreg24,ROI1 Area"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_ROI1_LEFT,ROI1 Area Left"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_ROI1_RIGHT,ROI1 Area Right"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_ROI1_TOP,ROI1 Area Top"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_ROI1_BOTTOM,ROI1 Area Bottom"
group.long 0x64++0x03
line.long 0x00 "swreg25,ROI2 Area"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_ROI2_LEFT,ROI2 Area Left"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_ROI2_RIGHT,ROI2 Area Right"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_ROI2_TOP,ROI2 Area Top"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_ROI2_BOTTOM,ROI2 Area Bottom"
group.long 0x68++0x03
line.long 0x00 "swreg26_H2V2,intra size factors"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_INTRA_SIZE_FACTOR_0,intra size factor 0"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_INTRA_SIZE_FACTOR_1,intra size factor 1"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_INTRA_SIZE_FACTOR_2,intra size factor 2"
group.long 0x6C++0x03
line.long 0x00 "swreg27_H2V2,intra mode factors"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_INTRA_SIZE_FACTOR_3,intra size factor 3"
newline
bitfld.long 0x00 17.--21. "SW_ENC_INTRA_MODE_FACTOR_0,intra mode factor 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 11.--16. "SW_ENC_INTRA_MODE_FACTOR_1,intra mode factor 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 4.--10. 1. "SW_ENC_INTRA_MODE_FACTOR_2,intra mode factor 2"
group.long 0x70++0x03
line.long 0x00 "swreg28_H2V5,inter me SATD lambda config 0"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT,lambda satd me 0"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT,lambda satd me 1"
group.long 0x74++0x03
line.long 0x00 "swreg29_H2V5,inter me SATD lambda config 1"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT,lambda satd me 2"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT,lambda satd me 3"
group.long 0x78++0x03
line.long 0x00 "swreg30_H2V5,inter me SATD lambda config 2"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT,lambda satd me 4"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT,lambda satd me 5"
group.long 0x7C++0x03
line.long 0x00 "swreg31_H2V5,inter me SATD lambda config 3"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT,lambda satd me 6"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT,lambda satd me 7"
group.long 0x80++0x03
line.long 0x00 "swreg32_H2V5,inter me SATD lambda config 4"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT,lambda satd me 8"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT,lambda satd me 9"
group.long 0x84++0x03
line.long 0x00 "swreg33_H2V5,inter me SATD lambda config 5"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT,lambda satd me 10"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT,lambda satd me 11"
group.long 0x88++0x03
line.long 0x00 "swreg34_H2V5,inter me SATD lambda config 6"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT,lambda satd me 12"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT,lambda satd me 13"
group.long 0x8C++0x03
line.long 0x00 "swreg35,inter prediction parameters1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_LAMDA_MOTION_SSE,lambda for motion SSE"
newline
bitfld.long 0x00 15.--17. "SW_ENC_BITS_EST_TU_SPLIT_PENALTY,bits estimation for tu split penalty" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 8.--14. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_8,bits estimation bias for intra cu 8"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_16,bits estimation bias for intra cu 16"
group.long 0x90++0x03
line.long 0x00 "swreg36,inter prediction parameters2"
hexmask.long.word 0x00 23.--31. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_32,bits estimation bias for intra cu 32"
newline
hexmask.long.word 0x00 13.--22. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_64,bits estimation bias for intra cu 64"
newline
hexmask.long.byte 0x00 6.--12. 1. "SW_ENC_INTER_SKIP_BIAS,inter skip bias"
newline
bitfld.long 0x00 2.--5. "SW_ENC_BITS_EST_1N_CU_PENALTY,bits estimation 1N cu penalty" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--1. "SW_ENC_OUTPUT_BITWIDTH_CHROMA,chroma output bitwidth" "0: bf_val_0,1: bf_val_1,2: bf_val_2,?..."
group.long 0x94++0x03
line.long 0x00 "swreg37,SAO lambda parameter"
bitfld.long 0x00 0.--3. "SW_ENC_CHROFFSET,Input chrominance offset (bytes) [0..15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x98++0x03
line.long 0x00 "swreg38,Pre-processor configuration"
bitfld.long 0x00 28.--31. "SW_ENC_INPUT_FORMAT,Input image format" "?,1: bf_val_0,2: bf_val_1,3: bf_val_2,4: bf_val_3,5: bf_val_4,6: bf_val_5,7: bf_val_6,8: RGB101010,9: bf_val_8,10: bf_val_9,11: PACKED10BITPLANAR,12: bf_val_11,13: bf_val_12,14: bf_val_13,?..."
newline
bitfld.long 0x00 26.--27. "SW_ENC_INPUT_ROTATION,Input image rotation" "0: disabled,1: 90 degrees right,2: 90 degrees left,3: 180 degree right"
newline
bitfld.long 0x00 24.--25. "SW_ENC_OUTPUT_BITWIDTH_LUM,luma output bitwidth" "0: bf_val_0,1: bf_val_1,2: bf_val_2,?..."
newline
bitfld.long 0x00 20.--23. "SW_ENC_LUMOFFSET,Input luminance offset (bytes) [0..15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 6.--19. 1. "SW_ENC_ROWLENGTH,Input luminance row length"
newline
bitfld.long 0x00 4.--5. "SW_ENC_XFILL,Overfill pixels on right edge of image div2 [0.1.2.3]" "0,1,2,3"
newline
bitfld.long 0x00 1.--3. "SW_ENC_YFILL,Overfill pixels on bottom edge of image" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SW_ENC_MIRROR,mirror or not" "0,1"
group.long 0x9C++0x03
line.long 0x00 "swreg39,Pre-processor color conversion parameters0"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFA,RGB to YUV conversion coefficient A"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_RGBCOEFFB,RGB to YUV conversion coefficient B"
group.long 0xA0++0x03
line.long 0x00 "swreg40,Pre-processor color conversion parameters1"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFC,RGB to YUV conversion coefficient C"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_RGBCOEFFE,RGB to YUV conversion coefficient D"
group.long 0xA4++0x03
line.long 0x00 "swreg41,Pre-processor color conversion parameters2"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFF,RGB to YUV conversion coefficient E"
newline
bitfld.long 0x00 11.--15. "SW_ENC_RMASKMSB,RGB R-component mask MSB bit position [0..31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "SW_ENC_GMASKMSB,RGB G-component mask MSB bit position [0..31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--5. "SW_ENC_BMASKMSB,RGB B-component mask MSB bit position [0..31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA8++0x03
line.long 0x00 "swreg42,Pre-processor Base address for down-scaled output"
hexmask.long 0x00 0.--31. 1. "SW_ENC_BASESCALEDOUTLUM,Base address for output of down-scaled encoder image in YUYV 4:2:2 format"
group.long 0xAC++0x03
line.long 0x00 "swreg43,Pre-processor down-scaled configuration0"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_SCALEDOUTWIDTH,Scaling width of down-scaled image"
newline
hexmask.long.word 0x00 3.--18. 1. "SW_ENC_SCALEDOUTWIDTHRATIO,Scaling ratio for width of down-scaled image"
newline
bitfld.long 0x00 2. "SW_ENC_SCALEDOUTWIDTHMSB,Scaling width of down-scaled image" "0,1"
newline
bitfld.long 0x00 0.--1. "SW_ENC_SCALE_MODE,Scaling mode" "0: disabled,1: scaling only,2: scale+encode,?..."
group.long 0xB0++0x03
line.long 0x00 "swreg44,Pre-processor down-scaled configuration1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_SCALEDOUTHEIGHT,Scaling height of down-scaled image"
newline
hexmask.long.word 0x00 2.--17. 1. "SW_ENC_SCALEDOUTHEIGHTRATIO,Scaling ratio for height of down-scaled image"
newline
bitfld.long 0x00 0.--1. "SW_ENC_INPUT_FORMAT_MSB,Input image format bit[5:4]" "0,1,2,3"
group.long 0xB4++0x03
line.long 0x00 "swreg45,Pre-processor down-scaled configuration2"
bitfld.long 0x00 28.--31. "SW_ENC_SCALEDOUT_SWAP,Byte swap configuration for scaledout data (scaledout)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 27. "SW_ENC_CHROMA_SWAP,Swap order of chroma bytes in semiplanar input format" "0,1"
newline
hexmask.long.word 0x00 14.--26. 1. "SW_ENC_ENCODED_CTB_NUMBER,MB count output"
newline
bitfld.long 0x00 12.--13. "SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN,skip left pixel column" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "SW_ENC_SCALEDSKIPTOPPIXELROW,skip top pixel row" "0,1,2,3"
newline
bitfld.long 0x00 9. "SW_ENC_VSCALE_WEIGHT_EN,vertical scale weight enable" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_SCALEDHORIZONTALCOPY,horizontal data copy directly" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_SCALEDVERTICALCOPY,vertical data copy directly" "0,1"
newline
bitfld.long 0x00 3.--6. "SW_ENC_NALUNITSIZE_SWAP,Byte swap configuration for Nal Unit size output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "SW_ENC_SCALEDOUT_FORMAT,out-loop scaler ouput format" "0,1"
group.long 0xB8++0x03
line.long 0x00 "swreg46,compressed coefficients base address for SAN module"
hexmask.long 0x00 0.--31. 1. "SW_ENC_COMPRESSEDCOEFF_BASE,Base address for compressed coefficients"
group.long 0xF0++0x03
line.long 0x00 "swreg60,Base address for recon luma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE,Base address for recon luma compress table LSB"
group.long 0xF8++0x03
line.long 0x00 "swreg62,Base address for recon Chroma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE,Base address for recon Chroma compress table LSB"
group.long 0x100++0x03
line.long 0x00 "swreg64,Base address for list 0 ref 0 luma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE,Base address for list 0 ref 0 luma compress table LSB"
group.long 0x108++0x03
line.long 0x00 "swreg66,Base address for list 0 ref 0 Chroma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE,Base address for list 0 ref 0 Chroma compress table LSB"
group.long 0x120++0x03
line.long 0x00 "swreg72,Base address for recon luma 4n base LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_LUMA_4N_BASE,Base address for recon luma 4n base LSB"
group.long 0x128++0x03
line.long 0x00 "swreg74,reference picture reconstructed list0 4n 0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L0_4N0_BASE,reference picture reconstructed list0 4n 0"
group.long 0x138++0x03
line.long 0x00 "swreg78_H2V5,inter me SATD lambda config 7"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT,lambda satd me 14"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT,lambda satd me 15"
group.long 0x13C++0x03
line.long 0x00 "swreg79_H2V5,inter me SSE lambda config 0"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT,inter me SSE lambda 0"
rgroup.long 0x140++0x03
line.long 0x00 "swreg80,HW synthesis config register read-only"
bitfld.long 0x00 31. "SW_ENC_HWH264SUPPORT,H264 encoding supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 30. "SW_ENC_HWSCALINGSUPPORT,Down-scaling supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 29. "SW_ENC_HWBFRAMESUPPORT,HW bframe support" "0: not support bframe,1: support bframe"
newline
bitfld.long 0x00 28. "SW_ENC_HWRGBSUPPORT,RGB to YUV conversion supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 27. "SW_ENC_HWHEVCSUPPORT,HEVC encoding supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 26. "SW_ENC_HWVP9SUPPORT,VP9 encoding supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 25. "SW_ENC_HWDENOISESUPPORT,denoise supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 24. "SW_ENC_HWMAIN10SUPPORT,main10 supported by HW" "0: main8 supported,1: main10 supported"
newline
bitfld.long 0x00 21.--23. "SW_ENC_HWBUS,Bus connection of HW" "?,1: bf_val_0,2: bf_val_1,3: bf_val_2,4: bf_val_3,5: bf_val_4,6: bf_val_5,?..."
newline
bitfld.long 0x00 20. "SW_ENC_HWCAVLCSUPPORT,CAVLC supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 19. "SW_ENC_HWLINEBUFSUPPORT,LineBuffer input mode supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 18. "SW_ENC_HWPROGRDOSUPPORT,Prog Rdo supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 17. "SW_ENC_HWRFCSUPPORT,Reference frame compression supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 16. "SW_ENC_HWTU32SUPPORT,TU32 supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 15. "SW_ENC_HWJPEGSUPPORT,JPEG encoder supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 13.--14. "SW_ENC_HWBUSWIDTH,Bus width of HW" "0: bf_val_0,1: bf_val_1,2: bf_val_2,?..."
newline
hexmask.long.word 0x00 0.--12. 1. "SW_ENC_HWMAXVIDEOWIDTH,Maximum video width supported by HW (pixels)"
group.long 0x144++0x03
line.long 0x00 "swreg81,hardware configuation 0"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_MAX_BURST,for support AXI4.0 burst length is programmable Default value:0x20"
newline
bitfld.long 0x00 23. "SW_TIMEOUT_OVERRIDE_E,enable signal if timeout period is controlled by software Default value: 0x0" "0,1"
newline
hexmask.long.tbyte 0x00 0.--22. 1. "SW_TIMEOUT_CYCLES,timeout cycles number default value: 0x0"
rgroup.long 0x148++0x03
line.long 0x00 "swreg82,record hardware performance"
hexmask.long 0x00 0.--31. 1. "SW_ENC_HW_PERFORMANCE,record hardware performance(cycles) of current picture"
group.long 0x14C++0x03
line.long 0x00 "swreg83,reference picture reconstructed list1 luma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L1_Y0,reference picture reconstructed list1 luma0"
group.long 0x150++0x03
line.long 0x00 "swreg84,reference picture reconstructed list1 chroma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L1_CHROMA0,reference picture reconstructed list1 chroma0"
group.long 0x16C++0x03
line.long 0x00 "swreg91,reference pictures list1 config"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_L1_DELTA_POC0,delta poc of list1 pic0"
newline
bitfld.long 0x00 21. "SW_ENC_L1_LONG_TERM_FLAG0,list1 pic0 is long term" "0,1"
newline
bitfld.long 0x00 20. "SW_ENC_L1_USED_BY_CURR_PIC0,list1 pic0 used by current" "0,1"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_ENC_L1_DELTA_POC1,delta poc of list1 pic1"
newline
bitfld.long 0x00 9. "SW_ENC_L1_LONG_TERM_FLAG1,list1 pic1 is long term" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_L1_USED_BY_CURR_PIC1,list1 pic1 used by current" "0,1"
newline
bitfld.long 0x00 6.--7. "SW_ENC_ACTIVE_L1_CNT,active l0 count" "0,1,2,3"
newline
bitfld.long 0x00 4. "SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG,long-term reference pictures may be used for inter prediction" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE,list1 ref0 frame luma compressor enable flag" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 2. "SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE,list1 ref0 frame chroma compressor enable flag" "0: bf_val_0,1: bf_val_1"
group.long 0x170++0x03
line.long 0x00 "swreg92,reference picture reconstructed list1 4n 0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L1_4N0_BASE,reference picture reconstructed list1 4n 0"
group.long 0x180++0x03
line.long 0x00 "swreg96,Base address for list 1 ref 0 luma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE,Base address for list 1 ref 0 luma compress table LSB"
group.long 0x188++0x03
line.long 0x00 "swreg98,Base address for list 1 ref 0 Chroma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE,Base address for list 1 ref 0 Chroma compress table LSB"
group.long 0x1A8++0x03
line.long 0x00 "swreg106,Min picture size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MINPICSIZE,Allowed minimum picture size for CTB rate control"
group.long 0x1AC++0x03
line.long 0x00 "swreg107,Max picture size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MAXPICSIZE,Allowed minimum picture size for CTB rate control"
group.long 0x1B4++0x03
line.long 0x00 "swreg109,Qp delta map"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAPDELTAQPADDR,Qp delta map"
rgroup.long 0x1BC++0x03
line.long 0x00 "swreg111,adaptive GOP configuration1"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_INTRACU8NUM,The number of block8x8 with type INTRA"
rgroup.long 0x1C0++0x03
line.long 0x00 "swreg112,adaptive GOP configuration2"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_SKIPCU8NUM,The number of block8x8 with type SKIP"
group.long 0x1C4++0x03
line.long 0x00 "swreg113,adaptive GOP configuration3"
hexmask.long 0x00 0.--31. 1. "SW_ENC_PBFRAME4NRDCOST,PBFrame4NRdCost"
group.long 0x1C8++0x03
line.long 0x00 "swreg114,ctb rate control bit memory address of current frame"
hexmask.long 0x00 0.--31. 1. "SW_ENC_COLCTBS_STORE_BASE,H.264 collocated mb memory address of current frame (for store)"
group.long 0x1D0++0x03
line.long 0x00 "swreg116,ctb rate control bit memory address of previous frame"
hexmask.long 0x00 0.--31. 1. "SW_ENC_COLCTBS_LOAD_BASE,H.264 collocated mb memory address of reference frame (for load)"
group.long 0x1DC++0x03
line.long 0x00 "swreg119,min/max lcu bits number of last picture"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_CTBBITSMIN,minimum lcu bits number of last picture"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_CTBBITSMAX,maximum lcu bits number of last picture"
group.long 0x1E0++0x03
line.long 0x00 "swreg120,total bits number of all lcus of last picture not including slice header bits"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALLCUBITS,total bits number of all lcus of last picture not including slice header bits"
group.long 0x1E8++0x03
line.long 0x00 "swreg122_H2V5,inter me SSE lambda config 1"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT,inter me SSE lambda 1"
group.long 0x1EC++0x03
line.long 0x00 "swreg123_H2V5,inter me SSE lambda config 2"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT,inter me SSE lambda 2"
group.long 0x1F0++0x03
line.long 0x00 "swreg124_H2V5,inter me SSE lambda config 3"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT,inter me SSE lambda 3"
group.long 0x1F4++0x03
line.long 0x00 "swreg125,intra SATD lambda config 0"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_0,intra SATD lambda 0"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_1,intra SATD lambda 1"
group.long 0x1F8++0x03
line.long 0x00 "swreg126,intra SATD lambda config 1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_2,intra SATD lambda 2"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_3,intra SATD lambda 3"
group.long 0x1FC++0x03
line.long 0x00 "swreg127,intra SATD lambda config 2"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_4,intra SATD lambda 4"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_5,intra SATD lambda 5"
group.long 0x200++0x03
line.long 0x00 "swreg128,intra SATD lambda config 3"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_6,intra SATD lambda 6"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_7,intra SATD lambda 7"
group.long 0x204++0x03
line.long 0x00 "swreg129,intra SATD lambda config 4"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_8,intra SATD lambda 8"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_9,intra SATD lambda 9"
group.long 0x208++0x03
line.long 0x00 "swreg130,intra SATD lambda config 5"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_10,intra SATD lambda 10"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_11,intra SATD lambda 11"
group.long 0x20C++0x03
line.long 0x00 "swreg131,intra SATD lambda config 6"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_12,intra SATD lambda 12"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_13,intra SATD lambda 13"
group.long 0x210++0x03
line.long 0x00 "swreg132,intra SATD lambda config 7"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_14,intra SATD lambda 14"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_15,intra SATD lambda 15"
group.long 0x214++0x03
line.long 0x00 "swreg133,SSE devide 256"
hexmask.long 0x00 0.--31. 1. "SW_ENC_SSE_DIV_256,sse divide 256"
group.long 0x228++0x03
line.long 0x00 "swreg138_H2V5,inter me SSE lambda config 4"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT,inter me SSE lambda 3"
group.long 0x22C++0x03
line.long 0x00 "swreg139_H2V5,inter me SSE lambda config 5"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT,inter me SSE lambda 5"
group.long 0x230++0x03
line.long 0x00 "swreg140_H2V5,inter me SSE lambda config 6"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT,inter me SSE lambda 6"
group.long 0x234++0x03
line.long 0x00 "swreg141_H2V5,inter me SSE lambda config 7"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT,inter me SSE lambda 7"
group.long 0x238++0x03
line.long 0x00 "swreg142_H2V5,inter me SSE lambda config 8"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT,inter me SSE lambda 8"
group.long 0x23C++0x03
line.long 0x00 "swreg143_H2V5,inter me SSE lambda config 9"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT,inter me SSE lambda 9"
group.long 0x240++0x03
line.long 0x00 "swreg144_H2V5,inter me SSE lambda config 10"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT,inter me SSE lambda 10"
group.long 0x244++0x03
line.long 0x00 "swreg145_H2V5,inter me SSE lambda config 11"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT,inter me SSE lambda 11"
group.long 0x248++0x03
line.long 0x00 "swreg146_H2V5,inter me SSE lambda config 12"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT,inter me SSE lambda 12"
group.long 0x24C++0x03
line.long 0x00 "swreg147_H2V5,inter me SSE lambda config 13"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT,inter me SSE lambda 13"
group.long 0x250++0x03
line.long 0x00 "swreg148_H2V5,inter me SSE lambda config 14"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT,inter me SSE lambda 14"
group.long 0x254++0x03
line.long 0x00 "swreg149_H2V5,inter me SSE lambda config 15"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT,inter me SSE lambda 15"
group.long 0x258++0x03
line.long 0x00 "swreg150,inter me SATD lambda config 8"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_16,lambda satd me 16"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_17,lambda satd me 17"
group.long 0x25C++0x03
line.long 0x00 "swreg151,inter me SATD lambda config 9"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_18,lambda satd me 18"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_19,lambda satd me 19"
group.long 0x260++0x03
line.long 0x00 "swreg152,inter me SATD lambda config 10"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_20,lambda satd me 20"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_21,lambda satd me 21"
group.long 0x264++0x03
line.long 0x00 "swreg153,inter me SATD lambda config 11"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_22,lambda satd me 22"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_23,lambda satd me 23"
group.long 0x268++0x03
line.long 0x00 "swreg154,inter me SATD lambda config 12"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_24,lambda satd me 24"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_25,lambda satd me 25"
group.long 0x26C++0x03
line.long 0x00 "swreg155,inter me SATD lambda config 13"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_26,lambda satd me 26"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_27,lambda satd me 27"
group.long 0x270++0x03
line.long 0x00 "swreg156,inter me SATD lambda config 14"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_28,lambda satd me 28"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_29,lambda satd me 29"
group.long 0x274++0x03
line.long 0x00 "swreg157,inter me SATD lambda config 15"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_30,lambda satd me 30"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_31,lambda satd me 31"
group.long 0x278++0x03
line.long 0x00 "swreg158,inter me SSE lambda config 16"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_16,inter me SSE lambda 16"
group.long 0x27C++0x03
line.long 0x00 "swreg159,inter me SSE lambda config 17"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_17,inter me SSE lambda 17"
group.long 0x280++0x03
line.long 0x00 "swreg160,inter me SSE lambda config 18"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_18,inter me SSE lambda 18"
group.long 0x284++0x03
line.long 0x00 "swreg161,inter me SSE lambda config 19"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_19,inter me SSE lambda 19"
group.long 0x288++0x03
line.long 0x00 "swreg162,inter me SSE lambda config 20"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_20,inter me SSE lambda 20"
group.long 0x28C++0x03
line.long 0x00 "swreg163,inter me SSE lambda config 21"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_21,inter me SSE lambda 21"
group.long 0x290++0x03
line.long 0x00 "swreg164,inter me SSE lambda config 22"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_22,inter me SSE lambda 22"
group.long 0x294++0x03
line.long 0x00 "swreg165,inter me SSE lambda config 23"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_23,inter me SSE lambda 23"
group.long 0x298++0x03
line.long 0x00 "swreg166,inter me SSE lambda config 24"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_24,inter me SSE lambda 24"
group.long 0x29C++0x03
line.long 0x00 "swreg167,inter me SSE lambda config 25"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_25,inter me SSE lambda 25"
group.long 0x2A0++0x03
line.long 0x00 "swreg168,inter me SSE lambda config 26"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_26,inter me SSE lambda 26"
group.long 0x2A4++0x03
line.long 0x00 "swreg169,inter me SSE lambda config 27"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_27,inter me SSE lambda 27"
group.long 0x2B0++0x03
line.long 0x00 "swreg172,inter me SSE lambda config 30"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_30,inter me SSE lambda 30"
newline
bitfld.long 0x00 5.--10. "SW_ENC_QP_MIN,min value of qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--4. "SW_ENC_COMPLEXITY_OFFSET,block rc complexity offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2B4++0x03
line.long 0x00 "swreg173,inter me SSE lambda config 31"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_31,inter me SSE lambda 31"
newline
bitfld.long 0x00 5.--10. "SW_ENC_QP_MAX,max value of qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--3. "SW_ENC_RC_QPDELTA_RANGE,rc qp delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2B8++0x03
line.long 0x00 "swreg174,intra SATD lambda config 8"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_16,intra SATD lambda 16"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_17,intra SATD lambda 17"
group.long 0x2BC++0x03
line.long 0x00 "swreg175,intra SATD lambda config 9"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_18,intra SATD lambda 18"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_19,intra SATD lambda 19"
group.long 0x2C0++0x03
line.long 0x00 "swreg176,intra SATD lambda config 10"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_20,intra SATD lambda 20"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_21,intra SATD lambda 21"
group.long 0x2C4++0x03
line.long 0x00 "swreg177,intra SATD lambda config 11"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_22,intra SATD lambda 22"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_23,intra SATD lambda 23"
group.long 0x2C8++0x03
line.long 0x00 "swreg178,intra SATD lambda config 12"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_24,intra SATD lambda 24"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_25,intra SATD lambda 25"
group.long 0x2CC++0x03
line.long 0x00 "swreg179,intra SATD lambda config 13"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_26,intra SATD lambda 26"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_27,intra SATD lambda 27"
group.long 0x2D0++0x03
line.long 0x00 "swreg180,intra SATD lambda config 14"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_28,intra SATD lambda 28"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_29,intra SATD lambda 29"
group.long 0x2D4++0x03
line.long 0x00 "swreg181,intra SATD lambda config 15"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_30,intra SATD lambda 30"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_31,intra SATD lambda 31"
newline
bitfld.long 0x00 2.--3. "SW_ENC_RC_BLOCK_SIZE,block rc block size" "0: bf_val_0,1: bf_val_1,2: bf_val_2,?..."
group.long 0x2D8++0x03
line.long 0x00 "swreg182,qp fractional part"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_QP_FRACTIONAL,qp fractional part"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_QP_DELTA_GAIN,qp delta gain"
rgroup.long 0x2DC++0x03
line.long 0x00 "swreg183,qp sum"
hexmask.long 0x00 6.--31. 1. "SW_ENC_QP_SUM,Block qp sum"
rgroup.long 0x2E0++0x03
line.long 0x00 "swreg184,qp num"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_QP_NUM,Block qp number"
group.long 0x2E4++0x03
line.long 0x00 "swreg185,picture complexity"
hexmask.long.tbyte 0x00 9.--31. 1. "SW_ENC_PIC_COMPLEXITY,Picture complexity"
newline
hexmask.long.word 0x00 0.--8. 1. "SW_TIMEOUT_CYCLES_MSB,Extend swreg81"
group.long 0x2F8++0x03
line.long 0x00 "swreg190,Long-term reference pictures config"
bitfld.long 0x00 30.--31. "SW_ENC_NUM_LONG_TERM_PICS,Number of long-term reference pictures directly signaled in the slice header" "0,1,2,3"
group.long 0x2FC++0x03
line.long 0x00 "swreg191,Temporal scalable config"
bitfld.long 0x00 26.--31. "SW_ENC_NAL_UNIT_TYPE,NAL unit type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 23.--25. "SW_ENC_NUH_TEMPORAL_ID,NAL temporal id" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--22. "SW_ENC_PPS_ID,PPS id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16. "SW_ENC_PREFIXNAL_SVC_EXT,H264 SVCT enable" "0: bf_val_1,1: enabled (insert H264Scalability SEI)"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_SLICE_HEADER_SIZE,Slice header size"
group.long 0x300++0x03
line.long 0x00 "swreg192,encoded Picture frame number (for H.264)"
hexmask.long 0x00 0.--31. 1. "SW_ENC_FRAMENUM,encoded Picture frame number"
group.long 0x304++0x03
line.long 0x00 "swreg193,reference pictures list0 config (for H.264)"
hexmask.long.word 0x00 21.--31. 1. "SW_ENC_L0_DELTA_FRAMENUM0,delta frame_num of list0 pic0"
newline
bitfld.long 0x00 20. "SW_ENC_L0_USED_BY_NEXT_PIC0,list0 pic0 used by later frames" "0,1"
newline
hexmask.long.word 0x00 9.--19. 1. "SW_ENC_L0_DELTA_FRAMENUM1,delta frame_num of list0 pic1"
newline
bitfld.long 0x00 8. "SW_ENC_L0_USED_BY_NEXT_PIC1,list0 pic1 used by later frames" "0,1"
newline
bitfld.long 0x00 6.--7. "SW_ENC_XFILL_MSB,Overfill pixels on right edge of image div2" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "SW_ENC_YFILL_MSB,Overfill pixels on bottom edge of image" "0,1,2,3"
newline
bitfld.long 0x00 3. "SW_ENC_NAL_REF_IDC,current pic is used as reference" "0,1"
newline
bitfld.long 0x00 2. "SW_ENC_IDR_PIC_ID,picture id for IDR frame" "0,1"
newline
bitfld.long 0x00 1. "SW_ENC_TRANSFORM8X8_ENABLE,Enable transform8x8" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_ENTROPY_CODING_MODE,Entropy coding mode flag" "0,1"
group.long 0x308++0x03
line.long 0x00 "swreg194,reference pictures list1 config (for H.264)"
hexmask.long.word 0x00 21.--31. 1. "SW_ENC_L1_DELTA_FRAMENUM0,delta frame_num of list1 pic0"
newline
bitfld.long 0x00 20. "SW_ENC_L1_USED_BY_NEXT_PIC0,list1 pic0 used by later frames" "0,1"
newline
hexmask.long.word 0x00 9.--19. 1. "SW_ENC_L1_DELTA_FRAMENUM1,delta frame_num of list1 pic1"
newline
bitfld.long 0x00 8. "SW_ENC_L1_USED_BY_NEXT_PIC1,list1 pic1 used by later frames" "0,1"
newline
bitfld.long 0x00 5.--7. "SW_ENC_MAX_LONGTERMIDX_PLUS1,max number of long term frames (for H.264)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--4. "SW_ENC_CUR_LONGTERMIDX,long term frame idx of current frame (for H.264)" "0,1,2,3,4,5,6,7"
group.long 0x30C++0x03
line.long 0x00 "swreg195,register extension for ctu_size=16"
bitfld.long 0x00 28.--31. "SW_ENC_ENCODED_CTB_NUMBER_MSB,MB count output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 26.--27. "SW_ENC_NUM_SLICES_READY_MSB,HEVC amount of completed slices" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "SW_ENC_SLICE_SIZE_MSB,slice size in ctu row" "0,1,2,3"
newline
bitfld.long 0x00 20.--23. "SW_ENC_CIR_START_MSB,cir start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "SW_ENC_CIR_INTERVAL_MSB,Cyclic Intra Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 15. "SW_ENC_INTRA_AREA_LEFT_MSB,intra Area Left" "0,1"
newline
bitfld.long 0x00 14. "SW_ENC_INTRA_AREA_RIGHT_MSB,intra Area Right" "0,1"
newline
bitfld.long 0x00 13. "SW_ENC_INTRA_AREA_TOP_MSB,intra Area Top" "0,1"
newline
bitfld.long 0x00 12. "SW_ENC_INTRA_AREA_BOTTOM_MSB,intra Area Bottom" "0,1"
newline
bitfld.long 0x00 11. "SW_ENC_ROI1_LEFT_MSB,ROI1 Area Left" "0,1"
newline
bitfld.long 0x00 10. "SW_ENC_ROI1_RIGHT_MSB,ROI1 Area Right" "0,1"
newline
bitfld.long 0x00 9. "SW_ENC_ROI1_TOP_MSB,ROI1 Area Top" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_ROI1_BOTTOM_MSB,ROI1 Area Bottom" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_ROI2_LEFT_MSB,ROI2 Area Left" "0,1"
newline
bitfld.long 0x00 6. "SW_ENC_ROI2_RIGHT_MSB,ROI2 Area Right" "0,1"
newline
bitfld.long 0x00 5. "SW_ENC_ROI2_TOP_MSB,ROI2 Area Top" "0,1"
newline
bitfld.long 0x00 4. "SW_ENC_ROI2_BOTTOM_MSB,ROI2 Area Bottom" "0,1"
newline
bitfld.long 0x00 2.--3. "SW_ENC_PIC_WIDTH_MSB,Encoded width" "0,1,2,3"
group.long 0x310++0x03
line.long 0x00 "swreg196,Low Latency Controls"
bitfld.long 0x00 31. "SW_LOW_LATENCY_HW_SYNC_EN,Low Latency Hardware Interface Enable" "0,1"
newline
bitfld.long 0x00 30. "SW_LOW_LATENCY_EN,Low Latency Enable" "0,1"
newline
bitfld.long 0x00 29. "SW_INPUT_BUF_LOOPBACK_EN,Input buffer loopback Enable" "0,1"
newline
hexmask.long.word 0x00 20.--28. 1. "SW_NUM_CTB_ROWS_PER_SYNC,Number of CTB rows for every HW sync"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_CTB_ROW_RD_PTR,The number of CTB rows that has been fetched from Input buffer by encoder"
newline
hexmask.long.word 0x00 0.--9. 1. "SW_CTB_ROW_WR_PTR,The number of CTB rows that has been filled into the input buffer by external application"
group.long 0x314++0x03
line.long 0x00 "swreg197,Delta POC extension"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_L0_DELTA_POC0_MSB,delta poc of list0 pic0 (bit[19..10])"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_L0_DELTA_POC1_MSB,delta poc of list0 pic1 (bit[19..10])"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_L1_DELTA_POC0_MSB,delta poc of list1 pic0 (bit[19..10])"
group.long 0x318++0x03
line.long 0x00 "swreg198,Long Term Reference Control"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_L1_DELTA_POC1_MSB,delta poc of list1 pic1 (bit[19..10])"
newline
hexmask.long.word 0x00 13.--21. 1. "SW_ENC_L0_DELTA_FRAMENUM0_MSB,delta frame_num of list0 pic0 (bit[19..11])"
newline
bitfld.long 0x00 12. "SW_ENC_MARK_CURRENT_LONGTERM,mark current frame as long term reference (for H.264)" "0,1"
newline
bitfld.long 0x00 9.--11. "SW_ENC_L0_LONGTERMIDX0,long term frame idx of list0 pic 0 (for H.264)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--8. "SW_ENC_L0_LONGTERMIDX1,long term frame idx of list0 pic 1 (for H.264)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "SW_ENC_L1_LONGTERMIDX0,long term frame idx of list1 pic 0 (for H.264)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "SW_ENC_L1_LONGTERMIDX1,long term frame idx of list1 pic 1 (for H.264)" "0,1,2,3,4,5,6,7"
group.long 0x31C++0x03
line.long 0x00 "swreg199,Hash Code Control"
hexmask.long.word 0x00 23.--31. 1. "SW_ENC_L0_DELTA_FRAMENUM1_MSB,delta frame_num of list0 pic1 (bit[19..11])"
newline
hexmask.long.word 0x00 14.--22. 1. "SW_ENC_L1_DELTA_FRAMENUM0_MSB,delta frame_num of list1 pic0 (bit[19..11])"
newline
hexmask.long.word 0x00 5.--13. 1. "SW_ENC_L1_DELTA_FRAMENUM1_MSB,delta frame_num of list1 pic1 (bit[19..11])"
newline
bitfld.long 0x00 3.--4. "SW_ENC_HASH_TYPE,hash type of frame data" "0: bf_val_0,1: bf_val_1,2: checksum32,?..."
newline
bitfld.long 0x00 1.--2. "SW_ENC_HASH_OFFSET,hash offset (byte offset of processed hashdata)" "0,1,2,3"
newline
bitfld.long 0x00 0. "SW_ENC_OSD_ALPHABLEND_ENABLE,enable OSD Alpha Blending" "0: bf_val_0,1: bf_val_1"
group.long 0x320++0x03
line.long 0x00 "swreg200,Hash Code Value"
hexmask.long 0x00 0.--31. 1. "SW_ENC_HASH_VAL,hash value of frame data"
group.long 0x324++0x03
line.long 0x00 "swreg201,Background SKIP Control 0"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_MEAN_THR0,A mean value threshold of out circle used for foreground decision"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_MEAN_THR1,A mean value threshold of second circle for foreground decision"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_MEAN_THR2,A mean value threshold of third circle"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_MEAN_THR3,A mean value threshold of the smallest circle"
group.long 0x32C++0x03
line.long 0x00 "swreg203,Background SKIP Control 2"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_LUM_DC_SUM_THR,A threshold value of DC for Y (for H.264)"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_CB_DC_SUM_THR,A threshold value of DC for U (for H.264)"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_CR_DC_SUM_THR,A threshold value of DC for V (for H.264)"
group.long 0x340++0x03
line.long 0x00 "swreg208,Background SKIP Control 7"
bitfld.long 0x00 26.--31. "SW_ENC_SMART_QP,A luma QP value for skip decision (for H.264)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 14.--19. "SW_ENC_FOREGROUND_PIXEL_THX,Foreground threshold number of pixel (0 ~ 63) used for foreground decision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "SW_ENC_ENABLE_SMART,enable smart featrue" "0,1"
newline
hexmask.long.word 0x00 4.--12. 1. "SW_ENC_IPCM1_LEFT,IPCM1 Area Left"
newline
bitfld.long 0x00 3. "SW_ENC_SKIP_MAP_ENABLE,enable skip map mode" "0,1"
group.long 0x344++0x03
line.long 0x00 "swreg209,IPCM Control 0"
hexmask.long.word 0x00 23.--31. 1. "SW_ENC_IPCM1_RIGHT,IPCM1 Area Right"
newline
hexmask.long.word 0x00 14.--22. 1. "SW_ENC_IPCM1_TOP,IPCM1 Area Top"
newline
hexmask.long.word 0x00 5.--13. 1. "SW_ENC_IPCM1_BOTTOM,IPCM1 Area Bottom"
newline
bitfld.long 0x00 4. "SW_ENC_PCM_FILTER_DISABLE,disable deblock filter for IPCM" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_IPCM_MAP_ENABLE,enable pcm map mode" "0,1"
group.long 0x348++0x03
line.long 0x00 "swreg210,IPCM Control 1"
hexmask.long.word 0x00 3.--11. 1. "SW_ENC_IPCM2_LEFT,IPCM2 Area Left"
group.long 0x34C++0x03
line.long 0x00 "swreg211,IPCM Control 2"
hexmask.long.word 0x00 3.--11. 1. "SW_ENC_IPCM2_RIGHT,IPCM2 Area Right"
group.long 0x350++0x03
line.long 0x00 "swreg212,IPCM Control 3"
hexmask.long.word 0x00 3.--11. 1. "SW_ENC_IPCM2_TOP,IPCM2 Area Top"
group.long 0x354++0x03
line.long 0x00 "swreg213,IPCM Control 4"
hexmask.long.word 0x00 5.--13. 1. "SW_ENC_IPCM2_BOTTOM,IPCM2 Area Bottom"
rgroup.long 0x358++0x03
line.long 0x00 "swreg214,HW synthesis config register 2 read-only"
bitfld.long 0x00 31. "SW_ENC_HWLJPEGSUPPORT,Lossless JPEG supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 30. "SW_ENC_HWABSQPSUPPORT,Absolute QP in ROI/ROI map supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 26.--28. "SW_ENC_HWROIMAPVERSION,ROI map buffer format version" "0: 4 bit per pixel,1: 8 bit per pixel,?..."
newline
hexmask.long.word 0x00 13.--25. 1. "SW_ENC_HWMAXVIDEOWIDTHH264,Maximum video width supported by HW for H264 encoding (unit 8 pixels)"
rgroup.long 0x35C++0x03
line.long 0x00 "swreg215,AXI Information 0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALARLEN,[AXI] Accumulated ARLEN+1"
rgroup.long 0x360++0x03
line.long 0x00 "swreg216,AXI Information 1"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALR,[AXI] RVALID & RREADY"
rgroup.long 0x364++0x03
line.long 0x00 "swreg217,AXI Information 2"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALAR,[AXI] ARVALID & ARREADY"
rgroup.long 0x368++0x03
line.long 0x00 "swreg218,AXI Information 3"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALRLAST,[AXI] RVALID & RREADY & RLAST"
rgroup.long 0x36C++0x03
line.long 0x00 "swreg219,AXI Information 4"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALAWLEN,[AXI] Accumulated AWLEN+1"
rgroup.long 0x370++0x03
line.long 0x00 "swreg220,AXI Information 5"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALW,[AXI] WVALID & WREADY"
rgroup.long 0x374++0x03
line.long 0x00 "swreg221,AXI Information 6"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALAW,[AXI] AWVALID & AWREADY"
rgroup.long 0x378++0x03
line.long 0x00 "swreg222,AXI Information 7"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALWLAST,[AXI] WVALID & WREADY & WLAST"
rgroup.long 0x37C++0x03
line.long 0x00 "swreg223,AXI Information 8"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALB,[AXI] BVALID & BREADY"
group.long 0x380++0x03
line.long 0x00 "swreg224,control register 4"
bitfld.long 0x00 31. "SW_ENC_CHROMA_CONST_EN,Force Chroma to be a constant pixel or not" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 21. "SW_ENC_SSIM_EN,Enable SSIM calculation" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 20. "SW_ENC_SKIPFRAME_EN,Force frame encode as SKIPFRAME" "0: bf_val_0,1: bf_val_1"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_ENC_CR_CONST_PIXEL,The constant pixel of CR if sw_enc_chroma_const_en=1"
newline
hexmask.long.word 0x00 0.--9. 1. "SW_ENC_CB_CONST_PIXEL,The constant pixel of CB if sw_enc_chroma_const_en=1"
group.long 0x384++0x03
line.long 0x00 "swreg225,Tile Control"
bitfld.long 0x00 13. "SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE,roi map cu ctrl index enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 12. "SW_ENC_ROIMAP_CUCTRL_ENABLE,roi map cu ctrl enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 9.--11. "SW_ENC_ROIMAP_CUCTRL_VER,roi map cu ctrl info version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--8. "SW_ENC_ROIMAP_QPDELTA_VER,roi map qp delta info version" "0,1,2,3,4,5,6,7"
rgroup.long 0x388++0x03
line.long 0x00 "swreg226,HW synthesis config register 3 read-only"
bitfld.long 0x00 31. "SW_ENC_HWSSIMSUPPORT,SSIM calculation supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 30. "SW_ENC_HWP010REFSUPPORT,Reference buffer format for 10-bit encoding" "0: normal format,1: P010 tile raster format"
newline
bitfld.long 0x00 27.--29. "SW_ENC_HWCUINFORVERSION,Version of the output CU information format" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21.--26. "SW_ENC_ME_VERT_SEARCHRANGE_HEVC,ME vertical search range in 8 pixel unit for HEVC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15.--20. "SW_ENC_ME_VERT_SEARCHRANGE_H264,ME vertical search range in 8 pixel unit for H264" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--14. "SW_ENC_HWCTBRCVERSION,CTB Rate Control Version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "SW_ENC_HWJPEG422SUPPORT,Jpeg422 supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 10. "SW_ENC_HWGMVSUPPORT,Global MV supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 9. "SW_ENC_HWROI8SUPPORT,support 8 ROIs" "0,1"
newline
bitfld.long 0x00 7.--8. "SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE,ME4N horizontal search range in 64 pixel unit" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 6. "SW_ENC_HWRDOQSUPPORT,RDOQ supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 5. "SW_ENC_HWMULTIPASSSUPPORT,Multipass Encoding supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 4. "SW_ENC_HWINLOOPDSRATIO,in-loop ds ratio supported by HW" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 3. "SW_ENC_HWSTREAMBUFCHAIN,Stream Buffer Chain supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 2. "SW_ENC_HWSTREAMSEGMENTSUPPORT,Stream segment supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 1. "SW_ENC_HWIFRAMEONLY,Only support I frame" "0: support I/P/B frame,1: only support I frame"
group.long 0x3AC++0x03
line.long 0x00 "swreg235,RPS encoding control 0"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_RPS_DELTA_POC_0,delta poc of pic0 in current rps"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_RPS_DELTA_POC_1,delta poc of pic1 in current rps"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_RPS_DELTA_POC_2,delta poc of pic2 in current rps"
newline
bitfld.long 0x00 1. "SW_ENC_RPS_USED_BY_CUR_0,pic0 in current rps is used for reference by current slice" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_RPS_USED_BY_CUR_1,pic1 in current rps is used for reference by current slice" "0,1"
group.long 0x3B0++0x03
line.long 0x00 "swreg236,RPS encoding control 1"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_RPS_DELTA_POC_3,delta poc of pic3 in current rps"
newline
bitfld.long 0x00 21. "SW_ENC_RPS_USED_BY_CUR_2,pic2 in current rps is used for reference by current slice" "0,1"
newline
bitfld.long 0x00 20. "SW_ENC_RPS_USED_BY_CUR_3,pic3 in current rps is used for reference by current slice" "0,1"
newline
bitfld.long 0x00 17.--19. "SW_ENC_RPS_NEG_PIC_NUM,number of negative pictures in current rps" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "SW_ENC_RPS_POS_PIC_NUM,number of positive pictures in current rps" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG,short term rps for current slice is encoded in sps" "0,1"
newline
bitfld.long 0x00 12. "SW_ENC_P010_REF_ENABLE,Enable/Disable P010 Reference format" "0: not supported,1: supported"
group.long 0x3B4++0x03
line.long 0x00 "swreg237,Stride Control"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_REF_CH_STRIDE,Chroma stride of reference frame"
newline
bitfld.long 0x00 11. "SW_ENC_DUMMYREADEN,enable dummy read when frame height not align to 64 or other possible condition" "0,1"
group.long 0x3B8++0x03
line.long 0x00 "swreg238,Dummy"
hexmask.long 0x00 0.--31. 1. "SW_ENC_DUMMYREADADDR,Dummy read address"
group.long 0x3BC++0x03
line.long 0x00 "swreg239,Base Address LSB of CTB MADs of current frame"
hexmask.long 0x00 0.--31. 1. "SW_ENC_CURRENT_CTB_MAD_BASE,Base Address LSB of CTB MADs of current frame used for CTB RC"
group.long 0x3C4++0x03
line.long 0x00 "swreg241,Base Address LSB of CTB MADs of previous frame"
hexmask.long 0x00 0.--31. 1. "SW_ENC_PREVIOUS_CTB_MAD_BASE,Base Address LSB of CTB MADs of previous frame used for CTB RC"
group.long 0x3CC++0x03
line.long 0x00 "swreg243,CTB RC Control 0"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_CTB_RC_MODEL_PARAM0,Parameter0 of CTB RC model"
group.long 0x3D0++0x03
line.long 0x00 "swreg244,CTB RC Control 1"
hexmask.long.tbyte 0x00 10.--31. 1. "SW_ENC_CTB_RC_MODEL_PARAM1,Parameter1 of CTB RC model"
newline
hexmask.long.byte 0x00 3.--9. 1. "SW_ENC_ROI3_QP_VALUE,ROI3 qp value"
newline
bitfld.long 0x00 2. "SW_ENC_ROI3_QP_TYPE,ROI3 qp type" "0: bf_val_0,1: Absolute value"
group.long 0x3D4++0x03
line.long 0x00 "swreg245,CTB RC Control 2"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_CTB_RC_MODEL_PARAM_MIN,Minimum parameter value of CTB RC model"
newline
hexmask.long.word 0x00 2.--17. 1. "SW_ENC_CTB_RC_ROW_FACTOR,Reciprocal of ctb per row"
group.long 0x3D8++0x03
line.long 0x00 "swreg246,CTB RC Control 3"
hexmask.long.tbyte 0x00 14.--31. 1. "SW_ENC_CTB_RC_QP_STEP,Maximum QP step per CTB for purpose of rate control"
newline
hexmask.long.byte 0x00 6.--13. 1. "SW_ENC_AXI_WRITE_OUTSTANDING_NUM,AXI outstanding number of write operation"
newline
bitfld.long 0x00 3.--5. "SW_ENC_CTB_RC_DELAY,Feedback delay of information for CTB RC" "0,1,2,3,4,5,6,7"
group.long 0x3DC++0x03
line.long 0x00 "swreg247,CTB RC Control 4"
hexmask.long 0x00 6.--31. 1. "SW_ENC_PREV_PIC_LUM_MAD,Luma MAD of the predict picture"
newline
bitfld.long 0x00 1. "SW_ENC_CTB_RC_PREV_MAD_VALID,Prev luma MADs are valid or not for ctb rc" "0: bf_val_0,1: bf_val_1"
group.long 0x3E0++0x03
line.long 0x00 "swreg248,CTB RC Control 5"
hexmask.long.tbyte 0x00 8.--31. 1. "SW_ENC_CTB_QP_SUM_FOR_RC,Sum of CTB QP used for rate control"
newline
hexmask.long.byte 0x00 1.--7. 1. "SW_ENC_ROI4_QP_VALUE,ROI4 qp value"
newline
bitfld.long 0x00 0. "SW_ENC_ROI4_QP_TYPE,ROI4 qp type" "0: bf_val_0,1: Absolute value"
group.long 0x3E4++0x03
line.long 0x00 "swreg249,register extension for 8K width"
bitfld.long 0x00 30.--31. "SW_ENC_ENCODED_CTB_NUMBER_MSB2,MB count output" "0,1,2,3"
newline
bitfld.long 0x00 29. "SW_ENC_NUM_SLICES_READY_MSB2,HEVC amount of completed slices" "0,1"
newline
bitfld.long 0x00 28. "SW_ENC_SLICE_SIZE_MSB2,slice size in ctu row" "0,1"
newline
bitfld.long 0x00 26.--27. "SW_ENC_CIR_START_MSB2,cir start" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "SW_ENC_CIR_INTERVAL_MSB2,Cyclic Intra Refresh" "0,1,2,3"
newline
bitfld.long 0x00 23. "SW_ENC_INTRA_AREA_LEFT_MSB2,intra Area Left" "0,1"
newline
bitfld.long 0x00 22. "SW_ENC_INTRA_AREA_RIGHT_MSB2,intra Area Right" "0,1"
newline
bitfld.long 0x00 21. "SW_ENC_INTRA_AREA_TOP_MSB2,intra Area Top" "0,1"
newline
bitfld.long 0x00 20. "SW_ENC_INTRA_AREA_BOTTOM_MSB2,intra Area Bottom" "0,1"
newline
bitfld.long 0x00 19. "SW_ENC_ROI1_LEFT_MSB2,ROI1 Area Left" "0,1"
newline
bitfld.long 0x00 18. "SW_ENC_ROI1_RIGHT_MSB2,ROI1 Area Right" "0,1"
newline
bitfld.long 0x00 17. "SW_ENC_ROI1_TOP_MSB2,ROI1 Area Top" "0,1"
newline
bitfld.long 0x00 16. "SW_ENC_ROI1_BOTTOM_MSB2,ROI1 Area Bottom" "0,1"
newline
bitfld.long 0x00 15. "SW_ENC_ROI2_LEFT_MSB2,ROI2 Area Left" "0,1"
newline
bitfld.long 0x00 14. "SW_ENC_ROI2_RIGHT_MSB2,ROI2 Area Right" "0,1"
newline
bitfld.long 0x00 13. "SW_ENC_ROI2_TOP_MSB2,ROI2 Area Top" "0,1"
newline
bitfld.long 0x00 12. "SW_ENC_ROI2_BOTTOM_MSB2,ROI2 Area Bottom" "0,1"
newline
bitfld.long 0x00 11. "SW_ENC_PIC_WIDTH_MSB2,Encoded width" "0,1"
newline
bitfld.long 0x00 10. "SW_ENC_IPCM1_LEFT_MSB,IPCM1 Area Left bit[9]" "0,1"
newline
bitfld.long 0x00 9. "SW_ENC_IPCM1_RIGHT_MSB,IPCM1 Area Right bit[9]" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_IPCM1_TOP_MSB,IPCM1 Area Top bit[9]" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_IPCM1_BOTTOM_MSB,IPCM2 Area Bottom bit[9]" "0,1"
newline
bitfld.long 0x00 6. "SW_ENC_IPCM2_LEFT_MSB,IPCM2 Area Left bit[9]" "0,1"
newline
bitfld.long 0x00 5. "SW_ENC_IPCM2_RIGHT_MSB,IPCM2 Area Right bit[9]" "0,1"
newline
bitfld.long 0x00 4. "SW_ENC_IPCM2_TOP_MSB,IPCM2 Area Top bit[9]" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_IPCM2_BOTTOM_MSB,IPCM1 Area Bottom bit[9]" "0,1"
group.long 0x3E8++0x03
line.long 0x00 "swreg250,Global MV Control 0"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_GLOBAL_HORIZONTAL_MV_L0,Global horizontal MV for LIST0 in integer pixel"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_GLOBAL_VERTICAL_MV_L0,Global vertical MV for LIST0 in integer pixel"
group.long 0x3EC++0x03
line.long 0x00 "swreg251,Global MV Control 1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_GLOBAL_HORIZONTAL_MV_L1,Global horizontal MV for LIST1 in integer pixel"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_GLOBAL_VERTICAL_MV_L1,Global vertical MV for LIST1 in integer pixel"
group.long 0x3F0++0x03
line.long 0x00 "swreg252,ROI3 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI3_LEFT,ROI3 Area Left"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI3_TOP,ROI3 Area Top"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI3_RIGHT,ROI3 Area Right"
group.long 0x3F4++0x03
line.long 0x00 "swreg253,ROI3&4 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI3_BOTTOM,ROI3 Area Bottom"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI4_LEFT,ROI4 Area Left"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI4_TOP,ROI4 Area Top"
group.long 0x3F8++0x03
line.long 0x00 "swreg254,ROI4&5 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI4_RIGHT,ROI4 Area Right"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI4_BOTTOM,ROI4 Area Bottom"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI5_LEFT,ROI5 Area Left"
group.long 0x3FC++0x03
line.long 0x00 "swreg255,ROI5 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI5_TOP,ROI5 Area Top"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI5_RIGHT,ROI5 Area Right"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI5_BOTTOM,ROI5 Area Bottom"
group.long 0x400++0x03
line.long 0x00 "swreg256,ROI6 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI6_LEFT,ROI6 Area Left"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI6_TOP,ROI6 Area Top"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI6_RIGHT,ROI6 Area Right"
group.long 0x404++0x03
line.long 0x00 "swreg257,ROI6&7 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI6_BOTTOM,ROI6 Area Bottom"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI7_LEFT,ROI7 Area Left"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI7_TOP,ROI7 Area Top"
group.long 0x408++0x03
line.long 0x00 "swreg258,ROI7&8 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI7_RIGHT,ROI7 Area Right"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI7_BOTTOM,ROI7 Area Bottom"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI8_LEFT,ROI8 Area Left"
group.long 0x40C++0x03
line.long 0x00 "swreg259,ROI8 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI8_TOP,ROI8 Area Top"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI8_RIGHT,ROI8 Area Right"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI8_BOTTOM,ROI8 Area Bottom"
newline
bitfld.long 0x00 1. "SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE,Decrease max tu size in current frame.[0]" "0: max tu size 32,1: max tu size 16"
group.long 0x410++0x03
line.long 0x00 "swreg260,ROI qp"
hexmask.long.byte 0x00 25.--31. 1. "SW_ENC_ROI8_QP_VALUE,ROI8 qp value"
newline
bitfld.long 0x00 24. "SW_ENC_ROI8_QP_TYPE,ROI8 qp type" "0: bf_val_0,1: Absolute value"
newline
hexmask.long.byte 0x00 17.--23. 1. "SW_ENC_ROI7_QP_VALUE,ROI7 qp value"
newline
bitfld.long 0x00 16. "SW_ENC_ROI7_QP_TYPE,ROI7 qp type" "0: bf_val_0,1: Absolute value"
newline
hexmask.long.byte 0x00 9.--15. 1. "SW_ENC_ROI6_QP_VALUE,ROI6 qp value"
newline
bitfld.long 0x00 8. "SW_ENC_ROI6_QP_TYPE,ROI6 qp type" "0: bf_val_0,1: Absolute value"
newline
hexmask.long.byte 0x00 1.--7. 1. "SW_ENC_ROI5_QP_VALUE,ROI5 qp value"
newline
bitfld.long 0x00 0. "SW_ENC_ROI5_QP_TYPE,ROI5 qp type" "0: bf_val_0,1: Absolute value"
group.long 0x414++0x03
line.long 0x00 "swreg261,Stride Control"
bitfld.long 0x00 13.--17. "SW_ENC_RGBLUMAOFFSET,RGB to YUV conversion luma offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12. "SW_ENC_PRP_IN_LOOP_DS_RATIO,down-scaling ratio of In-loop downscaler in prp" "0,1"
newline
hexmask.long.byte 0x00 4.--11. 1. "SW_ENC_AXI_READ_OUTSTANDING_NUM,AXI outstanding number of read operation"
newline
bitfld.long 0x00 3. "SW_ENC_MULTI_CORE_EN,Enable multi-core encoding mode" "0,1"
newline
bitfld.long 0x00 2. "SW_ENC_RDOQ_ENABLE,Enable RDOQ" "0,1"
newline
bitfld.long 0x00 1. "SW_ENC_PASS1_SKIP_CABAC,CABAC SKIP for pass one" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_MOTION_SCORE_ENABLE,Enable motion score computing for 2-pass Agop" "0,1"
group.long 0x424++0x03
line.long 0x00 "swreg265,Multicore sync ctrl"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_REF_READY_THRESHOLD,EXTRA_LINES_NUM bigger vertical search window ready"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_DDR_POLLING_INTERVAL,Interval cycles for HW reading the DDR RECON_PIXELLINES_READY when value not bigger than search window"
group.long 0x428++0x03
line.long 0x00 "swreg266,Multicore sync address L0 LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L0_ADDR,For multicore sync"
group.long 0x42C++0x03
line.long 0x00 "swreg267,Multicore sync address L0 MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB,For multicore sync"
group.long 0x430++0x03
line.long 0x00 "swreg268,Multicore sync address L1 LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L1_ADDR,For multicore sync"
group.long 0x434++0x03
line.long 0x00 "swreg269,Multicore sync address L1 MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB,For multicore sync"
group.long 0x438++0x03
line.long 0x00 "swreg270,Multicore sync address recon LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_REC_ADDR,For multicore sync"
group.long 0x43C++0x03
line.long 0x00 "swreg271,Multicore sync address recon MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB,For multicore sync"
group.long 0x440++0x03
line.long 0x00 "swreg272,Programmable AXI urgent sideband signals"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_RD_URGENT_ENABLE_THRESHOLD,axi_rd_urgent=1 when total number of rd cmds is bigger or equal to threshold.255=disable"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_RD_URGENT_DISABLE_THRESHOLD,axi_rd_urgent=0 when total number of rd cmds is smaller than threshold.255=disable"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_WR_URGENT_ENABLE_THRESHOLD,axi_wr_urgent=1 when total number of wr cmds is bigger or equal to threshold.255=disable"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_WR_URGENT_DISABLE_THRESHOLD,axi_wr_urgent=0 when total number of wr cmds is smaller than threshold.255=disable"
group.long 0x444++0x03
line.long 0x00 "swreg273,roimap cu ctrl index address LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR,Address LSB of roi map cu ctrlindex buffer"
group.long 0x448++0x03
line.long 0x00 "swreg274,roimap cu ctrl index address MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB,Address MSB of roi map cu ctrl index buffer"
group.long 0x44C++0x03
line.long 0x00 "swreg275,roimap cu ctrl address LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_ADDR,Address LSB of roi map cu ctrl buffer"
group.long 0x450++0x03
line.long 0x00 "swreg276,roimap cu ctrl address MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_ADDR_MSB,Address MSB of roi map cu ctrl buffer"
group.long 0x454++0x03
line.long 0x00 "swreg277,poc type/bits setting"
bitfld.long 0x00 27.--31. "SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB,number of bits in pic_order_cnt_lsb" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 22.--26. "SW_ENC_LOG2_MAX_FRAME_NUM,number of bits in frameNum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 20.--21. "SW_ENC_PIC_ORDER_CNT_TYPE,poc type" "0,1,2,3"
newline
hexmask.long.word 0x00 5.--19. 1. "SW_ENC_SYN_AMOUNT_PER_LOOPBACK,Handshake sync amount for every loopback"
group.long 0x458++0x03
line.long 0x00 "swreg278,stream output buffer1 address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BUF1_BASE,stream output buffer1 base address"
group.long 0x460++0x03
line.long 0x00 "swreg280,stream output buffer1 limit size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT,Stream buffer1 limit size (bytes)"
group.long 0x464++0x03
line.long 0x00 "swreg281,poc type/bits setting"
bitfld.long 0x00 31. "SW_ENC_STRM_SEGMENT_SW_SYNC_EN,Stream segment software handshake enable" "0,1"
newline
bitfld.long 0x00 30. "SW_ENC_STRM_SEGMENT_EN,Stream segment function enable" "0,1"
newline
hexmask.long.word 0x00 20.--29. 1. "SW_ENC_STRM_SEGMENT_RD_PTR,the number of segments that have been read out from output buffer"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_ENC_STRM_SEGMENT_WR_PTR,the number of segments that have been filled into the output buffer"
newline
bitfld.long 0x00 4.--9. "SW_NUM_CTB_ROWS_PER_SYNC_MSB,Number MSB of CTB rows for every HW sync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x47C++0x03
line.long 0x00 "swreg287,HW synthesis config register 4 read-only"
bitfld.long 0x00 31. "SW_ENC_HWVIDEOHEIGHTEXT,Maximum allowed video height extended from 8192 to 8640" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 30. "SW_ENC_HWCSCEXTENSIONSUPPORT,RGB to YUV conversion extension" "0: not supported,1: supported"
newline
bitfld.long 0x00 29. "SW_ENC_HWSCALER420SUPPORT,out-loop scaler output YUV420SP" "0: not supported,1: supported"
group.long 0x484++0x03
line.long 0x00 "swreg289,Pre-processor color conversion parameters1"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFG,RGB to YUV conversion coefficient G"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_RGBCOEFFH,RGB to YUV conversion coefficient H"
tree.end
tree "VPU_HEVC (DMA controller)"
base ad:0x38320000
group.long 0x04++0x03
line.long 0x00 "swreg1,Interrupt register encoder"
bitfld.long 0x00 12. "SW_ENC_STRM_SEGMENT_RDY_INT,Output stream segment IRQ" "0,1"
newline
bitfld.long 0x00 11. "SW_ENC_TIMEOUT_INT,enable timeout interrupt when 1" "0,1"
newline
bitfld.long 0x00 9. "SW_ENC_IRQ_FUSE_ERROR,Interrupt Interrupt status bit encoder" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_SLICE_RDY_STATUS,Interrupt status bit encoder" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_IRQ_LINE_BUFFER,Interrupt status bit encoder linebuffer empty" "0,1"
newline
bitfld.long 0x00 6. "SW_ENC_TIMEOUT,Interrupt status bit encoder timeout" "0,1"
newline
bitfld.long 0x00 5. "SW_ENC_BUFFER_FULL,IRQ buffer full status bit" "0,1"
newline
bitfld.long 0x00 4. "SW_ENC_SW_RESET,IRQ SW reset status bit" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_BUS_ERROR_STATUS,Interrupt status bit bus" "0,1"
newline
bitfld.long 0x00 2. "SW_ENC_FRAME_RDY_STATUS,Interrupt status bit encoder" "0,1"
newline
bitfld.long 0x00 1. "SW_ENC_IRQ_DIS,Encoder IRQ disable" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_IRQ,Encoder IRQ" "0,1"
group.long 0x08++0x03
line.long 0x00 "swreg2,Data configuration register0"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_AXI_WRITE_ID,AXI Write ID"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_AXI_READ_ID,AXI Read ID"
newline
bitfld.long 0x00 12.--15. "SW_ENC_STRM_SWAP,byte swap config for output stream data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "SW_ENC_PIC_SWAP,Byte swap configuration for picture data (encoder input)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP,Byte swap configuration for qp delta of ROI map" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SW_ENC_CTB_RC_MEM_OUT_SWAP,Byte swap configuration for ctb rate control memory out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "swreg3,Data configuration register1"
bitfld.long 0x00 31. "SW_ENC_CLOCK_GATE_ENCODER_E,ASIC encoder clock gating control" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 30. "SW_ENC_CLOCK_GATE_ENCODER_H265_E,ASIC encoder clock gating control for h265" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 29. "SW_ENC_CLOCK_GATE_ENCODER_H264_E,ASIC encoder clock gating control for h264" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 28. "SW_ENC_CLOCK_GATE_INTER_E,ASIC inter clock gating control" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 27. "SW_ENC_CLOCK_GATE_INTER_H265_E,ASIC inter clock gating control for h265" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 26. "SW_ENC_CLOCK_GATE_INTER_H264_E,ASIC inter clock gating control for h264" "0: clock always on,1: hardware clock gating control"
newline
bitfld.long 0x00 25. "SW_ENC_AXI_WR_ID_E,axi write enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 24. "SW_ENC_AXI_RD_ID_E,axi read enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 20.--23. "SW_ENC_CU_INFO_MEM_OUT_SWAP,Byte swap configuration for cu infomation memory out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SW_ENC_SLICE_INT,enable slice interrupt when 1" "0,1"
newline
bitfld.long 0x00 2. "SW_ENC_LINE_BUFFER_INT,enable line buffer interrupt when 1" "0,1"
newline
bitfld.long 0x00 1. "SW_ENC_STRM_SEGMENT_INT,enable stream segment interrupt when 1" "0,1"
group.long 0x10++0x03
line.long 0x00 "swreg4,control register 0"
bitfld.long 0x00 29.--31. "SW_ENC_MODE,Encoding mode" "?,1: bf_val_0,2: bf_val_1,?,4: bf_val_2,?..."
newline
bitfld.long 0x00 25.--26. "SW_ENC_MIN_CB_SIZE,min cb size (we only support 8x8)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 23.--24. "SW_ENC_MAX_CB_SIZE,max cb size (we only support 64x64)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 21.--22. "SW_ENC_MIN_TRB_SIZE,min tr block size (we only support 4x4)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 19.--20. "SW_ENC_MAX_TRB_SIZE,max tr block size (we only support 16x16)" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 18. "SW_ENC_OUTPUT_STRM_MODE,output stream mode" "0: byte stream,1: Nal stream"
newline
bitfld.long 0x00 13.--17. "SW_ENC_CHROMA_QP_OFFSET,chroma qp offset[-12~12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12. "SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG,HEVC IntraTU32x32 strong intra smoothing filter enable flag" "0,1"
newline
bitfld.long 0x00 11. "SW_BW_LINEBUF_DISABLE,BW line buffer disable" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_SCALING_LIST_ENABLED_FLAG,scaling_list_enabled_flag" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_ACTIVE_OVERRIDE_FLAG,active override flag" "0,1"
newline
bitfld.long 0x00 6. "SW_ENC_SAO_ENABLE,SAO enable" "0,1"
newline
bitfld.long 0x00 3.--5. "SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA,max transform hierarchy depth of intra" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER,max transform hierarchy depth of inter" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "swreg5,control register 1"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_PIC_WIDTH,Encoded width"
newline
hexmask.long.word 0x00 11.--21. 1. "SW_ENC_PIC_HEIGHT,Encoded height"
newline
bitfld.long 0x00 9. "SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG,deblocking filter override enable flag" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 8. "SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG,slice deblocking filter override flag" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 6. "SW_ENC_OUTPUT_CU_INFO_ENABLED,Enable dumping cu information to external memory" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 1.--2. "SW_ENC_FRAME_CODING_TYPE,Encoded picture type" "0,1,2,3"
newline
bitfld.long 0x00 0. "SW_ENC_E,encoder enable" "0,1"
group.long 0x1C++0x03
line.long 0x00 "swreg7,control register 3"
bitfld.long 0x00 26.--31. "SW_ENC_PIC_INIT_QP,picture header qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 25. "SW_ENC_CABAC_INIT_FLAG,cabac init flag" "0,1"
newline
hexmask.long.byte 0x00 17.--24. 1. "SW_ENC_NUM_SLICES_READY,HEVC amount of completed slices"
newline
bitfld.long 0x00 14.--15. "SW_ENC_DIFF_CU_QP_DELTA_DEPTH,difference of cu qp delta depth" "0,1,2,3"
newline
bitfld.long 0x00 8.--13. "SW_ENC_PIC_QP,qp of current picture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4.--7. "SW_ENC_ROI1_DELTA_QP,ROI1 delta qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SW_ENC_ROI2_DELTA_QP,ROI2 delta qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "swreg8,stream output buffer0 address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BASE,stream output buffer0 base address"
group.long 0x24++0x03
line.long 0x00 "swreg9,stream output buffer0 limit size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BUFFER_LIMIT,Stream buffer0 limit / Output stream size (bytes)"
group.long 0x28++0x03
line.long 0x00 "swreg10,sizeTblBase"
hexmask.long 0x00 0.--31. 1. "SW_ENC_SIZE_TBL_BASE,sizeTblBase"
group.long 0x2C++0x03
line.long 0x00 "swreg11,encoded Picture order count"
hexmask.long 0x00 0.--31. 1. "SW_ENC_POC,encoded Picture order count"
group.long 0x30++0x03
line.long 0x00 "swreg12,input lum base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_INPUT_Y_BASE,input image lum base address"
group.long 0x34++0x03
line.long 0x00 "swreg13,input cb base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_INPUT_CB_BASE,input image cb base address"
group.long 0x38++0x03
line.long 0x00 "swreg14,input cr base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_INPUT_CR_BASE,input image cr base address"
group.long 0x3C++0x03
line.long 0x00 "swreg15,recon image luma base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_Y_BASE,recon image lum base address"
group.long 0x40++0x03
line.long 0x00 "swreg16,recon image chroma base address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_CHROMA_BASE,recon image chroma base address"
group.long 0x48++0x03
line.long 0x00 "swreg18,reference picture reconstructed list0 luma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L0_Y0,reference picture reconstructed list0 luma0"
group.long 0x4C++0x03
line.long 0x00 "swreg19,reference picture reconstructed list0 chroma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L0_CHROMA0,reference picture reconstructed list0 chroma0"
group.long 0x58++0x03
line.long 0x00 "swreg22,Cyclic Intra"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_CIR_START,cir start"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_CIR_INTERVAL,Cyclic Intra Refresh"
newline
bitfld.long 0x00 0.--3. "SW_ENC_RCROI_ENABLE,bit3:RC enable bit2:Quatily adjustment enable bit1:roi map enable bit0:roi area enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "swreg23,intra Area"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_INTRA_AREA_LEFT,intra Area Left"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_INTRA_AREA_RIGHT,intra Area Right"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_INTRA_AREA_TOP,intra Area Top"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_INTRA_AREA_BOTTOM,intra Area Bottom"
group.long 0x60++0x03
line.long 0x00 "swreg24,ROI1 Area"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_ROI1_LEFT,ROI1 Area Left"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_ROI1_RIGHT,ROI1 Area Right"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_ROI1_TOP,ROI1 Area Top"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_ROI1_BOTTOM,ROI1 Area Bottom"
group.long 0x64++0x03
line.long 0x00 "swreg25,ROI2 Area"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_ROI2_LEFT,ROI2 Area Left"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_ROI2_RIGHT,ROI2 Area Right"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_ROI2_TOP,ROI2 Area Top"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_ROI2_BOTTOM,ROI2 Area Bottom"
group.long 0x68++0x03
line.long 0x00 "swreg26_H2V2,intra size factors"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_INTRA_SIZE_FACTOR_0,intra size factor 0"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_INTRA_SIZE_FACTOR_1,intra size factor 1"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_INTRA_SIZE_FACTOR_2,intra size factor 2"
group.long 0x6C++0x03
line.long 0x00 "swreg27_H2V2,intra mode factors"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_INTRA_SIZE_FACTOR_3,intra size factor 3"
newline
bitfld.long 0x00 17.--21. "SW_ENC_INTRA_MODE_FACTOR_0,intra mode factor 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 11.--16. "SW_ENC_INTRA_MODE_FACTOR_1,intra mode factor 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 4.--10. 1. "SW_ENC_INTRA_MODE_FACTOR_2,intra mode factor 2"
group.long 0x70++0x03
line.long 0x00 "swreg28_H2V5,inter me SATD lambda config 0"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT,lambda satd me 0"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT,lambda satd me 1"
group.long 0x74++0x03
line.long 0x00 "swreg29_H2V5,inter me SATD lambda config 1.For H2V5 or later version"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT,lambda satd me 2"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT,lambda satd me 3"
group.long 0x78++0x03
line.long 0x00 "swreg30_H2V5,inter me SATD lambda config 2"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT,lambda satd me 4"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT,lambda satd me 5"
group.long 0x7C++0x03
line.long 0x00 "swreg31_H2V5,inter me SATD lambda config 3"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT,lambda satd me 6"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT,lambda satd me 7"
group.long 0x80++0x03
line.long 0x00 "swreg32_H2V5,inter me SATD lambda config 4"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT,lambda satd me 8"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT,lambda satd me 9"
group.long 0x84++0x03
line.long 0x00 "swreg33_H2V5,inter me SATD lambda config 5"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT,lambda satd me 10"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT,lambda satd me 11"
group.long 0x88++0x03
line.long 0x00 "swreg34_H2V5,inter me SATD lambda config 6"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT,lambda satd me 12"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT,lambda satd me 13"
group.long 0x8C++0x03
line.long 0x00 "swreg35,inter prediction parameters1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_LAMDA_MOTION_SSE,lambda for motion SSE"
newline
bitfld.long 0x00 15.--17. "SW_ENC_BITS_EST_TU_SPLIT_PENALTY,bits estimation for tu split penalty" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 8.--14. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_8,bits estimation bias for intra cu 8"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_16,bits estimation bias for intra cu 16"
group.long 0x90++0x03
line.long 0x00 "swreg36,inter prediction parameters2"
hexmask.long.word 0x00 23.--31. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_32,bits estimation bias for intra cu 32"
newline
hexmask.long.word 0x00 13.--22. 1. "SW_ENC_BITS_EST_BIAS_INTRA_CU_64,bits estimation bias for intra cu 64"
newline
hexmask.long.byte 0x00 6.--12. 1. "SW_ENC_INTER_SKIP_BIAS,inter skip bias"
newline
bitfld.long 0x00 2.--5. "SW_ENC_BITS_EST_1N_CU_PENALTY,bits estimation 1N cu penalty" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--1. "SW_ENC_OUTPUT_BITWIDTH_CHROMA,chroma output bitwidth" "0: bf_val_0,1: bf_val_1,2: bf_val_2,?..."
group.long 0x94++0x03
line.long 0x00 "swreg37,SAO lambda parameter"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_LAMDA_SAO_CHROMA,lambda for SAO chroma"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_LAMDA_SAO_LUMA,lambda for SAO luma"
newline
bitfld.long 0x00 0.--3. "SW_ENC_CHROFFSET,Input chrominance offset (bytes) [0..15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x98++0x03
line.long 0x00 "swreg38,Pre-processor configuration"
bitfld.long 0x00 28.--31. "SW_ENC_INPUT_FORMAT,Input image format" "?,1: bf_val_0,2: bf_val_1,3: bf_val_2,4: bf_val_3,5: bf_val_4,6: bf_val_5,7: bf_val_6,8: RGB101010,9: bf_val_8,10: bf_val_9,11: PACKED10BITPLANAR,12: bf_val_11,13: bf_val_12,14: bf_val_13,?..."
newline
bitfld.long 0x00 26.--27. "SW_ENC_INPUT_ROTATION,Input image rotation" "0: disabled,1: 90 degrees right,2: 90 degrees left,3: 180 degree right"
newline
bitfld.long 0x00 24.--25. "SW_ENC_OUTPUT_BITWIDTH_LUM,luma output bitwidth" "0: bf_val_0,1: bf_val_1,2: bf_val_2,?..."
newline
bitfld.long 0x00 20.--23. "SW_ENC_LUMOFFSET,Input luminance offset (bytes) [0..15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 6.--19. 1. "SW_ENC_ROWLENGTH,Input luminance row length"
newline
bitfld.long 0x00 4.--5. "SW_ENC_XFILL,Overfill pixels on right edge of image div2 [0.1.2.3]" "0,1,2,3"
newline
bitfld.long 0x00 1.--3. "SW_ENC_YFILL,Overfill pixels on bottom edge of image" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SW_ENC_MIRROR,mirror or not" "0,1"
group.long 0x9C++0x03
line.long 0x00 "swreg39,Pre-processor color conversion parameters0"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFA,RGB to YUV conversion coefficient A"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_RGBCOEFFB,RGB to YUV conversion coefficient B"
group.long 0xA0++0x03
line.long 0x00 "swreg40,Pre-processor color conversion parameters1"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFC,RGB to YUV conversion coefficient C"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_RGBCOEFFE,RGB to YUV conversion coefficient D"
group.long 0xA4++0x03
line.long 0x00 "swreg41,Pre-processor color conversion parameters2"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFF,RGB to YUV conversion coefficient E"
newline
bitfld.long 0x00 11.--15. "SW_ENC_RMASKMSB,RGB R-component mask MSB bit position [0..31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "SW_ENC_GMASKMSB,RGB G-component mask MSB bit position [0..31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--5. "SW_ENC_BMASKMSB,RGB B-component mask MSB bit position [0..31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA8++0x03
line.long 0x00 "swreg42,Pre-processor Base address for down-scaled output"
hexmask.long 0x00 0.--31. 1. "SW_ENC_BASESCALEDOUTLUM,Base address for output of down-scaled encoder image in YUYV 4:2:2 format"
group.long 0xAC++0x03
line.long 0x00 "swreg43,Pre-processor down-scaled configuration0"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_SCALEDOUTWIDTH,Scaling width of down-scaled image"
newline
hexmask.long.word 0x00 3.--18. 1. "SW_ENC_SCALEDOUTWIDTHRATIO,Scaling ratio for width of down-scaled image"
newline
bitfld.long 0x00 2. "SW_ENC_SCALEDOUTWIDTHMSB,Scaling width of down-scaled image" "0,1"
newline
bitfld.long 0x00 0.--1. "SW_ENC_SCALE_MODE,Scaling mode" "0: disabled,1: scaling only,2: scale+encode,?..."
group.long 0xB0++0x03
line.long 0x00 "swreg44,Pre-processor down-scaled configuration1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_SCALEDOUTHEIGHT,Scaling height of down-scaled image"
newline
hexmask.long.word 0x00 2.--17. 1. "SW_ENC_SCALEDOUTHEIGHTRATIO,Scaling ratio for height of down-scaled image"
newline
bitfld.long 0x00 0.--1. "SW_ENC_INPUT_FORMAT_MSB,Input image format bit[5:4]" "0,1,2,3"
group.long 0xB4++0x03
line.long 0x00 "swreg45,Pre-processor down-scaled configuration2"
bitfld.long 0x00 28.--31. "SW_ENC_SCALEDOUT_SWAP,Byte swap configuration for scaledout data (scaledout)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 27. "SW_ENC_CHROMA_SWAP,Swap order of chroma bytes in semiplanar input format" "0,1"
newline
hexmask.long.word 0x00 14.--26. 1. "SW_ENC_ENCODED_CTB_NUMBER,MB count output"
newline
bitfld.long 0x00 12.--13. "SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN,skip left pixel column" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "SW_ENC_SCALEDSKIPTOPPIXELROW,skip top pixel row" "0,1,2,3"
newline
bitfld.long 0x00 9. "SW_ENC_VSCALE_WEIGHT_EN,vertical scale weight enable" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_SCALEDHORIZONTALCOPY,horizontal data copy directly" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_SCALEDVERTICALCOPY,vertical data copy directly" "0,1"
newline
bitfld.long 0x00 3.--6. "SW_ENC_NALUNITSIZE_SWAP,Byte swap configuration for Nal Unit size output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "SW_ENC_SCALEDOUT_FORMAT,out-loop scaler ouput format" "0,1"
group.long 0xB8++0x03
line.long 0x00 "swreg46,compressed coefficients base address for SAN module"
hexmask.long 0x00 0.--31. 1. "SW_ENC_COMPRESSEDCOEFF_BASE,Base address for compressed coefficients"
group.long 0xF0++0x03
line.long 0x00 "swreg60,Base address for recon luma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE,Base address for recon luma compress table LSB"
group.long 0xF8++0x03
line.long 0x00 "swreg62,Base address for recon Chroma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE,Base address for recon Chroma compress table LSB"
group.long 0x100++0x03
line.long 0x00 "swreg64,Base address for list 0 ref 0 luma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE,Base address for list 0 ref 0 luma compress table LSB"
group.long 0x108++0x03
line.long 0x00 "swreg66,Base address for list 0 ref 0 Chroma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE,Base address for list 0 ref 0 Chroma compress table LSB"
group.long 0x120++0x03
line.long 0x00 "swreg72,Base address for recon luma 4n base LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_RECON_LUMA_4N_BASE,Base address for recon luma 4n base LSB"
group.long 0x128++0x03
line.long 0x00 "swreg74,reference picture reconstructed list0 4n 0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L0_4N0_BASE,reference picture reconstructed list0 4n 0"
group.long 0x138++0x03
line.long 0x00 "swreg78_H2V5,inter me SATD lambda config 7"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT,lambda satd me 14"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT,lambda satd me 15"
group.long 0x13C++0x03
line.long 0x00 "swreg79_H2V5,inter me SSE lambda config 0"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT,inter me SSE lambda 0"
group.long 0x144++0x03
line.long 0x00 "swreg81,hardware configuation 0"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_MAX_BURST,for support AXI4.0 burst length is programmable Default value:0x20"
newline
bitfld.long 0x00 23. "SW_TIMEOUT_OVERRIDE_E,enable signal if timeout period is controlled by software Default value: 0x0" "0,1"
newline
hexmask.long.tbyte 0x00 0.--22. 1. "SW_TIMEOUT_CYCLES,timeout cycles number default value: 0x0"
rgroup.long 0x148++0x03
line.long 0x00 "swreg82,record hardware performance"
hexmask.long 0x00 0.--31. 1. "SW_ENC_HW_PERFORMANCE,record hardware performance(cycles) of current picture"
group.long 0x14C++0x03
line.long 0x00 "swreg83,reference picture reconstructed list1 luma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L1_Y0,reference picture reconstructed list1 luma0"
group.long 0x150++0x03
line.long 0x00 "swreg84,reference picture reconstructed list1 chroma0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L1_CHROMA0,reference picture reconstructed list1 chroma0"
group.long 0x16C++0x03
line.long 0x00 "swreg91,reference pictures list1 config"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_L1_DELTA_POC0,delta poc of list1 pic0"
newline
bitfld.long 0x00 21. "SW_ENC_L1_LONG_TERM_FLAG0,list1 pic0 is long term" "0,1"
newline
bitfld.long 0x00 20. "SW_ENC_L1_USED_BY_CURR_PIC0,list1 pic0 used by current" "0,1"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_ENC_L1_DELTA_POC1,delta poc of list1 pic1"
newline
bitfld.long 0x00 9. "SW_ENC_L1_LONG_TERM_FLAG1,list1 pic1 is long term" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_L1_USED_BY_CURR_PIC1,list1 pic1 used by current" "0,1"
newline
bitfld.long 0x00 6.--7. "SW_ENC_ACTIVE_L1_CNT,active l0 count" "0,1,2,3"
newline
bitfld.long 0x00 4. "SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG,long-term reference pictures may be used for inter prediction" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE,list1 ref0 frame luma compressor enable flag" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 2. "SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE,list1 ref0 frame chroma compressor enable flag" "0: bf_val_0,1: bf_val_1"
group.long 0x170++0x03
line.long 0x00 "swreg92,reference picture reconstructed list1 4n 0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_REFPIC_RECON_L1_4N0_BASE,reference picture reconstructed list1 4n 0"
group.long 0x180++0x03
line.long 0x00 "swreg96,Base address for list 1 ref 0 luma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE,Base address for list 1 ref 0 luma compress table LSB"
group.long 0x188++0x03
line.long 0x00 "swreg98,Base address for list 1 ref 0 Chroma compress table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE,Base address for list 1 ref 0 Chroma compress table LSB"
group.long 0x1A0++0x03
line.long 0x00 "swreg104,reference picture lists modification"
bitfld.long 0x00 31. "SW_ENC_LISTS_MODI_PRESENT_FLAG,lists_modification_present_flag from pps" "0,1"
newline
bitfld.long 0x00 29.--30. "SW_ENC_RDO_LEVEL,RDO level" "0,1,2,3"
newline
bitfld.long 0x00 17.--20. "SW_ENC_LIST_ENTRY_L1_PIC0,list1 picture0 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16. "SW_ENC_REF_PIC_LIST_MODI_FLAG_L1,reference picture list1 modification flag" "0,1"
newline
bitfld.long 0x00 1.--4. "SW_ENC_LIST_ENTRY_L0_PIC0,list0 picture0 index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "SW_ENC_REF_PIC_LIST_MODI_FLAG_L0,reference picture list0 modification flag" "0,1"
group.long 0x1A8++0x03
line.long 0x00 "swreg106,Min picture size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MINPICSIZE,Allowed minimum picture size for CTB rate control"
group.long 0x1AC++0x03
line.long 0x00 "swreg107,Max picture size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MAXPICSIZE,Allowed minimum picture size for CTB rate control"
group.long 0x1B4++0x03
line.long 0x00 "swreg109,Qp delta map"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAPDELTAQPADDR,Qp delta map"
rgroup.long 0x1BC++0x03
line.long 0x00 "swreg111,adaptive GOP configuration1"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_INTRACU8NUM,The number of block8x8 with type INTRA"
rgroup.long 0x1C0++0x03
line.long 0x00 "swreg112,adaptive GOP configuration2"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_SKIPCU8NUM,The number of block8x8 with type SKIP"
group.long 0x1C4++0x03
line.long 0x00 "swreg113,adaptive GOP configuration3"
hexmask.long 0x00 0.--31. 1. "SW_ENC_PBFRAME4NRDCOST,PBFrame4NRdCost"
group.long 0x1DC++0x03
line.long 0x00 "swreg119,min/max lcu bits number of last picture"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_CTBBITSMIN,minimum lcu bits number of last picture"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_CTBBITSMAX,maximum lcu bits number of last picture"
group.long 0x1E0++0x03
line.long 0x00 "swreg120,total bits number of all lcus of last picture not including slice header bits"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALLCUBITS,total bits number of all lcus of last picture not including slice header bits"
group.long 0x1E8++0x03
line.long 0x00 "swreg122_H2V5,inter me SSE lambda config 1"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT,inter me SSE lambda 1"
group.long 0x1EC++0x03
line.long 0x00 "swreg123_H2V5,inter me SSE lambda config 2"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT,inter me SSE lambda 2"
group.long 0x1F0++0x03
line.long 0x00 "swreg124_H2V5,inter me SSE lambda config 3"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT,inter me SSE lambda 3"
group.long 0x1F4++0x03
line.long 0x00 "swreg125,intra SATD lambda config 0"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_0,intra SATD lambda 0"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_1,intra SATD lambda 1"
group.long 0x1F8++0x03
line.long 0x00 "swreg126,intra SATD lambda config 1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_2,intra SATD lambda 2"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_3,intra SATD lambda 3"
group.long 0x1FC++0x03
line.long 0x00 "swreg127,intra SATD lambda config 2"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_4,intra SATD lambda 4"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_5,intra SATD lambda 5"
group.long 0x200++0x03
line.long 0x00 "swreg128,intra SATD lambda config 3"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_6,intra SATD lambda 6"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_7,intra SATD lambda 7"
group.long 0x204++0x03
line.long 0x00 "swreg129,intra SATD lambda config 4"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_8,intra SATD lambda 8"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_9,intra SATD lambda 9"
group.long 0x208++0x03
line.long 0x00 "swreg130,intra SATD lambda config 5"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_10,intra SATD lambda 10"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_11,intra SATD lambda 11"
group.long 0x20C++0x03
line.long 0x00 "swreg131,intra SATD lambda config 6"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_12,intra SATD lambda 12"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_13,intra SATD lambda 13"
group.long 0x210++0x03
line.long 0x00 "swreg132,intra SATD lambda config 7"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_14,intra SATD lambda 14"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_15,intra SATD lambda 15"
group.long 0x214++0x03
line.long 0x00 "swreg133,SSE devide 256"
hexmask.long 0x00 0.--31. 1. "SW_ENC_SSE_DIV_256,sse divide 256"
group.long 0x218++0x03
line.long 0x00 "swreg134,noise reduction"
bitfld.long 0x00 30.--31. "SW_ENC_NOISE_REDUCTION_ENABLE,enable/disable the de-noise function" "0,1,2,3"
newline
bitfld.long 0x00 24.--29. "SW_ENC_NOISE_LOW,the low boundary for noise estimation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_NR_MBNUM_INVERT_REG,inverter of luma16 num *N"
group.long 0x21C++0x03
line.long 0x00 "swreg135,noise reduction 1"
bitfld.long 0x00 26.--31. "SW_ENC_SLICEQP_PREV,previous frame slice QP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.tbyte 0x00 5.--25. 1. "SW_ENC_THRESH_SIGMA_CUR,sigma threshold for current frame"
group.long 0x220++0x03
line.long 0x00 "swreg136,noise reduction 2"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_SIGMA_CUR,noise sigma for current frame"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_FRAME_SIGMA_CALCED,calculated sigma of coding frame"
group.long 0x224++0x03
line.long 0x00 "swreg137,noise reduction 3"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_THRESH_SIGMA_CALCED,noise sigma for current frame"
group.long 0x228++0x03
line.long 0x00 "swreg138_H2V5,inter me SSE lambda config 4"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT,inter me SSE lambda 3"
group.long 0x22C++0x03
line.long 0x00 "swreg139_H2V5,inter me SSE lambda config 5"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT,inter me SSE lambda 5"
group.long 0x230++0x03
line.long 0x00 "swreg140_H2V5,inter me SSE lambda config 6"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT,inter me SSE lambda 6"
group.long 0x234++0x03
line.long 0x00 "swreg141_H2V5,inter me SSE lambda config 7"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT,inter me SSE lambda 7"
group.long 0x238++0x03
line.long 0x00 "swreg142_H2V5,inter me SSE lambda config 8"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT,inter me SSE lambda 8"
group.long 0x23C++0x03
line.long 0x00 "swreg143_H2V5,inter me SSE lambda config 9"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT,inter me SSE lambda 9"
group.long 0x240++0x03
line.long 0x00 "swreg144_H2V5,inter me SSE lambda config 10"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT,inter me SSE lambda 10"
group.long 0x244++0x03
line.long 0x00 "swreg145_H2V5,inter me SSE lambda config 11"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT,inter me SSE lambda 11"
group.long 0x248++0x03
line.long 0x00 "swreg146_H2V5,inter me SSE lambda config 12"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT,inter me SSE lambda 12"
group.long 0x24C++0x03
line.long 0x00 "swreg147_H2V5,inter me SSE lambda config 13"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT,inter me SSE lambda 13"
group.long 0x250++0x03
line.long 0x00 "swreg148_H2V5,inter me SSE lambda config 14"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT,inter me SSE lambda 14"
group.long 0x254++0x03
line.long 0x00 "swreg149_H2V5,inter me SSE lambda config 15"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT,inter me SSE lambda 15"
group.long 0x258++0x03
line.long 0x00 "swreg150,inter me SATD lambda config 8"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_16,lambda satd me 16"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_17,lambda satd me 17"
group.long 0x25C++0x03
line.long 0x00 "swreg151,inter me SATD lambda config 9"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_18,lambda satd me 18"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_19,lambda satd me 19"
group.long 0x260++0x03
line.long 0x00 "swreg152,inter me SATD lambda config 10"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_20,lambda satd me 20"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_21,lambda satd me 21"
group.long 0x264++0x03
line.long 0x00 "swreg153,inter me SATD lambda config 11"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_22,lambda satd me 22"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_23,lambda satd me 23"
group.long 0x268++0x03
line.long 0x00 "swreg154,inter me SATD lambda config 12"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_24,lambda satd me 24"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_25,lambda satd me 25"
group.long 0x26C++0x03
line.long 0x00 "swreg155,inter me SATD lambda config 13"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_26,lambda satd me 26"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_27,lambda satd me 27"
group.long 0x270++0x03
line.long 0x00 "swreg156,inter me SATD lambda config 14"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_28,lambda satd me 28"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_29,lambda satd me 29"
group.long 0x274++0x03
line.long 0x00 "swreg157,inter me SATD lambda config 15"
hexmask.long.word 0x00 19.--31. 1. "SW_ENC_LAMDA_SATD_ME_30,lambda satd me 30"
newline
hexmask.long.word 0x00 6.--18. 1. "SW_ENC_LAMDA_SATD_ME_31,lambda satd me 31"
group.long 0x278++0x03
line.long 0x00 "swreg158,inter me SSE lambda config 16"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_16,inter me SSE lambda 16"
group.long 0x27C++0x03
line.long 0x00 "swreg159,inter me SSE lambda config 17"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_17,inter me SSE lambda 17"
group.long 0x280++0x03
line.long 0x00 "swreg160,inter me SSE lambda config 18"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_18,inter me SSE lambda 18"
group.long 0x284++0x03
line.long 0x00 "swreg161,inter me SSE lambda config 19"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_19,inter me SSE lambda 19"
group.long 0x288++0x03
line.long 0x00 "swreg162,inter me SSE lambda config 20"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_20,inter me SSE lambda 20"
group.long 0x28C++0x03
line.long 0x00 "swreg163,inter me SSE lambda config 21"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_21,inter me SSE lambda 21"
group.long 0x290++0x03
line.long 0x00 "swreg164,inter me SSE lambda config 22"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_22,inter me SSE lambda 22"
group.long 0x294++0x03
line.long 0x00 "swreg165,inter me SSE lambda config 23"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_23,inter me SSE lambda 23"
group.long 0x298++0x03
line.long 0x00 "swreg166,inter me SSE lambda config 24"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_24,inter me SSE lambda 24"
group.long 0x29C++0x03
line.long 0x00 "swreg167,inter me SSE lambda config 25"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_25,inter me SSE lambda 25"
group.long 0x2A0++0x03
line.long 0x00 "swreg168,inter me SSE lambda config 26"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_26,inter me SSE lambda 26"
group.long 0x2A4++0x03
line.long 0x00 "swreg169,inter me SSE lambda config 27"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_27,inter me SSE lambda 27"
group.long 0x2B0++0x03
line.long 0x00 "swreg172,inter me SSE lambda config 30"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_30,inter me SSE lambda 30"
newline
bitfld.long 0x00 5.--10. "SW_ENC_QP_MIN,min value of qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--4. "SW_ENC_COMPLEXITY_OFFSET,block rc complexity offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2B4++0x03
line.long 0x00 "swreg173,inter me SSE lambda config 31"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_LAMDA_SSE_ME_31,inter me SSE lambda 31"
newline
bitfld.long 0x00 5.--10. "SW_ENC_QP_MAX,max value of qp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--3. "SW_ENC_RC_QPDELTA_RANGE,rc qp delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2B8++0x03
line.long 0x00 "swreg174,intra SATD lambda config 8"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_16,intra SATD lambda 16"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_17,intra SATD lambda 17"
group.long 0x2BC++0x03
line.long 0x00 "swreg175,intra SATD lambda config 9"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_18,intra SATD lambda 18"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_19,intra SATD lambda 19"
group.long 0x2C0++0x03
line.long 0x00 "swreg176,intra SATD lambda config 10"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_20,intra SATD lambda 20"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_21,intra SATD lambda 21"
group.long 0x2C4++0x03
line.long 0x00 "swreg177,intra SATD lambda config 11"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_22,intra SATD lambda 22"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_23,intra SATD lambda 23"
group.long 0x2C8++0x03
line.long 0x00 "swreg178,intra SATD lambda config 12"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_24,intra SATD lambda 24"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_25,intra SATD lambda 25"
group.long 0x2CC++0x03
line.long 0x00 "swreg179,intra SATD lambda config 13"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_26,intra SATD lambda 26"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_27,intra SATD lambda 27"
group.long 0x2D0++0x03
line.long 0x00 "swreg180,intra SATD lambda config 14"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_28,intra SATD lambda 28"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_29,intra SATD lambda 29"
group.long 0x2D4++0x03
line.long 0x00 "swreg181,intra SATD lambda config 15"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_INTRA_SATD_LAMDA_30,intra SATD lambda 30"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_INTRA_SATD_LAMDA_31,intra SATD lambda 31"
newline
bitfld.long 0x00 2.--3. "SW_ENC_RC_BLOCK_SIZE,block rc block size" "0: bf_val_0,1: bf_val_1,2: bf_val_2,?..."
group.long 0x2D8++0x03
line.long 0x00 "swreg182,qp fractional part"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_QP_FRACTIONAL,qp fractional part"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_QP_DELTA_GAIN,qp delta gain"
rgroup.long 0x2DC++0x03
line.long 0x00 "swreg183,qp sum"
hexmask.long 0x00 6.--31. 1. "SW_ENC_QP_SUM,Block qp sum"
rgroup.long 0x2E0++0x03
line.long 0x00 "swreg184,qp num"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_QP_NUM,Block qp number"
group.long 0x2E4++0x03
line.long 0x00 "swreg185,picture complexity"
hexmask.long.tbyte 0x00 9.--31. 1. "SW_ENC_PIC_COMPLEXITY,Picture complexity"
newline
hexmask.long.word 0x00 0.--8. 1. "SW_TIMEOUT_CYCLES_MSB,Extend swreg81"
group.long 0x2E8++0x03
line.long 0x00 "swreg186,Base address for CU information table LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_CU_INFORMATION_TABLE_BASE,Base address for CU information table LSB"
group.long 0x2F0++0x03
line.long 0x00 "swreg188,Base address for CU information LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_CU_INFORMATION_BASE,Base address for CU information LSB"
group.long 0x2F8++0x03
line.long 0x00 "swreg190,Long-term reference pictures config"
bitfld.long 0x00 30.--31. "SW_ENC_NUM_LONG_TERM_PICS,Number of long-term reference pictures directly signaled in the slice header" "0,1,2,3"
group.long 0x2FC++0x03
line.long 0x00 "swreg191,Temporal scalable config"
bitfld.long 0x00 26.--31. "SW_ENC_NAL_UNIT_TYPE,NAL unit type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 23.--25. "SW_ENC_NUH_TEMPORAL_ID,NAL temporal id" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--22. "SW_ENC_PPS_ID,PPS id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_SLICE_HEADER_SIZE,Slice header size"
group.long 0x30C++0x03
line.long 0x00 "swreg195,register extension for ctu_size=16"
bitfld.long 0x00 28.--31. "SW_ENC_ENCODED_CTB_NUMBER_MSB,MB count output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 26.--27. "SW_ENC_NUM_SLICES_READY_MSB,HEVC amount of completed slices" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "SW_ENC_SLICE_SIZE_MSB,slice size in ctu row" "0,1,2,3"
newline
bitfld.long 0x00 20.--23. "SW_ENC_CIR_START_MSB,cir start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "SW_ENC_CIR_INTERVAL_MSB,Cyclic Intra Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 15. "SW_ENC_INTRA_AREA_LEFT_MSB,intra Area Left" "0,1"
newline
bitfld.long 0x00 14. "SW_ENC_INTRA_AREA_RIGHT_MSB,intra Area Right" "0,1"
newline
bitfld.long 0x00 13. "SW_ENC_INTRA_AREA_TOP_MSB,intra Area Top" "0,1"
newline
bitfld.long 0x00 12. "SW_ENC_INTRA_AREA_BOTTOM_MSB,intra Area Bottom" "0,1"
newline
bitfld.long 0x00 11. "SW_ENC_ROI1_LEFT_MSB,ROI1 Area Left" "0,1"
newline
bitfld.long 0x00 10. "SW_ENC_ROI1_RIGHT_MSB,ROI1 Area Right" "0,1"
newline
bitfld.long 0x00 9. "SW_ENC_ROI1_TOP_MSB,ROI1 Area Top" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_ROI1_BOTTOM_MSB,ROI1 Area Bottom" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_ROI2_LEFT_MSB,ROI2 Area Left" "0,1"
newline
bitfld.long 0x00 6. "SW_ENC_ROI2_RIGHT_MSB,ROI2 Area Right" "0,1"
newline
bitfld.long 0x00 5. "SW_ENC_ROI2_TOP_MSB,ROI2 Area Top" "0,1"
newline
bitfld.long 0x00 4. "SW_ENC_ROI2_BOTTOM_MSB,ROI2 Area Bottom" "0,1"
newline
bitfld.long 0x00 2.--3. "SW_ENC_PIC_WIDTH_MSB,Encoded width" "0,1,2,3"
group.long 0x310++0x03
line.long 0x00 "swreg196,Low Latency Controls"
bitfld.long 0x00 31. "SW_LOW_LATENCY_HW_SYNC_EN,Low Latency Hardware Interface Enable" "0,1"
newline
bitfld.long 0x00 30. "SW_LOW_LATENCY_EN,Low Latency Enable" "0,1"
newline
bitfld.long 0x00 29. "SW_INPUT_BUF_LOOPBACK_EN,Input buffer loopback Enable" "0,1"
newline
hexmask.long.word 0x00 20.--28. 1. "SW_NUM_CTB_ROWS_PER_SYNC,Number of CTB rows for every HW sync"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_CTB_ROW_RD_PTR,The number of CTB rows that has been fetched from Input buffer by encoder"
newline
hexmask.long.word 0x00 0.--9. 1. "SW_CTB_ROW_WR_PTR,The number of CTB rows that has been filled into the input buffer by external application"
group.long 0x314++0x03
line.long 0x00 "swreg197,Delta POC extension"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_L0_DELTA_POC0_MSB,delta poc of list0 pic0 (bit[19..10])"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_L0_DELTA_POC1_MSB,delta poc of list0 pic1 (bit[19..10])"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_L1_DELTA_POC0_MSB,delta poc of list1 pic0 (bit[19..10])"
group.long 0x318++0x03
line.long 0x00 "swreg198,Long Term Reference Control"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_L1_DELTA_POC1_MSB,delta poc of list1 pic1 (bit[19..10])"
group.long 0x31C++0x03
line.long 0x00 "swreg199,Hash Code Control"
bitfld.long 0x00 3.--4. "SW_ENC_HASH_TYPE,hash type of frame data" "0: bf_val_0,1: bf_val_1,2: checksum32,?..."
newline
bitfld.long 0x00 1.--2. "SW_ENC_HASH_OFFSET,hash offset (byte offset of processed hashdata)" "0,1,2,3"
newline
bitfld.long 0x00 0. "SW_ENC_OSD_ALPHABLEND_ENABLE,enable OSD Alpha Blending" "0: bf_val_0,1: bf_val_1"
group.long 0x320++0x03
line.long 0x00 "swreg200,Hash Code Value"
hexmask.long 0x00 0.--31. 1. "SW_ENC_HASH_VAL,hash value of frame data"
group.long 0x324++0x03
line.long 0x00 "swreg201,Background SKIP Control 0"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_MEAN_THR0,A mean value threshold of out circle used for foreground decision"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_MEAN_THR1,A mean value threshold of second circle for foreground decision"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_MEAN_THR2,A mean value threshold of third circle"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_MEAN_THR3,A mean value threshold of the smallest circle"
group.long 0x328++0x03
line.long 0x00 "swreg202,Background SKIP Control 1"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_THR_DC_LUM_8X8,A threshold value of DC for CU08 luma"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_THR_DC_CHROMA_8X8,A threshold value of DC for CU08 chroma"
group.long 0x32C++0x03
line.long 0x00 "swreg203,Background SKIP Control 2"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_THR_DC_LUM_16X16,A threshold value of DC for CU16 luma"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_THR_DC_CHROMA_16X16,A threshold value of DC for CU16 chroma"
group.long 0x330++0x03
line.long 0x00 "swreg204,Background SKIP Control 3"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_THR_DC_LUM_32X32,A threshold value of DC for CU32 luma"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_THR_DC_CHROMA_32X32,A threshold value of DC for CU32 chroma"
group.long 0x334++0x03
line.long 0x00 "swreg205,Background SKIP Control 4"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_THR_AC_NUM_LUM_8X8,A threshold value of number of non-zero AC for CU08 luma"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_THR_AC_NUM_CHROMA_8X8,A threshold value of number of non-zero AC for CU08 chroma"
group.long 0x338++0x03
line.long 0x00 "swreg206,Background SKIP Control 5"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_THR_AC_NUM_LUM_16X16,A threshold value of number of non-zero AC for CU16 luma"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_THR_AC_NUM_CHROMA_16X16,A threshold value of number of non-zero AC for CU16 chroma"
group.long 0x33C++0x03
line.long 0x00 "swreg207,Background SKIP Control 6"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_THR_AC_NUM_LUM_32X32,A threshold value of number of non-zero AC for CU32 luma"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_THR_AC_NUM_CHROMA_32X32,A threshold value of number of non-zero AC for CU32 chroma"
group.long 0x340++0x03
line.long 0x00 "swreg208,Background SKIP Control 7"
bitfld.long 0x00 26.--31. "SW_ENC_MDQPY,A luma QP value for skip decision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 20.--25. "SW_ENC_MDQPC,A chroma QP value for skip decision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 14.--19. "SW_ENC_FOREGROUND_PIXEL_THX,Foreground threshold number of pixel (0 ~ 63) used for foreground decision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "SW_ENC_ENABLE_SMART,enable smart featrue" "0,1"
newline
hexmask.long.word 0x00 4.--12. 1. "SW_ENC_IPCM1_LEFT,IPCM1 Area Left"
newline
bitfld.long 0x00 3. "SW_ENC_SKIP_MAP_ENABLE,enable skip map mode" "0,1"
group.long 0x344++0x03
line.long 0x00 "swreg209,IPCM Control 0"
hexmask.long.word 0x00 23.--31. 1. "SW_ENC_IPCM1_RIGHT,IPCM1 Area Right"
newline
hexmask.long.word 0x00 14.--22. 1. "SW_ENC_IPCM1_TOP,IPCM1 Area Top"
newline
hexmask.long.word 0x00 5.--13. 1. "SW_ENC_IPCM1_BOTTOM,IPCM1 Area Bottom"
newline
bitfld.long 0x00 4. "SW_ENC_PCM_FILTER_DISABLE,disable deblock filter for IPCM" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_IPCM_MAP_ENABLE,enable pcm map mode" "0,1"
group.long 0x348++0x03
line.long 0x00 "swreg210,IPCM Control 1"
hexmask.long.word 0x00 3.--11. 1. "SW_ENC_IPCM2_LEFT,IPCM2 Area Left"
group.long 0x34C++0x03
line.long 0x00 "swreg211,IPCM Control 2"
hexmask.long.word 0x00 3.--11. 1. "SW_ENC_IPCM2_RIGHT,IPCM2 Area Right"
group.long 0x350++0x03
line.long 0x00 "swreg212,IPCM Control 3"
hexmask.long.word 0x00 3.--11. 1. "SW_ENC_IPCM2_TOP,IPCM2 Area Top"
group.long 0x354++0x03
line.long 0x00 "swreg213,IPCM Control 4"
hexmask.long.word 0x00 5.--13. 1. "SW_ENC_IPCM2_BOTTOM,IPCM2 Area Bottom"
rgroup.long 0x358++0x03
line.long 0x00 "swreg214,HW synthesis config register 2 read-only"
bitfld.long 0x00 31. "SW_ENC_HWLJPEGSUPPORT,Lossless JPEG supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 30. "SW_ENC_HWABSQPSUPPORT,Absolute QP in ROI/ROI map supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 29. "SW_ENC_HWINTRATU32SUPPORT,IntraPath TU32x32 supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 26.--28. "SW_ENC_HWROIMAPVERSION,ROI map buffer format version" "0: 4 bit per pixel,1: 8 bit per pixel,?..."
rgroup.long 0x35C++0x03
line.long 0x00 "swreg215,AXI Information 0"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALARLEN,[AXI] Accumulated ARLEN+1"
rgroup.long 0x360++0x03
line.long 0x00 "swreg216,AXI Information 1"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALR,[AXI] RVALID & RREADY"
rgroup.long 0x364++0x03
line.long 0x00 "swreg217,AXI Information 2"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALAR,[AXI] ARVALID & ARREADY"
rgroup.long 0x368++0x03
line.long 0x00 "swreg218,AXI Information 3"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALRLAST,[AXI] RVALID & RREADY & RLAST"
rgroup.long 0x36C++0x03
line.long 0x00 "swreg219,AXI Information 4"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALAWLEN,[AXI] Accumulated AWLEN+1"
rgroup.long 0x370++0x03
line.long 0x00 "swreg220,AXI Information 5"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALW,[AXI] WVALID & WREADY"
rgroup.long 0x374++0x03
line.long 0x00 "swreg221,AXI Information 6"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALAW,[AXI] AWVALID & AWREADY"
rgroup.long 0x378++0x03
line.long 0x00 "swreg222,AXI Information 7"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALWLAST,[AXI] WVALID & WREADY & WLAST"
rgroup.long 0x37C++0x03
line.long 0x00 "swreg223,AXI Information 8"
hexmask.long 0x00 0.--31. 1. "SW_ENC_TOTALB,[AXI] BVALID & BREADY"
group.long 0x380++0x03
line.long 0x00 "swreg224,control register 4"
bitfld.long 0x00 31. "SW_ENC_CHROMA_CONST_EN,Force Chroma to be a constant pixel or not" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 21. "SW_ENC_SSIM_EN,Enable SSIM calculation" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 20. "SW_ENC_SKIPFRAME_EN,Force frame encode as SKIPFRAME" "0: bf_val_0,1: bf_val_1"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_ENC_CR_CONST_PIXEL,The constant pixel of CR if sw_enc_chroma_const_en=1"
newline
hexmask.long.word 0x00 0.--9. 1. "SW_ENC_CB_CONST_PIXEL,The constant pixel of CB if sw_enc_chroma_const_en=1"
group.long 0x384++0x03
line.long 0x00 "swreg225,Tile Control"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_NUM_TILE_COLUMNS,the number of tile columns partitioning the picture"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_NUM_TILE_ROWS,the number of tile rows partitioning the picture"
newline
bitfld.long 0x00 15. "SW_ENC_TILES_ENABLED_FLAG,enable HEVC tile partition" "0: disabled,1: bf_val_1"
newline
bitfld.long 0x00 14. "SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG,enable in-loop filtering operations across tile boundaries" "0: disabled,1: bf_val_1"
newline
bitfld.long 0x00 13. "SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE,roi map cu ctrl index enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 12. "SW_ENC_ROIMAP_CUCTRL_ENABLE,roi map cu ctrl enable" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 9.--11. "SW_ENC_ROIMAP_CUCTRL_VER,roi map cu ctrl info version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--8. "SW_ENC_ROIMAP_QPDELTA_VER,roi map qp delta info version" "0,1,2,3,4,5,6,7"
rgroup.long 0x388++0x03
line.long 0x00 "swreg226,HW synthesis config register 3 read-only"
bitfld.long 0x00 31. "SW_ENC_HWSSIMSUPPORT,SSIM calculation supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 30. "SW_ENC_HWP010REFSUPPORT,Reference buffer format for 10-bit encoding" "0: normal format,1: P010 tile raster format"
newline
bitfld.long 0x00 27.--29. "SW_ENC_HWCUINFORVERSION,Version of the output CU information format" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 21.--26. "SW_ENC_ME_VERT_SEARCHRANGE_HEVC,ME vertical search range in 8 pixel unit for HEVC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15.--20. "SW_ENC_ME_VERT_SEARCHRANGE_H264,ME vertical search range in 8 pixel unit for H264" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--14. "SW_ENC_HWCTBRCVERSION,CTB Rate Control Version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "SW_ENC_HWJPEG422SUPPORT,Jpeg422 supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 10. "SW_ENC_HWGMVSUPPORT,Global MV supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 9. "SW_ENC_HWROI8SUPPORT,support 8 ROIs" "0,1"
newline
bitfld.long 0x00 7.--8. "SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE,ME4N horizontal search range in 64 pixel unit" "0: bf_val_0,1: bf_val_1,2: bf_val_2,3: bf_val_3"
newline
bitfld.long 0x00 6. "SW_ENC_HWRDOQSUPPORT,RDOQ supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 5. "SW_ENC_HWMULTIPASSSUPPORT,Multipass Encoding supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 4. "SW_ENC_HWINLOOPDSRATIO,in-loop ds ratio supported by HW" "0: bf_val_0,1: bf_val_1"
newline
bitfld.long 0x00 3. "SW_ENC_HWSTREAMBUFCHAIN,Stream Buffer Chain supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 2. "SW_ENC_HWSTREAMSEGMENTSUPPORT,Stream segment supported by HW" "0: not supported,1: supported"
newline
bitfld.long 0x00 1. "SW_ENC_HWIFRAMEONLY,Only support I frame" "0: support I/P/B frame,1: only support I frame"
newline
bitfld.long 0x00 0. "SW_ENC_HWDYNAMICMAXTUSIZE,HW support dynamic max TU size change per frame" "0: not supported,1: supported"
group.long 0x3AC++0x03
line.long 0x00 "swreg235,RPS encoding control 0"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_RPS_DELTA_POC_0,delta poc of pic0 in current rps"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_RPS_DELTA_POC_1,delta poc of pic1 in current rps"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_RPS_DELTA_POC_2,delta poc of pic2 in current rps"
newline
bitfld.long 0x00 1. "SW_ENC_RPS_USED_BY_CUR_0,pic0 in current rps is used for reference by current slice" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_RPS_USED_BY_CUR_1,pic1 in current rps is used for reference by current slice" "0,1"
group.long 0x3B0++0x03
line.long 0x00 "swreg236,RPS encoding control 1"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_RPS_DELTA_POC_3,delta poc of pic3 in current rps"
newline
bitfld.long 0x00 21. "SW_ENC_RPS_USED_BY_CUR_2,pic2 in current rps is used for reference by current slice" "0,1"
newline
bitfld.long 0x00 20. "SW_ENC_RPS_USED_BY_CUR_3,pic3 in current rps is used for reference by current slice" "0,1"
newline
bitfld.long 0x00 17.--19. "SW_ENC_RPS_NEG_PIC_NUM,number of negative pictures in current rps" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "SW_ENC_RPS_POS_PIC_NUM,number of positive pictures in current rps" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG,short term rps for current slice is encoded in sps" "0,1"
newline
bitfld.long 0x00 12. "SW_ENC_P010_REF_ENABLE,Enable/Disable P010 Reference format" "0: not supported,1: supported"
group.long 0x3B4++0x03
line.long 0x00 "swreg237,Stride Control"
hexmask.long.tbyte 0x00 12.--31. 1. "SW_ENC_REF_CH_STRIDE,Chroma stride of reference frame"
newline
bitfld.long 0x00 11. "SW_ENC_DUMMYREADEN,enable dummy read when frame height not align to 64 or other possible condition" "0,1"
group.long 0x3B8++0x03
line.long 0x00 "swreg238,Dummy"
hexmask.long 0x00 0.--31. 1. "SW_ENC_DUMMYREADADDR,Dummy read address"
group.long 0x3BC++0x03
line.long 0x00 "swreg239,Base Address LSB of CTB MADs of current frame"
hexmask.long 0x00 0.--31. 1. "SW_ENC_CURRENT_CTB_MAD_BASE,Base Address LSB of CTB MADs of current frame used for CTB RC"
group.long 0x3C4++0x03
line.long 0x00 "swreg241,Base Address LSB of CTB MADs of previous frame"
hexmask.long 0x00 0.--31. 1. "SW_ENC_PREVIOUS_CTB_MAD_BASE,Base Address LSB of CTB MADs of previous frame used for CTB RC"
group.long 0x3CC++0x03
line.long 0x00 "swreg243,CTB RC Control 0"
hexmask.long.tbyte 0x00 11.--31. 1. "SW_ENC_CTB_RC_MODEL_PARAM0,Parameter0 of CTB RC model"
group.long 0x3D0++0x03
line.long 0x00 "swreg244,CTB RC Control 1"
hexmask.long.tbyte 0x00 10.--31. 1. "SW_ENC_CTB_RC_MODEL_PARAM1,Parameter1 of CTB RC model"
newline
hexmask.long.byte 0x00 3.--9. 1. "SW_ENC_ROI3_QP_VALUE,ROI3 qp value"
newline
bitfld.long 0x00 2. "SW_ENC_ROI3_QP_TYPE,ROI3 qp type" "0: bf_val_0,1: Absolute value"
group.long 0x3D4++0x03
line.long 0x00 "swreg245,CTB RC Control 2"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_CTB_RC_MODEL_PARAM_MIN,Minimum parameter value of CTB RC model"
newline
hexmask.long.word 0x00 2.--17. 1. "SW_ENC_CTB_RC_ROW_FACTOR,Reciprocal of ctb per row"
group.long 0x3D8++0x03
line.long 0x00 "swreg246,CTB RC Control 3"
hexmask.long.tbyte 0x00 14.--31. 1. "SW_ENC_CTB_RC_QP_STEP,Maximum QP step per CTB for purpose of rate control"
newline
hexmask.long.byte 0x00 6.--13. 1. "SW_ENC_AXI_WRITE_OUTSTANDING_NUM,AXI outstanding number of write operation"
newline
bitfld.long 0x00 3.--5. "SW_ENC_CTB_RC_DELAY,Feedback delay of information for CTB RC" "0,1,2,3,4,5,6,7"
group.long 0x3DC++0x03
line.long 0x00 "swreg247,CTB RC Control 4"
hexmask.long 0x00 6.--31. 1. "SW_ENC_PREV_PIC_LUM_MAD,Luma MAD of the predict picture"
newline
bitfld.long 0x00 1. "SW_ENC_CTB_RC_PREV_MAD_VALID,Prev luma MADs are valid or not for ctb rc" "0: bf_val_0,1: bf_val_1"
group.long 0x3E0++0x03
line.long 0x00 "swreg248,CTB RC Control 5"
hexmask.long.tbyte 0x00 8.--31. 1. "SW_ENC_CTB_QP_SUM_FOR_RC,Sum of CTB QP used for rate control"
newline
hexmask.long.byte 0x00 1.--7. 1. "SW_ENC_ROI4_QP_VALUE,ROI4 qp value"
newline
bitfld.long 0x00 0. "SW_ENC_ROI4_QP_TYPE,ROI4 qp type" "0: bf_val_0,1: Absolute value"
group.long 0x3E4++0x03
line.long 0x00 "swreg249,register extension for 8K width"
bitfld.long 0x00 30.--31. "SW_ENC_ENCODED_CTB_NUMBER_MSB2,MB count output" "0,1,2,3"
newline
bitfld.long 0x00 29. "SW_ENC_NUM_SLICES_READY_MSB2,HEVC amount of completed slices" "0,1"
newline
bitfld.long 0x00 28. "SW_ENC_SLICE_SIZE_MSB2,slice size in ctu row" "0,1"
newline
bitfld.long 0x00 26.--27. "SW_ENC_CIR_START_MSB2,cir start" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "SW_ENC_CIR_INTERVAL_MSB2,Cyclic Intra Refresh" "0,1,2,3"
newline
bitfld.long 0x00 23. "SW_ENC_INTRA_AREA_LEFT_MSB2,intra Area Left" "0,1"
newline
bitfld.long 0x00 22. "SW_ENC_INTRA_AREA_RIGHT_MSB2,intra Area Right" "0,1"
newline
bitfld.long 0x00 21. "SW_ENC_INTRA_AREA_TOP_MSB2,intra Area Top" "0,1"
newline
bitfld.long 0x00 20. "SW_ENC_INTRA_AREA_BOTTOM_MSB2,intra Area Bottom" "0,1"
newline
bitfld.long 0x00 19. "SW_ENC_ROI1_LEFT_MSB2,ROI1 Area Left" "0,1"
newline
bitfld.long 0x00 18. "SW_ENC_ROI1_RIGHT_MSB2,ROI1 Area Right" "0,1"
newline
bitfld.long 0x00 17. "SW_ENC_ROI1_TOP_MSB2,ROI1 Area Top" "0,1"
newline
bitfld.long 0x00 16. "SW_ENC_ROI1_BOTTOM_MSB2,ROI1 Area Bottom" "0,1"
newline
bitfld.long 0x00 15. "SW_ENC_ROI2_LEFT_MSB2,ROI2 Area Left" "0,1"
newline
bitfld.long 0x00 14. "SW_ENC_ROI2_RIGHT_MSB2,ROI2 Area Right" "0,1"
newline
bitfld.long 0x00 13. "SW_ENC_ROI2_TOP_MSB2,ROI2 Area Top" "0,1"
newline
bitfld.long 0x00 12. "SW_ENC_ROI2_BOTTOM_MSB2,ROI2 Area Bottom" "0,1"
newline
bitfld.long 0x00 11. "SW_ENC_PIC_WIDTH_MSB2,Encoded width" "0,1"
newline
bitfld.long 0x00 10. "SW_ENC_IPCM1_LEFT_MSB,IPCM1 Area Left bit[9]" "0,1"
newline
bitfld.long 0x00 9. "SW_ENC_IPCM1_RIGHT_MSB,IPCM1 Area Right bit[9]" "0,1"
newline
bitfld.long 0x00 8. "SW_ENC_IPCM1_TOP_MSB,IPCM1 Area Top bit[9]" "0,1"
newline
bitfld.long 0x00 7. "SW_ENC_IPCM1_BOTTOM_MSB,IPCM2 Area Bottom bit[9]" "0,1"
newline
bitfld.long 0x00 6. "SW_ENC_IPCM2_LEFT_MSB,IPCM2 Area Left bit[9]" "0,1"
newline
bitfld.long 0x00 5. "SW_ENC_IPCM2_RIGHT_MSB,IPCM2 Area Right bit[9]" "0,1"
newline
bitfld.long 0x00 4. "SW_ENC_IPCM2_TOP_MSB,IPCM2 Area Top bit[9]" "0,1"
newline
bitfld.long 0x00 3. "SW_ENC_IPCM2_BOTTOM_MSB,IPCM1 Area Bottom bit[9]" "0,1"
group.long 0x3E8++0x03
line.long 0x00 "swreg250,Global MV Control 0"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_GLOBAL_HORIZONTAL_MV_L0,Global horizontal MV for LIST0 in integer pixel"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_GLOBAL_VERTICAL_MV_L0,Global vertical MV for LIST0 in integer pixel"
group.long 0x3EC++0x03
line.long 0x00 "swreg251,Global MV Control 1"
hexmask.long.word 0x00 18.--31. 1. "SW_ENC_GLOBAL_HORIZONTAL_MV_L1,Global horizontal MV for LIST1 in integer pixel"
newline
hexmask.long.word 0x00 4.--17. 1. "SW_ENC_GLOBAL_VERTICAL_MV_L1,Global vertical MV for LIST1 in integer pixel"
group.long 0x3F0++0x03
line.long 0x00 "swreg252,ROI3 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI3_LEFT,ROI3 Area Left"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI3_TOP,ROI3 Area Top"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI3_RIGHT,ROI3 Area Right"
group.long 0x3F4++0x03
line.long 0x00 "swreg253,ROI3&4 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI3_BOTTOM,ROI3 Area Bottom"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI4_LEFT,ROI4 Area Left"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI4_TOP,ROI4 Area Top"
group.long 0x3F8++0x03
line.long 0x00 "swreg254,ROI4&5 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI4_RIGHT,ROI4 Area Right"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI4_BOTTOM,ROI4 Area Bottom"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI5_LEFT,ROI5 Area Left"
group.long 0x3FC++0x03
line.long 0x00 "swreg255,ROI5 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI5_TOP,ROI5 Area Top"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI5_RIGHT,ROI5 Area Right"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI5_BOTTOM,ROI5 Area Bottom"
group.long 0x400++0x03
line.long 0x00 "swreg256,ROI6 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI6_LEFT,ROI6 Area Left"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI6_TOP,ROI6 Area Top"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI6_RIGHT,ROI6 Area Right"
group.long 0x404++0x03
line.long 0x00 "swreg257,ROI6&7 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI6_BOTTOM,ROI6 Area Bottom"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI7_LEFT,ROI7 Area Left"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI7_TOP,ROI7 Area Top"
group.long 0x408++0x03
line.long 0x00 "swreg258,ROI7&8 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI7_RIGHT,ROI7 Area Right"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI7_BOTTOM,ROI7 Area Bottom"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI8_LEFT,ROI8 Area Left"
group.long 0x40C++0x03
line.long 0x00 "swreg259,ROI8 Area"
hexmask.long.word 0x00 22.--31. 1. "SW_ENC_ROI8_TOP,ROI8 Area Top"
newline
hexmask.long.word 0x00 12.--21. 1. "SW_ENC_ROI8_RIGHT,ROI8 Area Right"
newline
hexmask.long.word 0x00 2.--11. 1. "SW_ENC_ROI8_BOTTOM,ROI8 Area Bottom"
newline
bitfld.long 0x00 1. "SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE,Decrease max tu size in current frame.[0]" "0: max tu size 32,1: max tu size 16"
group.long 0x410++0x03
line.long 0x00 "swreg260,ROI qp"
hexmask.long.byte 0x00 25.--31. 1. "SW_ENC_ROI8_QP_VALUE,ROI8 qp value"
newline
bitfld.long 0x00 24. "SW_ENC_ROI8_QP_TYPE,ROI8 qp type" "0: bf_val_0,1: Absolute value"
newline
hexmask.long.byte 0x00 17.--23. 1. "SW_ENC_ROI7_QP_VALUE,ROI7 qp value"
newline
bitfld.long 0x00 16. "SW_ENC_ROI7_QP_TYPE,ROI7 qp type" "0: bf_val_0,1: Absolute value"
newline
hexmask.long.byte 0x00 9.--15. 1. "SW_ENC_ROI6_QP_VALUE,ROI6 qp value"
newline
bitfld.long 0x00 8. "SW_ENC_ROI6_QP_TYPE,ROI6 qp type" "0: bf_val_0,1: Absolute value"
newline
hexmask.long.byte 0x00 1.--7. 1. "SW_ENC_ROI5_QP_VALUE,ROI5 qp value"
newline
bitfld.long 0x00 0. "SW_ENC_ROI5_QP_TYPE,ROI5 qp type" "0: bf_val_0,1: Absolute value"
group.long 0x414++0x03
line.long 0x00 "swreg261,Stride Control"
bitfld.long 0x00 13.--17. "SW_ENC_RGBLUMAOFFSET,RGB to YUV conversion luma offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12. "SW_ENC_PRP_IN_LOOP_DS_RATIO,down-scaling ratio of In-loop downscaler in prp" "0,1"
newline
hexmask.long.byte 0x00 4.--11. 1. "SW_ENC_AXI_READ_OUTSTANDING_NUM,AXI outstanding number of read operation"
newline
bitfld.long 0x00 3. "SW_ENC_MULTI_CORE_EN,Enable multi-core encoding mode" "0,1"
newline
bitfld.long 0x00 2. "SW_ENC_RDOQ_ENABLE,Enable RDOQ" "0,1"
newline
bitfld.long 0x00 1. "SW_ENC_PASS1_SKIP_CABAC,CABAC SKIP for pass one" "0,1"
newline
bitfld.long 0x00 0. "SW_ENC_MOTION_SCORE_ENABLE,Enable motion score computing for 2-pass Agop" "0,1"
group.long 0x424++0x03
line.long 0x00 "swreg265,Multicore sync ctrl"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_REF_READY_THRESHOLD,EXTRA_LINES_NUM bigger vertical search window ready"
newline
hexmask.long.word 0x00 0.--15. 1. "SW_ENC_DDR_POLLING_INTERVAL,Interval cycles for HW reading the DDR RECON_PIXELLINES_READY when value not bigger than search window"
group.long 0x428++0x03
line.long 0x00 "swreg266,Multicore sync address L0 LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L0_ADDR,For multicore sync"
group.long 0x42C++0x03
line.long 0x00 "swreg267,Multicore sync address L0 MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB,For multicore sync"
group.long 0x430++0x03
line.long 0x00 "swreg268,Multicore sync address L1 LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L1_ADDR,For multicore sync"
group.long 0x434++0x03
line.long 0x00 "swreg269,Multicore sync address L1 MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB,For multicore sync"
group.long 0x438++0x03
line.long 0x00 "swreg270,Multicore sync address recon LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_REC_ADDR,For multicore sync"
group.long 0x43C++0x03
line.long 0x00 "swreg271,Multicore sync address recon MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB,For multicore sync"
group.long 0x440++0x03
line.long 0x00 "swreg272,Programmable AXI urgent sideband signals"
hexmask.long.byte 0x00 24.--31. 1. "SW_ENC_RD_URGENT_ENABLE_THRESHOLD,axi_rd_urgent=1 when total number of rd cmds is bigger or equal to threshold.255=disable"
newline
hexmask.long.byte 0x00 16.--23. 1. "SW_ENC_RD_URGENT_DISABLE_THRESHOLD,axi_rd_urgent=0 when total number of rd cmds is smaller than threshold.255=disable"
newline
hexmask.long.byte 0x00 8.--15. 1. "SW_ENC_WR_URGENT_ENABLE_THRESHOLD,axi_wr_urgent=1 when total number of wr cmds is bigger or equal to threshold.255=disable"
newline
hexmask.long.byte 0x00 0.--7. 1. "SW_ENC_WR_URGENT_DISABLE_THRESHOLD,axi_wr_urgent=0 when total number of wr cmds is smaller than threshold.255=disable"
group.long 0x444++0x03
line.long 0x00 "swreg273,roimap cu ctrl index address LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR,Address LSB of roi map cu ctrlindex buffer"
group.long 0x448++0x03
line.long 0x00 "swreg274,roimap cu ctrl index address MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB,Address MSB of roi map cu ctrl index buffer"
group.long 0x44C++0x03
line.long 0x00 "swreg275,roimap cu ctrl address LSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_ADDR,Address LSB of roi map cu ctrl buffer"
group.long 0x450++0x03
line.long 0x00 "swreg276,roimap cu ctrl address MSB"
hexmask.long 0x00 0.--31. 1. "SW_ENC_ROIMAP_CUCTRL_ADDR_MSB,Address MSB of roi map cu ctrl buffer"
group.long 0x454++0x03
line.long 0x00 "swreg277,poc type/bits setting"
bitfld.long 0x00 27.--31. "SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB,number of bits in pic_order_cnt_lsb" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 5.--19. 1. "SW_ENC_SYN_AMOUNT_PER_LOOPBACK,Handshake sync amount for every loopback"
group.long 0x458++0x03
line.long 0x00 "swreg278,stream output buffer1 address"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BUF1_BASE,stream output buffer1 base address"
group.long 0x460++0x03
line.long 0x00 "swreg280,stream output buffer1 limit size"
hexmask.long 0x00 0.--31. 1. "SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT,Stream buffer1 limit size (bytes)"
group.long 0x464++0x03
line.long 0x00 "swreg281,poc type/bits setting"
bitfld.long 0x00 31. "SW_ENC_STRM_SEGMENT_SW_SYNC_EN,Stream segment software handshake enable" "0,1"
newline
bitfld.long 0x00 30. "SW_ENC_STRM_SEGMENT_EN,Stream segment function enable" "0,1"
newline
hexmask.long.word 0x00 20.--29. 1. "SW_ENC_STRM_SEGMENT_RD_PTR,the number of segments that have been read out from output buffer"
newline
hexmask.long.word 0x00 10.--19. 1. "SW_ENC_STRM_SEGMENT_WR_PTR,the number of segments that have been filled into the output buffer"
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bitfld.long 0x00 4.--9. "SW_NUM_CTB_ROWS_PER_SYNC_MSB,Number MSB of CTB rows for every HW sync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x47C++0x03
line.long 0x00 "swreg287,HW synthesis config register 4 read-only"
bitfld.long 0x00 31. "SW_ENC_HWVIDEOHEIGHTEXT,Maximum allowed video height extended from 8192 to 8640" "0: bf_val_0,1: bf_val_1"
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bitfld.long 0x00 30. "SW_ENC_HWCSCEXTENSIONSUPPORT,RGB to YUV conversion extension" "0: not supported,1: supported"
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bitfld.long 0x00 29. "SW_ENC_HWSCALER420SUPPORT,out-loop scaler output YUV420SP" "0: not supported,1: supported"
group.long 0x484++0x03
line.long 0x00 "swreg289,Pre-processor color conversion parameters1"
hexmask.long.word 0x00 16.--31. 1. "SW_ENC_RGBCOEFFG,RGB to YUV conversion coefficient G"
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hexmask.long.word 0x00 0.--15. 1. "SW_ENC_RGBCOEFFH,RGB to YUV conversion coefficient H"
tree.end
tree "WDOG (Watchdog Timer Unit)"
repeat 3. (list 1. 2. 3.) (list ad:0x30280000 ad:0x30290000 ad:0x302A0000)
tree "WDOG$1"
base $2
group.word 0x00++0x01
line.word 0x00 "WCR,Watchdog Control Register"
hexmask.word.byte 0x00 8.--15. 1. "WT,Watchdog Time-out Field"
bitfld.word 0x00 7. "WDW,Watchdog Disable for Wait" "0: Continue WDOG timer operation (Default),1: Suspend WDOG timer operation"
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bitfld.word 0x00 6. "SRE,Software Reset Extension" "?,1: This bit must be set to 1"
bitfld.word 0x00 5. "WDA,WDOG_B assertion" "0: Assert WDOG_B output,1: No effect on system (Default)"
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bitfld.word 0x00 4. "SRS,Software Reset Signal" "0: Assert system reset signal,1: No effect on the system (Default)"
bitfld.word 0x00 3. "WDT,WDOG_B Time-out assertion" "0: No effect on WDOG_B (Default),1: Assert WDOG_B upon a Watchdog Time-out event"
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bitfld.word 0x00 2. "WDE,Watchdog Enable" "0: Disable the Watchdog (Default),1: Enable the Watchdog"
bitfld.word 0x00 1. "WDBG,Watchdog DEBUG Enable" "0: Continue WDOG timer operation (Default),1: Suspend the watchdog timer"
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bitfld.word 0x00 0. "WDZST,Watchdog Low Power" "0: Continue timer operation (Default),1: Suspend the watchdog timer"
group.word 0x02++0x01
line.word 0x00 "WSR,Watchdog Service Register"
hexmask.word 0x00 0.--15. 1. "WSR,Watchdog Service Register"
rgroup.word 0x04++0x01
line.word 0x00 "WRSR,Watchdog Reset Status Register"
bitfld.word 0x00 4. "POR,Power On Reset" "0: Reset is not the result of a power on reset,1: Reset is the result of a power on reset"
bitfld.word 0x00 1. "TOUT,Timeout" "0: Reset is not the result of a WDOG timeout,1: Reset is the result of a WDOG timeout"
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bitfld.word 0x00 0. "SFTW,Software Reset" "0: Reset is not the result of a software reset,1: Reset is the result of a software reset"
group.word 0x06++0x01
line.word 0x00 "WICR,Watchdog Interrupt Control Register"
bitfld.word 0x00 15. "WIE,Watchdog Timer Interrupt enable bit" "0: Disable Interrupt (Default),1: Enable Interrupt"
eventfld.word 0x00 14. "WTIS,Watchdog Timer Interrupt Status bit will reflect the timer interrupt status whether interrupt has occurred or not" "0: No interrupt has occurred (Default),1: Interrupt has occurred"
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hexmask.word.byte 0x00 0.--7. 1. "WICT,Watchdog Interrupt Count Time-out (WICT) field determines how long before the counter time-out must the interrupt occur"
group.word 0x08++0x01
line.word 0x00 "WMCR,Watchdog Miscellaneous Control Register"
bitfld.word 0x00 0. "PDE,Power Down Enable bit" "0: Power Down Counter of WDOG is disabled,1: Power Down Counter of WDOG is enabled (Default)"
tree.end
repeat.end
tree.end
tree "XTALOSC"
base ad:0x30270000
group.long 0x00++0x03
line.long 0x00 "SYS_OSCNML_CTL0,OSC Normal Clock Generation Control Register0"
bitfld.long 0x00 31. "EN,Enable Oscillator" "0,1"
bitfld.long 0x00 4. "RTO,Retention Enable" "0,1"
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bitfld.long 0x00 2. "SP,Select Power" "0,1"
bitfld.long 0x00 1. "SF1,Select Frequency1" "0,1"
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bitfld.long 0x00 0. "SF0,Select Frequency0" "0,1"
group.long 0x04++0x03
line.long 0x00 "SYS_OSCNML_CTL1,OSC Normal Clock Generation Control Register1"
hexmask.long.byte 0x00 4.--11. 1. "LOCK_COUNT,Lock Signal Gen Counter"
bitfld.long 0x00 2. "CLK_CKE,Oscillator Clock Gating Enable" "0,1"
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bitfld.long 0x00 1. "CLK_CKE_OVERRIDE,Oscillator Clock Gating Enable Override" "0,1"
tree.end
autoindent.off
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